diff --git a/scripts/helper/do_implementation_finish.tcl b/scripts/helper/do_implementation_finish.tcl
index 4c674c9f75a3c7b5015e3b80932e345553144c0a..b78d7b1219d89460fad77dd403764f0653d932d8 100644
--- a/scripts/helper/do_implementation_finish.tcl
+++ b/scripts/helper/do_implementation_finish.tcl
@@ -67,7 +67,7 @@ set CARD_TYPE_STR $CARD_TYPE
 
 set GIT_BRANCH [string map { / - } [exec git rev-parse --abbrev-ref HEAD]]
 
-set FileName FLX${CARD_TYPE_STR}${FW_MODE}_RM${REG_MAP_VERSION_STR}_${GBT_NUM}CH_${CLKSRC}${SICHIP}_GIT_${GIT_BRANCH}_${git_tag_str}_${GIT_COMMIT_NUMBER}_${TIMESTAMP}
+set FileName FLX${CARD_TYPE_STR}${FW_MODE}_${GBT_NUM}CH_${CLKSRC}${SICHIP}_GIT_${GIT_BRANCH}_${git_tag_str}_${GIT_COMMIT_NUMBER}_${TIMESTAMP}
 
 write_bitstream -force $HDLDIR/output/${FileName}.bit
 
@@ -94,7 +94,6 @@ COMMIT_DATETIME:                $COMMIT_DATETIME
 GIT_HASH:                       $GIT_HASH 
 GIT_TAG:                        $GIT_TAG 
 GIT_COMMIT_NUMBER:              $GIT_COMMIT_NUMBER 
-REG_MAP_VERSION:                $REG_MAP_VERSION 
 GENERATE_GBT:                   $GENERATE_GBT 
 NUMBER_OF_INTERRUPTS:           $NUMBER_OF_INTERRUPTS 
 NUMBER_OF_DESCRIPTORS:          $NUMBER_OF_DESCRIPTORS
diff --git a/scripts/helper/do_implementation_post.tcl b/scripts/helper/do_implementation_post.tcl
index 6a15f2de2c03750604a1414ae8b76b8a9e2022d7..9a9c3ba1e93f2d8241a0e08ac29392c61f48c83d 100644
--- a/scripts/helper/do_implementation_post.tcl
+++ b/scripts/helper/do_implementation_post.tcl
@@ -24,13 +24,6 @@ set systemTime [clock seconds]
 set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
 puts "BUILD_DATE = $build_date"
 
-# Read Register Map version from autogenerated file
-set ver [open "../../sources/templates/version.txt" "r"]
-set REG_MAP_VERSION "16'h[read $ver]"
-seek $ver 0
-set REG_MAP_VERSION_STR  "[read $ver]"
-close $ver
-
 #For 711 / 712 cards the core location in the PCIe endpoint must be selected correctly.
 if {$CARD_TYPE == 711} {
     set loc_7039 [get_property CONFIG.pcie_blk_locn [get_ips pcie3_ultrascale_7039]]
@@ -171,7 +164,6 @@ COMMIT_DATETIME=$COMMIT_DATETIME \
 GIT_HASH=$GIT_HASH \
 GIT_TAG=$GIT_TAG \
 GIT_COMMIT_NUMBER=$GIT_COMMIT_NUMBER \
-REG_MAP_VERSION=$REG_MAP_VERSION \
 GENERATE_GBT=$GENERATE_GBT \
 NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS \
 NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS \
diff --git a/simulation/Wupper/pcie_ep_wrap_sim_circularDMA.vhd b/simulation/Wupper/pcie_ep_wrap_sim_circularDMA.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..23c34f18f58c1155232d1590e014375224215409
--- /dev/null
+++ b/simulation/Wupper/pcie_ep_wrap_sim_circularDMA.vhd
@@ -0,0 +1,328 @@
+
+--!------------------------------------------------------------------------------
+--!                                                             
+--!           NIKHEF - National Institute for Subatomic Physics 
+--!
+--!                       Electronics Department                
+--!                                                             
+--!-----------------------------------------------------------------------------
+--! @class pcie_ep_wrap
+--! 
+--!
+--! @author      Andrea Borga    (andrea.borga@nikhef.nl)<br>
+--!              Frans Schreuder (frans.schreuder@nikhef.nl)
+--!
+--!
+--! @date        07/01/2015    created
+--!
+--! @version     1.0
+--!
+--! @brief 
+--! Wrapper unit for the PCI Express core, and the clock generator 
+--!
+--! @detail
+--!
+--!-----------------------------------------------------------------------------
+--! @TODO
+--!  
+--!
+--! ------------------------------------------------------------------------------
+--! Virtex7 PCIe Gen3 DMA Core
+--! 
+--! \copyright GNU LGPL License
+--! Copyright (c) Nikhef, Amsterdam, All rights reserved. <br>
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3.0 of the License, or (at your option) any later version.
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.<br>
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library.
+--! 
+-- 
+--! @brief ieee
+
+
+
+library ieee, UNISIM, work;
+use ieee.numeric_std.all;
+use UNISIM.VCOMPONENTS.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_1164.all;
+use work.pcie_package.all;
+
+entity pcie_ep_wrap is
+  generic(
+    CARD_TYPE : integer := 710;
+    DEVID     : std_logic_vector(15 downto 0) := x"7038");
+  port (
+    cfg_fc_cpld                : out    std_logic_vector(11 downto 0);
+    cfg_fc_cplh                : out    std_logic_vector(7 downto 0);
+    cfg_fc_npd                 : out    std_logic_vector(11 downto 0);
+    cfg_fc_nph                 : out    std_logic_vector(7 downto 0);
+    cfg_fc_pd                  : out    std_logic_vector(11 downto 0);
+    cfg_fc_ph                  : out    std_logic_vector(7 downto 0);
+    cfg_fc_sel                 : in     std_logic_vector(2 downto 0);
+    cfg_interrupt_msix_address : in     std_logic_vector(63 downto 0);
+    cfg_interrupt_msix_data    : in     std_logic_vector(31 downto 0);
+    cfg_interrupt_msix_enable  : out    std_logic_vector(3 downto 0);
+    cfg_interrupt_msix_fail    : out    std_logic;
+    cfg_interrupt_msix_int     : in     std_logic;
+    cfg_interrupt_msix_sent    : out    std_logic;
+    cfg_mgmt_addr              : in     std_logic_vector(18 downto 0);
+    cfg_mgmt_byte_enable       : in     std_logic_vector(3 downto 0);
+    cfg_mgmt_read              : in     std_logic;
+    cfg_mgmt_read_data         : out    std_logic_vector(31 downto 0);
+    cfg_mgmt_read_write_done   : out    std_logic;
+    cfg_mgmt_write             : in     std_logic;
+    cfg_mgmt_write_data        : in     std_logic_vector(31 downto 0);
+    clk                        : out    std_logic;
+    m_axis_cq                  : out    axis_type;
+    m_axis_r_cq                : in     axis_r_type;
+    m_axis_r_rc                : in     axis_r_type;
+    m_axis_rc                  : out    axis_type;
+    pci_exp_rxn                : in     std_logic_vector(7 downto 0);
+    pci_exp_rxp                : in     std_logic_vector(7 downto 0);
+    pci_exp_txn                : out    std_logic_vector(7 downto 0);
+    pci_exp_txp                : out    std_logic_vector(7 downto 0);
+    reset                      : out    std_logic;
+    s_axis_cc                  : in     axis_type;
+    s_axis_r_cc                : out    axis_r_type;
+    s_axis_r_rq                : out    axis_r_type;
+    s_axis_rq                  : in     axis_type;
+    sys_clk_n                  : in     std_logic;
+    sys_clk_p                  : in     std_logic;
+    sys_rst_n                  : in     std_logic;
+    user_lnk_up                : out    std_logic);
+end entity pcie_ep_wrap;
+
+
+
+architecture structure of pcie_ep_wrap is
+  
+  signal user_clk: std_logic;
+  constant user_clk_period: time  := 4 ns;
+      
+  constant BAR0: std_logic_vector(31 downto 0) := x"BA00_8000";   
+  constant BAR1: std_logic_vector(31 downto 0) := x"BA00_8001";   
+  constant BAR2: std_logic_vector(31 downto 0) := x"BA00_8002";   
+  type slv256_array is array (natural range <>) of std_logic_vector(255 downto 0);
+  signal ToHostMem: slv256_array(0 to 127);  
+  signal FromHostMem: slv256_array(0 to 127);  
+begin
+    user_clk_proc: process
+    begin
+        user_clk <= '1';
+        wait for user_clk_period / 2;
+        user_clk <= '0';
+        wait for user_clk_period / 2;
+    end process;
+
+    cfg_fc_cpld                <= (others => '0');--: out    std_logic_vector(11 downto 0);
+    cfg_fc_cplh                <= (others => '0');--: out    std_logic_vector(7 downto 0);
+    cfg_fc_npd                 <= (others => '0');--: out    std_logic_vector(11 downto 0);
+    cfg_fc_nph                 <= (others => '0');--: out    std_logic_vector(7 downto 0);
+    cfg_fc_pd                  <= (others => '0');--: out    std_logic_vector(11 downto 0);
+    cfg_fc_ph                  <= (others => '0');--: out    std_logic_vector(7 downto 0);
+    --cfg_fc_sel                 : in     std_logic_vector(2 downto 0);
+    --cfg_interrupt_msix_address : in     std_logic_vector(63 downto 0);
+    --cfg_interrupt_msix_data    : in     std_logic_vector(31 downto 0);
+    cfg_interrupt_msix_enable  <= (others => '1');--: out    std_logic_vector(3 downto 0);
+    cfg_interrupt_msix_fail    <= '0';--: out    std_logic;
+    cfg_interrupt_msix_sent    <= cfg_interrupt_msix_int;--: out    std_logic;
+    
+    mgmt_proc: process(user_clk)
+    begin
+        if rising_edge(user_clk) then
+            cfg_mgmt_read_write_done <= cfg_mgmt_read or cfg_mgmt_write;
+            if cfg_mgmt_addr = "000"&x"0004" and cfg_mgmt_read = '1' then --read BAR0
+              cfg_mgmt_read_data <= BAR0; --BAR0 address
+            end if;
+            if cfg_mgmt_addr = "000"&x"0005" and cfg_mgmt_read = '1' then --read BAR0
+              cfg_mgmt_read_data <= BAR1; --BAR0 address
+            end if;
+            if cfg_mgmt_addr = "000"&x"0006" and cfg_mgmt_read = '1' then --read BAR0
+              cfg_mgmt_read_data <= BAR2; --BAR0 address
+            end if;            
+        end if;
+    end process;
+    
+    reg_write: process
+        procedure w
+     (RegAddr: in std_logic_vector(19 downto 0);
+      BarAddr: in std_logic_vector(31 downto 0);
+      Data:    in std_logic_vector(63 downto 0)) is
+      variable bar_id: std_logic_vector(2 downto 0):= "000";
+    begin
+      wait until rising_edge(user_clk);
+      m_axis_cq.tdata <= (others => '0');
+      
+      m_axis_cq.tdata(1 downto 0) <= "00"; --address type
+      m_axis_cq.tdata(63 downto 32) <= x"0000_0000";
+      m_axis_cq.tdata(31 downto 20) <= BarAddr(31 downto 20);
+      m_axis_cq.tdata(19 downto 2) <= RegAddr(19 downto 2);
+      
+      m_axis_cq.tdata(74 downto 64) <= "00000000010";-- 2 words, 64 bit write dword_count_s;
+      m_axis_cq.tdata(78 downto 75) <= "0001"; --Memory write, request_type_v
+      m_axis_cq.tdata(95 downto 80)    <= x"0000";--requester_id_s
+      m_axis_cq.tdata(103 downto 96)   <= x"00";--tag_s
+      m_axis_cq.tdata(111 downto 104)  <= x"00";--target_function_s
+      if BarAddr = BAR0 then
+        bar_id := "000";
+      end if;
+      if BarAddr = BAR1 then
+        bar_id := "001";
+      end if;
+      if BarAddr = BAR2 then
+        bar_id := "010";
+      end if;
+      m_axis_cq.tdata(114 downto 112)  <= bar_id;
+      m_axis_cq.tdata(120 downto 115)  <= "000000";--bar_aperture_s
+      m_axis_cq.tdata(123 downto 121)  <= "000";--transaction_class_s
+      m_axis_cq.tdata(126 downto 124)  <= "000";--attributes_s
+      m_axis_cq.tdata(191 downto 128)  <= Data; --register_write_data_250_s
+      m_axis_cq.tdata(255 downto 192)  <= (others => '0'); --register_write_data_250_s
+      m_axis_cq.tuser(3 downto 0)      <= "1111";--first_be_s
+      m_axis_cq.tuser(7 downto 4)      <= "1111";--last_be_s
+      m_axis_cq.tuser(84 downto 8)      <= (others => '0');
+      m_axis_cq.tkeep                  <= "00111111"; --64b writes, don't care about the MSB 64 bits
+      m_axis_cq.tvalid                 <= '1';
+      m_axis_cq.tlast                  <= '1';
+      wait until rising_edge(user_clk);
+      m_axis_cq.tvalid                 <= '0';
+      m_axis_cq.tlast                  <= '0';
+      while m_axis_r_cq.tready = '0' loop
+        wait until rising_edge(user_clk);
+      end loop;
+           
+    end w;
+    begin
+        wait for 1 us; --startup time
+        w(REG_PC_PTR_GAP, BAR0, x"0000_0000_0000_0000"); --set pc_ptr_gap to 0
+                
+        w(REG_DESCRIPTOR_0,      BAR0, x"ABCD_0000_0000_0000"); --descr 0 start address
+        w(REG_DESCRIPTOR_0+8,    BAR0, x"ABCD_0000_0000_1000"); --descr 0 end address = end address + 4096 (16 TLPs of 256 bytes)
+        w(REG_DESCRIPTOR_0a+8,   BAR0, x"ABCD_0000_0000_0000"); --init PC pointer at start_address
+        w(REG_DESCRIPTOR_0a,     BAR0, x"0000_0000_0000_1040"); --wrap around, ToHost, 256 bytes  
+        w(REG_DESCRIPTOR_1,      BAR0, x"DEF8_0000_0000_0000"); --descr 1 start address
+        w(REG_DESCRIPTOR_1+8,    BAR0, x"DEF8_0000_0000_1000"); --descr 1 end address = end address + 4096 (16 TLPs of 256 bytes)
+        w(REG_DESCRIPTOR_1a+8,   BAR0, x"DEF8_0000_0000_0000"); --init PC pointer at start_address
+        w(REG_DESCRIPTOR_1a,     BAR0, x"0000_0000_0000_1808"); --wrap around, FromHost, 32 bytes  
+        w(REG_DESCRIPTOR_ENABLE, BAR0, x"0000_0000_0000_0003"); --Enable both descriptors  
+        wait for 1 us;
+        w(REG_DESCRIPTOR_1a+8  , BAR0, x"DEF8_0000_0000_0020"); --increment PC pointer with 1 TLP
+        wait for 1 us;
+        w(REG_DESCRIPTOR_1a+8  , BAR0, x"DEF8_0000_0000_0060"); --increment PC pointer with 2 TLPs
+        wait for 1 us;
+        w(REG_DESCRIPTOR_1a+8  , BAR0, x"DEF8_0000_0000_0020"); --Wrap around to 0x20
+        
+        wait for 1 us;
+        w(REG_DESCRIPTOR_0a+8,   BAR0, x"ABCD_0000_0000_0800"); --Icrement ToHost pc_pointer with 8 TLPs (half way the buffer)
+        w(REG_DESCRIPTOR_1a+8,   BAR0, x"DEF8_0000_0000_0800"); --Also start reading FromHost
+                
+                
+                        
+        wait;
+        
+        
+    end process;
+    s_axis_r_cc.tready <= '1';
+    
+    g_FromHostMem: for i in 0 to 127 generate
+        FromHostMem(i) <= x"DEADBEEF_01234567_AABBAABB_00000000_01234567_89ABCDEF" & std_logic_vector(to_unsigned(i,64));
+    end generate;
+    
+    response_proc: process(user_clk)
+        variable ToHost_tlp_busy: std_logic := '0';
+        variable address: std_logic_vector(63 downto 0);
+        variable dword_count: std_logic_vector(10 downto 0);
+        variable request_type: std_logic_vector(3 downto 0); --"0001" for write, "0000" for read.
+        variable ToHost_pipe_data: std_logic_vector(127 downto 0);
+        variable TLPsToSend: integer range 0 to 65536:= 0;
+        variable FromHostIndex: integer range 0 to 127;
+        variable ToHostIndex: integer range 0 to 127;
+        variable FromHost_pipe_data: std_logic_vector(95 downto 0);
+        variable TlpIndex: integer range 0 to 127:= 0;
+    begin
+        if rising_edge(user_clk) then
+            if s_axis_rq.tvalid = '1' then
+                if ToHost_tlp_busy = '0' then --first word, decode everything from header.
+                    address := s_axis_rq.tdata(63 downto 2) & "00";
+                    dword_count := s_axis_rq.tdata(74 downto 64);
+                    request_type := s_axis_rq.tdata(78 downto 75);
+                    ToHost_pipe_data := s_axis_rq.tdata(255 downto 128);
+                    if request_type = "0000" then 
+                        FromHostIndex := to_integer(unsigned(address(11 downto 5)));
+                        TLPsToSend := TLPsToSend + 1;
+                    end if;
+                    if request_type = "0001" then 
+                        ToHostIndex := to_integer(unsigned(address(11 downto 5)));
+                    end if;
+                    ToHost_tlp_busy := '1';
+                else
+                    ToHostMem(ToHostIndex) <=  s_axis_rq.tdata(127 downto 0) & ToHost_pipe_data; --write the TLP in the host memory.
+                    ToHost_pipe_data := s_axis_rq.tdata(255 downto 128);
+                    ToHostIndex := ToHostIndex + 1;
+                end if;
+                if s_axis_rq.tlast = '1' then
+                    ToHost_tlp_busy := '0';
+                end if;
+            end if;
+            if(m_axis_r_rc.tready = '1') then
+                m_axis_rc.tvalid <= '0';
+                m_axis_rc.tdata <= (others => '0');
+                m_axis_rc.tuser <= (others => '0');
+                m_axis_rc.tkeep <= x"00";                    
+                if TLPsToSend > 0 and TlpIndex = 0 then
+                    m_axis_rc.tdata(255 downto 96) <= FromHostMem(FromHostIndex)(159 downto 0);
+                    FromHost_pipe_data := FromHostMem(FromHostIndex)(255 downto 160);
+                    m_axis_rc.tdata(42 downto 32) <= dword_count;
+                    m_axis_rc.tvalid <= '1';
+                    TlpIndex := to_integer(unsigned(dword_count(10 downto 3)));
+                    FromHostIndex := FromHostIndex + 1;            
+                    m_axis_rc.tlast <= '0';
+                    TLPsToSend := TLPsToSend - 1 ;
+                    m_axis_rc.tkeep <= x"FF";
+                elsif TlpIndex /= 0 then
+                    m_axis_rc.tdata(95 downto 0) <= FromHost_pipe_data;
+                    m_axis_rc.tvalid <= '1';
+                    if(TlpIndex > 1) then
+                        m_axis_rc.tdata(255 downto 96) <= FromHostMem(FromHostIndex)(159 downto 0);
+                        FromHost_pipe_data := FromHostMem(FromHostIndex)(255 downto 160);
+                        m_axis_rc.tlast <= '0';
+                        m_axis_rc.tkeep <= x"FF";
+                    else
+                        m_axis_rc.tdata(255 downto 96) <= (others => '0');
+                        m_axis_rc.tlast <= '1';
+                        m_axis_rc.tkeep <= x"07";
+                    end if;
+                    TlpIndex := TlpIndex - 1;
+                    FromHostIndex := FromHostIndex + 1;
+                                
+                    
+                end if;
+            end if;
+        end if;
+    end process;
+                  
+    
+    
+    
+    --m_axis_r_rc                : in     axis_r_type;
+    --m_axis_rc                  : out    axis_type;
+    s_axis_r_rq.tready <= '1';
+    --s_axis_rq                  : in     axis_type;
+    
+    pci_exp_txn         <= (others => '0');--       : out    std_logic_vector(7 downto 0);
+    pci_exp_txp         <= (others => '0');--       : out    std_logic_vector(7 downto 0);
+    user_lnk_up   <= '1';--             : out    std_logic
+
+   
+    reset <= not sys_rst_n;
+    clk   <= user_clk;
+
+end architecture structure ; -- of pcie_ep_wrap
+
diff --git a/simulation/Wupper/wupper_tb.vhd b/simulation/Wupper/wupper_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d11b50ca8e9cdac15cfe0996f70db51e699dd902
--- /dev/null
+++ b/simulation/Wupper/wupper_tb.vhd
@@ -0,0 +1,260 @@
+
+--!------------------------------------------------------------------------------
+--!                                                             
+--!           NIKHEF - National Institute for Subatomic Physics 
+--!
+--!                       Electronics Department                
+--!                                                             
+--!-----------------------------------------------------------------------------
+--! @class felix_top
+--! 
+--!
+--! @author      Andrea Borga    (andrea.borga@nikhef.nl)<br>
+--!              Frans Schreuder (frans.schreuder@nikhef.nl)
+--!
+--!
+--! @date        07/01/2015    created
+--!
+--! @version     1.0
+--!
+--! @brief 
+--! Top level for the FELIX project, containing GBT, CentralRouter and PCIe DMA core
+--! 
+--! 
+--! 
+--! @detail
+--!
+--!-----------------------------------------------------------------------------
+--! @TODO
+--!  
+--!
+--! ------------------------------------------------------------------------------
+--! Virtex7 PCIe Gen3 DMA Core
+--! 
+--! \copyright GNU LGPL License
+--! Copyright (c) Nikhef, Amsterdam, All rights reserved. <br>
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3.0 of the License, or (at your option) any later version.
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.<br>
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library.
+--! 
+-- 
+--! @brief ieee
+
+
+
+library ieee, UNISIM, work;
+use ieee.numeric_std.all;
+use UNISIM.VCOMPONENTS.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_1164.all;
+use work.pcie_package.all;
+
+entity wupper_tb is
+  
+end entity wupper_tb;
+
+architecture structure of wupper_tb is
+
+  
+
+  component fifo128KB_256bit
+    port (
+      rst                     : in     std_logic;
+      wr_clk                  : in     std_logic;
+      rd_clk                  : in     std_logic;
+      din                     : in     std_logic_vector(255 downto 0);
+      wr_en                   : in     std_logic;
+      rd_en                   : in     std_logic;
+      prog_empty_thresh       : in     std_logic_vector(11 downto 0);
+      prog_full_thresh_assert : in     std_logic_vector(11 downto 0);
+      prog_full_thresh_negate : in     std_logic_vector(11 downto 0);
+      dout                    : out    std_logic_vector(255 downto 0);
+      full                    : out    std_logic;
+      empty                   : out    std_logic;
+      prog_full               : out    std_logic;
+      prog_empty              : out    std_logic;
+      wr_data_count           : out    std_logic_vector(11 downto 0));
+  end component fifo128KB_256bit;
+
+  component fifo16KB_256bit
+    port (
+      rst                     : in     std_logic;
+      wr_clk                  : in     std_logic;
+      rd_clk                  : in     std_logic;
+      din                     : in     std_logic_vector(255 downto 0);
+      wr_en                   : in     std_logic;
+      rd_en                   : in     std_logic;
+      prog_full_thresh_assert : in     std_logic_vector(8 downto 0);
+      prog_full_thresh_negate : in     std_logic_vector(8 downto 0);
+      dout                    : out    std_logic_vector(255 downto 0);
+      full                    : out    std_logic;
+      empty                   : out    std_logic;
+      prog_full               : out    std_logic);
+  end component fifo16KB_256bit;
+  constant NUMBER_OF_INTERRUPTS: integer := 8;
+  constant NUMBER_OF_DESCRIPTORS: integer := 2;
+  
+  signal fromHostFifo_din: std_logic_vector(255 downto 0);
+  signal fromHostFifo_pfull_threshold_assert : std_logic_vector(8 downto 0);
+  signal fromHostFifo_pfull_threshold_negate : std_logic_vector(8 downto 0);
+  signal fromHostFifo_prog_full, fromHostFifo_we, fromHostFifo_wr_clk: std_logic;
+  signal pcie_rxn: std_logic_vector(7 downto 0);
+  signal pcie_rxp: std_logic_vector(7 downto 0);
+  signal pcie_txn: std_logic_vector(7 downto 0);
+  signal pcie_txp: std_logic_vector(7 downto 0);
+  
+  signal sys_reset_n: std_logic;
+  
+  signal toHostFifo_dout: std_logic_vector(255 downto 0);
+  signal toHostFifo_empty_thresh: std_logic_vector(11 downto 0);
+  signal toHostFifo_pfull_threshold_assert: std_logic_vector(11 downto 0);
+  signal toHostFifo_pfull_threshold_negate: std_logic_vector(11 downto 0);
+  
+  signal toHostFifo_prog_empty, toHostFifo_rd_clk, toHostFifo_re: std_logic;
+  
+  
+  
+  signal clk240: std_logic;
+  constant clk240_period: time := 4.17ns;
+  signal reset_hard: std_logic;
+  signal toHostFifo_rst: std_logic;
+  signal fromHostFifo_rst: std_logic;
+  
+  signal toHostFifo_din       : std_logic_vector(255 downto 0);
+  signal toHostFifo_wr_en     : std_logic;
+  signal toHostFifo_prog_full : std_logic;
+
+  signal fromHostFifo_rd_en   : std_logic;
+  signal fromHostFifo_dout    : std_logic_vector(255 downto 0);
+  signal fromHostFifo_empty   : std_logic;
+  signal register_map_monitor: register_map_monitor_type;
+  
+begin
+  pcie_rxn <= pcie_txn;
+  pcie_rxp <= pcie_txp;
+  
+  process
+  begin
+    sys_reset_n <= '0';
+    wait for 100 ns;
+    sys_reset_n <= '1';
+    wait;
+  end process;
+  
+  toHostFifo_rst <= reset_hard;
+  fromHostFifo_rst <= reset_hard;
+  
+  process
+  begin
+    clk240 <= '1';
+    wait for clk240_period/2;
+    clk240 <= '0';
+    wait for clk240_period/2;
+  end process;
+
+  pcie0: entity work.wupper
+    generic map(
+      NUMBER_OF_INTERRUPTS  => NUMBER_OF_INTERRUPTS,
+      NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
+      BUILD_DATETIME        => (others => '0'),
+      SVN_VERSION           => 0,
+      CARD_TYPE             => 709,
+      DEVID                 => x"7038",
+      GIT_HASH              => (others => '0'),
+      COMMIT_DATETIME       => (others => '0'),
+      GIT_TAG               => (others => '0'),
+      GIT_COMMIT_NUMBER     => 42,
+      GBT_GENERATE_ALL_REGS => true,
+      EMU_GENERATE_REGS     => false,
+      PCIE_ENDPOINT         => 0)
+    port map(
+      appreg_clk                          => open,
+      flush_fifo                          => open,
+      fromHostFifo_din                    => fromHostFifo_din,
+      fromHostFifo_pfull_threshold_assert => fromHostFifo_pfull_threshold_assert,
+      fromHostFifo_pfull_threshold_negate => fromHostFifo_pfull_threshold_negate,
+      fromHostFifo_prog_full              => fromHostFifo_prog_full,
+      fromHostFifo_we                     => fromHostFifo_we,
+      fromHostFifo_wr_clk                 => fromHostFifo_wr_clk,
+      fromhost_busy_out                   => open,
+      interrupt_call                      => (others => '0'),
+      lnk_up                              => open,
+      pcie_rxn                            => pcie_rxn,
+      pcie_rxp                            => pcie_rxp,
+      pcie_txn                            => pcie_txn,
+      pcie_txp                            => pcie_txp,
+      pll_locked                          => open,
+      register_map_control                => open,
+      register_map_monitor                => register_map_monitor,
+      reset_hard                          => reset_hard,
+      reset_soft                          => open,
+      sys_clk_n                           => '0', -- not used, 250 MHz clock generated internally
+      sys_clk_p                           => '0', -- not used, 250 MHz clock generated internally
+      sys_reset_n                         => sys_reset_n,
+      toHostFifo_dout                     => toHostFifo_dout,
+      toHostFifo_empty_thresh             => toHostFifo_empty_thresh,
+      toHostFifo_pfull_threshold_assert   => toHostFifo_pfull_threshold_assert,
+      toHostFifo_pfull_threshold_negate   => toHostFifo_pfull_threshold_negate,
+      toHostFifo_prog_empty               => toHostFifo_prog_empty,
+      toHostFifo_rd_clk                   => toHostFifo_rd_clk,
+      toHostFifo_re                       => toHostFifo_re,
+      tohost_busy_out                     => open);
+
+  
+
+  toHostFifo: fifo128KB_256bit
+    port map(
+      rst                     => toHostFifo_rst,
+      wr_clk                  => clk240,
+      rd_clk                  => toHostFifo_rd_clk,
+      din                     => toHostFifo_din,
+      wr_en                   => toHostFifo_wr_en,
+      rd_en                   => toHostFifo_re,
+      prog_empty_thresh       => toHostFifo_empty_thresh,
+      prog_full_thresh_assert => toHostFifo_pfull_threshold_assert,
+      prog_full_thresh_negate => toHostFifo_pfull_threshold_negate,
+      dout                    => toHostFifo_dout,
+      full                    => open,
+      empty                   => open,
+      prog_full               => toHostFifo_prog_full,
+      prog_empty              => toHostFifo_prog_empty,
+      wr_data_count           => open);
+
+  fromHostFifo: fifo16KB_256bit
+    port map(
+      rst                     => fromHostFifo_rst,
+      wr_clk                  => fromHostFifo_wr_clk,
+      rd_clk                  => clk240,
+      din                     => fromHostFifo_din,
+      wr_en                   => fromHostFifo_we,
+      rd_en                   => fromHostFifo_rd_en,
+      prog_full_thresh_assert => fromHostFifo_pfull_threshold_assert,
+      prog_full_thresh_negate => fromHostFifo_pfull_threshold_negate,
+      dout                    => fromHostFifo_dout,
+      full                    => open,
+      empty                   => fromHostFifo_empty,
+      prog_full               => fromHostFifo_prog_full);
+
+
+toHostFifo_din <= fromHostFifo_dout;
+
+process(clk240)
+begin
+    if reset_hard = '1' then
+        toHostFifo_wr_en <= '0'; 
+    elsif rising_edge(clk240) then
+        toHostFifo_wr_en <= fromHostFifo_rd_en;
+    end if;
+end process;
+
+fromHostFifo_rd_en <= not fromHostFifo_empty and not toHostFifo_prog_full;
+
+end architecture structure ; -- of felix_top
+
diff --git a/simulation/Wupper/wupper_tb_behav.wcfg b/simulation/Wupper/wupper_tb_behav.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..9e8ac72bddd409aa65a3c51c82b17fc2895e545d
--- /dev/null
+++ b/simulation/Wupper/wupper_tb_behav.wcfg
@@ -0,0 +1,817 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="wupper_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="centralrouter_package" />
+            <top_module name="glbl" />
+            <top_module name="pcie_package" />
+            <top_module name="wupper_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="10281800000fs"></ZoomStartTime>
+      <ZoomEndTime time="10328400001fs"></ZoomEndTime>
+      <Cursor1Time time="10304000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="194"></NameColumnWidth>
+      <ValueColumnWidth column_width="260"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="4" />
+   <wvobject type="group" fp_name="group33">
+      <obj_property name="label">wupper_tb</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="/wupper_tb/fromHostFifo_din">
+         <obj_property name="ElementShortName">fromHostFifo_din[255:0]</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_din[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_prog_full">
+         <obj_property name="ElementShortName">fromHostFifo_prog_full</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_prog_full</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_we">
+         <obj_property name="ElementShortName">fromHostFifo_we</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_we</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_wr_clk">
+         <obj_property name="ElementShortName">fromHostFifo_wr_clk</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_wr_clk</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/toHostFifo_dout">
+         <obj_property name="ElementShortName">toHostFifo_dout[255:0]</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_dout[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_prog_empty">
+         <obj_property name="ElementShortName">toHostFifo_prog_empty</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_prog_empty</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_rd_clk">
+         <obj_property name="ElementShortName">toHostFifo_rd_clk</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_rd_clk</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_re">
+         <obj_property name="ElementShortName">toHostFifo_re</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_re</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/clk240">
+         <obj_property name="ElementShortName">clk240</obj_property>
+         <obj_property name="ObjectShortName">clk240</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/reset_hard">
+         <obj_property name="ElementShortName">reset_hard</obj_property>
+         <obj_property name="ObjectShortName">reset_hard</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_rst">
+         <obj_property name="ElementShortName">toHostFifo_rst</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_rst</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_rst">
+         <obj_property name="ElementShortName">fromHostFifo_rst</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_rst</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/toHostFifo_din">
+         <obj_property name="ElementShortName">toHostFifo_din[255:0]</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_din[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_wr_en">
+         <obj_property name="ElementShortName">toHostFifo_wr_en</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_wr_en</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/toHostFifo_prog_full">
+         <obj_property name="ElementShortName">toHostFifo_prog_full</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_prog_full</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_rd_en">
+         <obj_property name="ElementShortName">fromHostFifo_rd_en</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_rd_en</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/fromHostFifo_dout">
+         <obj_property name="ElementShortName">fromHostFifo_dout[255:0]</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_dout[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/fromHostFifo_empty">
+         <obj_property name="ElementShortName">fromHostFifo_empty</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_empty</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group120">
+      <obj_property name="label">dma_control</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar0">
+         <obj_property name="ElementShortName">bar0[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar0[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar1">
+         <obj_property name="ElementShortName">bar1[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar1[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar2">
+         <obj_property name="ElementShortName">bar2[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar2[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/clk">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/regmap_clk">
+         <obj_property name="ElementShortName">regmap_clk</obj_property>
+         <obj_property name="ObjectShortName">regmap_clk</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors">
+         <obj_property name="ElementShortName">dma_descriptors[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors[0:1]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/dma_soft_reset">
+         <obj_property name="ElementShortName">dma_soft_reset</obj_property>
+         <obj_property name="ObjectShortName">dma_soft_reset</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status">
+         <obj_property name="ElementShortName">dma_status[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_status[0:1]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status[0]">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">[0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status[1]">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">[1]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/flush_fifo">
+         <obj_property name="ElementShortName">flush_fifo</obj_property>
+         <obj_property name="ObjectShortName">flush_fifo</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/m_axis_cc">
+         <obj_property name="ElementShortName">m_axis_cc</obj_property>
+         <obj_property name="ObjectShortName">m_axis_cc</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/m_axis_r_cc">
+         <obj_property name="ElementShortName">m_axis_r_cc</obj_property>
+         <obj_property name="ObjectShortName">m_axis_r_cc</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/reset">
+         <obj_property name="ElementShortName">reset</obj_property>
+         <obj_property name="ObjectShortName">reset</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/reset_global_soft">
+         <obj_property name="ElementShortName">reset_global_soft</obj_property>
+         <obj_property name="ObjectShortName">reset_global_soft</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/s_axis_cq">
+         <obj_property name="ElementShortName">s_axis_cq</obj_property>
+         <obj_property name="ObjectShortName">s_axis_cq</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/s_axis_r_cq">
+         <obj_property name="ElementShortName">s_axis_r_cq</obj_property>
+         <obj_property name="ObjectShortName">s_axis_r_cq</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/fifo_full">
+         <obj_property name="ElementShortName">fifo_full</obj_property>
+         <obj_property name="ObjectShortName">fifo_full</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/fifo_empty">
+         <obj_property name="ElementShortName">fifo_empty</obj_property>
+         <obj_property name="ObjectShortName">fifo_empty</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_interrupt_call">
+         <obj_property name="ElementShortName">dma_interrupt_call[3:0]</obj_property>
+         <obj_property name="ObjectShortName">dma_interrupt_call[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/dma0/u1/completer_state">
+         <obj_property name="ElementShortName">completer_state</obj_property>
+         <obj_property name="ObjectShortName">completer_state</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_s">
+         <obj_property name="ElementShortName">dma_descriptors_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_s[0:1]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_s[0]">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">[0]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_s[1]">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">[1]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_r_s">
+         <obj_property name="ElementShortName">dma_descriptors_25_r_s[0:7]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_25_r_s[0:7]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s">
+         <obj_property name="ElementShortName">dma_descriptors_25_w_s[0:7]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_25_w_s[0:7]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[0]">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">[0]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[1]">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">[1]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[2]">
+            <obj_property name="ElementShortName">[2]</obj_property>
+            <obj_property name="ObjectShortName">[2]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[3]">
+            <obj_property name="ElementShortName">[3]</obj_property>
+            <obj_property name="ObjectShortName">[3]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[4]">
+            <obj_property name="ElementShortName">[4]</obj_property>
+            <obj_property name="ObjectShortName">[4]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[5]">
+            <obj_property name="ElementShortName">[5]</obj_property>
+            <obj_property name="ObjectShortName">[5]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[6]">
+            <obj_property name="ElementShortName">[6]</obj_property>
+            <obj_property name="ObjectShortName">[6]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_25_w_s[7]">
+            <obj_property name="ElementShortName">[7]</obj_property>
+            <obj_property name="ObjectShortName">[7]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_w_250_s">
+         <obj_property name="ElementShortName">dma_descriptors_w_250_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_w_250_s[0:1]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_sync250_s">
+         <obj_property name="ElementShortName">dma_descriptors_sync250_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_sync250_s[0:1]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status_sync250_s">
+         <obj_property name="ElementShortName">dma_status_sync250_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_status_sync250_s[0:1]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status_s">
+         <obj_property name="ElementShortName">dma_status_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_status_s[0:1]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dma_status_25_s">
+         <obj_property name="ElementShortName">dma_status_25_s[0:7]</obj_property>
+         <obj_property name="ObjectShortName">dma_status_25_s[0:7]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_address_s">
+         <obj_property name="ElementShortName">register_address_s[63:0]</obj_property>
+         <obj_property name="ObjectShortName">register_address_s[63:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/address_type_s">
+         <obj_property name="ElementShortName">address_type_s[1:0]</obj_property>
+         <obj_property name="ObjectShortName">address_type_s[1:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dword_count_s">
+         <obj_property name="ElementShortName">dword_count_s[10:0]</obj_property>
+         <obj_property name="ObjectShortName">dword_count_s[10:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/request_type_s">
+         <obj_property name="ElementShortName">request_type_s[3:0]</obj_property>
+         <obj_property name="ObjectShortName">request_type_s[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/requester_id_s">
+         <obj_property name="ElementShortName">requester_id_s[15:0]</obj_property>
+         <obj_property name="ObjectShortName">requester_id_s[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/tag_s">
+         <obj_property name="ElementShortName">tag_s[7:0]</obj_property>
+         <obj_property name="ObjectShortName">tag_s[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/target_function_s">
+         <obj_property name="ElementShortName">target_function_s[7:0]</obj_property>
+         <obj_property name="ObjectShortName">target_function_s[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar_id_s">
+         <obj_property name="ElementShortName">bar_id_s[2:0]</obj_property>
+         <obj_property name="ObjectShortName">bar_id_s[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar_aperture_s">
+         <obj_property name="ElementShortName">bar_aperture_s[5:0]</obj_property>
+         <obj_property name="ObjectShortName">bar_aperture_s[5:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/bar0_valid">
+         <obj_property name="ElementShortName">bar0_valid</obj_property>
+         <obj_property name="ObjectShortName">bar0_valid</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/transaction_class_s">
+         <obj_property name="ElementShortName">transaction_class_s[2:0]</obj_property>
+         <obj_property name="ObjectShortName">transaction_class_s[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/attributes_s">
+         <obj_property name="ElementShortName">attributes_s[2:0]</obj_property>
+         <obj_property name="ObjectShortName">attributes_s[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/first_be_s">
+         <obj_property name="ElementShortName">first_be_s[3:0]</obj_property>
+         <obj_property name="ObjectShortName">first_be_s[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/first_be_25_s">
+         <obj_property name="ElementShortName">first_be_25_s[3:0]</obj_property>
+         <obj_property name="ObjectShortName">first_be_25_s[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/last_be_s">
+         <obj_property name="ElementShortName">last_be_s[3:0]</obj_property>
+         <obj_property name="ObjectShortName">last_be_s[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/last_be_25_s">
+         <obj_property name="ElementShortName">last_be_25_s[3:0]</obj_property>
+         <obj_property name="ObjectShortName">last_be_25_s[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_data_r">
+         <obj_property name="ElementShortName">register_data_r[127:0]</obj_property>
+         <obj_property name="ObjectShortName">register_data_r[127:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/tlast_timer_s">
+         <obj_property name="ElementShortName">tlast_timer_s[7:0]</obj_property>
+         <obj_property name="ObjectShortName">tlast_timer_s[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_address_250_s">
+         <obj_property name="ElementShortName">register_read_address_250_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">register_read_address_250_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_address_25_s">
+         <obj_property name="ElementShortName">register_read_address_25_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">register_read_address_25_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_enable_250_s">
+         <obj_property name="ElementShortName">register_read_enable_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_read_enable_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_enable1_250_s">
+         <obj_property name="ElementShortName">register_read_enable1_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_read_enable1_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_enable_25_s">
+         <obj_property name="ElementShortName">register_read_enable_25_s</obj_property>
+         <obj_property name="ObjectShortName">register_read_enable_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_done_250_s">
+         <obj_property name="ElementShortName">register_read_done_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_read_done_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_done_25_s">
+         <obj_property name="ElementShortName">register_read_done_25_s</obj_property>
+         <obj_property name="ObjectShortName">register_read_done_25_s</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_data_250_s">
+         <obj_property name="ElementShortName">register_read_data_250_s[127:0]</obj_property>
+         <obj_property name="ObjectShortName">register_read_data_250_s[127:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_read_data_25_s">
+         <obj_property name="ElementShortName">register_read_data_25_s[127:0]</obj_property>
+         <obj_property name="ObjectShortName">register_read_data_25_s[127:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_address_250_s">
+         <obj_property name="ElementShortName">register_write_address_250_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">register_write_address_250_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_address_25_s">
+         <obj_property name="ElementShortName">register_write_address_25_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">register_write_address_25_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_enable_250_s">
+         <obj_property name="ElementShortName">register_write_enable_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_write_enable_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_enable1_250_s">
+         <obj_property name="ElementShortName">register_write_enable1_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_write_enable1_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_enable_25_s">
+         <obj_property name="ElementShortName">register_write_enable_25_s</obj_property>
+         <obj_property name="ObjectShortName">register_write_enable_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_done_250_s">
+         <obj_property name="ElementShortName">register_write_done_250_s</obj_property>
+         <obj_property name="ObjectShortName">register_write_done_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_done_25_s">
+         <obj_property name="ElementShortName">register_write_done_25_s</obj_property>
+         <obj_property name="ObjectShortName">register_write_done_25_s</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_data_250_s">
+         <obj_property name="ElementShortName">register_write_data_250_s[63:0]</obj_property>
+         <obj_property name="ObjectShortName">register_write_data_250_s[63:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_write_data_25_nobe_s">
+         <obj_property name="ElementShortName">register_write_data_25_nobe_s[63:0]</obj_property>
+         <obj_property name="ObjectShortName">register_write_data_25_nobe_s[63:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_word_address_25_s">
+         <obj_property name="ElementShortName">register_word_address_25_s[3:2]</obj_property>
+         <obj_property name="ObjectShortName">register_word_address_25_s[3:2]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/register_word_address_250_s">
+         <obj_property name="ElementShortName">register_word_address_250_s[3:2]</obj_property>
+         <obj_property name="ObjectShortName">register_word_address_250_s[3:2]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/dword_count_25_s">
+         <obj_property name="ElementShortName">dword_count_25_s[2:0]</obj_property>
+         <obj_property name="ObjectShortName">dword_count_25_s[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar0_25_s">
+         <obj_property name="ElementShortName">bar0_25_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar0_25_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar1_25_s">
+         <obj_property name="ElementShortName">bar1_25_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar1_25_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/bar2_25_s">
+         <obj_property name="ElementShortName">bar2_25_s[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bar2_25_s[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/fifo_full_interrupt_25_s">
+         <obj_property name="ElementShortName">fifo_full_interrupt_25_s</obj_property>
+         <obj_property name="ObjectShortName">fifo_full_interrupt_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/data_available_interrupt_25_s">
+         <obj_property name="ElementShortName">data_available_interrupt_25_s</obj_property>
+         <obj_property name="ObjectShortName">data_available_interrupt_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/flush_fifo_25_s">
+         <obj_property name="ElementShortName">flush_fifo_25_s</obj_property>
+         <obj_property name="ObjectShortName">flush_fifo_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/dma_soft_reset_25_s">
+         <obj_property name="ElementShortName">dma_soft_reset_25_s</obj_property>
+         <obj_property name="ObjectShortName">dma_soft_reset_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/reset_global_soft_25_s">
+         <obj_property name="ElementShortName">reset_global_soft_25_s</obj_property>
+         <obj_property name="ObjectShortName">reset_global_soft_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/reset_register_map_25_s">
+         <obj_property name="ElementShortName">reset_register_map_25_s</obj_property>
+         <obj_property name="ObjectShortName">reset_register_map_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/reset_register_map_s">
+         <obj_property name="ElementShortName">reset_register_map_s</obj_property>
+         <obj_property name="ObjectShortName">reset_register_map_s</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/next_current_address_s">
+         <obj_property name="ElementShortName">next_current_address_s[0:1][63:0]</obj_property>
+         <obj_property name="ObjectShortName">next_current_address_s[0:1][63:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u1/last_pc_pointer_s">
+         <obj_property name="ElementShortName">last_pc_pointer_s[0:1][63:0]</obj_property>
+         <obj_property name="ObjectShortName">last_pc_pointer_s[0:1][63:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_enable_written_25_s">
+         <obj_property name="ElementShortName">dma_descriptors_enable_written_25_s</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_enable_written_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/dma_descriptors_enable_written_250_s">
+         <obj_property name="ElementShortName">dma_descriptors_enable_written_250_s</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors_enable_written_250_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/tohost_busy_25_s">
+         <obj_property name="ElementShortName">tohost_busy_25_s</obj_property>
+         <obj_property name="ObjectShortName">tohost_busy_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/fromhost_busy_25_s">
+         <obj_property name="ElementShortName">fromhost_busy_25_s</obj_property>
+         <obj_property name="ObjectShortName">fromhost_busy_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/tohost_busy_latched_25_s">
+         <obj_property name="ElementShortName">tohost_busy_latched_25_s</obj_property>
+         <obj_property name="ObjectShortName">tohost_busy_latched_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/fromhost_busy_latched_25_s">
+         <obj_property name="ElementShortName">fromhost_busy_latched_25_s</obj_property>
+         <obj_property name="ObjectShortName">fromhost_busy_latched_25_s</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u1/mask_data_available_interrupt">
+         <obj_property name="ElementShortName">mask_data_available_interrupt</obj_property>
+         <obj_property name="ObjectShortName">mask_data_available_interrupt</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group162">
+      <obj_property name="label">dma_read_write</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/clk">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_descriptors">
+         <obj_property name="ElementShortName">dma_descriptors[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_descriptors[0:1]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_descriptors[0]">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">[0]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_descriptors[1]">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">[1]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/dma_soft_reset">
+         <obj_property name="ElementShortName">dma_soft_reset</obj_property>
+         <obj_property name="ObjectShortName">dma_soft_reset</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_status">
+         <obj_property name="ElementShortName">dma_status[0:1]</obj_property>
+         <obj_property name="ObjectShortName">dma_status[0:1]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_status[0]">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">[0]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/dma_status[1]">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">[1]</obj_property>
+            <obj_property name="isExpanded"></obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/fromHostFifo_din">
+         <obj_property name="ElementShortName">fromHostFifo_din[255:0]</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_din[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/fromHostFifo_prog_full">
+         <obj_property name="ElementShortName">fromHostFifo_prog_full</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_prog_full</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/fromHostFifo_we">
+         <obj_property name="ElementShortName">fromHostFifo_we</obj_property>
+         <obj_property name="ObjectShortName">fromHostFifo_we</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/m_axis_r_rq">
+         <obj_property name="ElementShortName">m_axis_r_rq</obj_property>
+         <obj_property name="ObjectShortName">m_axis_r_rq</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/m_axis_rq">
+         <obj_property name="ElementShortName">m_axis_rq</obj_property>
+         <obj_property name="ObjectShortName">m_axis_rq</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/reset">
+         <obj_property name="ElementShortName">reset</obj_property>
+         <obj_property name="ObjectShortName">reset</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/s_axis_r_rc">
+         <obj_property name="ElementShortName">s_axis_r_rc</obj_property>
+         <obj_property name="ObjectShortName">s_axis_r_rc</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/s_axis_rc">
+         <obj_property name="ElementShortName">s_axis_rc</obj_property>
+         <obj_property name="ObjectShortName">s_axis_rc</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/toHostFifo_dout">
+         <obj_property name="ElementShortName">toHostFifo_dout[255:0]</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_dout[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/toHostFifo_empty_thresh">
+         <obj_property name="ElementShortName">toHostFifo_empty_thresh[11:0]</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_empty_thresh[11:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/toHostFifo_prog_empty">
+         <obj_property name="ElementShortName">toHostFifo_prog_empty</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_prog_empty</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/toHostFifo_re">
+         <obj_property name="ElementShortName">toHostFifo_re</obj_property>
+         <obj_property name="ObjectShortName">toHostFifo_re</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/dma0/u0/rw_state">
+         <obj_property name="ElementShortName">rw_state</obj_property>
+         <obj_property name="ObjectShortName">rw_state</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/rw_state_slv">
+         <obj_property name="ElementShortName">rw_state_slv[2:0]</obj_property>
+         <obj_property name="ObjectShortName">rw_state_slv[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/dma0/u0/strip_state">
+         <obj_property name="ElementShortName">strip_state</obj_property>
+         <obj_property name="ObjectShortName">strip_state</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/strip_state_slv">
+         <obj_property name="ElementShortName">strip_state_slv[2:0]</obj_property>
+         <obj_property name="ObjectShortName">strip_state_slv[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/current_descriptor">
+         <obj_property name="ElementShortName">current_descriptor</obj_property>
+         <obj_property name="ObjectShortName">current_descriptor</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/downfifo_dout_pipe">
+         <obj_property name="ElementShortName">downfifo_dout_pipe[127:0]</obj_property>
+         <obj_property name="ObjectShortName">downfifo_dout_pipe[127:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/upfifo_din_pipe">
+         <obj_property name="ElementShortName">upfifo_din_pipe[159:0]</obj_property>
+         <obj_property name="ObjectShortName">upfifo_din_pipe[159:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/descriptor_done_s">
+         <obj_property name="ElementShortName">descriptor_done_s[0:1]</obj_property>
+         <obj_property name="ObjectShortName">descriptor_done_s[0:1]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/s_axis_rc_tlast_pipe">
+         <obj_property name="ElementShortName">s_axis_rc_tlast_pipe</obj_property>
+         <obj_property name="ObjectShortName">s_axis_rc_tlast_pipe</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/dma0/u0/s_axis_rc_tvalid_pipe">
+         <obj_property name="ElementShortName">s_axis_rc_tvalid_pipe</obj_property>
+         <obj_property name="ObjectShortName">s_axis_rc_tvalid_pipe</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/receive_word_count">
+         <obj_property name="ElementShortName">receive_word_count[10:0]</obj_property>
+         <obj_property name="ObjectShortName">receive_word_count[10:0]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/dma0/u0/active_descriptor_s">
+         <obj_property name="ElementShortName">active_descriptor_s</obj_property>
+         <obj_property name="ObjectShortName">active_descriptor_s</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/current_dword_count_s">
+         <obj_property name="ElementShortName">current_dword_count_s[10:0]</obj_property>
+         <obj_property name="ObjectShortName">current_dword_count_s[10:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/s_m_axis_rq">
+         <obj_property name="ElementShortName">s_m_axis_rq</obj_property>
+         <obj_property name="ObjectShortName">s_m_axis_rq</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/dma0/u0/NUMBER_OF_DESCRIPTORS">
+         <obj_property name="ElementShortName">NUMBER_OF_DESCRIPTORS</obj_property>
+         <obj_property name="ObjectShortName">NUMBER_OF_DESCRIPTORS</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/IDLE_SLV">
+         <obj_property name="ElementShortName">IDLE_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">IDLE_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/START_WRITE_SLV">
+         <obj_property name="ElementShortName">START_WRITE_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">START_WRITE_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/CONT_WRITE_SLV">
+         <obj_property name="ElementShortName">CONT_WRITE_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">CONT_WRITE_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/END_WRITE_SLV">
+         <obj_property name="ElementShortName">END_WRITE_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">END_WRITE_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/START_READ_SLV">
+         <obj_property name="ElementShortName">START_READ_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">START_READ_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/CONT_READ_SLV">
+         <obj_property name="ElementShortName">CONT_READ_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">CONT_READ_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/END_READ_SLV">
+         <obj_property name="ElementShortName">END_READ_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">END_READ_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/PUSH_DATA_SLV">
+         <obj_property name="ElementShortName">PUSH_DATA_SLV[2:0]</obj_property>
+         <obj_property name="ObjectShortName">PUSH_DATA_SLV[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/req_tc">
+         <obj_property name="ElementShortName">req_tc[2:0]</obj_property>
+         <obj_property name="ObjectShortName">req_tc[2:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/dma0/u0/req_attr">
+         <obj_property name="ElementShortName">req_attr[2:0]</obj_property>
+         <obj_property name="ObjectShortName">req_attr[2:0]</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group372">
+      <obj_property name="label">pcie_endpoint</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/clk">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/m_axis_cq">
+         <obj_property name="ElementShortName">m_axis_cq</obj_property>
+         <obj_property name="ObjectShortName">m_axis_cq</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/m_axis_r_cq">
+         <obj_property name="ElementShortName">m_axis_r_cq</obj_property>
+         <obj_property name="ObjectShortName">m_axis_r_cq</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/m_axis_r_rc">
+         <obj_property name="ElementShortName">m_axis_r_rc</obj_property>
+         <obj_property name="ObjectShortName">m_axis_r_rc</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/m_axis_rc">
+         <obj_property name="ElementShortName">m_axis_rc</obj_property>
+         <obj_property name="ObjectShortName">m_axis_rc</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/pci_exp_rxn">
+         <obj_property name="ElementShortName">pci_exp_rxn[7:0]</obj_property>
+         <obj_property name="ObjectShortName">pci_exp_rxn[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/pci_exp_rxp">
+         <obj_property name="ElementShortName">pci_exp_rxp[7:0]</obj_property>
+         <obj_property name="ObjectShortName">pci_exp_rxp[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/pci_exp_txn">
+         <obj_property name="ElementShortName">pci_exp_txn[7:0]</obj_property>
+         <obj_property name="ObjectShortName">pci_exp_txn[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/pci_exp_txp">
+         <obj_property name="ElementShortName">pci_exp_txp[7:0]</obj_property>
+         <obj_property name="ObjectShortName">pci_exp_txp[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/reset">
+         <obj_property name="ElementShortName">reset</obj_property>
+         <obj_property name="ObjectShortName">reset</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/s_axis_cc">
+         <obj_property name="ElementShortName">s_axis_cc</obj_property>
+         <obj_property name="ObjectShortName">s_axis_cc</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/s_axis_r_cc">
+         <obj_property name="ElementShortName">s_axis_r_cc</obj_property>
+         <obj_property name="ObjectShortName">s_axis_r_cc</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/s_axis_r_rq">
+         <obj_property name="ElementShortName">s_axis_r_rq</obj_property>
+         <obj_property name="ObjectShortName">s_axis_r_rq</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/s_axis_rq">
+         <obj_property name="ElementShortName">s_axis_rq</obj_property>
+         <obj_property name="ObjectShortName">s_axis_rq</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/sys_clk_n">
+         <obj_property name="ElementShortName">sys_clk_n</obj_property>
+         <obj_property name="ObjectShortName">sys_clk_n</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/sys_clk_p">
+         <obj_property name="ElementShortName">sys_clk_p</obj_property>
+         <obj_property name="ObjectShortName">sys_clk_p</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/sys_rst_n">
+         <obj_property name="ElementShortName">sys_rst_n</obj_property>
+         <obj_property name="ObjectShortName">sys_rst_n</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/user_lnk_up">
+         <obj_property name="ElementShortName">user_lnk_up</obj_property>
+         <obj_property name="ObjectShortName">user_lnk_up</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/wupper_tb/pcie0/u1/user_clk">
+         <obj_property name="ElementShortName">user_clk</obj_property>
+         <obj_property name="ObjectShortName">user_clk</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/ToHostMem">
+         <obj_property name="ElementShortName">ToHostMem[0:127][255:0]</obj_property>
+         <obj_property name="ObjectShortName">ToHostMem[0:127][255:0]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/FromHostMem">
+         <obj_property name="ElementShortName">FromHostMem[0:127][255:0]</obj_property>
+         <obj_property name="ObjectShortName">FromHostMem[0:127][255:0]</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/u1/CARD_TYPE">
+         <obj_property name="ElementShortName">CARD_TYPE</obj_property>
+         <obj_property name="ObjectShortName">CARD_TYPE</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/DEVID">
+         <obj_property name="ElementShortName">DEVID[15:0]</obj_property>
+         <obj_property name="ObjectShortName">DEVID[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/wupper_tb/pcie0/u1/user_clk_period">
+         <obj_property name="ElementShortName">user_clk_period</obj_property>
+         <obj_property name="ObjectShortName">user_clk_period</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/BAR0">
+         <obj_property name="ElementShortName">BAR0[31:0]</obj_property>
+         <obj_property name="ObjectShortName">BAR0[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/BAR1">
+         <obj_property name="ElementShortName">BAR1[31:0]</obj_property>
+         <obj_property name="ObjectShortName">BAR1[31:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/wupper_tb/pcie0/u1/BAR2">
+         <obj_property name="ElementShortName">BAR2[31:0]</obj_property>
+         <obj_property name="ObjectShortName">BAR2[31:0]</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/sources/FelixTop/felix_fullmode_top.vhd b/sources/FelixTop/felix_fullmode_top.vhd
index bd1f454bd246f8c4e5c9fe7b87ba9fe424aeaf9c..1ec487e3dadba72de27ce5bce5316a0cf6dc5b50 100644
--- a/sources/FelixTop/felix_fullmode_top.vhd
+++ b/sources/FelixTop/felix_fullmode_top.vhd
@@ -74,7 +74,6 @@ entity felix_fullmode_top is
     crInternalLoopbackMode         : boolean := false;
     TTC_test_mode                  : boolean := false;
     generateTTCemu                 : boolean := false;
-    REG_MAP_VERSION                : std_logic_vector(15 downto 0) := X"0300";
     useToHostGBTdataEmulator       : boolean := true;
     COMMIT_DATETIME                : std_logic_vector(39 downto 0) := x"0000FE71CE";
     GIT_HASH                       : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
@@ -697,7 +696,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7038",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
diff --git a/sources/FelixTop/felix_fullmode_top_bnl711.vhd b/sources/FelixTop/felix_fullmode_top_bnl711.vhd
index 37d05a193836434063f0a543e6dc1746fb59c352..c46dc531439d50a0e7efebea8149490160d819e0 100644
--- a/sources/FelixTop/felix_fullmode_top_bnl711.vhd
+++ b/sources/FelixTop/felix_fullmode_top_bnl711.vhd
@@ -77,7 +77,6 @@ entity felix_fullmode_top_bnl711 is
     crInternalLoopbackMode         : boolean := false;
     TTC_test_mode                  : boolean := false;
     generateTTCemu                 : boolean := false;
-    REG_MAP_VERSION                : std_logic_vector(15 downto 0) := X"0300";
     GIT_HASH                       : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     COMMIT_DATETIME                : std_logic_vector(39 downto 0) := x"0000FE71CE";
     STATIC_CENTRALROUTER           : boolean := false; -- removes update process from central router register map, only initial constant values are used
@@ -814,7 +813,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7038",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
@@ -1056,7 +1054,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7039",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
diff --git a/sources/FelixTop/felix_top.vhd b/sources/FelixTop/felix_top.vhd
index a834cd60e350030301cc214d43071a3e4e4c25df..0780018dea20d130cbc121aee58622a11b741dea 100644
--- a/sources/FelixTop/felix_top.vhd
+++ b/sources/FelixTop/felix_top.vhd
@@ -77,7 +77,6 @@ entity felix_top is
     crInternalLoopbackMode          : boolean := false;
     TTC_test_mode                   : boolean := false;
     generateTTCemu                  : boolean := false;
-    REG_MAP_VERSION                 : std_logic_vector(15 downto 0) := X"0300";
     useToHostGBTdataEmulator        : boolean := true;
     COMMIT_DATETIME                 : std_logic_vector(39 downto 0) := x"0000FE71CE";
     GIT_HASH                        : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
@@ -805,7 +804,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7038",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
diff --git a/sources/FelixTop/felix_top_bnl711.vhd b/sources/FelixTop/felix_top_bnl711.vhd
index 9a4167e1d7ce55e051de41cc86f17baffeb74ac5..027e4359d5d818ccdde362a146a306ec5f6436b6 100644
--- a/sources/FelixTop/felix_top_bnl711.vhd
+++ b/sources/FelixTop/felix_top_bnl711.vhd
@@ -77,7 +77,6 @@ entity felix_top_bnl711 is
     crInternalLoopbackMode          : boolean := false;
     TTC_test_mode                   : boolean := false;
     generateTTCemu                  : boolean := false;
-    REG_MAP_VERSION                 : std_logic_vector(15 downto 0) := X"0300";
     GIT_HASH                        : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     COMMIT_DATETIME                 : std_logic_vector(39 downto 0) := x"0000FE71CE";
     STATIC_CENTRALROUTER            : boolean := false; -- removes update process from central router register map, only initial constant values are used
@@ -990,7 +989,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7038",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
@@ -1467,7 +1465,6 @@ begin
       BUILD_DATETIME        => BUILD_DATETIME,
       SVN_VERSION           => SVN_VERSION,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       DEVID                 => x"7039",
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
diff --git a/sources/pcie/dma_read_write.vhd b/sources/pcie/dma_read_write.vhd
index 9f68ac642f0e5aba8275fb4f2aa3f2b940fe04d7..3a3451d79c4b1a93a9f2b00d95c96596553087a2 100644
--- a/sources/pcie/dma_read_write.vhd
+++ b/sources/pcie/dma_read_write.vhd
@@ -117,7 +117,7 @@ architecture rtl of dma_read_write is
   signal current_dword_count_s: std_logic_vector(10 downto 0);
   
   signal s_m_axis_rq : axis_type;
-
+  signal evencycle_dma_s: std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
   
 begin
 
@@ -161,6 +161,8 @@ begin
   add_header: process(clk, reset, dma_soft_reset)
     variable next_active_descriptor_v: integer range 0 to (NUMBER_OF_DESCRIPTORS-1);
     variable read_idle_counter: integer range 0 to 255;
+    variable dma_wait: std_logic;
+    variable evencycle_dma_v: std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
   begin
     if(rising_edge(clk)) then
       if(reset = '1') or (dma_soft_reset = '1') then
@@ -172,9 +174,10 @@ begin
                                   current_address   => (others => '0'),
                                   end_address       => (others => '0'),
                                   wrap_around       => '0',
-                                  evencycle_dma     => '0',
                                   evencycle_pc      => '0',
-                                  pc_pointer        => (others => '0'));
+                                  pc_pointer        => (others => '0'),
+                                  address_wrapped   => '0');
+        evencycle_dma_v := (others => '0');
         active_descriptor_s <= 0;
         current_dword_count_s <= "00001000000"; --256 bytes
         for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
@@ -197,9 +200,18 @@ begin
         end if;
         
         for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-            descriptor_done_s(i) <= '0'; --clear done flag, controller may load a new descriptor
+          descriptor_done_s(i) <= '0'; --clear done flag, controller may load a new descriptor
+          if (dma_descriptors(i).enable = '1' ) then
+            if (dma_descriptors(i).address_wrapped = '1' ) then
+              evencycle_dma_v(i) := not evencycle_dma_s(i);
+            end if;
+          else
+            evencycle_dma_v(i) := '0';
+          end if;
+          evencycle_dma_s(i) <= evencycle_dma_v(i);
         end loop;
         for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
+        
           next_active_descriptor_v := active_descriptor_s;
           if((i /= active_descriptor_s) and (dma_descriptors(i).enable='1')) then
             if(((dma_descriptors(i).read_not_write = '0') and (toHostFifo_prog_empty = '0'))) then
@@ -211,21 +223,32 @@ begin
               exit;
             end if;
           end if;
+          
         end loop;
         case(rw_state) is
           when IDLE =>
+            
             rw_state_slv <= IDLE_SLV;
             current_descriptor <= dma_descriptors(active_descriptor_s);
             if(dma_descriptors(active_descriptor_s).read_not_write = '0' and dma_descriptors(active_descriptor_s).dword_count>0) then
                 current_dword_count_s <= dma_descriptors(active_descriptor_s).dword_count; --assign dword count to a signal to calculate the prog_empty threshold.
             end if;
             active_descriptor_s <= next_active_descriptor_v;
-            if((m_axis_r_rq.tready = '1') and (dma_descriptors(active_descriptor_s).enable = '1')) then
+            if(dma_descriptors(active_descriptor_s).wrap_around = '1' and (evencycle_dma_v(active_descriptor_s) xor dma_descriptors(active_descriptor_s).read_not_write) /= dma_descriptors(active_descriptor_s).evencycle_pc) then
+              if(dma_descriptors(active_descriptor_s).current_address=dma_descriptors(active_descriptor_s).pc_pointer) then
+                dma_wait := '1'; --the PC is not ready to accept data, so we have to wait. dma_wait will clear the enable flag of the descriptors towards dma_read_write
+              else
+                dma_wait := '0'; 
+              end if;
+            else
+                dma_wait := '0';
+            end if;
+            if((m_axis_r_rq.tready = '1') and (dma_descriptors(active_descriptor_s).enable = '1') and dma_wait = '0') then
               if(((dma_descriptors(active_descriptor_s).read_not_write = '0') and (toHostFifo_prog_empty = '0'))) then
                 rw_state <= START_WRITE;
                 descriptor_done_s(active_descriptor_s) <= '1'; --pulse only once
               end if;
-              if(((dma_descriptors(active_descriptor_s).read_not_write = '1') and (fromHostFifo_prog_full = '0')) and (read_idle_counter = 0)) then
+              if(((dma_descriptors(active_descriptor_s).read_not_write = '1') and (fromHostFifo_prog_full = '0')) and (read_idle_counter = 0) and dma_wait = '0') then
                 rw_state <= START_READ;
                 descriptor_done_s(active_descriptor_s) <= '1'; --pulse only once
               end if;
@@ -358,6 +381,7 @@ begin
 
   g0: for i in 0 to (NUMBER_OF_DESCRIPTORS-1) generate
     dma_status(i).descriptor_done <= descriptor_done_s(i);
+    dma_status(i).evencycle_dma <= evencycle_dma_s(i);
   end generate;
    
 
diff --git a/sources/pcie/wupper.vhd b/sources/pcie/wupper.vhd
index cde0b63cf17ae9fc6d8216f1d19fe441fdc9ab09..04fd556c911a0d0129da1756f4a20964498944d4 100644
--- a/sources/pcie/wupper.vhd
+++ b/sources/pcie/wupper.vhd
@@ -63,7 +63,6 @@ entity wupper is
     BUILD_DATETIME        : std_logic_vector(39 downto 0) := x"0000FE71CE";
     SVN_VERSION           : integer := 0;
     CARD_TYPE             : integer := 710;
-    REG_MAP_VERSION       : std_logic_vector(15 downto 0) := X"0300";
     DEVID                 : std_logic_vector(15 downto 0) := x"7038";
     GIT_HASH              : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     COMMIT_DATETIME       : std_logic_vector(39 downto 0) := x"0000FE71CE";
@@ -201,7 +200,6 @@ architecture structure of wupper is
       SVN_VERSION           : integer := 0;
       BUILD_DATETIME        : std_logic_vector(39 downto 0) := x"0000FE71CE";
       CARD_TYPE             : integer := 710;
-      REG_MAP_VERSION       : std_logic_vector(15 downto 0) := X"0300";
       GIT_HASH              : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
       COMMIT_DATETIME       : std_logic_vector(39 downto 0) := x"0000FE71CE";
       GIT_TAG               : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
@@ -360,7 +358,6 @@ begin
       SVN_VERSION           => SVN_VERSION,
       BUILD_DATETIME        => BUILD_DATETIME,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
       GIT_TAG               => GIT_TAG,
diff --git a/sources/pcie/wupper_core.vhd b/sources/pcie/wupper_core.vhd
index 98b71f05649ce6f39cf89c1f00b9672db1019a3c..d5b96e325b2d74ffc93dbab35b66a2698261cc7d 100644
--- a/sources/pcie/wupper_core.vhd
+++ b/sources/pcie/wupper_core.vhd
@@ -63,7 +63,6 @@ entity wupper_core is
     SVN_VERSION           : integer := 0;
     BUILD_DATETIME        : std_logic_vector(39 downto 0) := x"0000FE71CE";
     CARD_TYPE             : integer := 710;
-    REG_MAP_VERSION       : std_logic_vector(15 downto 0) := X"0300";
     GIT_HASH              : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     COMMIT_DATETIME       : std_logic_vector(39 downto 0) := x"0000FE71CE";
     GIT_TAG               : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
@@ -145,7 +144,6 @@ architecture structure of wupper_core is
       SVN_VERSION           : integer := 0;
       BUILD_DATETIME        : std_logic_vector(39 downto 0) := x"0000FE71CE";
       CARD_TYPE             : integer := 710;
-      REG_MAP_VERSION       : std_logic_vector(15 downto 0) := x"0340";
       GIT_HASH              : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
       COMMIT_DATETIME       : std_logic_vector(39 downto 0) := x"0000FE71CE";
       GIT_TAG               : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
@@ -214,7 +212,6 @@ begin
       SVN_VERSION           => SVN_VERSION,
       BUILD_DATETIME        => BUILD_DATETIME,
       CARD_TYPE             => CARD_TYPE,
-      REG_MAP_VERSION       => REG_MAP_VERSION,
       GIT_HASH              => GIT_HASH,
       COMMIT_DATETIME       => COMMIT_DATETIME,
       GIT_TAG               => GIT_TAG,
diff --git a/sources/templates/build-doc.sh b/sources/templates/build-doc.sh
index 43ea55de17bb7db6036162ed45cd495db029a2df..df086b20ef2b790c29244113b8a83d8d1b4b546d 100755
--- a/sources/templates/build-doc.sh
+++ b/sources/templates/build-doc.sh
@@ -1,7 +1,7 @@
 #!/bin/sh -e
 
 wuppercodegen=../../../software/wuppercodegen/wuppercodegen/cli.py
-registers=registers-4.6.yaml
+registers=registers-4.7.yaml
 $wuppercodegen --version
 $wuppercodegen $registers registermap.tex.template registermap.tex
 latex registers.tex
diff --git a/sources/templates/build.sh b/sources/templates/build.sh
index d55885ff2a31b8a1f07f58f7c4de789d0dbc795f..d10e0429321f83a9d54687a50f8eef97cc5e53f2 100755
--- a/sources/templates/build.sh
+++ b/sources/templates/build.sh
@@ -3,9 +3,9 @@
 #
 # Script to rebuild the derived files from templates
 #
-prev_version=4.5
-current_version=4.6
-next_version=4.6
+prev_version=4.6
+current_version=4.7
+next_version=4.7
 
 #
 # firmware directory:
@@ -27,8 +27,8 @@ $wuppercodegen --version
 echo "Previous version: $prev_version"
 echo "Current  version: $current_version"
 echo "Next     version: $next_version"
-echo "Generating version.txt, pcie_package.vhd and dma_control.vhd for current version..."
-$wuppercodegen $current_registers $template_dir/version.txt.template $template_dir/version.txt
+echo "Generating pcie_package.vhd and dma_control.vhd for current version..."
+#$wuppercodegen $current_registers $template_dir/version.txt.template $template_dir/version.txt
 $wuppercodegen $current_registers $template_dir/pcie_package.vhd.template $template_dir/pcie_package.vhd
 $wuppercodegen $current_registers $template_dir/dma_control.vhd.template $template_dir/dma_control.vhd
 echo "Generating html documentation for previous, current and next version..."
diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd
index a1ad43c8def0d0e50872fe18ed30326289a8e121..cb791e022c240736f70e1bb6420473c1522e3972 100644
--- a/sources/templates/dma_control.vhd
+++ b/sources/templates/dma_control.vhd
@@ -6,11 +6,11 @@
 -- DO NOT EDIT THIS FILE
 -- 
 -- This file was generated from template '../../sources/templates/dma_control.vhd.template'
--- and register map ../../sources/templates/registers-4.6.yaml, version 4.6
+-- and register map ../../sources/templates/registers-4.7.yaml, version 4.7
 -- by the script 'wuppercodegen', version: 0.8.0,
 -- using the following commandline:
 -- 
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.6.yaml ../../sources/templates/dma_control.vhd.template ../../sources/templates/dma_control.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.7.yaml ../../sources/templates/dma_control.vhd.template ../../sources/templates/dma_control.vhd
 -- 
 -- Please do NOT edit this file, but edit the source file at '../../sources/templates/dma_control.vhd.template'
 -- 
@@ -85,7 +85,6 @@ entity dma_control is
     SVN_VERSION              : integer := 0;
     CARD_TYPE                : integer := 710;
     BUILD_DATETIME           : std_logic_vector(39 downto 0) := x"0000FE71CE";
-    REG_MAP_VERSION          : std_logic_vector(15 downto 0) := x"0340";
     GIT_HASH                 : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     GIT_TAG                  : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
     GIT_COMMIT_NUMBER        : integer := 0;
@@ -214,21 +213,22 @@ architecture rtl of dma_control is
   signal read_interrupt_250_s             : std_logic;
   type slv64_arr is array(0 to (NUMBER_OF_DESCRIPTORS -1)) of std_logic_vector(63 downto 0);
   signal next_current_address_s           : slv64_arr;
-  signal last_current_address_s           : slv64_arr;
   signal last_pc_pointer_s                : slv64_arr;
 
-  signal dma_wait                         : std_logic_vector(0 to (NUMBER_OF_DESCRIPTORS-1));
   signal tohost_pfull_threshold_assert_s         : std_logic_vector(11 downto 0);
   signal tohost_pfull_threshold_negate_s         : std_logic_vector(11 downto 0);
   signal fromhost_pfull_threshold_assert_s         : std_logic_vector(8 downto 0);
   signal fromhost_pfull_threshold_negate_s         : std_logic_vector(8 downto 0);
   signal dma_descriptors_enable_written_25_s, dma_descriptors_enable_written_250_s: std_logic;
-  signal busy_threshold_assert, busy_threshold_assert_25_s       : std_logic_vector(63 downto 0);
-  signal busy_threshold_negate, busy_threshold_negate_25_s       : std_logic_vector(63 downto 0);
-  signal tohost_busy_250_s, fromhost_busy_250_s            : std_logic;
+  signal busy_threshold_assert       : std_logic_vector(63 downto 0);
+  signal busy_threshold_negate       : std_logic_vector(63 downto 0);
   signal tohost_busy_25_s, fromhost_busy_25_s              : std_logic;
   signal tohost_busy_latched_25_s, fromhost_busy_latched_25_s : std_logic;
   signal mask_data_available_interrupt: std_logic;
+  
+  constant PC_PTR_GAP_C : std_logic_vector(63 downto 0) := x"0000_0000_0100_0000";
+  signal pc_ptr_gap_25_s, pc_ptr_gap_250_s: std_logic_vector(63 downto 0); 
+  
 begin
 
   tohost_pfull_threshold_assert <= tohost_pfull_threshold_assert_s;
@@ -242,8 +242,9 @@ begin
   pipe_descriptors: process(clk, dma_descriptors_s)
   begin
     for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-      dma_descriptors(i).enable          <= dma_descriptors_s(i).enable and not dma_wait(i);
+      dma_descriptors(i).enable          <= dma_descriptors_s(i).enable;
       dma_descriptors(i).current_address <= dma_descriptors_s(i).current_address;
+      dma_descriptors(i).address_wrapped <= dma_descriptors_s(i).address_wrapped;
     end loop;
     if(rising_edge(clk)) then
 
@@ -254,30 +255,11 @@ begin
         dma_descriptors(i).read_not_write <= dma_descriptors_s(i).read_not_write;
         dma_descriptors(i).wrap_around    <= dma_descriptors_s(i).wrap_around;
         dma_descriptors(i).pc_pointer     <= dma_descriptors_s(i).pc_pointer;
-        dma_descriptors(i).evencycle_dma  <= dma_descriptors_s(i).evencycle_dma;
         dma_descriptors(i).evencycle_pc   <= dma_descriptors_s(i).evencycle_pc;
-
       end loop;
     end if;
   end process;
 
-
-dma_wait_proc: process(dma_descriptors_s, last_pc_pointer_s)
-begin
-  for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
-    --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
-    if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
-      if(dma_descriptors_s(i).current_address<last_pc_pointer_s(i)) then
-        dma_wait(i) <= '0';
-      else
-        dma_wait(i) <= '1'; --the PC is not ready to accept data, so we have to wait. dma_wait will clear the enable flag of the descriptors towards dma_read_write
-      end if;
-    else
-        dma_wait(i) <= '0';
-    end if;
-  end loop;
-end process;
-
   comp: process(clk, reset)
     variable request_type_v         : std_logic_vector(3 downto 0);
     variable poisoned_completion_v  : std_logic;
@@ -289,12 +271,17 @@ end process;
     variable dma_descriptors_enable_written_250_v : std_logic;
     variable tohost_busy_v          : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
     variable fromhost_busy_v        : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable evencycle_dma_v        : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable evencycle_pc_v         : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable current_address_v      : slv64_arr;
   begin
     if(reset = '1') then
       for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-        dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_dma => '0',   evencycle_pc  => '0',   pc_pointer    => (others => '0'));
+        dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_pc  => '0',   pc_pointer    => (others => '0'), address_wrapped => '0');
         read_interrupt_250_s <= '0';
         write_interrupt_250_s <= '0';
+        evencycle_dma_v(i) := '0';
+        evencycle_pc_v(i) := '0';
       end loop;
     else
       if(rising_edge(clk)) then
@@ -348,55 +335,23 @@ end process;
           dma_descriptors_s(i).pc_pointer      <= dma_descriptors_w_250_s(i).pc_pointer;
           dma_descriptors_s(i).wrap_around     <= dma_descriptors_w_250_s(i).wrap_around;
           
-          last_current_address_s(i) <= dma_descriptors_s(i).current_address;
-
-
           last_pc_pointer_s(i) <= dma_descriptors_s(i).pc_pointer;
 
 
           next_current_address_s(i) <= (dma_descriptors_s(i).current_address + (dma_descriptors_s(i).dword_count&"00"));
-          
-          --Create a a busy signal if the pc pointer comes too close to the current address.
-          --First check tohost busy 
-          if(dma_descriptors_s(i).wrap_around = '1' and dma_descriptors_s(i).read_not_write = '0' and dma_descriptors_s(i).enable = '1') then
-          --ToHost direction, so the nex_current_address has to be < last_pc_pointer_s
-            if((last_pc_pointer_s(i) - next_current_address_s(i)) < busy_threshold_assert) then
-                tohost_busy_v(i) := '1';
-            end if;
-            if(tohost_busy_v(i) = '1' and ((last_pc_pointer_s(i) - next_current_address_s(i)) > busy_threshold_negate)) then
-                tohost_busy_v(i) := '0';
-            end if;
-          else
-            tohost_busy_v(i) := '0';
-          end if;
-          --Then check fromhost busy 
-          if(dma_descriptors_s(i).wrap_around = '1' and dma_descriptors_s(i).read_not_write = '1' and dma_descriptors_s(i).enable = '1') then
-          --FromHost direction, so the nex_current_address has to be > last_pc_pointer_s
-            if((next_current_address_s(i) - last_pc_pointer_s(i)) < busy_threshold_assert) then
-                fromhost_busy_v(i) := '1';
-            end if;
-            if(fromhost_busy_v(i) = '1' and ((next_current_address_s(i) - last_pc_pointer_s(i)) > busy_threshold_negate)) then
-                fromhost_busy_v(i) := '0';
-            end if;
-          else
-            fromhost_busy_v(i) := '0';
-          end if;
-
+          dma_descriptors_s(i).address_wrapped <= '0';
           if(dma_descriptors_s(i).enable = '1') then
-            if(last_pc_pointer_s(i) > dma_descriptors_s(i).pc_pointer + x"0000_0000_1000_000") then --If the current pc_pointer is 16MB smaller than the last one, we change cycles.
-              dma_descriptors_s(i).evencycle_pc <= not dma_descriptors_s(i).evencycle_pc; --Toggle on wrap around
+            if(last_pc_pointer_s(i) > dma_descriptors_s(i).pc_pointer + pc_ptr_gap_250_s) then --If the current pc_pointer is 16MB smaller than the last one, we change cycles. The 16MB can be changed in the register PC_PTR_GAP (bar0).
+              evencycle_pc_v(i) := not dma_descriptors_s(i).evencycle_pc; --Toggle on wrap around
+
             end if;
             if(dma_status_s(i).descriptor_done = '1') then
               --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
-              if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
-                --if(next_current_address_s(i)<last_pc_pointer_s(i)) then
-                  dma_descriptors_s(i).current_address <= next_current_address_s(i);
-                --else
-                --  dma_descriptors_s(i).current_address <= dma_descriptors_s(i).current_address;
-                --end if;
+              if(dma_descriptors_s(i).wrap_around = '1' and ((dma_status_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
+                current_address_v(i) := next_current_address_s(i);          
               else
                 if(next_current_address_s(i)<dma_descriptors_s(i).end_address) then
-                  dma_descriptors_s(i).current_address <= next_current_address_s(i);
+                  current_address_v(i) := next_current_address_s(i);
                 else
                   dma_descriptors_s(i).enable <= dma_descriptors_s(i).wrap_around;
                   if(dma_descriptors_s(i).read_not_write='1') then
@@ -409,38 +364,30 @@ end process;
               --When wrapping around, regardless of the cycle, when the end address has been reached, the current address must be reset to start_address.
               if(next_current_address_s(i)=dma_descriptors_s(i).end_address) then
                 if(dma_descriptors_s(i).wrap_around = '1') then
-                  dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
-                  dma_descriptors_s(i).evencycle_dma <= not dma_descriptors_s(i).evencycle_dma; --Toggle on wrap around
+                  current_address_v(i) := dma_descriptors_s(i).start_address;
+                  dma_descriptors_s(i).address_wrapped <= '1';
+                  --evencycle_dma_v(i) := not dma_descriptors_s(i).evencycle_dma; --Toggle on wrap around
                 end if;
               end if;
             end if;
           else
-            dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
-            dma_descriptors_s(i).evencycle_pc <= '0';
-            dma_descriptors_s(i).evencycle_dma <= '0';
+            current_address_v(i) := dma_descriptors_s(i).start_address;
+            evencycle_pc_v(i) := '0';
+            --evencycle_dma_v(i) := '0';
+
           end if;
-          
+          --dma_descriptors_s(i).evencycle_dma <= evencycle_dma_v(i);
+          dma_descriptors_s(i).evencycle_pc <= evencycle_pc_v(i);
+          dma_descriptors_s(i).current_address <= current_address_v(i);
           if ( dma_descriptors_enable_written_250_s = '1' and dma_descriptors_enable_written_250_v = '0') then  --only write when the ENABLE register is actually accessed, else it can be cleared some lines below when DMA finished.
             dma_descriptors_s(i).enable <= dma_descriptors_w_250_s(i).enable; 
           end if;
-          
+          --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
+
+              
                     
         end loop;
         
-        if(tohost_busy_v /= std_logic_vector(to_unsigned(0, tohost_busy_v'length))) then
-            tohost_busy_250_s <= '1';
-        else
-            tohost_busy_250_s <= '0';
-        end if;
-        
-        if(fromhost_busy_v/= std_logic_vector(to_unsigned(0, fromhost_busy_v'length))) then
-            fromhost_busy_250_s <= '1';
-        else
-            fromhost_busy_250_s <= '0';
-        end if;
-        
-        
-        
         dma_descriptors_enable_written_250_v := dma_descriptors_enable_written_250_s;
 
         case (completer_state) is
@@ -701,9 +648,6 @@ end process;
       read_interrupt_25_s <= read_interrupt_250_s;
       write_interrupt_25_s <= write_interrupt_250_s;
       
-      fromhost_busy_25_s <= fromhost_busy_250_s;
-      tohost_busy_25_s   <= tohost_busy_250_s;
-
       if(fifo_full_interrupt_v(2 downto 1) = "01") then --rising edge detected on full flag
         fifo_full_interrupt_25_s <= '1';
       else
@@ -749,8 +693,6 @@ end process;
     variable read_interrupt_25_pipe_v : std_logic;
     variable cnt10: integer range 0 to 15;
     variable dma_descriptors_enable_written_v: std_logic;
-    variable busy_threshold_assert_v             : std_logic_vector(63 downto 0);
-    variable busy_threshold_negate_v             : std_logic_vector(63 downto 0);
   begin
     if(rising_edge(clk)) then
       register_write_done_250_s <= register_write_done2_v;
@@ -775,11 +717,7 @@ end process;
       flush_fifo_v          := flush_fifo_25_s;
       dma_soft_reset_v      := dma_soft_reset_25_s;
       
-      busy_threshold_assert        <= busy_threshold_assert_v;
-      busy_threshold_assert_v      := busy_threshold_assert_25_s;
-      
-      busy_threshold_negate        <= busy_threshold_negate_v;
-      busy_threshold_negate_v      := busy_threshold_negate_25_s;
+      pc_ptr_gap_250_s <= pc_ptr_gap_25_s;
       
       -- dma_status and dma_descriptor can be changing fast, so only update at rising edge 
       -- of regmap_clk, then synchronize to regmap_clk
@@ -808,9 +746,57 @@ end process;
   register_map_monitor_s <= register_map_monitor;
   register_map_control   <= register_map_control_s;
 
+dma_busy_proc: process(regmap_clk)
+  variable tohost_busy_v, fromhost_busy_v: std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+begin
+  if rising_edge(regmap_clk) then
+    for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
+      --Create a a busy signal if the pc pointer comes too close to the current address.
+      --First check tohost busy 
+      if(dma_descriptors_25_w_s(i).wrap_around = '1' and dma_descriptors_25_w_s(i).read_not_write = '0' and dma_descriptors_25_w_s(i).enable = '1') then
+        --ToHost direction, so the current_address has to be < pc_pointer
+        if((dma_descriptors_25_w_s(i).pc_pointer - dma_descriptors_25_r_s(i).current_address) < busy_threshold_assert) then
+          tohost_busy_v(i) := '1';
+        end if;
+        if(tohost_busy_v(i) = '1' and ((dma_descriptors_25_w_s(i).pc_pointer  - dma_descriptors_25_r_s(i).current_address) > busy_threshold_negate)) then
+          tohost_busy_v(i) := '0';
+        end if;
+      else
+        tohost_busy_v(i) := '0';
+      end if;
+      --Then check fromhost busy 
+      if(dma_descriptors_25_w_s(i).wrap_around = '1' and dma_descriptors_25_w_s(i).read_not_write = '1' and dma_descriptors_25_w_s(i).enable = '1') then
+        --FromHost direction, so the current_address has to be > pc_pointer
+        if((dma_descriptors_25_r_s(i).current_address - dma_descriptors_25_w_s(i).pc_pointer ) < busy_threshold_assert) then
+          fromhost_busy_v(i) := '1';
+        end if;
+        if(fromhost_busy_v(i) = '1' and ((dma_descriptors_25_r_s(i).current_address - dma_descriptors_25_w_s(i).pc_pointer) > busy_threshold_negate)) then
+          fromhost_busy_v(i) := '0';
+        end if;
+      else
+        fromhost_busy_v(i) := '0';
+      end if;
+    end loop;
+    
+    if(tohost_busy_v /= std_logic_vector(to_unsigned(0, tohost_busy_v'length))) then
+      tohost_busy_25_s <= '1';
+    else
+      tohost_busy_25_s <= '0';
+    end if;
+    
+    if(fromhost_busy_v/= std_logic_vector(to_unsigned(0, fromhost_busy_v'length))) then
+      fromhost_busy_25_s <= '1';
+    else
+      fromhost_busy_25_s <= '0';
+    end if;
+  end if;
+end process;
+
+
   regrw: process(regmap_clk)
     variable register_write_data_25_v: std_logic_vector(127 downto 0);
-
+    variable register_read_address_v: std_logic_vector(19 downto 0);
+    variable register_write_address_v: std_logic_vector(19 downto 0);
   begin
     if(rising_edge(regmap_clk)) then
         if(reset = '1' or reset_register_map_25_s='1') then
@@ -819,7 +805,7 @@ end process;
           register_read_data_25_s  <= (others => '0');
           reset_register_map_s <= '0';
           for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-            dma_descriptors_25_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0',  evencycle_dma => '0',   evencycle_pc  => '0',   pc_pointer    => (others => '0'));
+            dma_descriptors_25_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_pc  => '0',   pc_pointer    => (others => '0'), address_wrapped => '0');
           end loop;
           --for i in 0 to (NUMBER_OF_INTERRUPTS-1) loop
           --  int_vector_25_s(i) <= (int_vec_add => (others => '0'), int_vec_data => (others => '0'),int_vec_ctrl => (others => '0') );
@@ -834,9 +820,9 @@ end process;
           tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4050, 12));
           tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(3744, 12));
           
-          busy_threshold_assert_25_s             <= REG_BUSY_THRESH_ASSERT_C;
-          busy_threshold_negate_25_s             <= REG_BUSY_THRESH_NEGATE_C;
-          
+          busy_threshold_assert             <= REG_BUSY_THRESH_ASSERT_C;
+          busy_threshold_negate             <= REG_BUSY_THRESH_NEGATE_C;
+          pc_ptr_gap_25_s                   <= PC_PTR_GAP_C;
           
           --!
           --! generate registers initialization
@@ -6933,6 +6919,7 @@ end process;
                                                                                                         --   0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
                                                                                                         --   
                                                                                                         
+          register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR        <= REG_TTC_DEC_CTRL_BCID_ONBCR_C;           -- BCID is set to this value when BCR arrives
           register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP      <= REG_TTC_DEC_CTRL_ECR_BCR_SWAP_C;         -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
           register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT <= REG_TTC_DEC_CTRL_BUSY_OUTPUT_INHIBIT_C;  -- forces the Busy LEMO output to BUSY-OFF
           register_map_control_s.TTC_DEC_CTRL.TOHOST_RST        <= REG_TTC_DEC_CTRL_TOHOST_RST_C;           -- reset toHost in ttc decoder
@@ -6941,7 +6928,7 @@ end process;
           register_map_control_s.TTC_DEC_CTRL.XL1ID_RST         <= REG_TTC_DEC_CTRL_XL1ID_RST_C;            -- giving a trigger signal to reset XL1ID value
           register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY       <= REG_TTC_DEC_CTRL_MASTER_BUSY_C;          -- L1A trigger throttling
           register_map_control_s.TTC_EMU.SEL                    <= REG_TTC_EMU_SEL_C;                       -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
-          register_map_control_s.TTC_EMU.ENA                    <= REG_TTC_EMU_ENA_C;                       -- Enable TTC data generator (10 bit counter)
+          register_map_control_s.TTC_EMU.ENA                    <= REG_TTC_EMU_ENA_C;                       -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
           register_map_control_s.TTC_DELAY_00                   <= REG_TTC_DELAY_00_C;                      -- Controls the TTC Fanout delay values
           register_map_control_s.TTC_DELAY_01                   <= REG_TTC_DELAY_01_C;                      -- Controls the TTC Fanout delay values
           register_map_control_s.TTC_DELAY_02                   <= REG_TTC_DELAY_02_C;                      -- Controls the TTC Fanout delay values
@@ -6993,6 +6980,18 @@ end process;
           register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE  <= REG_TTC_BUSY_TIMING_CTRL_PRESCALE_C;     -- Prescales the 40MHz clock to create an internal slow clock
           register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= REG_TTC_BUSY_TIMING_CTRL_BUSY_WIDTH_C;   -- Minimum number of 40MHz clocks that the busy is asserted
           register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= REG_TTC_BUSY_TIMING_CTRL_LIMIT_TIME_C;   -- Number of prescaled clocks a given busy must be asserted before it is recognized
+          register_map_control_s.TTC_EMU_CONTROL.LAST_LINE      <= REG_TTC_EMU_CONTROL_LAST_LINE_C;         -- Last line of the sequence
+          register_map_control_s.TTC_EMU_CONTROL.REPEAT         <= REG_TTC_EMU_CONTROL_REPEAT_C;            -- Repeat the sequence
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST5     <= REG_TTC_EMU_CONTROL_BROADCAST5_C;        -- Broadcast 5
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST4     <= REG_TTC_EMU_CONTROL_BROADCAST4_C;        -- Broadcast 4
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST3     <= REG_TTC_EMU_CONTROL_BROADCAST3_C;        -- Broadcast 3
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST2     <= REG_TTC_EMU_CONTROL_BROADCAST2_C;        -- Broadcast 2
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST1     <= REG_TTC_EMU_CONTROL_BROADCAST1_C;        -- Broadcast 1
+          register_map_control_s.TTC_EMU_CONTROL.BROADCAST0     <= REG_TTC_EMU_CONTROL_BROADCAST0_C;        -- Broadcast 0
+          register_map_control_s.TTC_EMU_CONTROL.ECR            <= REG_TTC_EMU_CONTROL_ECR_C;               -- Event counter reset
+          register_map_control_s.TTC_EMU_CONTROL.BCR            <= REG_TTC_EMU_CONTROL_BCR_C;               -- Bunch counter reset
+          register_map_control_s.TTC_EMU_CONTROL.L1A            <= REG_TTC_EMU_CONTROL_L1A_C;               -- Level 1 Accept
+          register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER   <= REG_TTC_EMU_CONTROL_STEP_COUNTER_C;      -- Step counter value
           register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH11 <= REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH11_C;   -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
           register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH10 <= REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH10_C;   -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
           register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH09 <= REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH09_C;   -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
@@ -8975,6 +8974,7 @@ end process;
           register_map_control_s.CR_BLOCK_COUNT_GBT23.RESET     <= REG_CR_BLOCK_COUNT_GBT23_RESET_C;  -- Any write clears the counter value
       end if;
       register_map_control_s.TTC_BUSY_CLEAR                 <= REG_TTC_BUSY_CLEAR_C;              -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+      register_map_control_s.TTC_EMU_CONTROL.WE             <= REG_TTC_EMU_CONTROL_WE_C;          -- Any write to this register executes a write enable
       register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= REG_XOFF_FM_HIGH_THRESH_CLEAR_LATCH_C; -- Writing this register will clear all CROSS_LATCHED bits
       register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH    <= REG_DMA_BUSY_STATUS_CLEAR_LATCH_C; -- Any write to this register clears TOHOST_BUSY_LATCHED
       register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= REG_FM_BUSY_CHANNEL_STATUS_CLEAR_LATCH_C; -- Any write to this register will clear the BUSY_LATCHED bits
@@ -8996,7 +8996,8 @@ end process;
         register_read_data_25_s  <= (others => '0'); --default value
         --Read registers in BAR0
         if(register_read_address_25_s(31 downto 20) = bar0_25_s(31 downto 20)) then
-          case(register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             when REG_DESCRIPTOR_0  => register_read_data_25_s <= dma_descriptors_25_r_s( 0).end_address&
                                                                  dma_descriptors_25_r_s( 0).start_address;
             when REG_DESCRIPTOR_0a => register_read_data_25_s <= dma_descriptors_25_r_s( 0).pc_pointer&
@@ -9055,42 +9056,42 @@ end process;
                                                                  dma_descriptors_25_r_s( 7).dword_count;
             when REG_STATUS_0      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(0 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(0 ).evencycle_dma&
+                                                                 dma_status_25_s(0 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(0 ).enable)&
                                                                  dma_descriptors_25_r_s(0 ).current_address;
             when REG_STATUS_1      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(1 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(1 ).evencycle_dma&
+                                                                 dma_status_25_s(1 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(1 ).enable)&
                                                                  dma_descriptors_25_r_s(1 ).current_address;
             when REG_STATUS_2      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(2 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(2 ).evencycle_dma&
+                                                                 dma_status_25_s(2 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(2 ).enable)&
                                                                  dma_descriptors_25_r_s(2 ).current_address;
             when REG_STATUS_3      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(3 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(3 ).evencycle_dma&
+                                                                 dma_status_25_s(2 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(3 ).enable)&
                                                                  dma_descriptors_25_r_s(3 ).current_address;
             when REG_STATUS_4      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(4 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(4 ).evencycle_dma&
+                                                                 dma_status_25_s(4 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(4 ).enable)&
                                                                  dma_descriptors_25_r_s(4 ).current_address;
             when REG_STATUS_5      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(5 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(5 ).evencycle_dma&
+                                                                 dma_status_25_s(5 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(5 ).enable)&
                                                                  dma_descriptors_25_r_s(5 ).current_address;
             when REG_STATUS_6      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(6 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(6 ).evencycle_dma&
+                                                                 dma_status_25_s(6 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(6 ).enable)&
                                                                  dma_descriptors_25_r_s(6 ).current_address;
             when REG_STATUS_7      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(7 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(7 ).evencycle_dma&
+                                                                 dma_status_25_s(7 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(7 ).enable)&
                                                                  dma_descriptors_25_r_s(7 ).current_address;
             when REG_BAR0          => register_read_data_25_s     <=  x"000000000000000000000000"&bar0_25_s;
@@ -9110,18 +9111,20 @@ end process;
             when REG_TOHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
                                                                         x"0000_0000_0"&tohost_pfull_threshold_assert_s&
                                                                         x"0"&tohost_pfull_threshold_negate_s;  
-            when REG_BUSY_THRESH_ASSERT   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert_25_s;
-            when REG_BUSY_THRESH_NEGATE   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate_25_s;
+            when REG_BUSY_THRESH_ASSERT   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert;
+            when REG_BUSY_THRESH_NEGATE   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate;
             when REG_BUSY_STATUS          => register_read_data_25_s <= x"0000_0000_0000_0000_0000_0000_0000_000"&"00"&
                                                                                              fromhost_busy_25_s&
                                                                                              tohost_busy_25_s;
+            when REG_PC_PTR_GAP           => register_read_data_25_s <= x"0000_0000_0000_0000"&pc_ptr_gap_25_s;                                                                                             
             when others            => register_read_data_25_s <= (others => '0');
 
 
           end case;
         --Read registers in BAR1
         elsif(register_read_address_25_s(31 downto 20) = bar1_25_s(31 downto 20)) then
-          case (register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             when REG_INT_VEC_00      => register_read_data_25_s(63 downto 0)   <=  int_vector_25_s(0).int_vec_add;
                                         register_read_data_25_s(95 downto 64)  <=  int_vector_25_s(0).int_vec_data;
                                         register_read_data_25_s(127 downto 96) <=  int_vector_25_s(0).int_vec_ctrl;
@@ -9175,7 +9178,8 @@ end process;
           end case;
         --Read registers in BAR2
         elsif(register_read_address_25_s(31 downto 20) = bar2_25_s(31 downto 20)) then
-          case (register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             --!
             --! generated registers read
             ------------------------------------
@@ -13551,7 +13555,8 @@ end process;
                                                                                                                                                         --   0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
                                                                                                                                                         --   
                                                                                                                                                         
-            when REG_TTC_DEC_CTRL                   => register_read_data_25_s(14 downto 14)   <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_CTRL.BUSY_OUTPUT_STATUS; -- Actual status of the BUSY LEMO output signal
+            when REG_TTC_DEC_CTRL                   => register_read_data_25_s(26 downto 15)   <= register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR;       -- BCID is set to this value when BCR arrives
+                                                         register_read_data_25_s(14 downto 14)   <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_CTRL.BUSY_OUTPUT_STATUS; -- Actual status of the BUSY LEMO output signal
                                                        register_read_data_25_s(13 downto 13)   <= register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP;     -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
                                                        register_read_data_25_s(12 downto 12)   <= register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT; -- forces the Busy LEMO output to BUSY-OFF
                                                        register_read_data_25_s(11 downto 11)   <= register_map_control_s.TTC_DEC_CTRL.TOHOST_RST;       -- reset toHost in ttc decoder
@@ -13559,8 +13564,9 @@ end process;
                                                        register_read_data_25_s(9 downto 2)     <= register_map_control_s.TTC_DEC_CTRL.XL1ID_SW;         -- set XL1ID value, the value to be set by XL1ID_RST signal
                                                        register_read_data_25_s(1 downto 1)     <= register_map_control_s.TTC_DEC_CTRL.XL1ID_RST;        -- giving a trigger signal to reset XL1ID value
                                                        register_read_data_25_s(0 downto 0)     <= register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY;      -- L1A trigger throttling
-            when REG_TTC_EMU                        => register_read_data_25_s(1 downto 1)     <= register_map_control_s.TTC_EMU.SEL;                   -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
-                                                       register_read_data_25_s(0 downto 0)     <= register_map_control_s.TTC_EMU.ENA;                   -- Enable TTC data generator (10 bit counter)
+            when REG_TTC_EMU                        => register_read_data_25_s(2 downto 2)     <= register_map_monitor_s.register_map_ttc_monitor.TTC_EMU.FULL;                  -- TTC Emulator memory full indication
+                                                       register_read_data_25_s(1 downto 1)     <= register_map_control_s.TTC_EMU.SEL;                   -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
+                                                       register_read_data_25_s(0 downto 0)     <= register_map_control_s.TTC_EMU.ENA;                   -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
             when REG_TTC_DELAY_00                   => register_read_data_25_s(3 downto 0)     <= register_map_control_s.TTC_DELAY_00;                  -- Controls the TTC Fanout delay values
             when REG_TTC_DELAY_01                   => register_read_data_25_s(3 downto 0)     <= register_map_control_s.TTC_DELAY_01;                  -- Controls the TTC Fanout delay values
             when REG_TTC_DELAY_02                   => register_read_data_25_s(3 downto 0)     <= register_map_control_s.TTC_DELAY_02;                  -- Controls the TTC Fanout delay values
@@ -13613,6 +13619,19 @@ end process;
                                                        register_read_data_25_s(31 downto 16)   <= register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH; -- Minimum number of 40MHz clocks that the busy is asserted
                                                        register_read_data_25_s(15 downto 0)    <= register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME; -- Number of prescaled clocks a given busy must be asserted before it is recognized
             when REG_TTC_BUSY_CLEAR                 => register_read_data_25_s(64 downto 64)   <= register_map_control_s.TTC_BUSY_CLEAR;                -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+            when REG_TTC_EMU_CONTROL                => register_read_data_25_s(64 downto 64)   <= register_map_control_s.TTC_EMU_CONTROL.WE;            -- Any write to this register executes a write enable
+                                                       register_read_data_25_s(35 downto 35)   <= register_map_control_s.TTC_EMU_CONTROL.LAST_LINE;     -- Last line of the sequence
+                                                       register_read_data_25_s(34 downto 34)   <= register_map_control_s.TTC_EMU_CONTROL.REPEAT;        -- Repeat the sequence
+                                                       register_read_data_25_s(32 downto 32)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST5;    -- Broadcast 5
+                                                       register_read_data_25_s(31 downto 31)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST4;    -- Broadcast 4
+                                                       register_read_data_25_s(30 downto 30)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST3;    -- Broadcast 3
+                                                       register_read_data_25_s(29 downto 29)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST2;    -- Broadcast 2
+                                                       register_read_data_25_s(28 downto 28)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST1;    -- Broadcast 1
+                                                       register_read_data_25_s(27 downto 27)   <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST0;    -- Broadcast 0
+                                                       register_read_data_25_s(26 downto 26)   <= register_map_control_s.TTC_EMU_CONTROL.ECR;           -- Event counter reset
+                                                       register_read_data_25_s(25 downto 25)   <= register_map_control_s.TTC_EMU_CONTROL.BCR;           -- Bunch counter reset
+                                                       register_read_data_25_s(24 downto 24)   <= register_map_control_s.TTC_EMU_CONTROL.L1A;           -- Level 1 Accept
+                                                       register_read_data_25_s(21 downto 0)    <= register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER;  -- Step counter value
             when REG_XOFF_FM_CH_FIFO_THRESH_LOW     => register_read_data_25_s(47 downto 44)   <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH11; -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
                                                        register_read_data_25_s(43 downto 40)   <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH10; -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
                                                        register_read_data_25_s(39 downto 36)   <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH09; -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
@@ -14619,7 +14638,7 @@ end process;
 
 
 -- GenericBoardInformation
-              when REG_REG_MAP_VERSION                => register_read_data_25_s(15 downto 0)    <= REG_MAP_VERSION;                                                                  -- Register Map Version, 4.6 formatted as 0x0406
+              when REG_REG_MAP_VERSION                => register_read_data_25_s(15 downto 0)    <= std_logic_vector(to_unsigned(1031,16));                     -- Register Map Version, 4.7 formatted as 0x0407
               when REG_BOARD_ID_TIMESTAMP             => register_read_data_25_s(39 downto 0)    <= BUILD_DATETIME;                                                                   -- Board ID Date / Time in BCD format YYMMDDhhmm
               when REG_BOARD_ID_SVN                   => register_read_data_25_s(15 downto 0)    <= std_logic_vector(to_unsigned(SVN_VERSION,16));                                    -- Board ID SVN Revision
               when REG_GIT_COMMIT_TIME                => register_read_data_25_s(39 downto 0)    <= COMMIT_DATETIME;                                                                  -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
@@ -16272,8 +16291,8 @@ end process;
         register_write_done_25_s <= '1';
         --Write registers in BAR0
         if(register_write_address_25_s(31 downto 20) = bar0_25_s(31 downto 20)) then
-
-          case(register_write_address_25_s(19 downto 4)&"0000") is  --only check 128 bit addressing
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             when REG_DESCRIPTOR_0   =>   dma_descriptors_25_w_s( 0).end_address            <= register_write_data_25_v(127 downto 64);
                                          dma_descriptors_25_w_s( 0).start_address          <= register_write_data_25_v(63 downto 0);
             when REG_DESCRIPTOR_0a  =>   dma_descriptors_25_w_s( 0).pc_pointer             <= register_write_data_25_v(127 downto 64);
@@ -16334,14 +16353,16 @@ end process;
                                              fromhost_pfull_threshold_negate_s <= register_write_data_25_v( 8 downto 0);
             when REG_TOHOST_FULL_THRESH =>   tohost_pfull_threshold_assert_s   <= register_write_data_25_v(27 downto 16);
                                              tohost_pfull_threshold_negate_s   <= register_write_data_25_v(11 downto 0);
-            when REG_BUSY_THRESH_ASSERT   => busy_threshold_assert_25_s <= register_write_data_25_v(63 downto 0);
-            when REG_BUSY_THRESH_NEGATE   => busy_threshold_negate_25_s <= register_write_data_25_v(63 downto 0);
+            when REG_BUSY_THRESH_ASSERT   => busy_threshold_assert <= register_write_data_25_v(63 downto 0);
+            when REG_BUSY_THRESH_NEGATE   => busy_threshold_negate <= register_write_data_25_v(63 downto 0);
+            when REG_PC_PTR_GAP           => pc_ptr_gap_25_s <= register_write_data_25_v(63 downto 0);
             when others => --do nothing
 
           end case;
         --Write registers in BAR1
         elsif(register_write_address_25_s(31 downto 20) = bar1_25_s(31 downto 20)) then
-          case (register_write_address_25_s(19 downto 4)&"0000") is
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             when REG_INT_VEC_00      => int_vector_25_s(0).int_vec_add   <= register_write_data_25_v(63 downto 0);
                                         int_vector_25_s(0).int_vec_data  <= register_write_data_25_v(95 downto 64);
                                         int_vector_25_s(0).int_vec_ctrl  <= register_write_data_25_v(127 downto 96);
@@ -16395,7 +16416,8 @@ end process;
           end case;
         --Write registers in BAR2
         elsif(register_write_address_25_s(31 downto 20) = bar2_25_s(31 downto 20)) then
-          case (register_write_address_25_s(19 downto 4)&"0000") is
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             --!
             --! generated registers write
             -------------------------------------
@@ -20671,7 +20693,8 @@ end process;
                                                                                                                                                          --   0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
                                                                                                                                                          --   
                                                                                                                                                          
-            when REG_TTC_DEC_CTRL                   => register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP      <= register_write_data_25_v(13 downto 13);  -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
+            when REG_TTC_DEC_CTRL                   => register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR        <= register_write_data_25_v(26 downto 15);  -- BCID is set to this value when BCR arrives
+                                                       register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP      <= register_write_data_25_v(13 downto 13);  -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
                                                        register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT <= register_write_data_25_v(12 downto 12);  -- forces the Busy LEMO output to BUSY-OFF
                                                        register_map_control_s.TTC_DEC_CTRL.TOHOST_RST        <= register_write_data_25_v(11 downto 11);  -- reset toHost in ttc decoder
                                                        register_map_control_s.TTC_DEC_CTRL.TT_BCH_EN         <= register_write_data_25_v(10 downto 10);  -- trigger type enable / disable for TTC-ToHost
@@ -20679,7 +20702,7 @@ end process;
                                                        register_map_control_s.TTC_DEC_CTRL.XL1ID_RST         <= register_write_data_25_v(1 downto 1);    -- giving a trigger signal to reset XL1ID value
                                                        register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY       <= register_write_data_25_v(0 downto 0);    -- L1A trigger throttling
             when REG_TTC_EMU                        => register_map_control_s.TTC_EMU.SEL                    <= register_write_data_25_v(1 downto 1);    -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
-                                                       register_map_control_s.TTC_EMU.ENA                    <= register_write_data_25_v(0 downto 0);    -- Enable TTC data generator (10 bit counter)
+                                                       register_map_control_s.TTC_EMU.ENA                    <= register_write_data_25_v(0 downto 0);    -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
             when REG_TTC_DELAY_00                   => register_map_control_s.TTC_DELAY_00                   <= register_write_data_25_v(3 downto 0);    -- Controls the TTC Fanout delay values
             when REG_TTC_DELAY_01                   => register_map_control_s.TTC_DELAY_01                   <= register_write_data_25_v(3 downto 0);    -- Controls the TTC Fanout delay values
             when REG_TTC_DELAY_02                   => register_map_control_s.TTC_DELAY_02                   <= register_write_data_25_v(3 downto 0);    -- Controls the TTC Fanout delay values
@@ -20732,6 +20755,19 @@ end process;
                                                        register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= register_write_data_25_v(31 downto 16);  -- Minimum number of 40MHz clocks that the busy is asserted
                                                        register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= register_write_data_25_v(15 downto 0);   -- Number of prescaled clocks a given busy must be asserted before it is recognized
             when REG_TTC_BUSY_CLEAR                 => register_map_control_s.TTC_BUSY_CLEAR                 <= "1";                                     -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+            when REG_TTC_EMU_CONTROL                => register_map_control_s.TTC_EMU_CONTROL.WE             <= "1";                                     -- Any write to this register executes a write enable
+                                                       register_map_control_s.TTC_EMU_CONTROL.LAST_LINE      <= register_write_data_25_v(35 downto 35);  -- Last line of the sequence
+                                                       register_map_control_s.TTC_EMU_CONTROL.REPEAT         <= register_write_data_25_v(34 downto 34);  -- Repeat the sequence
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST5     <= register_write_data_25_v(32 downto 32);  -- Broadcast 5
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST4     <= register_write_data_25_v(31 downto 31);  -- Broadcast 4
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST3     <= register_write_data_25_v(30 downto 30);  -- Broadcast 3
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST2     <= register_write_data_25_v(29 downto 29);  -- Broadcast 2
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST1     <= register_write_data_25_v(28 downto 28);  -- Broadcast 1
+                                                       register_map_control_s.TTC_EMU_CONTROL.BROADCAST0     <= register_write_data_25_v(27 downto 27);  -- Broadcast 0
+                                                       register_map_control_s.TTC_EMU_CONTROL.ECR            <= register_write_data_25_v(26 downto 26);  -- Event counter reset
+                                                       register_map_control_s.TTC_EMU_CONTROL.BCR            <= register_write_data_25_v(25 downto 25);  -- Bunch counter reset
+                                                       register_map_control_s.TTC_EMU_CONTROL.L1A            <= register_write_data_25_v(24 downto 24);  -- Level 1 Accept
+                                                       register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER   <= register_write_data_25_v(21 downto 0);   -- Step counter value
             when REG_XOFF_FM_CH_FIFO_THRESH_LOW     => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH11 <= register_write_data_25_v(47 downto 44);  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
                                                        register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH10 <= register_write_data_25_v(43 downto 40);  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
                                                        register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW.CH09 <= register_write_data_25_v(39 downto 36);  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
diff --git a/sources/templates/dma_control.vhd.template b/sources/templates/dma_control.vhd.template
index d283c30d3236feeae5096c4bb1f69033eb7354f1..8f4b2550bef582e5319048a1e241830c0f683c62 100644
--- a/sources/templates/dma_control.vhd.template
+++ b/sources/templates/dma_control.vhd.template
@@ -64,7 +64,6 @@ entity dma_control is
     SVN_VERSION              : integer := 0;
     CARD_TYPE                : integer := 710;
     BUILD_DATETIME           : std_logic_vector(39 downto 0) := x"0000FE71CE";
-    REG_MAP_VERSION          : std_logic_vector(15 downto 0) := x"0340";
     GIT_HASH                 : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
     GIT_TAG                  : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
     GIT_COMMIT_NUMBER        : integer := 0;
@@ -193,21 +192,22 @@ architecture rtl of dma_control is
   signal read_interrupt_250_s             : std_logic;
   type slv64_arr is array(0 to (NUMBER_OF_DESCRIPTORS -1)) of std_logic_vector(63 downto 0);
   signal next_current_address_s           : slv64_arr;
-  signal last_current_address_s           : slv64_arr;
   signal last_pc_pointer_s                : slv64_arr;
 
-  signal dma_wait                         : std_logic_vector(0 to (NUMBER_OF_DESCRIPTORS-1));
   signal tohost_pfull_threshold_assert_s         : std_logic_vector(11 downto 0);
   signal tohost_pfull_threshold_negate_s         : std_logic_vector(11 downto 0);
   signal fromhost_pfull_threshold_assert_s         : std_logic_vector(8 downto 0);
   signal fromhost_pfull_threshold_negate_s         : std_logic_vector(8 downto 0);
   signal dma_descriptors_enable_written_25_s, dma_descriptors_enable_written_250_s: std_logic;
-  signal busy_threshold_assert, busy_threshold_assert_25_s       : std_logic_vector(63 downto 0);
-  signal busy_threshold_negate, busy_threshold_negate_25_s       : std_logic_vector(63 downto 0);
-  signal tohost_busy_250_s, fromhost_busy_250_s            : std_logic;
+  signal busy_threshold_assert       : std_logic_vector(63 downto 0);
+  signal busy_threshold_negate       : std_logic_vector(63 downto 0);
   signal tohost_busy_25_s, fromhost_busy_25_s              : std_logic;
   signal tohost_busy_latched_25_s, fromhost_busy_latched_25_s : std_logic;
   signal mask_data_available_interrupt: std_logic;
+  
+  constant PC_PTR_GAP_C : std_logic_vector(63 downto 0) := x"0000_0000_0100_0000";
+  signal pc_ptr_gap_25_s, pc_ptr_gap_250_s: std_logic_vector(63 downto 0); 
+  
 begin
 
   tohost_pfull_threshold_assert <= tohost_pfull_threshold_assert_s;
@@ -221,8 +221,9 @@ begin
   pipe_descriptors: process(clk, dma_descriptors_s)
   begin
     for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-      dma_descriptors(i).enable          <= dma_descriptors_s(i).enable and not dma_wait(i);
+      dma_descriptors(i).enable          <= dma_descriptors_s(i).enable;
       dma_descriptors(i).current_address <= dma_descriptors_s(i).current_address;
+      dma_descriptors(i).address_wrapped <= dma_descriptors_s(i).address_wrapped;
     end loop;
     if(rising_edge(clk)) then
 
@@ -233,30 +234,11 @@ begin
         dma_descriptors(i).read_not_write <= dma_descriptors_s(i).read_not_write;
         dma_descriptors(i).wrap_around    <= dma_descriptors_s(i).wrap_around;
         dma_descriptors(i).pc_pointer     <= dma_descriptors_s(i).pc_pointer;
-        dma_descriptors(i).evencycle_dma  <= dma_descriptors_s(i).evencycle_dma;
         dma_descriptors(i).evencycle_pc   <= dma_descriptors_s(i).evencycle_pc;
-
       end loop;
     end if;
   end process;
 
-
-dma_wait_proc: process(dma_descriptors_s, last_pc_pointer_s)
-begin
-  for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
-    --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
-    if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
-      if(dma_descriptors_s(i).current_address<last_pc_pointer_s(i)) then
-        dma_wait(i) <= '0';
-      else
-        dma_wait(i) <= '1'; --the PC is not ready to accept data, so we have to wait. dma_wait will clear the enable flag of the descriptors towards dma_read_write
-      end if;
-    else
-        dma_wait(i) <= '0';
-    end if;
-  end loop;
-end process;
-
   comp: process(clk, reset)
     variable request_type_v         : std_logic_vector(3 downto 0);
     variable poisoned_completion_v  : std_logic;
@@ -268,12 +250,17 @@ end process;
     variable dma_descriptors_enable_written_250_v : std_logic;
     variable tohost_busy_v          : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
     variable fromhost_busy_v        : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable evencycle_dma_v        : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable evencycle_pc_v         : std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+    variable current_address_v      : slv64_arr;
   begin
     if(reset = '1') then
       for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-        dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_dma => '0',   evencycle_pc  => '0',   pc_pointer    => (others => '0'));
+        dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_pc  => '0',   pc_pointer    => (others => '0'), address_wrapped => '0');
         read_interrupt_250_s <= '0';
         write_interrupt_250_s <= '0';
+        evencycle_dma_v(i) := '0';
+        evencycle_pc_v(i) := '0';
       end loop;
     else
       if(rising_edge(clk)) then
@@ -327,55 +314,23 @@ end process;
           dma_descriptors_s(i).pc_pointer      <= dma_descriptors_w_250_s(i).pc_pointer;
           dma_descriptors_s(i).wrap_around     <= dma_descriptors_w_250_s(i).wrap_around;
           
-          last_current_address_s(i) <= dma_descriptors_s(i).current_address;
-
-
           last_pc_pointer_s(i) <= dma_descriptors_s(i).pc_pointer;
 
 
           next_current_address_s(i) <= (dma_descriptors_s(i).current_address + (dma_descriptors_s(i).dword_count&"00"));
-          
-          --Create a a busy signal if the pc pointer comes too close to the current address.
-          --First check tohost busy 
-          if(dma_descriptors_s(i).wrap_around = '1' and dma_descriptors_s(i).read_not_write = '0' and dma_descriptors_s(i).enable = '1') then
-          --ToHost direction, so the nex_current_address has to be < last_pc_pointer_s
-            if((last_pc_pointer_s(i) - next_current_address_s(i)) < busy_threshold_assert) then
-                tohost_busy_v(i) := '1';
-            end if;
-            if(tohost_busy_v(i) = '1' and ((last_pc_pointer_s(i) - next_current_address_s(i)) > busy_threshold_negate)) then
-                tohost_busy_v(i) := '0';
-            end if;
-          else
-            tohost_busy_v(i) := '0';
-          end if;
-          --Then check fromhost busy 
-          if(dma_descriptors_s(i).wrap_around = '1' and dma_descriptors_s(i).read_not_write = '1' and dma_descriptors_s(i).enable = '1') then
-          --FromHost direction, so the nex_current_address has to be > last_pc_pointer_s
-            if((next_current_address_s(i) - last_pc_pointer_s(i)) < busy_threshold_assert) then
-                fromhost_busy_v(i) := '1';
-            end if;
-            if(fromhost_busy_v(i) = '1' and ((next_current_address_s(i) - last_pc_pointer_s(i)) > busy_threshold_negate)) then
-                fromhost_busy_v(i) := '0';
-            end if;
-          else
-            fromhost_busy_v(i) := '0';
-          end if;
-
+          dma_descriptors_s(i).address_wrapped <= '0';
           if(dma_descriptors_s(i).enable = '1') then
-            if(last_pc_pointer_s(i) > dma_descriptors_s(i).pc_pointer + x"0000_0000_1000_000") then --If the current pc_pointer is 16MB smaller than the last one, we change cycles.
-              dma_descriptors_s(i).evencycle_pc <= not dma_descriptors_s(i).evencycle_pc; --Toggle on wrap around
+            if(last_pc_pointer_s(i) > dma_descriptors_s(i).pc_pointer + pc_ptr_gap_250_s) then --If the current pc_pointer is 16MB smaller than the last one, we change cycles. The 16MB can be changed in the register PC_PTR_GAP (bar0).
+              evencycle_pc_v(i) := not dma_descriptors_s(i).evencycle_pc; --Toggle on wrap around
+
             end if;
             if(dma_status_s(i).descriptor_done = '1') then
               --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
-              if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
-                --if(next_current_address_s(i)<last_pc_pointer_s(i)) then
-                  dma_descriptors_s(i).current_address <= next_current_address_s(i);
-                --else
-                --  dma_descriptors_s(i).current_address <= dma_descriptors_s(i).current_address;
-                --end if;
+              if(dma_descriptors_s(i).wrap_around = '1' and ((dma_status_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
+                current_address_v(i) := next_current_address_s(i);          
               else
                 if(next_current_address_s(i)<dma_descriptors_s(i).end_address) then
-                  dma_descriptors_s(i).current_address <= next_current_address_s(i);
+                  current_address_v(i) := next_current_address_s(i);
                 else
                   dma_descriptors_s(i).enable <= dma_descriptors_s(i).wrap_around;
                   if(dma_descriptors_s(i).read_not_write='1') then
@@ -388,38 +343,30 @@ end process;
               --When wrapping around, regardless of the cycle, when the end address has been reached, the current address must be reset to start_address.
               if(next_current_address_s(i)=dma_descriptors_s(i).end_address) then
                 if(dma_descriptors_s(i).wrap_around = '1') then
-                  dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
-                  dma_descriptors_s(i).evencycle_dma <= not dma_descriptors_s(i).evencycle_dma; --Toggle on wrap around
+                  current_address_v(i) := dma_descriptors_s(i).start_address;
+                  dma_descriptors_s(i).address_wrapped <= '1';
+                  --evencycle_dma_v(i) := not dma_descriptors_s(i).evencycle_dma; --Toggle on wrap around
                 end if;
               end if;
             end if;
           else
-            dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
-            dma_descriptors_s(i).evencycle_pc <= '0';
-            dma_descriptors_s(i).evencycle_dma <= '0';
+            current_address_v(i) := dma_descriptors_s(i).start_address;
+            evencycle_pc_v(i) := '0';
+            --evencycle_dma_v(i) := '0';
+
           end if;
-          
+          --dma_descriptors_s(i).evencycle_dma <= evencycle_dma_v(i);
+          dma_descriptors_s(i).evencycle_pc <= evencycle_pc_v(i);
+          dma_descriptors_s(i).current_address <= current_address_v(i);
           if ( dma_descriptors_enable_written_250_s = '1' and dma_descriptors_enable_written_250_v = '0') then  --only write when the ENABLE register is actually accessed, else it can be cleared some lines below when DMA finished.
             dma_descriptors_s(i).enable <= dma_descriptors_w_250_s(i).enable; 
           end if;
-          
+          --dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
+
+              
                     
         end loop;
         
-        if(tohost_busy_v /= std_logic_vector(to_unsigned(0, tohost_busy_v'length))) then
-            tohost_busy_250_s <= '1';
-        else
-            tohost_busy_250_s <= '0';
-        end if;
-        
-        if(fromhost_busy_v/= std_logic_vector(to_unsigned(0, fromhost_busy_v'length))) then
-            fromhost_busy_250_s <= '1';
-        else
-            fromhost_busy_250_s <= '0';
-        end if;
-        
-        
-        
         dma_descriptors_enable_written_250_v := dma_descriptors_enable_written_250_s;
 
         case (completer_state) is
@@ -680,9 +627,6 @@ end process;
       read_interrupt_25_s <= read_interrupt_250_s;
       write_interrupt_25_s <= write_interrupt_250_s;
       
-      fromhost_busy_25_s <= fromhost_busy_250_s;
-      tohost_busy_25_s   <= tohost_busy_250_s;
-
       if(fifo_full_interrupt_v(2 downto 1) = "01") then --rising edge detected on full flag
         fifo_full_interrupt_25_s <= '1';
       else
@@ -728,8 +672,6 @@ end process;
     variable read_interrupt_25_pipe_v : std_logic;
     variable cnt10: integer range 0 to 15;
     variable dma_descriptors_enable_written_v: std_logic;
-    variable busy_threshold_assert_v             : std_logic_vector(63 downto 0);
-    variable busy_threshold_negate_v             : std_logic_vector(63 downto 0);
   begin
     if(rising_edge(clk)) then
       register_write_done_250_s <= register_write_done2_v;
@@ -754,11 +696,7 @@ end process;
       flush_fifo_v          := flush_fifo_25_s;
       dma_soft_reset_v      := dma_soft_reset_25_s;
       
-      busy_threshold_assert        <= busy_threshold_assert_v;
-      busy_threshold_assert_v      := busy_threshold_assert_25_s;
-      
-      busy_threshold_negate        <= busy_threshold_negate_v;
-      busy_threshold_negate_v      := busy_threshold_negate_25_s;
+      pc_ptr_gap_250_s <= pc_ptr_gap_25_s;
       
       -- dma_status and dma_descriptor can be changing fast, so only update at rising edge 
       -- of regmap_clk, then synchronize to regmap_clk
@@ -787,9 +725,57 @@ end process;
   register_map_monitor_s <= register_map_monitor;
   register_map_control   <= register_map_control_s;
 
+dma_busy_proc: process(regmap_clk)
+  variable tohost_busy_v, fromhost_busy_v: std_logic_vector(NUMBER_OF_DESCRIPTORS-1 downto 0);
+begin
+  if rising_edge(regmap_clk) then
+    for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
+      --Create a a busy signal if the pc pointer comes too close to the current address.
+      --First check tohost busy 
+      if(dma_descriptors_25_w_s(i).wrap_around = '1' and dma_descriptors_25_w_s(i).read_not_write = '0' and dma_descriptors_25_w_s(i).enable = '1') then
+        --ToHost direction, so the current_address has to be < pc_pointer
+        if((dma_descriptors_25_w_s(i).pc_pointer - dma_descriptors_25_r_s(i).current_address) < busy_threshold_assert) then
+          tohost_busy_v(i) := '1';
+        end if;
+        if(tohost_busy_v(i) = '1' and ((dma_descriptors_25_w_s(i).pc_pointer  - dma_descriptors_25_r_s(i).current_address) > busy_threshold_negate)) then
+          tohost_busy_v(i) := '0';
+        end if;
+      else
+        tohost_busy_v(i) := '0';
+      end if;
+      --Then check fromhost busy 
+      if(dma_descriptors_25_w_s(i).wrap_around = '1' and dma_descriptors_25_w_s(i).read_not_write = '1' and dma_descriptors_25_w_s(i).enable = '1') then
+        --FromHost direction, so the current_address has to be > pc_pointer
+        if((dma_descriptors_25_r_s(i).current_address - dma_descriptors_25_w_s(i).pc_pointer ) < busy_threshold_assert) then
+          fromhost_busy_v(i) := '1';
+        end if;
+        if(fromhost_busy_v(i) = '1' and ((dma_descriptors_25_r_s(i).current_address - dma_descriptors_25_w_s(i).pc_pointer) > busy_threshold_negate)) then
+          fromhost_busy_v(i) := '0';
+        end if;
+      else
+        fromhost_busy_v(i) := '0';
+      end if;
+    end loop;
+    
+    if(tohost_busy_v /= std_logic_vector(to_unsigned(0, tohost_busy_v'length))) then
+      tohost_busy_25_s <= '1';
+    else
+      tohost_busy_25_s <= '0';
+    end if;
+    
+    if(fromhost_busy_v/= std_logic_vector(to_unsigned(0, fromhost_busy_v'length))) then
+      fromhost_busy_25_s <= '1';
+    else
+      fromhost_busy_25_s <= '0';
+    end if;
+  end if;
+end process;
+
+
   regrw: process(regmap_clk)
     variable register_write_data_25_v: std_logic_vector(127 downto 0);
-
+    variable register_read_address_v: std_logic_vector(19 downto 0);
+    variable register_write_address_v: std_logic_vector(19 downto 0);
   begin
     if(rising_edge(regmap_clk)) then
         if(reset = '1' or reset_register_map_25_s='1') then
@@ -798,7 +784,7 @@ end process;
           register_read_data_25_s  <= (others => '0');
           reset_register_map_s <= '0';
           for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
-            dma_descriptors_25_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0',  evencycle_dma => '0',   evencycle_pc  => '0',   pc_pointer    => (others => '0'));
+            dma_descriptors_25_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around   => '0', evencycle_pc  => '0',   pc_pointer    => (others => '0'), address_wrapped => '0');
           end loop;
           --for i in 0 to (NUMBER_OF_INTERRUPTS-1) loop
           --  int_vector_25_s(i) <= (int_vec_add => (others => '0'), int_vec_data => (others => '0'),int_vec_ctrl => (others => '0') );
@@ -813,9 +799,9 @@ end process;
           tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4050, 12));
           tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(3744, 12));
           
-          busy_threshold_assert_25_s             <= REG_BUSY_THRESH_ASSERT_C;
-          busy_threshold_negate_25_s             <= REG_BUSY_THRESH_NEGATE_C;
-          
+          busy_threshold_assert             <= REG_BUSY_THRESH_ASSERT_C;
+          busy_threshold_negate             <= REG_BUSY_THRESH_NEGATE_C;
+          pc_ptr_gap_25_s                   <= PC_PTR_GAP_C;
           
           --!
           --! generate registers initialization
@@ -884,7 +870,8 @@ end process;
         register_read_data_25_s  <= (others => '0'); --default value
         --Read registers in BAR0
         if(register_read_address_25_s(31 downto 20) = bar0_25_s(31 downto 20)) then
-          case(register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             when REG_DESCRIPTOR_0  => register_read_data_25_s <= dma_descriptors_25_r_s( 0).end_address&
                                                                  dma_descriptors_25_r_s( 0).start_address;
             when REG_DESCRIPTOR_0a => register_read_data_25_s <= dma_descriptors_25_r_s( 0).pc_pointer&
@@ -943,42 +930,42 @@ end process;
                                                                  dma_descriptors_25_r_s( 7).dword_count;
             when REG_STATUS_0      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(0 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(0 ).evencycle_dma&
+                                                                 dma_status_25_s(0 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(0 ).enable)&
                                                                  dma_descriptors_25_r_s(0 ).current_address;
             when REG_STATUS_1      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(1 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(1 ).evencycle_dma&
+                                                                 dma_status_25_s(1 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(1 ).enable)&
                                                                  dma_descriptors_25_r_s(1 ).current_address;
             when REG_STATUS_2      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(2 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(2 ).evencycle_dma&
+                                                                 dma_status_25_s(2 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(2 ).enable)&
                                                                  dma_descriptors_25_r_s(2 ).current_address;
             when REG_STATUS_3      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(3 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(3 ).evencycle_dma&
+                                                                 dma_status_25_s(2 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(3 ).enable)&
                                                                  dma_descriptors_25_r_s(3 ).current_address;
             when REG_STATUS_4      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(4 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(4 ).evencycle_dma&
+                                                                 dma_status_25_s(4 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(4 ).enable)&
                                                                  dma_descriptors_25_r_s(4 ).current_address;
             when REG_STATUS_5      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(5 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(5 ).evencycle_dma&
+                                                                 dma_status_25_s(5 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(5 ).enable)&
                                                                  dma_descriptors_25_r_s(5 ).current_address;
             when REG_STATUS_6      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(6 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(6 ).evencycle_dma&
+                                                                 dma_status_25_s(6 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(6 ).enable)&
                                                                  dma_descriptors_25_r_s(6 ).current_address;
             when REG_STATUS_7      => register_read_data_25_s <= x"000000000000000"&"0"&
                                                                  dma_descriptors_25_r_s(7 ).evencycle_pc&
-                                                                 dma_descriptors_25_r_s(7 ).evencycle_dma&
+                                                                 dma_status_25_s(7 ).evencycle_dma&
                                                                  (not dma_descriptors_25_r_s(7 ).enable)&
                                                                  dma_descriptors_25_r_s(7 ).current_address;
             when REG_BAR0          => register_read_data_25_s     <=  x"000000000000000000000000"&bar0_25_s;
@@ -998,18 +985,20 @@ end process;
             when REG_TOHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
                                                                         x"0000_0000_0"&tohost_pfull_threshold_assert_s&
                                                                         x"0"&tohost_pfull_threshold_negate_s;  
-            when REG_BUSY_THRESH_ASSERT   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert_25_s;
-            when REG_BUSY_THRESH_NEGATE   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate_25_s;
+            when REG_BUSY_THRESH_ASSERT   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert;
+            when REG_BUSY_THRESH_NEGATE   => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate;
             when REG_BUSY_STATUS          => register_read_data_25_s <= x"0000_0000_0000_0000_0000_0000_0000_000"&"00"&
                                                                                              fromhost_busy_25_s&
                                                                                              tohost_busy_25_s;
+            when REG_PC_PTR_GAP           => register_read_data_25_s <= x"0000_0000_0000_0000"&pc_ptr_gap_25_s;                                                                                             
             when others            => register_read_data_25_s <= (others => '0');
 
 
           end case;
         --Read registers in BAR1
         elsif(register_read_address_25_s(31 downto 20) = bar1_25_s(31 downto 20)) then
-          case (register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             when REG_INT_VEC_00      => register_read_data_25_s(63 downto 0)   <=  int_vector_25_s(0).int_vec_add;
                                         register_read_data_25_s(95 downto 64)  <=  int_vector_25_s(0).int_vec_data;
                                         register_read_data_25_s(127 downto 96) <=  int_vector_25_s(0).int_vec_ctrl;
@@ -1063,7 +1052,8 @@ end process;
           end case;
         --Read registers in BAR2
         elsif(register_read_address_25_s(31 downto 20) = bar2_25_s(31 downto 20)) then
-          case (register_read_address_25_s(19 downto 4)&"0000") is
+          register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+          case(register_read_address_v) is
             --!
             --! generated registers read
             ------------------------------------
@@ -1247,8 +1237,8 @@ end process;
         register_write_done_25_s <= '1';
         --Write registers in BAR0
         if(register_write_address_25_s(31 downto 20) = bar0_25_s(31 downto 20)) then
-
-          case(register_write_address_25_s(19 downto 4)&"0000") is  --only check 128 bit addressing
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             when REG_DESCRIPTOR_0   =>   dma_descriptors_25_w_s( 0).end_address            <= register_write_data_25_v(127 downto 64);
                                          dma_descriptors_25_w_s( 0).start_address          <= register_write_data_25_v(63 downto 0);
             when REG_DESCRIPTOR_0a  =>   dma_descriptors_25_w_s( 0).pc_pointer             <= register_write_data_25_v(127 downto 64);
@@ -1309,14 +1299,16 @@ end process;
                                              fromhost_pfull_threshold_negate_s <= register_write_data_25_v( 8 downto 0);
             when REG_TOHOST_FULL_THRESH =>   tohost_pfull_threshold_assert_s   <= register_write_data_25_v(27 downto 16);
                                              tohost_pfull_threshold_negate_s   <= register_write_data_25_v(11 downto 0);
-            when REG_BUSY_THRESH_ASSERT   => busy_threshold_assert_25_s <= register_write_data_25_v(63 downto 0);
-            when REG_BUSY_THRESH_NEGATE   => busy_threshold_negate_25_s <= register_write_data_25_v(63 downto 0);
+            when REG_BUSY_THRESH_ASSERT   => busy_threshold_assert <= register_write_data_25_v(63 downto 0);
+            when REG_BUSY_THRESH_NEGATE   => busy_threshold_negate <= register_write_data_25_v(63 downto 0);
+            when REG_PC_PTR_GAP           => pc_ptr_gap_25_s <= register_write_data_25_v(63 downto 0);
             when others => --do nothing
 
           end case;
         --Write registers in BAR1
         elsif(register_write_address_25_s(31 downto 20) = bar1_25_s(31 downto 20)) then
-          case (register_write_address_25_s(19 downto 4)&"0000") is
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             when REG_INT_VEC_00      => int_vector_25_s(0).int_vec_add   <= register_write_data_25_v(63 downto 0);
                                         int_vector_25_s(0).int_vec_data  <= register_write_data_25_v(95 downto 64);
                                         int_vector_25_s(0).int_vec_ctrl  <= register_write_data_25_v(127 downto 96);
@@ -1370,7 +1362,8 @@ end process;
           end case;
         --Write registers in BAR2
         elsif(register_write_address_25_s(31 downto 20) = bar2_25_s(31 downto 20)) then
-          case (register_write_address_25_s(19 downto 4)&"0000") is
+          register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+          case(register_write_address_v) is
             --!
             --! generated registers write
             -------------------------------------
diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd
index 4e7f59c08dd76db728aab2995476a5eb1d6088c3..410b82a4c5142d1f983c9df4fe027f82fb702b65 100644
--- a/sources/templates/pcie_package.vhd
+++ b/sources/templates/pcie_package.vhd
@@ -6,11 +6,11 @@
 -- DO NOT EDIT THIS FILE
 -- 
 -- This file was generated from template '../../sources/templates/pcie_package.vhd.template'
--- and register map ../../sources/templates/registers-4.6.yaml, version 4.6
+-- and register map ../../sources/templates/registers-4.7.yaml, version 4.7
 -- by the script 'wuppercodegen', version: 0.8.0,
 -- using the following commandline:
 -- 
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.6.yaml ../../sources/templates/pcie_package.vhd.template ../../sources/templates/pcie_package.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.7.yaml ../../sources/templates/pcie_package.vhd.template ../../sources/templates/pcie_package.vhd
 -- 
 -- Please do NOT edit this file, but edit the source file at '../../sources/templates/pcie_package.vhd.template'
 -- 
@@ -107,14 +107,15 @@ package pcie_package is
     read_not_write  : std_logic;     --1 means this is a read descriptor, 0: write descriptor
     enable          : std_logic;     --descriptor is valid
     wrap_around     : std_logic;     --1 means when end is reached, keep enabled and start over
-    evencycle_dma   : std_logic;     --For every time the current_address overflows, this bit toggles
     evencycle_pc    : std_logic;     --For every time the pc pointer overflows, this bit toggles.
     pc_pointer      : std_logic_vector(63 downto 0); --Last address that the PC has read / written. For write: overflow and read until this cycle.
+    address_wrapped : std_logic;
   end record;
 
   type dma_descriptors_type is array (natural range <>) of dma_descriptor_type;
 
   type dma_status_type is record
+    evencycle_dma   : std_logic;     --For every time the current_address overflows, this bit toggles
     descriptor_done: std_logic;  -- means the dma_descriptor in the array above has been handled, the enable field should then be cleared.
   end record;
 
@@ -194,6 +195,7 @@ package pcie_package is
   constant REG_BUSY_THRESH_ASSERT  : std_logic_vector(19 downto 0) := x"00470";
   constant REG_BUSY_THRESH_NEGATE  : std_logic_vector(19 downto 0) := x"00480";
   constant REG_BUSY_STATUS         : std_logic_vector(19 downto 0) := x"00490";
+  constant REG_PC_PTR_GAP          : std_logic_vector(19 downto 0) := x"004A0";
   
   -- BAR0 registers: end
 
@@ -1007,6 +1009,7 @@ package pcie_package is
   constant REG_TTC_DELAY_47                   : std_logic_vector(19 downto 0) := x"084a0";
   constant REG_TTC_BUSY_TIMING_CTRL           : std_logic_vector(19 downto 0) := x"084b0";
   constant REG_TTC_BUSY_CLEAR                 : std_logic_vector(19 downto 0) := x"084c0";
+  constant REG_TTC_EMU_CONTROL                : std_logic_vector(19 downto 0) := x"084d0";
 
   --** XOFF_BUSYControlsAndMonitors
   constant REG_XOFF_FM_CH_FIFO_THRESH_LOW     : std_logic_vector(19 downto 0) := x"08800";
@@ -1518,6 +1521,7 @@ package pcie_package is
   end record;
 
   type bitfield_ttc_dec_ctrl_w_type is record
+    BCID_ONBCR                     : std_logic_vector(26 downto 15);  -- BCID is set to this value when BCR arrives
     ECR_BCR_SWAP                   : std_logic_vector(13 downto 13);  -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
     BUSY_OUTPUT_INHIBIT            : std_logic_vector(12 downto 12);  -- forces the Busy LEMO output to BUSY-OFF
     TOHOST_RST                     : std_logic_vector(11 downto 11);  -- reset toHost in ttc decoder
@@ -1529,7 +1533,7 @@ package pcie_package is
 
   type bitfield_ttc_emu_w_type is record
     SEL                            : std_logic_vector(1 downto 1);    -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
-    ENA                            : std_logic_vector(0 downto 0);    -- Enable TTC data generator (10 bit counter)
+    ENA                            : std_logic_vector(0 downto 0);    -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
   end record;
 
   type bitfield_ttc_busy_timing_ctrl_w_type is record
@@ -1538,6 +1542,22 @@ package pcie_package is
     LIMIT_TIME                     : std_logic_vector(15 downto 0);   -- Number of prescaled clocks a given busy must be asserted before it is recognized
   end record;
 
+  type bitfield_ttc_emu_control_t_type is record
+    WE                             : std_logic_vector(64 downto 64);  -- Any write to this register executes a write enable
+    LAST_LINE                      : std_logic_vector(35 downto 35);  -- Last line of the sequence
+    REPEAT                         : std_logic_vector(34 downto 34);  -- Repeat the sequence
+    BROADCAST5                     : std_logic_vector(32 downto 32);  -- Broadcast 5
+    BROADCAST4                     : std_logic_vector(31 downto 31);  -- Broadcast 4
+    BROADCAST3                     : std_logic_vector(30 downto 30);  -- Broadcast 3
+    BROADCAST2                     : std_logic_vector(29 downto 29);  -- Broadcast 2
+    BROADCAST1                     : std_logic_vector(28 downto 28);  -- Broadcast 1
+    BROADCAST0                     : std_logic_vector(27 downto 27);  -- Broadcast 0
+    ECR                            : std_logic_vector(26 downto 26);  -- Event counter reset
+    BCR                            : std_logic_vector(25 downto 25);  -- Bunch counter reset
+    L1A                            : std_logic_vector(24 downto 24);  -- Level 1 Accept
+    STEP_COUNTER                   : std_logic_vector(21 downto 0);   -- Step counter value
+  end record;
+
   type bitfield_xoff_fm_ch_fifo_thresh_low_w_type is record
     CH11                           : std_logic_vector(47 downto 44);  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
     CH10                           : std_logic_vector(43 downto 40);  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
@@ -2282,6 +2302,7 @@ package pcie_package is
     TTC_DELAY_47                   : std_logic_vector(3 downto 0);    -- Controls the TTC Fanout delay values
     TTC_BUSY_TIMING_CTRL           : bitfield_ttc_busy_timing_ctrl_w_type;
     TTC_BUSY_CLEAR                 : std_logic_vector(64 downto 64);  -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+    TTC_EMU_CONTROL                : bitfield_ttc_emu_control_t_type;
     XOFF_FM_CH_FIFO_THRESH_LOW     : bitfield_xoff_fm_ch_fifo_thresh_low_w_type;
     XOFF_FM_CH_FIFO_THRESH_HIGH    : bitfield_xoff_fm_ch_fifo_thresh_high_w_type;
     XOFF_FM_HIGH_THRESH            : bitfield_xoff_fm_high_thresh_t_type;
@@ -5468,6 +5489,7 @@ package pcie_package is
                                                                                                                 --   0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
                                                                                                                 --   
                                                                                                                 
+  constant REG_TTC_DEC_CTRL_BCID_ONBCR_C           : std_logic_vector(26 downto 15)   := x"000";                -- BCID is set to this value when BCR arrives
   constant REG_TTC_DEC_CTRL_ECR_BCR_SWAP_C         : std_logic_vector(13 downto 13)   := "0";                   -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
   constant REG_TTC_DEC_CTRL_BUSY_OUTPUT_INHIBIT_C  : std_logic_vector(12 downto 12)   := "0";                   -- forces the Busy LEMO output to BUSY-OFF
   constant REG_TTC_DEC_CTRL_TOHOST_RST_C           : std_logic_vector(11 downto 11)   := "0";                   -- reset toHost in ttc decoder
@@ -5476,7 +5498,7 @@ package pcie_package is
   constant REG_TTC_DEC_CTRL_XL1ID_RST_C            : std_logic_vector(1 downto 1)     := "0";                   -- giving a trigger signal to reset XL1ID value
   constant REG_TTC_DEC_CTRL_MASTER_BUSY_C          : std_logic_vector(0 downto 0)     := "0";                   -- L1A trigger throttling
   constant REG_TTC_EMU_SEL_C                       : std_logic_vector(1 downto 1)     := "0";                   -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
-  constant REG_TTC_EMU_ENA_C                       : std_logic_vector(0 downto 0)     := "0";                   -- Enable TTC data generator (10 bit counter)
+  constant REG_TTC_EMU_ENA_C                       : std_logic_vector(0 downto 0)     := "0";                   -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
   constant REG_TTC_DELAY_00_C                      : std_logic_vector(3 downto 0)     := x"0";                  -- Controls the TTC Fanout delay values
   constant REG_TTC_DELAY_01_C                      : std_logic_vector(3 downto 0)     := x"0";                  -- Controls the TTC Fanout delay values
   constant REG_TTC_DELAY_02_C                      : std_logic_vector(3 downto 0)     := x"0";                  -- Controls the TTC Fanout delay values
@@ -5529,6 +5551,19 @@ package pcie_package is
   constant REG_TTC_BUSY_TIMING_CTRL_BUSY_WIDTH_C   : std_logic_vector(31 downto 16)   := x"000f";               -- Minimum number of 40MHz clocks that the busy is asserted
   constant REG_TTC_BUSY_TIMING_CTRL_LIMIT_TIME_C   : std_logic_vector(15 downto 0)    := x"000f";               -- Number of prescaled clocks a given busy must be asserted before it is recognized
   constant REG_TTC_BUSY_CLEAR_C                    : std_logic_vector(64 downto 64)   := "0";                   -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+  constant REG_TTC_EMU_CONTROL_WE_C                : std_logic_vector(64 downto 64)   := "0";                   -- Any write to this register executes a write enable
+  constant REG_TTC_EMU_CONTROL_LAST_LINE_C         : std_logic_vector(35 downto 35)   := "0";                   -- Last line of the sequence
+  constant REG_TTC_EMU_CONTROL_REPEAT_C            : std_logic_vector(34 downto 34)   := "0";                   -- Repeat the sequence
+  constant REG_TTC_EMU_CONTROL_BROADCAST5_C        : std_logic_vector(32 downto 32)   := "0";                   -- Broadcast 5
+  constant REG_TTC_EMU_CONTROL_BROADCAST4_C        : std_logic_vector(31 downto 31)   := "0";                   -- Broadcast 4
+  constant REG_TTC_EMU_CONTROL_BROADCAST3_C        : std_logic_vector(30 downto 30)   := "0";                   -- Broadcast 3
+  constant REG_TTC_EMU_CONTROL_BROADCAST2_C        : std_logic_vector(29 downto 29)   := "0";                   -- Broadcast 2
+  constant REG_TTC_EMU_CONTROL_BROADCAST1_C        : std_logic_vector(28 downto 28)   := "0";                   -- Broadcast 1
+  constant REG_TTC_EMU_CONTROL_BROADCAST0_C        : std_logic_vector(27 downto 27)   := "0";                   -- Broadcast 0
+  constant REG_TTC_EMU_CONTROL_ECR_C               : std_logic_vector(26 downto 26)   := "0";                   -- Event counter reset
+  constant REG_TTC_EMU_CONTROL_BCR_C               : std_logic_vector(25 downto 25)   := "0";                   -- Bunch counter reset
+  constant REG_TTC_EMU_CONTROL_L1A_C               : std_logic_vector(24 downto 24)   := "0";                   -- Level 1 Accept
+  constant REG_TTC_EMU_CONTROL_STEP_COUNTER_C      : std_logic_vector(21 downto 0)    := "0000000000000000000000"; -- Step counter value
   constant REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH11_C   : std_logic_vector(47 downto 44)   := x"b";                  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
   constant REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH10_C   : std_logic_vector(43 downto 40)   := x"b";                  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
   constant REG_XOFF_FM_CH_FIFO_THRESH_LOW_CH09_C   : std_logic_vector(39 downto 36)   := x"b";                  -- Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
@@ -6302,7 +6337,7 @@ package pcie_package is
 
   -- GenericBoardInformation
   type register_map_gen_board_info_type is record
-    REG_MAP_VERSION                : std_logic_vector(15 downto 0);   -- Register Map Version, 4.6 formatted as 0x0406
+    REG_MAP_VERSION                : std_logic_vector(15 downto 0);   -- Register Map Version, 4.7 formatted as 0x0407
     BOARD_ID_TIMESTAMP             : std_logic_vector(39 downto 0);   -- Board ID Date / Time in BCD format YYMMDDhhmm
     BOARD_ID_SVN                   : std_logic_vector(15 downto 0);   -- Board ID SVN Revision
     GIT_COMMIT_TIME                : std_logic_vector(39 downto 0);   -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
@@ -7412,6 +7447,10 @@ end record;
     TTC_BIT_ERR                    : std_logic_vector(2 downto 0);    -- double bit, single bit and comm error in TTC data
   end record;
 
+  type bitfield_ttc_emu_r_type is record
+    FULL                           : std_logic_vector(2 downto 2);    -- TTC Emulator memory full indication
+  end record;
+
 
   -- TTCBUSYControlsAndMonitors
   type register_map_ttc_monitor_type is record
@@ -7441,6 +7480,7 @@ end record;
     TTC_BUSY_ACCEPTED21            : std_logic_vector(56 downto 0);   -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
     TTC_BUSY_ACCEPTED22            : std_logic_vector(56 downto 0);   -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
     TTC_BUSY_ACCEPTED23            : std_logic_vector(56 downto 0);   -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+    TTC_EMU                        : bitfield_ttc_emu_r_type;      
 end record;
 --
 -- XOFF_BUSYControlsAndMonitors
diff --git a/sources/templates/pcie_package.vhd.template b/sources/templates/pcie_package.vhd.template
index c546d4ca0e297cac8846a02ad4fa96e92eef6472..24f992b84b0ad5d85a416da84799f65336c85040 100644
--- a/sources/templates/pcie_package.vhd.template
+++ b/sources/templates/pcie_package.vhd.template
@@ -86,14 +86,15 @@ package pcie_package is
     read_not_write  : std_logic;     --1 means this is a read descriptor, 0: write descriptor
     enable          : std_logic;     --descriptor is valid
     wrap_around     : std_logic;     --1 means when end is reached, keep enabled and start over
-    evencycle_dma   : std_logic;     --For every time the current_address overflows, this bit toggles
     evencycle_pc    : std_logic;     --For every time the pc pointer overflows, this bit toggles.
     pc_pointer      : std_logic_vector(63 downto 0); --Last address that the PC has read / written. For write: overflow and read until this cycle.
+    address_wrapped : std_logic;
   end record;
 
   type dma_descriptors_type is array (natural range <>) of dma_descriptor_type;
 
   type dma_status_type is record
+    evencycle_dma   : std_logic;     --For every time the current_address overflows, this bit toggles
     descriptor_done: std_logic;  -- means the dma_descriptor in the array above has been handled, the enable field should then be cleared.
   end record;
 
@@ -173,6 +174,7 @@ package pcie_package is
   constant REG_BUSY_THRESH_ASSERT  : std_logic_vector(19 downto 0) := x"00470";
   constant REG_BUSY_THRESH_NEGATE  : std_logic_vector(19 downto 0) := x"00480";
   constant REG_BUSY_STATUS         : std_logic_vector(19 downto 0) := x"00490";
+  constant REG_PC_PTR_GAP          : std_logic_vector(19 downto 0) := x"004A0";
   
   -- BAR0 registers: end
 
diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index 4cf0db4759f16317a62ace38469f4a248ca12c54..642d4dc0894acd8f7449c4338f149e9f853c60b9 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -6,11 +6,11 @@
 % DO NOT EDIT THIS FILE
 % 
 % This file was generated from template 'registermap.tex.template'
-% and register map registers-4.6.yaml, version 4.6
+% and register map registers-4.7.yaml, version 4.7
 % by the script 'wuppercodegen', version: 0.8.0,
 % using the following commandline:
 % 
-% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.6.yaml registermap.tex.template registermap.tex
+% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.7.yaml registermap.tex.template registermap.tex
 % 
 % Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
 % 
@@ -20,7 +20,7 @@
 % ***************************************************************************
 % ***************************************************************************
 
-\section{FELIX register map, version 4.6}
+\section{FELIX register map, version 4.7}
 
 Starting from the offset address of BAR0, BAR1 and BAR2, the register map for BAR0 expands from 0x0000 to 0x0430 for the PCIe control registers. BAR0 only contains registers associated with DMA. The offset for BAR0 is usually 0xFBB00000.
 
@@ -124,6 +124,9 @@ any & T & Resets the register map to default values. Any write triggers this res
  & & & FROMHOST\_BUSY & 1 & R & A fromhost descriptor passed BUSY\_THRESHOLD\_ASSERT, busy flag set \\
  & & & TOHOST\_BUSY & 0 & R & A tohost descriptor passed BUSY\_THRESHOLD\_ASSERT, busy flag set \\
 \hline
+0x04A0 & 0,1 & \multicolumn{2}{l|}{PC\_PTR\_GAP} &
+63:0 & W & This is the minimum value that the pc\_pointer in a descriptor has to decrease in order to flip the evencycle\_pc bit \\
+\hline
 \caption{FELIX register map BAR0}\label{tab:dma_register_map_bar0} \\
 \end{longtabu}
 
@@ -176,7 +179,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \multicolumn{7}{|c|}{Generic Board Information} \\
 \hline
 0x0000 & 0,1 & \multicolumn{2}{l|}{REG\_MAP\_VERSION} &
-15:0 & R & Register Map Version, 4.6 formatted as 0x0406 \\
+15:0 & R & Register Map Version, 4.7 formatted as 0x0407 \\
 \hline
 0x0010 & 0,1 & \multicolumn{2}{l|}{BOARD\_ID\_TIMESTAMP} &
 39:0 & R & Board ID Date / Time in BCD format YYMMDDhhmm \\
@@ -777,6 +780,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x8000 & 0 & \multicolumn{5}{l|}{TTC\_DEC\_CTRL} \\
 \cline{3-7}
+ & & & BCID\_ONBCR & 26:15 & W & BCID is set to this value when BCR arrives \\
  & & & BUSY\_OUTPUT\_STATUS & 14 & R & Actual status of the BUSY LEMO output signal \\
  & & & ECR\_BCR\_SWAP & 13 & W & ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC) \\
  & & & BUSY\_OUTPUT\_INHIBIT & 12 & W & forces the Busy LEMO output to BUSY-OFF \\
@@ -805,8 +809,9 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x81A0 & 0 & \multicolumn{5}{l|}{TTC\_EMU} \\
 \cline{3-7}
+ & & & FULL & 2 & R & TTC Emulator memory full indication \\
  & & & SEL & 1 & W & Select TTC data source 1 TTC Emu | 0 TTC Decoder \\
- & & & ENA & 0 & W & Enable TTC data generator (10 bit counter) \\
+ & & & ENA & 0 & W & Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence \\
 \hline
 \multicolumn{7}{|c|}{TTC\_DELAY} \\
 \hline
@@ -827,6 +832,22 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x84C0 & 0 & \multicolumn{2}{l|}{TTC\_BUSY\_CLEAR} &
 any & T & clears the latching busy bits in TTC\_BUSY\_ACCEPTED \\
 \hline
+0x84D0 & 0 & \multicolumn{5}{l|}{TTC\_EMU\_CONTROL} \\
+\cline{3-7}
+ & & & WE & any & T & Any write to this register executes a write enable \\
+ & & & LAST\_LINE & 35 & W & Last line of the sequence \\
+ & & & REPEAT & 34 & W & Repeat the sequence \\
+ & & & BROADCAST5 & 32 & W & Broadcast 5 \\
+ & & & BROADCAST4 & 31 & W & Broadcast 4 \\
+ & & & BROADCAST3 & 30 & W & Broadcast 3 \\
+ & & & BROADCAST2 & 29 & W & Broadcast 2 \\
+ & & & BROADCAST1 & 28 & W & Broadcast 1 \\
+ & & & BROADCAST0 & 27 & W & Broadcast 0 \\
+ & & & ECR & 26 & W & Event counter reset \\
+ & & & BCR & 25 & W & Bunch counter reset \\
+ & & & L1A & 24 & W & Level 1 Accept \\
+ & & & STEP\_COUNTER & 21:0 & W & Step counter value \\
+\hline
 \multicolumn{7}{|c|}{XOFF\_BUSY Controls And Monitors} \\
 \hline
 0x8800 & 0, 1 & \multicolumn{5}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_LOW} \\
diff --git a/sources/templates/registers-4.6.yaml b/sources/templates/registers-4.6.yaml
index c2b52cb1f7c3563119cc7fc27c4292760f1637ef..4695257e216c71c37573c7a16759fd872916e40c 100644
--- a/sources/templates/registers-4.6.yaml
+++ b/sources/templates/registers-4.6.yaml
@@ -169,6 +169,12 @@ Bar0:
           name: TOHOST_BUSY
           desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
 
+    - name: PC_PTR_GAP
+      type: W
+      desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
+      default: 0x1000000
+      bitfield:
+        - range: 63..0
 
 DMA_DESC:
   number: 8
diff --git a/sources/templates/registers-4.7.yaml b/sources/templates/registers-4.7.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..7a7c1d400b2b15b2a6cc00be3276630f42d0fc59
--- /dev/null
+++ b/sources/templates/registers-4.7.yaml
@@ -0,0 +1,2681 @@
+Registers:
+  version: '4.7'
+  warning: |
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+    DO NOT EDIT THIS FILE
+
+    This file was generated from template '{{ metadata.template }}'
+    and register map {{ metadata.config }}, version {{ tree.version }}
+    by the script '{{ metadata.name }}', version: {{ metadata.version }},
+    using the following commandline:
+
+    {{ metadata.cmdline }}
+
+    Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
+
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+    ***************************************************************************
+
+  type: R
+  step: 0x010
+  default: 0
+  endpoints: 0,1
+  entries:
+    - ref: Bar0
+      offset: 0x0000
+    - ref: Bar1
+      offset: 0x0000
+    - ref: Bar2
+      offset: 0x0000
+    - ref: Monitorsections
+      offset: 0x0000
+    
+Monitorsections:
+  endpoints: 0,1
+  entries:
+    - name: GenericBoardInformation
+      record_name: register_map_gen_board_info
+      bitfield: 
+        - range: 0..0
+          type: R
+    - name: CentralRouterControlsAndMonitors
+      record_name: register_map_cr_monitor
+      bitfield: 
+        - range: 0..0
+          type: R
+    - name: GBTEmulatorControlsAndMonitors
+      record_name: register_map_gbtemu_monitor
+      bitfield:
+        - range: 0..0
+          type: R
+    - name: GBTWrapperMonitors
+      record_name: register_map_gbt_monitor
+      bitfield: 
+        - range: 0..0
+          type: R
+    - name: TTCBUSYControlsAndMonitors
+      record_name: register_map_ttc_monitor
+      bitfield:
+        - range: 0..0
+          type: R
+    - name: XOFF_BUSYControlsAndMonitors
+      record_name: register_map_xoff_monitor
+      bitfield:
+        - range: 0..0
+          type: R
+    - name: HouseKeepingControlsAndMonitors
+      record_name: register_map_hk_monitor
+      bitfield: 
+        - range: 0..0
+          type: R
+    - name: Generators
+      record_name: register_map_generators
+      bitfield: 
+        - range: 0..0
+          type: R
+
+#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
+#Registers in this group will not be generated with WupperCodeGen
+Bar0:
+  endpoints: 0,1
+  entries:
+    - ref: DMA_DESC
+    - ref: DMA_DESC_STATUS
+      offset: 0x0200
+    - name: BAR0_VALUE
+      offset: 0x0300
+      bitfield:
+        - range: 31..0
+          desc: Copy of BAR0 offset reg.
+    - name: BAR1_VALUE
+      bitfield:
+        - range: 31..0
+          desc: Copy of BAR1 offset reg.
+    - name: BAR2_VALUE
+      bitfield:
+        - range: 31..0
+          desc: Copy of BAR2 offset reg.
+    - name: DMA_DESC_ENABLE
+      offset: 0x0400
+      bitfield:
+        - range: 7..0
+          type: W
+          desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
+    - name: DMA_FIFO_FLUSH
+      type: T
+      bitfield:
+        - range: any
+          desc: Flush (reset). Any write clears the DMA Main output FIFO
+    - name: DMA_RESET
+      type: T
+      bitfield:
+        - range: any
+          desc: Reset Wupper Core (DMA Controller FSMs)
+    - name: SOFT_RESET
+      type: T
+      bitfield:
+        - range: any
+          desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
+    - name: REGISTER_RESET
+      type: T
+      bitfield:
+        - range: any
+          desc: Resets the register map to default values. Any write triggers this reset.
+    - name: FROMHOST_FULL_THRESH
+      type: W
+      bitfield:
+        - range: 22..16
+          name: THRESHOLD_ASSERT
+          desc: Assert value of the FromHost programmable full flag
+        - range: 6..0
+          name: THRESHOLD_NEGATE
+          desc: Negate value of the FromHost programmalbe full flag
+    - name: TOHOST_FULL_THRESH
+      type: W
+      bitfield:
+        - range: 27..16
+          name: THRESHOLD_ASSERT
+          desc: Assert value of the ToHost programmable full flag
+        - range: 11..0
+          name: THRESHOLD_NEGATE
+          desc: Negate value of the ToHost programmalbe full flag
+    
+    - name: BUSY_THRESHOLD_ASSERT
+      type: W
+      desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
+      default: 0x6400000
+      bitfield:
+        - range: 63..0
+        
+    - name: BUSY_THRESHOLD_NEGATE
+      type: W
+      desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
+      default: 0x6E00000
+      bitfield:
+        - range: 63..0
+
+    - name: BUSY_STATUS
+      type: R
+      bitfield:
+        - range: 1
+          name: FROMHOST_BUSY
+          desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+        - range: 0
+          name: TOHOST_BUSY
+          desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+
+    - name: PC_PTR_GAP
+      type: W
+      desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
+      default: 0x1000000
+      bitfield:
+        - range: 63..0
+
+DMA_DESC:
+  number: 8
+  type: W
+  entries:
+    - name: DMA_DESC_{index}
+      bitfield:
+        - range: 127..64
+          name: END_ADDRESS
+          desc: End Address
+        - range: 63..0
+          name: START_ADDRESS
+          desc: Start Address
+    - name: DMA_DESC_{index}a
+      bitfield:
+        - range: 127..64
+          name: SW_POINTER
+          desc: Pointer controlled by the software, indicating read or write status for circular DMA
+        - range: 12
+          name: WRAP_AROUND
+          desc: Wrap around
+        - range: 11
+          name: FROMHOST
+          desc: "1: fromHost/ 0: toHost"
+        - range: 10..0
+          name: NUM_WORDS
+          desc: Number of 32 bit words
+
+DMA_DESC_STATUS:
+  number: 8
+  entries:
+    - name: DMA_DESC_STATUS_{index}
+      bitfield:
+        - range: 66
+          name: EVEN_PC
+          desc: Even address cycle PC
+        - range: 65
+          name: EVEN_DMA
+          desc: Even address cycle DMA
+        - range: 64
+          name: DESC_DONE
+          desc: Descriptor Done
+        - range: 63..0
+          name: FW_POINTER
+          desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
+
+
+#Bar1 contains the registers dedicated to the Wupper interrupg controller.
+#Please only edit registers in Bar2.
+#Registers in this group will not be generated with WupperCodeGen
+Bar1:
+  endpoints: 0,1
+  type: W
+  entries:
+    - ref: INT_VEC
+    - name: INT_TAB_ENABLE
+      offset: 0x100
+      bitfield:
+        - range: 7..0
+          desc: |
+            Interrupt Table enable
+            Selectively enable Interrupts
+
+INT_VEC:
+  number: 16
+  type: W
+  entries:
+    - name: INT_VEC_{index}
+      bitfield:
+        - range: 127..96
+          name: INT_CTRL
+          desc: Interrupt Control
+        - range: 95..64
+          name: INT_DATA
+          desc: Interrupt Data
+        - range: 64..0
+          name: INT_ADDRESS
+          desc: Interrupt Address
+
+#Bar 2 contains application specific registers, used in the example application.
+#Registers in this group (and it's referenced subroups) will be generated with
+#WupperCodeGen for wupper Firmware, Software and Documentation
+Bar2:
+  entries:
+    - ref: GenericBoardInformation
+      offset: 0x0000
+    - ref: CentralRouterControlsAndMonitors
+      offset: 0x1000
+    - ref: GBTEmulatorControlsAndMonitors
+      offset: 0x5000
+    - ref: GBTWrapperControls
+      offset: 0x6000
+    - ref: GBTWrapperMonitors
+      offset: 0x7000
+    - ref: TTCBUSYControlsAndMonitors
+      offset: 0x8000
+    - ref: XOFF_BUSYControlsAndMonitors
+      offset: 0x8800
+    - ref: HouseKeepingControlsAndMonitors
+      offset: 0x9000
+    - ref: Generators
+      offset: 0xA000
+
+GenericBoardInformation:
+  group: GEN
+  desc: Generic Board Information
+  endpoints: 0,1
+  entries:
+    - name: REG_MAP_VERSION
+      bitfield:
+        - range: 15..0
+          value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
+          desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
+
+    - name: BOARD_ID_TIMESTAMP
+      bitfield:
+        - range: 39..0
+          value: BUILD_DATETIME
+          desc: Board ID Date / Time in BCD format YYMMDDhhmm
+
+    - name: BOARD_ID_SVN
+      bitfield:
+        - range: 15..0
+          value: std_logic_vector(to_unsigned(SVN_VERSION,16))
+          desc: Board ID SVN Revision
+
+    - name: GIT_COMMIT_TIME
+      bitfield:
+        - range: 39..0
+          value: COMMIT_DATETIME
+          desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
+          
+    - name: GIT_TAG
+      bitfield:
+        - range: 63..0
+          value: GIT_TAG(63 downto 0)
+          desc: String containing the current GIT TAG
+
+    - name: GIT_COMMIT_NUMBER
+      bitfield:
+        - range: 31..0
+          value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
+          desc: Number of GIT commits after current GIT_TAG
+          
+    - name: GIT_HASH
+      bitfield:
+        - range: 31..0
+          value: GIT_HASH(159 downto 128)
+          desc: Short GIT hash (32 bit)
+
+    - name: STATUS_LEDS
+      type: W
+      bitfield:
+        - range: 7..0
+          default: 0xAB
+          desc: Board GPIO Leds
+
+    - name: GENERIC_CONSTANTS
+      bitfield:
+        - range: 15..8
+          name: INTERRUPTS
+          value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
+          desc: Number of Interrupts
+        - range: 7..0
+          name: DESCRIPTORS
+          value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
+          desc: Number of Descriptors
+
+    - name: NUM_OF_CHANNELS
+      bitfield:
+        - range: 7..0
+          desc: Number of GBT Channels
+
+    - name: CARD_TYPE
+      bitfield:
+        - range: 63..0
+          value: std_logic_vector(to_unsigned(CARD_TYPE,64))
+          desc: |
+            Card Type:
+              - 709 (0x2c5): VC-709
+              - 710 (0x2c6): HTG-710
+              - 711 (0x2c7): BNL-711
+              - 712 (0x2c8): BNL-712
+
+    - name: GBT_MAPPING
+      bitfield:
+        - range: 7..0
+          desc: |
+            CXP-to-GBT mapping:
+              0: NORMAL CXP1 1-12 CXP2 13-24
+              1: ALTERNATE CXP1 1-4,9-12,17-20
+
+    - name: GENERATE_GBT
+      bitfield:
+        - range: 0
+          desc: 1 when the GBT Wrapper is included in the design
+
+    - name: OPTO_TRX_NUM
+      bitfield:
+        - range: 7..0
+          desc: Number of optical transceivers in the design
+
+    - name: TTC_EMU_CONST
+      type: R
+      bitfield:
+        - range: 1
+          type: R
+          name: GENERATE_TTC_EMU
+          desc: 1 when TTC emulator is generated
+        - range: 0
+          type: R
+          name: TTC_TEST_MODE
+          desc: 1 when TTC Test mode is anabled
+
+    - name: CR_INTERNAL_LOOPBACK_MODE
+      type: R
+      bitfield:
+        - range: 0
+          desc: 1 when Central Router internal loopback mode is enabled
+
+    - ref: INCLUDE_EGROUP
+      
+
+    - name: WIDE_MODE
+      type: R
+      bitfield:
+        - range: 0
+          desc: GBT is configured in Wide mode
+
+    - name: DEBUG_MODE
+      type: R
+      bitfield:
+        - range: 0
+          desc: |
+            0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
+            1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
+
+    - name: FIRMWARE_MODE
+      type: R
+      bitfield:
+        - range: 3..0
+          desc: |
+            0: GBT mode
+            1: FULL mode
+            2: LTDB mode (GBT mode with only IC and TTC links)
+            3: FEI4 mode
+            4: ITK Pixel
+            5: ITK Strip
+            6: FELIG
+            7: FULL mode emulator
+                        
+    - name: GTREFCLK_SOURCE
+      type: R
+      bitfield:
+        - range: 1..0
+          desc: |
+            0: Transceiver reference Clock source from Si5345
+            1: Transceiver reference Clock source from Si5324
+            2: Transceiver reference Clock from internal BUFG (GREFCLK)
+            
+    - name: CR_GENERICS
+      type: R
+      bitfield:
+        - range: 2
+          name: XOFF_INCLUDED
+          desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
+        - range: 1
+          name: DIRECT_MODE_INCLUDED
+          desc: Indicates that the Direct mode functionality was built in the Central Router
+        - range: 0
+          name: FROM_HOST_INCLUDED
+          desc: Indicates that the From Host path of the Central router was included in the design
+          
+    - name: BLOCKSIZE
+      type: R
+      desc: Number of bytes in a block
+      bitfield:
+        - range: 15..0
+          
+    - name: PCIE_ENDPOINT
+      type: R
+      desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
+      bitfield:
+        - range: 0
+          value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
+
+
+INCLUDE_EGROUP:
+  number: 7
+  entries:
+    - format_name: INCLUDE_EGROUP_{index}
+      name: INCLUDE_EGROUP
+      #type_name: INCLUDE_EGROUP
+      type: R
+      bitfield:
+        - range: 8
+          name: FROMHOST_02
+          desc: FromHost EPROC02 is included in this EGROUP
+        - range: 7
+          name: FROMHOST_04
+          desc: FromHost EPROC04 is included in this EGROUP
+        - range: 6
+          name: FROMHOST_08
+          desc: FromHost EPROC8 is included in this EGROUP
+        - range: 5
+          name: FROMHOST_HDLC
+          desc: FromHost HDLC is included in this EGROUP
+        - range: 4
+          name: TOHOST_02
+          desc: ToHost EPROC02 is included in this EGROUP
+        - range: 3
+          name: TOHOST_04
+          desc: ToHost EPROC04 is included in this EGROUP
+        - range: 2
+          name: TOHOST_08
+          desc: ToHost EPROC08 is included in this EGROUP
+        - range: 1
+          name: TOHOST_16
+          desc: ToHost EPROC16 is included in this EGROUP
+        - range: 0
+          name: TOHOST_HDLC
+          desc: ToHost HDLC is included in this EGROUP
+
+
+CentralRouterControlsAndMonitors:
+  group: CRC
+  desc: Central Router Controls and Monitors
+  endpoints: 0,1
+  entries:
+    - name: IC_FROMHOST_PACKET_RDY
+      type: W
+      bitfield:
+        - range: 23..0
+          desc: Rising edge indicates the complete packet can be read
+
+    - name: TIMEOUT_CTRL
+      type: W
+      descr: Controls the timout mechanism in the ToHost central router.
+      bitfield:
+        - range: 32
+          name: ENABLE
+          default: 1
+          desc: 1 enables the timout trailer generation for ToHost mode
+        - range: 31..0
+          name: TIMEOUT
+          default: 0xFFFFFFFF
+          desc: Number of 40 MHz clock cycles after which a timeout occurs.
+
+    - ref: CR_GBT_CTRL
+      desc: See Central Router Doc
+      offset: 0x0100
+
+    - ref: IC_FIFOS
+      desc: See Central Router Doc
+      offset: 0x1400
+
+    - ref: MINI_EGROUP_CTRL
+      desc: Controls EC and TTC channels of Mini Egroups
+
+    - name: CR_FALLBACK_OPTIONS
+      desc: Julias personal register with Hello Kitty options
+      type: W
+      bitfield:
+        - range: 63..0
+
+    - name: CR_TTC_TOHOST
+      desc: Enables the ToHost Mini Egroup in TTC mode
+      type: W
+      bitfield:
+        - range: 63
+          name: EMU_FAKE_READY_ENABLE
+          default: 0
+        - range: 60..48
+          name: EMU_FAKE_READY_VALUE
+          default: 0x1000
+        - range: 15..4
+          name: TIMEOUT_VALUE
+          default: 0xFFF
+        - range: 2
+          name: EMU_ENABLE
+          default: 0
+        - range: 1
+          name: TIMEOUT_ENABLE
+          default: 1
+        - range: 0
+          name: ENABLE
+          default: 1
+
+    - name: CR_REVERSE_10B
+      desc: Reverse 10-bit word of elink data
+      type: W
+      bitfield:
+        - range: 1
+          name: FROMHOST
+          default: 1
+          desc: |
+                1: Serialize 10-bit word in FromHost EPROCS MSB first
+                0: Serialize 10-bit word in FromHost EPROCS LSB first
+        - range: 0
+          name: TOHOST
+          default: 1
+          desc: |
+                1: Receive 10-bit word in ToHost EPROCS, MSB first
+                0: Receive 10-bit word in ToHost EPROCS, LSB first
+                
+    - name: CR_LTDB_TTC_DELAY
+      desc: Controls TTC BCR delay in LTDB mode firmware
+      type: W
+      bitfield: 
+        - range: 7
+          name: EGROUP4_EPATH6
+          default: 0
+          desc: |
+                Egroup 4, Epath 6
+                1: Half a clock delay
+                0: no delay
+        - range: 6
+          name: EGROUP4_EPATH5
+          default: 0
+          desc: |
+                Egroup 4, Epath 5
+                1: Half a clock delay
+                0: no delay
+        - range: 5
+          name: EGROUP4_EPATH4
+          default: 0
+          desc: |
+                Egroup 4, Epath 4
+                1: Half a clock delay
+                0: no delay
+        - range: 4
+          name: EGROUP4_EPATH3
+          default: 0
+          desc: |
+                Egroup 4, Epath 3
+                1: Half a clock delay
+                0: no delay
+        - range: 3
+          name: EGROUP4_EPATH0
+          default: 0
+          desc: |
+                Egroup 4, Epath 0
+                1: Half a clock delay
+                0: no delay
+        - range: 2
+          name: EGROUP3
+          default: 0
+          desc: |
+                Egroup 3, Epath 0
+                1: Half a clock delay
+                0: no delay
+        - range: 1
+          name: EGROUP2
+          default: 0
+          desc: |
+                Egroup 2, Epath 0
+                1: Half a clock delay
+                0: no delay
+        - range: 0
+          name: EGROUP1
+          default: 0
+          desc: |
+                Egroup 1, Epath 0
+                1: Half a clock delay
+                0: no delay
+#    - ref: CR_XOFF_CTRL
+#      offset: 0x2800
+#      desc: Configure FromHost Xoff
+
+
+#Central Router monitors          
+    - ref: CR_GBT_MON
+      offset: 0x3000
+    - name: CR_STATIC_CONFIGURATION
+      type: R
+      bitfield:
+        - range: 0
+    - ref: CR_DEFAULT_EPROC_ENA
+    - ref: CR_DEFAULT_EPROC_ENCODING
+    - name: MAX_TIMEOUT
+      type: R
+      desc: Maximum allowed timeout value
+      bitfield: 
+        - range: 31..0
+    - ref: CR_BLOCK_COUNTERS
+    
+ 
+CR_GBT_CTRL:
+  number: 24
+  bitfield:
+    - range: 50..0
+  type: W
+  generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+  entries:
+    - ref: EGROUP_TOHOST
+    - ref: EGROUP_FROMHOST
+
+EGROUP_TOHOST:
+  number: 7
+  format_name: GBT{index:02}
+  name: GBT
+  entries:
+    - name: TOHOST
+      format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
+      type_name: CR_TOHOST_EGROUP_CTRL
+      bitfield:
+        - range: 58..51
+          name: INSTANT_TIMEOUT_ENA
+          default: 0x0
+          desc: instantly initiate a timeout for the given epath
+        - range: 50..43
+          name: REVERSE_ELINKS
+          default: 0x0
+          desc: enables bit reversing for the elink in the given epath
+        - range: 42..31
+          name: MAX_CHUNK_LEN
+          default: MAX_CHUNK_LEN_array
+          desc: set the maximum length of a chunk, 0 disables truncation
+        - range: 30..15
+          name: PATH_ENCODING
+          desc: |
+            Encoding for every EPATH, 8 EPATHS per EGROUP
+            0: direct mode
+            1: 8b10b mode
+            2: HDLC mode
+          default: 
+            - PATH_ENCODING_array(0)
+            - PATH_ENCODING_array(1)
+            - PATH_ENCODING_array(2)
+            - PATH_ENCODING_array(3)
+            - PATH_ENCODING_array(4)
+            - PATH_ENCODING_array(5)
+            - PATH_ENCODING_array(6)
+
+        - range: 14..0
+          name: EPROC_ENA
+          desc: Enable bits per EPROC
+          default:
+            - EPROC_ENA_bits_array(0)
+            - EPROC_ENA_bits_array(1)
+            - EPROC_ENA_bits_array(2)
+            - EPROC_ENA_bits_array(3)
+            - EPROC_ENA_bits_array(4)
+            - EPROC_ENA_bits_array(5)
+            - EPROC_ENA_bits_array(6)
+      
+EGROUP_FROMHOST:
+  number: 5
+  format_name: GBT{index:02}
+  entries:
+    - name: FROMHOST
+      desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
+      format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
+      type_name: CR_FROMHOST_EGROUP_CTRL
+      bitfield:
+        - range: 54..47
+          name: REVERSE_ELINKS
+          default: 0x0
+          desc: enables bit reversing for the elink in the given epath
+        - range: 46..15
+          name: PATH_ENCODING
+          desc: |
+            Encoding for every EPATH, 8 EPATHS per EGROUP
+            0: direct mode
+            1: 8b10b mode
+            2: HDLC mode
+            greater than 3: TTC mode, see CentralRouter doc
+          default:
+            - FROMHOST_PATH_ENCODING_array(0)
+            - FROMHOST_PATH_ENCODING_array(1)
+            - FROMHOST_PATH_ENCODING_array(2)
+            - FROMHOST_PATH_ENCODING_array(3)
+            - FROMHOST_PATH_ENCODING_array(4)
+            - FROMHOST_PATH_ENCODING_array(5)
+            - FROMHOST_PATH_ENCODING_array(6)
+        - range: 14..0
+          desc: Enable bits per EPROC
+          name: EPROC_ENA
+
+#CR_XOFF_CTRL:
+#  number: 24
+#  type: W
+#  bitfield:
+#    - range: 39..0
+#  entries:
+#    - name: FROMHOST_XOFF_ENABLE
+#      format_name: FROMHOST_XOFF_ENABLE_{index:02}
+#      desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
+#      range: 39..0
+#      default: 0
+#    - name: FROMHOST_SOFT_XOFF
+#      format_name: FROMHOST_SOFT_XOFF_{index:02}
+#      desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
+#      range: 39..0
+#      default: 0
+
+
+IC_FIFOS:
+  number: 24
+  format_name: IC_FROMHOST_TOHOST_FIFOS
+  entries:
+    - name: FROMHOST
+      format_name: IC_FROMHOST_FIFO_{index:02}
+      type_name: IC_FROMHOST_FIFO
+      type: W
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: any
+          type: T
+          value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
+          name: WE
+          format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+          desc: Any write to this register will trigger a write to the FIFO
+        - range: 8
+          type: R
+          name: FULL
+          format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+          desc: Full flag of the fifo, do not write if 1
+        - range: 7..0
+          type: W
+          name: DATAIN
+          format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+          desc: Data input of fifo
+    - name: TOHOST
+      format_name: IC_TOHOST_FIFO_{index:02}
+      type_name: IC_TOHOST_FIFO
+      type: W
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: any
+          type: T
+          value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
+          name: RE
+          format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+          desc: Any write to this register will trigger a read enable from the fifo
+        - range: 8
+          type: R
+          name: EMPTY
+          format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+          desc: Empty flag of the fifo, do not read if 1
+        - range: 7..0
+          type: R
+          name: DATAOUT
+          format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+          desc: Data output of fifo
+
+
+MINI_EGROUP_CTRL:
+  number: 24
+  format_name: MINI_EGROUP_CTRLS
+  entries:
+    - name: EC_TOHOST
+      format_name: EC_TOHOST_{index:02}
+      type_name: EC_TOHOST
+      desc: Configures the ToHost Mini egroup in EC mode
+      type: W
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: 7
+          name: SCA_AUX_BIT_SWAPPING
+          desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
+          default: 0
+        - range: 6
+          name: SCA_AUX_ENABLE
+          desc: Enables the SCA AUX channel
+          default: 1
+        - range: 5
+          name: IC_BIT_SWAPPING
+          desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
+          default: 1
+        - range: 4
+          name: IC_ENABLE
+          desc: Enables the IC channel
+          default: 1
+        - range: 3
+          name: BIT_SWAPPING
+          desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
+          default: 0
+        - range: 2..1
+          name: ENCODING
+          desc: Configures encoding of the EC channel
+          default: 0x2
+        - range: 0
+          name: ENABLE
+          desc: Enables the EC channel
+          default: 1
+    - name: EC_FROMHOST
+      format_name: EC_FROMHOST_{index:02}
+      type_name: EC_FROMHOST
+      type: W
+      desc: Configures the FromHost Mini egroup in EC mode
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: 9
+          name: SCA_AUX_BIT_SWAPPING
+          desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
+          default: 0
+        - range: 8
+          name: SCA_AUX_ENABLE
+          desc: Enables the SCA AUX channel
+          default: 1
+        - range: 7
+          name: IC_BIT_SWAPPING
+          desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
+          default: 1
+        - range: 6
+          name: IC_ENABLE
+          desc: Enables the IC channel
+          default: 1
+        - range: 5
+          name: BIT_SWAPPING
+          desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
+          default: 0
+        - range: 4..1
+          name: ENCODING
+          desc: Configures encoding of the EC channel
+          default: 0x2
+        - range: 0
+          name: ENABLE
+          default: 1
+
+
+CR_GBT_MON:
+  desc: See Central Router Doc
+  endpoints: 0
+  number: 24
+  entries:
+    - name: TOHOST
+      type_name: TOHOST
+      format_name: CR_{name}_GBT{index:02}_MON
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: 58
+          name: CROUTFIFO_PROG_FULL
+        - range: 57
+          name: WMFIFO_FULL
+        - range: 56
+          name: MINI_EGROUP_ALMOST_FULL
+        - range: 55..48
+          name: EPATH6_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP6
+        - range: 47..40
+          name: EPATH5_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP5
+        - range: 39..32
+          name: EPATH4_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP4
+        - range: 31..24
+          name: EPATH3_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP3
+        - range: 23..16
+          name: EPATH2_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP2
+        - range: 15..8
+          name: EPATH1_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP1
+        - range: 7..0
+          name: EPATH0_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP0
+    - name: FROMHOST
+      type_name: FROMHOST
+      format_name: CR_{name}_GBT{index:02}_MON
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      bitfield:
+        - range: 40
+          name: MINI_EGROUP_ALMOST_FULL
+        - range: 39..32
+          name: EPATH4_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP4
+        - range: 31..24
+          name: EPATH3_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP3
+        - range: 23..16
+          name: EPATH2_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP2
+        - range: 15..8
+          name: EPATH1_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP1
+        - range: 7..0
+          name: EPATH0_ALMOST_FULL
+          desc: Almost full bits of the EPATH fifos in EGROUP0
+      
+CR_DEFAULT_EPROC_ENA:
+  desc: Static CR default enable bits
+  endpoints: 0,1
+  number: 8
+  type: R
+  bitfield:
+    - range: 14..0
+  entries:
+    - name: ENABLE
+      format_name: CR_DEFAULT_EPROC_ENA{index}
+      
+CR_DEFAULT_EPROC_ENCODING:
+  desc: Static CR default encoding bits
+  endpoints: 0,1
+  number: 8
+  type: R
+  bitfield:
+    - range: 15..0
+  entries:
+    - name: ENCODING
+      format_name: CR_DEFAULT_EPROC_ENCODING{index}      
+
+CR_BLOCK_COUNTERS:
+  desc: Counters to count blocks per GBT channel
+  endpoints: 0,1
+  number: 24
+  entries:
+    - name: BLOCK_COUNT
+      type_name: CR_BLOCK_COUNT
+      format_name: CR_{name}_GBT{index:02}
+      generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
+      type: W
+      bitfield:
+        - range: any
+          type: T
+          name: RESET
+          desc: Any write clears the counter value
+          value: 1
+        - range: 31..0
+          type: R
+          name: VAL
+          desc: Counts the number of blocks that were transferred ToHost in the specified GBT
+
+GBTEmulatorControlsAndMonitors:
+  group: GEC
+  desc: GBT Emulator Controls and Monitors
+  endpoints: 0
+  entries:
+    - name: GBT_EMU_ENA
+      type: W
+      bitfield:
+        - range: 1
+          name: TOFRONTEND
+          desc: Enable GBT dummy emulator ToFrontEnd
+        - range: 0
+          name: TOHOST
+          desc: Enable GBT dummy emulator ToHost
+
+    - name: GBT_EMU_CONFIG_WE_ARRAY
+      type: W
+      bitfield:
+        - range: 6..0
+          desc: write enable array, every bit is one emulator RAM block
+
+    - name: GBT_EMU_CONFIG
+      type: W
+      bitfield:
+        - range: 63..48
+          name: RDDATA
+          type: R
+          desc: read data bus
+        - range: 45..32
+          name: WRADDR
+          desc: write address bus
+        - range: 15..0
+          name: WRDATA
+          desc: write data bus
+
+    - name: GBT_FM_EMU_ENA_TOHOST
+      type: W
+      bitfield:
+        - range: 0
+          desc: Enable FULL mode dummy emulator ToHost
+
+    - name: GBT_FM_EMU_CONFIG_WE_ARRAY
+      type: W
+      bitfield:
+        - range: 0
+          desc: write enable for the full mode emulator ram block
+
+    - name: GBT_FM_EMU_CONFIG
+      type: W
+      bitfield:
+        - range: 53..40
+          name: WRADDR
+          desc: write address bus
+        - range: 35..0
+          name: WRDATA
+          desc: write data bus
+
+    - name: GBT_FM_EMU_READ
+      type: R
+      bitfield:
+        - range: 35..0
+          desc: read emu ram data
+
+
+    - name: CR_FM_PATH_ENA
+      type: W
+      bitfield:
+        - range: 11..0
+          desc: FULL mode CR enable array, every bit is one path
+
+
+GBTWrapperControls:
+  group: GWC
+  desc: GBT Wrapper Controls
+  type: W
+  endpoints: 0
+  entries:
+    - name: GBT_CHANNEL_DISABLE
+      offset: 0x0400
+      bitfield:
+        - range: 47..0
+          desc: Disable selected GBT or FULL mode channel
+
+    - name: GBT_GENERAL_CTRL
+      bitfield:
+        - range: 63..0
+          desc: Alignment chk reset (not self clearing)
+
+    - name: GBT_MODE_CTRL
+      bitfield:
+        - range: 2
+          name: RX_ALIGN_TB_SW
+          desc: RX_ALIGN_TB_SW
+        - range: 1
+          name: RX_ALIGN_SW
+          desc: RX_ALIGN_SW
+        - range: 0
+          name: DESMUX_USE_SW
+          desc: DESMUX_USE_SW
+
+    - name: GBT_RXSLIDE_SELECT
+      offset: 0x0480
+      desc: RxSlide select [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RXSLIDE_MANUAL
+      desc: RxSlide select [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+      
+    - name: GBT_TXUSRRDY
+      desc: TxUsrRdy [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+          default: 0xFFFFFFFFFFFF
+
+    - name: GBT_RXUSRRDY
+      desc: RxUsrRdy [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+          default: 0xFFFFFFFFFFFF
+
+    - name: GBT_SOFT_RESET
+      desc: SOFT_RESET [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_GTTX_RESET
+      desc: GTTX_RESET [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_GTRX_RESET
+      desc: GTRX_RESET [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_PLL_RESET
+      bitfield:
+        - range: 59..48
+          name: QPLL_RESET
+          desc: QPLL_RESET [11:0]
+        - range: 47..0
+          name: CPLL_RESET
+          desc: CPLL_RESET [47:0]
+
+    - name: GBT_SOFT_TX_RESET
+      offset: 0x0500
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 59..48
+          name: RESET_ALL
+          desc: SOFT_TX_RESET_ALL [11:0]
+        - range: 47..0
+          name: RESET_GT
+          desc: SOFT_TX_RESET_GT [47:0]
+
+    - name: GBT_SOFT_RX_RESET
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 59..48
+          name: RESET_ALL
+          desc: SOFT_TX_RESET_ALL [11:0]
+        - range: 47..0
+          name: RESET_GT
+          desc: SOFT_TX_RESET_GT [47:0]
+
+    - name: GBT_ODD_EVEN
+      desc: OddEven [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TOPBOT
+      desc: TopBot [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TX_TC_DLY_VALUE1
+      bitfield:
+        - range: 47..0
+          default: 0x333333333333
+          desc: TX_TC_DLY_VALUE [47:0]
+
+    - name: GBT_TX_TC_DLY_VALUE2
+      bitfield:
+        - range: 47..0
+          default: 0x333333333333
+          desc: TX_TC_DLY_VALUE [95:48]
+
+    - name: GBT_TX_TC_DLY_VALUE3
+      bitfield:
+        - range: 47..0
+          default: 0x333333333333
+          desc: TX_TC_DLY_VALUE [143:96]
+
+    - name: GBT_TX_TC_DLY_VALUE4
+      bitfield:
+        - range: 47..0
+          default: 0x333333333333
+          desc: TX_TC_DLY_VALUE [191:144]
+
+    - name: GBT_DATA_TXFORMAT1
+      desc: DATA_TXFORMAT [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_DATA_TXFORMAT2
+      desc: DATA_TXFORMAT [95:48]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_DATA_RXFORMAT1
+      desc: DATA_RXFORMAT [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_DATA_RXFORMAT2
+      desc: DATA_RXFORMAT [95:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TX_RESET
+      desc: TX Logic reset [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RX_RESET
+      desc: RX Logic reset [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TX_TC_METHOD
+      desc: TX time domain crossing method [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_OUTMUX_SEL
+      desc: Descrambler output MUX selection [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TC_EDGE
+      desc: Sampling edge selection for TX domain crossing [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TXPOLARITY
+      desc: |
+        0: default polarity
+        1: reversed polarity for transmitter of GTH channels
+      bitfield:
+        - range: 47..0
+          default: 0
+
+    - name: GBT_RXPOLARITY
+      desc: |
+        0: default polarity
+        1: reversed polarity for the receiver of the GTH channels
+      bitfield:
+        - range: 47..0
+          default: 0
+
+    - name: GTH_LOOPBACK_CONTROL
+      bitfield:
+        - range: 2..0
+          default: 0x0
+          desc: |
+            Controls loopback  for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
+              000: Normal operation
+              001: Near-End PCS Loopback
+              010: Near-End PMA Loopback
+              011: Reserved
+              100: Far-End PMA Loopback
+              101: Reserved
+              110: Far-End PCS Loopback 
+
+    - name: GBT_TOHOST_FANOUT
+      offset: 0x0700
+      bitfield:
+        - range: 48
+          name: LOCK
+          default: 0x0
+          desc: Locks this particular register. If set prevents software from touching it.
+        - range: 47..0
+          name: SEL
+          default: 0xFFFFFFFFFFFF
+          desc: |
+            ToHost FanOut/Selector. Every bitfield is a channel:
+              1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
+              0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
+
+    - name: GBT_TOFRONTEND_FANOUT
+      bitfield:
+        - range: 48
+          name: LOCK
+          default: 0x0
+          desc: Locks this particular register. If set prevents software from touching it.
+        - range: 47..0
+          name: SEL
+          default: 0xFFFFFFFFFFFF
+          desc: |
+            ToFrontEnd FanOut/Selector. Every bitfield is a channel:
+              1 : GBT_EMU, select GBT Emulator for a specific GBT link
+              0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
+              
+
+GBTWrapperMonitors:
+  group: GWM
+  desc: GBT Wrapper Monitors
+  endpoints: 0
+  entries:
+    - name: GBT_VERSION
+      offset: 0x0600
+      bitfield:
+        - range: 63..48
+          name: DATE
+          desc: Date
+        - range: 47..32
+          name: GBT_VERSION
+          desc: GBT Version
+        - range: 31..16
+          name: GTH_IP_VERSION
+          desc: GTH IP Version
+        - range: 15..3
+          name: RESERVED
+          desc: Reserved
+        - range: 2
+          name: GTHREFCLK_SEL
+          desc: GTHREFCLK SEL
+        - range: 1
+          name: RX_CLK_SEL
+          desc: RX CLK SEL
+        - range: 0
+          name: PLL_SEL
+          desc: PLL SEL
+
+    - name: GBT_TXRESET_DONE
+      offset: 0x0680
+      desc: TX Reset done [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RXRESET_DONE
+      desc: RX Reset done [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_TXFSMRESET_DONE
+      desc: TX FSM Reset done [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RXFSMRESET_DONE
+      desc: RX FSM Reset done [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_CPLL_FBCLK_LOST
+      desc: CPLL FBCLK LOST [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_PLL_LOCK
+      bitfield:
+        - range: 59..48
+          name: QPLL_LOCK
+          desc: QPLL LOCK [11:0]
+        - range: 47..0
+          name: CPLL_LOCK
+          desc: CPLL LOCK [47:0]
+
+    - name: GBT_RXCDR_LOCK
+      desc: RX CDR LOCK [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_CLK_SAMPLED
+      desc: clk sampled [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RX_IS_HEADER
+      desc: RX IS HEADER [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RX_IS_DATA
+      desc: RX IS DATA [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_RX_HEADER_FOUND
+      desc: RX HEADER FOUND [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_ALIGNMENT_DONE
+      desc: RX ALIGNMENT DONE [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_OUT_MUX_STATUS
+      desc: GBT output mux status [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_ERROR
+      desc: Error flags [47:0]
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_GBT_TOPBOT_C
+      desc: TopBot_c [47:0]
+      generate: GBT_GENERATE_ALL_REGS = true
+      bitfield:
+        - range: 47..0
+
+    - name: GBT_FM_RX_DISP_ERROR1
+      offset: 0x0800
+      bitfield:
+        - range: 47..0
+          desc: Rx disparity error [47:0]
+
+    - name: GBT_FM_RX_DISP_ERROR2
+      bitfield:
+        - range: 47..0
+          desc: Rx disparity error [96:48]
+
+    - name: GBT_FM_RX_NOTINTABLE1
+      bitfield:
+        - range: 47..0
+          desc: Rx not in table [47:0]
+
+    - name: GBT_FM_RX_NOTINTABLE2
+      bitfield:
+        - range: 47..0
+          desc: Rx not in table [96:48]
+
+TTCBUSYControlsAndMonitors:
+  group: TTCBUSY
+  desc: TTC and BUSY Controls and Monitors
+  endpoints: 0
+  entries:
+
+    - ref: TTC_DEC_CTRLMON
+      desc: control and monitor bits for TTC decoder
+
+    - ref: TTC_BUSY_ACCEPTED
+
+    - name: TTC_EMU
+      type: W
+      bitfield:
+        - range: 2
+          name: FULL
+          type: R
+          desc: TTC Emulator memory full indication
+        - range: 1
+          name: SEL
+          desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
+        - range: 0
+          name: ENA
+          desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
+
+    - ref: TTC_DELAY
+ 
+    - name: TTC_BUSY_TIMING_CTRL
+      descr: Controls the BUSY Logic
+      type: W
+      bitfield:
+        - range: 51..32
+          name: PRESCALE
+          default: 0x0000F
+          desc: Prescales the 40MHz clock to create an internal slow clock
+        - range: 31..16
+          name: BUSY_WIDTH
+          default: 0x000F
+          desc: Minimum number of 40MHz clocks that the busy is asserted
+        - range: 15..0
+          name: LIMIT_TIME
+          default: 0x000F
+          desc: Number of prescaled clocks a given busy must be asserted before it is recognized
+    
+    - name: TTC_BUSY_CLEAR
+      desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
+      type: T
+      value: 1
+      bitfield:
+        - range: any
+        
+    - name: TTC_EMU_CONTROL
+      type: W
+      bitfield:
+        - range: any
+          name: WE
+          type: T
+          desc: Any write to this register executes a write enable
+          value: 1
+        - range: 35
+          name: LAST_LINE
+          desc: Last line of the sequence
+        - range: 34
+          name: REPEAT
+          desc: Repeat the sequence
+        - range: 32
+          name: BROADCAST5
+          desc: Broadcast 5
+        - range: 31
+          name: BROADCAST4
+          desc: Broadcast 4
+        - range: 30
+          name: BROADCAST3
+          desc: Broadcast 3
+        - range: 29
+          name: BROADCAST2
+          desc: Broadcast 2
+        - range: 28
+          name: BROADCAST1
+          desc: Broadcast 1
+        - range: 27
+          name: BROADCAST0
+          desc: Broadcast 0
+        - range: 26
+          name: ECR
+          desc: Event counter reset
+        - range: 25
+          name: BCR
+          desc: Bunch counter reset
+        - range: 24
+          name: L1A
+          desc: Level 1 Accept
+        - range: 21..0
+          name: STEP_COUNTER
+          desc: Step counter value
+        
+TTC_DEC_CTRLMON:
+  group: TDCM 
+  format_name: TTC_DEC_CTRLMON
+  entries:
+    - name: TTC_DEC_CTRL
+      format_name: TTC_DEC_CTRL
+      type_name: TTC_DEC_CTRLS
+      type: W
+      bitfield:
+        - range: 26..15
+          name: BCID_ONBCR
+          type: W
+          desc: BCID is set to this value when BCR arrives
+        - range: 14
+          name: BUSY_OUTPUT_STATUS
+          type: R
+          desc: Actual status of the BUSY LEMO output signal
+        - range: 13
+          name: ECR_BCR_SWAP
+          default: 0
+          desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
+        - range: 12
+          name: BUSY_OUTPUT_INHIBIT
+          default: 0
+          desc: forces the Busy LEMO output to BUSY-OFF
+        - range: 11
+          name: TOHOST_RST
+          desc: reset toHost in ttc decoder
+          default: 0
+        - range: 10
+          name: TT_BCH_EN
+          desc: trigger type enable / disable for TTC-ToHost
+          default: 1
+        - range: 9..2
+          name: XL1ID_SW
+          desc: set XL1ID value, the value to be set by XL1ID_RST signal
+          default: 0x00
+        - range: 1
+          name: XL1ID_RST
+          desc: giving a trigger signal to reset XL1ID value
+          default: 0
+        - range: 0 
+          name: MASTER_BUSY
+          desc: L1A trigger throttling
+          default: 0
+    - name: TTC_DEC_MON
+      format_name: TTC_DEC_MON
+      type_name: TTC_DEC_MONS
+      type: R 
+      bitfield:
+        - range: 15..5
+          name: TH_FF_COUNT
+          desc: ToHostData Fifo counts
+        - range: 4
+          name: TH_FF_FULL
+          desc: ToHostData Fifo status 1:full 0:not full
+        - range: 3 
+          name: TH_FF_EMPTY
+          desc: ToHostData Fifo status 1:empty 0:not empty
+        - range: 2..0
+          name: TTC_BIT_ERR
+          desc: double bit, single bit and comm error in TTC data
+
+TTC_BUSY_ACCEPTED:
+  desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+  number: 24
+  endpoints: 0,1
+  type: R
+  bitfield: 
+    - range: 56..0
+  entries:
+    - name: BUSY_ACCEPTED
+      format_name: TTC_BUSY_ACCEPTED{index:02}
+
+
+TTC_DELAY:
+  number: 48
+  type: W
+  entries:
+    - name: TTC_DELAY
+      format_name: TTC_DELAY_{index:02}
+      type_name: TTC_DELAY
+      desc: Controls the TTC Fanout delay values
+      bitfield:
+        - range: 3..0
+          default: 0
+          
+XOFF_BUSYControlsAndMonitors:
+  group: XOFF
+  desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
+  endpoints: 0, 1
+  entries:
+    - name: XOFF_FM_CH_FIFO_THRESH_LOW
+      desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
+      type: W
+      bitfield:
+        - range: 47..44
+          name: CH11
+          default: 0xB
+        - range: 43..40
+          name: CH10
+          default: 0xB
+        - range: 39..36
+          name: CH09
+          default: 0xB
+        - range: 35..32
+          name: CH08
+          default: 0xB
+        - range: 31..28
+          name: CH07
+          default: 0xB
+        - range: 27..24
+          name: CH06
+          default: 0xB
+        - range: 23..20
+          name: CH05
+          default: 0xB
+        - range: 19..16
+          name: CH04
+          default: 0xB
+        - range: 15..12
+          name: CH03
+          default: 0xB
+        - range: 11..8
+          name: CH02
+          default: 0xB
+        - range: 7..4
+          name: CH01
+          default: 0xB
+        - range: 3..0
+          name: CH00
+          default: 0xB
+          
+    - name: XOFF_FM_CH_FIFO_THRESH_HIGH
+      desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
+      type: W
+      bitfield:
+        - range: 47..44
+          name: CH11
+          default: 0xB
+        - range: 43..40
+          name: CH10
+          default: 0xB
+        - range: 39..36
+          name: CH09
+          default: 0xB
+        - range: 35..32
+          name: CH08
+          default: 0xB
+        - range: 31..28
+          name: CH07
+          default: 0xB
+        - range: 27..24
+          name: CH06
+          default: 0xB
+        - range: 23..20
+          name: CH05
+          default: 0xB
+        - range: 19..16
+          name: CH04
+          default: 0xB
+        - range: 15..12
+          name: CH03
+          default: 0xB
+        - range: 11..8
+          name: CH02
+          default: 0xB
+        - range: 7..4
+          name: CH01
+          default: 0xB
+        - range: 3..0
+          name: CH00
+          default: 0xB  
+          
+    - name: XOFF_FM_LOW_THRESH_CROSSED
+      desc: FIFO filled beyond the low threshold, 1 bit per channel
+      type: R
+      bitfield:
+        - range: 11..0
+    - name: XOFF_FM_HIGH_THRESH
+      type: W
+      bitfield:
+        - range: any
+          name: CLEAR_LATCH
+          desc: Writing this register will clear all CROSS_LATCHED bits
+          type: T
+          value: 1
+        - range: 23..12    
+          type: R
+          name: CROSS_LATCHED
+          desc: FIFO filled beyond the high threshold, 1 latch bit per channel
+        - range: 11..0
+          type: R
+          name: CROSSED
+          desc: FIFO filled beyond the high threshold, 1 bit per channel
+        
+    - name: XOFF_FM_SOFT_XOFF
+      type: W
+      desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
+      bitfield:
+        - range: 23..0 
+        
+    - name: XOFF_ENABLE
+      type: W
+      desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
+      bitfield:
+        - range: 23..0
+
+    - name: DMA_BUSY_STATUS
+      type: W
+      bitfield:
+        - range: any
+          type: T
+          value: 1
+          name: CLEAR_LATCH
+          desc: Any write to this register clears TOHOST_BUSY_LATCHED
+        - range: 4
+          type: W
+          name: ENABLE
+          desc: Enable the DMA buffer on the server as a source of busy
+          default: 0
+        - range: 3
+          type: R
+          name: TOHOST_BUSY_LATCHED
+          desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
+          value: (others => tohost_busy_latched_40_s) 
+        - range: 2
+          type: R
+          name: FROMHOST_BUSY_LATCHED
+          desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
+          value: (others => fromhost_busy_latched_40_s) 
+        - range: 1
+          type: R
+          name: FROMHOST_BUSY
+          desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+          value: (others => fromhost_busy_40_s)
+        - range: 0
+          type: R
+          name: TOHOST_BUSY
+          desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+          value: (others => tohost_busy_40_s)
+    
+    - name: FM_BUSY_CHANNEL_STATUS
+      type: W
+      bitfield:
+        - range: any
+          name: CLEAR_LATCH
+          type: T
+          value: 1
+          desc: Any write to this register will clear the BUSY_LATCHED bits
+        - range: 23..12
+          type: R
+          name: BUSY_LATCHED
+          desc: one Indicates that the given FULL mode channel has received BUSY-ON
+        - range: 11..0
+          type: R
+          name: BUSY
+          desc: one Indicates that the given FULL mode channel is currently in BUSY state
+          
+    - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
+      type: W
+      bitfield:
+        - range: 24
+          name: BUSY_ENABLE
+          desc: Enable busy generation if thresholds are crossed
+          default: 0
+        - range: 23..12
+          name: LOW
+          desc: Low, Negate threshold of busy generation from main output fifo
+          default: 0x3FF
+        - range: 11..0
+          name: HIGH
+          desc: High, Assert threshold of busy generation from main output fifo
+          default: 0x4FF
+          
+    - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
+      type: W
+      bitfield:
+        - range: any
+          name: CLEAR_LATCHED
+          value: 1
+          desc: Any write to this register will clear the 
+          type: T
+        - range: 2
+          type: R
+          name: HIGH_THRESH_CROSSED_LATCHED
+          desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
+        - range: 1
+          type: R
+          name: HIGH_THRESH_CROSSED
+          desc: Main output fifo is full beyond HIGH THRESHOLD
+        - range: 0
+          type: R
+          name: LOW_THRESH_CROSSED
+          desc: Main output fifo is full beyond LOW THRESHOLD
+    - ref: ELINK_BUSY_ENABLE
+    
+          
+ELINK_BUSY_ENABLE:
+  desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+  number: 24
+  endpoints: 0
+  type: W
+  bitfield: 
+    - range: 56..0
+  entries:
+    - name: ELINK_BUSY_ENABLE
+      format_name: ELINK_BUSY_ENABLE{index:02}          
+
+HouseKeepingControlsAndMonitors:
+  group: HKC
+  desc: House Keeping Controls and Monitors
+  endpoints: 0
+  entries:
+ 
+    - name: HK_CTRL_I2C
+      type: W
+      bitfield:
+        - range: 1
+          name: CONFIG_TRIG
+          desc: i2c_config_trig
+        - range: 0
+          name: CLKFREQ_SEL
+          desc: i2c_clkfreq_sel
+
+    - name: HK_CTRL_FMC
+      type: W
+      bitfield:
+        - range: 7
+          name: SI5345_LOL
+          type: R
+          desc: Loss of lock pin, only connected on FLX711
+        - range: 6..5
+          name: SI5345_INSEL
+          default: 0x0
+          desc: |
+            Selects the input clock source
+              0 : FPGA (FMC LA01)
+              1 : FMC OSC (40.079 MHz)
+              2 : FPGA (FMC LA18)
+        - range: 4..3
+          name: SI5345_A
+          default: 0x0
+          desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
+        - range: 2
+          name: SI5345_OE
+          default: 0x1
+          desc: Si5345 active low output enable  (0:enable)
+        - range: 1
+          name: SI5345_RSTN
+          default: 0x0
+          desc: Si5345 active low output enable  (0:reset)
+        - range: 0
+          name: SI5345_SEL
+          default: 0x1
+          desc: |
+            Si5345 programming mode
+              1 : I2C mode (default)
+              0 : SPI mode
+
+    - name: HK_MON_FMC
+      type: W
+      bitfield:
+        - range: 1
+          name: SI5345_LOL
+          desc: Si5345 Loss Of Lock pin
+        - range: 0
+          name: SI5345_INTR
+          desc: Si5345 Interrupt flagging chip change of status
+
+    - name: MMCM_MAIN
+      type: W
+      offset: 0x0300
+      bitfield:
+        - range: 3
+          type: W
+          name: LCLK_SEL
+          default: 0x1
+          desc: |
+              1: LCLK
+              0: TTC
+        - range: 2..1
+          type: R
+          name: MAIN_INPUT
+          desc: |
+              Main MMCM Oscillator Input
+              2: LCLK fixed
+              1: TTC fixed
+              0: selectable
+        - range: 0
+          type: R
+          name: PLL_LOCK
+          desc: Main MMCM PLL Lock Status
+
+    - name: LMK_LOCKED
+      type: R
+      bitfield:
+        - range: 0
+          desc: LMK Chip on BNL-711 locked
+
+    - name: FPGA_CORE_TEMP
+      type: R
+      bitfield:
+        - range: 11..0
+          desc:  |
+                 XADC temperature monitor for the FPGA CORE
+                 for FLX709, FLX710
+                 temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
+                 for FLX711
+                 temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
+    - name: FPGA_CORE_VCCINT
+      type: R
+      bitfield:
+        - range: 11..0
+          desc:  XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
+    - name: FPGA_CORE_VCCAUX
+      type: R
+      bitfield:
+        - range: 11..0
+          desc:  XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
+    - name: FPGA_CORE_VCCBRAM
+      type: R
+      bitfield:
+        - range: 11..0
+          desc:  XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
+
+    - name: FPGA_DNA
+      type: R
+      bitfield:
+        - range: 63..0
+          desc: Unique identifier of the FPGA
+
+
+    - name: SPI_WR
+      type: W
+      offset: 0x0400
+      bitfield:
+        - range: any
+          type: T
+          value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
+          name: SPI_WREN
+          desc: Any write to this register triggers an SPI Write
+        - range: 32
+          type: R
+          name: SPI_FULL
+          desc: SPI FIFO Full
+        - range: 31..0
+          type: W
+          name: SPI_DIN
+          desc: SPI WRITE Data
+
+    - name: SPI_RD
+      type: T
+      bitfield:
+        - range: any
+          type: T
+          value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
+          name: SPI_RDEN
+          desc: Any write to this register pops the last SPI data from the FIFO
+        - range: 32
+          type: R
+          name: SPI_EMPTY
+          desc: SPI FIFO Empty
+        - range: 31..0
+          type: R
+          name: SPI_DOUT
+          desc: SPI READ Data
+
+    - name: I2C_WR
+      type: W
+      bitfield:
+        - range: any
+          name: I2C_WREN
+          type: T
+          value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
+          desc: Any write to this register triggers an I2C read or write sequence
+        - range: 25
+          type: R
+          name: I2C_FULL
+          desc: I2C FIFO full
+        - range: 24
+          name: WRITE_2BYTES
+          type: W
+          desc: Write two bytes
+        - range: 23..16
+          name: DATA_BYTE2
+          type: W
+          desc: Data byte 2
+        - range: 15..8
+          name: DATA_BYTE1
+          type: W
+          desc: Data byte 1
+        - range: 7..1
+          name: SLAVE_ADDRESS
+          type: W
+          desc: Slave address
+        - range: 0
+          name: READ_NOT_WRITE
+          type: W
+          desc: READ/<o>WRITE</o>
+
+    - name: I2C_RD
+      type: T
+      bitfield:
+        - range: any
+          name: I2C_RDEN
+          type: T
+          value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
+          desc: Any write to this register pops the last I2C data from the FIFO
+        - range: 8
+          type: R
+          name: I2C_EMPTY
+          desc: I2C FIFO Empty
+        - range: 7..0
+          type: R
+          name: I2C_DOUT
+          desc: I2C READ Data
+
+
+    - name: DEBUG_PORT_GBT
+      offset: 0x0500
+      type: W
+      bitfield:
+        - range: 6..0
+          desc: Debug GBT data bit N (119..0) on SMA HTGx#3
+
+    - name: DEBUG_PORT_CLK
+      type: W
+      bitfield:
+        - range: 3..0
+          desc: Debug clock and L1A port on SMA HTGx#4
+
+    - name: INT_TEST_4
+      offset: 0x0800
+      type: T
+      value: 1
+      bitfield:
+        - range: any
+          desc: Fire a test MSIx interrupt \#4
+
+    - name: CONFIG_FLASH_WR
+      type: W
+      bitfield:
+        - range: 57
+          type: W
+          name: FAST_WRITE
+          desc: Write command only. Only used for fast programming.
+        - range: 56
+          type: W
+          name: FAST_READ
+          desc: Status reading without command writing. Only used for fast programming.
+        - range: 55
+          type: W
+          name: PAR_CTRL
+          desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
+        - range: 54..53
+          type: W
+          name: PAR_WR
+          desc: Choose Flash partition. Valid when PAR_CTRL is 1.
+        - range: 52
+          type: W
+          name: FLASH_SEL
+          desc: 1 takes control over flash, 0 gives JTAG control over flash
+        - range: 51
+          type: W
+          name: DO_INIT
+          desc: Untested feature, don't use it yet.
+        - range: 50
+          type: W
+          name: DO_READSTATUS
+          desc: Reads status from flash
+        - range: 49
+          type: W
+          name: DO_CLEARSTATUS
+          desc: Clears status reading from flash, back to normal flash operation
+        - range: 48
+          type: W
+          name: DO_ERASEBLOCK
+          desc: Erased the current block of the flash, this register has to be cleared by software
+        - range: 47
+          name: DO_UNLOCK_BLOCK
+          type: W
+          desc: Unlock writes to the current block, this register has to be cleared by software
+        - range: 46
+          name: DO_READ
+          type: W
+          desc: Reads the 16 bits from current address, this register has to be cleared by software
+        - range: 45
+          name: DO_WRITE
+          type: W
+          desc: Writes the 16 bits to current address, this register has to be cleared by software
+        - range: 44
+          name: DO_READDEVICEID
+          type: W
+          desc: DIN should return 0x0089, this register has to be cleared by software
+        - range: 43
+          name: DO_RESET
+          type: W
+          desc: Can be used in the future, currently disconnected in firmware
+        - range: 42..16
+          name: ADDRESS
+          type: W
+          desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
+        - range: 15..0
+          name: WRITE_DATA
+          type: W
+          desc: Value of data to write towards flash
+    - name: CONFIG_FLASH_RD
+      type: R
+      bitfield:
+        - range: 19..18
+          name: PAR_RD
+          type: R
+          desc: Show which Flash partition is selected.
+        - range: 17
+          name: FLASH_REQ_DONE
+          type: R
+          desc: Request done
+        - range: 16
+          name: FLASH_BUSY
+          type: R
+          desc: Flash operation busy
+        - range: 15..0
+          name: READ_DATA
+          type: R
+          desc: Value of data read from flash
+    - name: SI5324_STATUS
+      type: R
+      bitfield:
+        - range: 15..8
+          name: LOL
+          desc: Loss of Lock Si5324
+        - range: 8..0
+          name: LOS
+          desc: Loss of Signal Si5324
+          
+    - name: TACH_CNT
+      type: R
+      desc: Readout of the Fan tachometer speed of the BNL712 board
+      bitfield:
+        - range: 19..0
+
+Generators:
+  group: GEN
+  desc: Specific registers for Hardware based Generators
+  endpoints: 0
+  generate: EMU_GENERATE_REGS = true
+  entries:
+
+    - ref: FELIG_DATA_GEN_CONFIG_ARR
+      offset: 0x20
+    - ref: FELIG_ELINK_CONFIG_ARR
+    - ref: FELIG_ELINK_ENABLE_ARR
+    
+    - name: FELIG_GLOBAL_CONTROL
+      type: W
+      bitfield:
+        - range: 63..36
+          name: FAKE_L1A_RATE
+          default: 0
+          desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
+        - range: 35..14
+          name: PICXO_OFFSET_PPM
+          default: 0
+          desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
+        - range: 12..12
+          name: TRACK_DATA
+          default: 0
+          desc: FELIG GT core control.  Must be set to enable normal operation.
+        - range: 11..11
+          name: RXUSERRDY
+          default: 0
+          desc: FELIG GT core control.  Must be set to enable normal operation.
+        - range: 10..10
+          name: TXUSERRDY
+          default: 0
+          desc: FELIG GT core control.  Must be set to enable normal operation.
+        - range: 9..9
+          name: AUTO_RESET
+          default: 0
+          desc: FELIG GT core control.  If set the GT core automatically resets on data error.
+        - range: 8..8
+          name: PICXO_RESET
+          default: 0
+          desc: FELIG GT core control.  Manual PICXO reset.
+        - range: 7..7
+          name: GTTX_RESET
+          default: 0
+          desc: FELIG GT core control.  Manual GT TX reset
+        - range: 6..6
+          name: CPLL_RESET
+          default: 0
+          desc: FELIG GT core control.  Manual CPLL reset.
+        - range: 5..0
+          name: X3_X4_OUTPUT_SELECT
+          default: 0
+          desc: X3/X4 SMA output source select.
+    
+    - ref: FELIG_LANE_CONFIG_ARR
+    - ref: FELIG_MON_TTC_0_ARR
+    - ref: FELIG_MON_TTC_1_ARR
+    - ref: FELIG_MON_COUNTERS_ARR
+    - ref: FELIG_MON_FREQ_ARR
+
+    - name: FELIG_MON_FREQ_GLOBAL
+      type: W
+      bitfield:
+        - range: 63..32
+          name:  XTAL_100MHZ
+          default: 0
+          desc: FELIG local oscillator frequency[Hz].
+        - range: 31..0
+          name: CLK_41_667MHZ
+          desc: FELIG PCIE MGTREFCLK frequency[Hz].
+    
+    - ref: FELIG_MON_L1A_ID_ARR
+    - ref: FELIG_MON_PICXO_ARR
+    
+    - name: FELIG_RESET
+      type: W
+      bitfield:
+        - range: 63..48
+          name: LB_FIFO
+          default: 0
+          desc: One bit per lane.  When set to 1, resets all loopback FIFOs.
+        - range: 47..24
+          name: FRAMEGEN
+          default: 0
+          desc: One bit per lane.  When set to 1, resets all FELIG link checking logic.
+        - range: 23..0
+          name: LANE
+          default: 0
+          desc: One bit per lane.  When set to 1, resets all FELIG lane logic.
+    
+    - name: FELIG_RX_SLIDE_RESET
+      type: W
+      bitfield:
+        - range: 23..0
+          default: 0
+          desc: One bit per lane.  When set to 1, resets the gbt rx slide counter.
+          
+    - name: FMEMU_EVENT_INFO
+      type: W
+      offset: 0x1800
+      bitfield:
+        - range: 63..32
+          name: L1ID
+          default: 0
+          desc: 32b field to show L1ID
+        - range: 31..0
+          name: BCID
+          default: 0
+          desc: 32b field to show BCID
+
+    - name: FMEMU_COUNTERS
+      type: W
+      bitfield:
+        - range: 63..48
+          name: WORD_CNT
+          default: 32
+          desc: Number of 32b words in one chunk
+        - range: 47..32
+          name: IDLE_CNT
+          default: 3
+          desc: Minimum number of idles between chunks 
+        - range: 31..16
+          name: L1A_CNT
+          default: 256
+          desc: Number of chunks to send if not in TTC mode
+        - range: 15..8
+          name: BUSY_TH_HIGH
+          default: 20
+          desc: Assert BUSY-ON above this threshold
+        - range: 7..0
+          name: BUSY_TH_LOW
+          default: 15
+          desc: De-assert BUSY-ON below this threshold
+
+    - name: FMEMU_CONTROL
+      type: W
+      bitfield:
+        - range: 63..56
+          type: W
+          name: L1A_BITNR
+          default: 32
+          desc: Bitfield for L1A in TTC frame
+        - range: 55..48
+          type: W
+          name: XONXOFF_BITNR
+          default: 32
+          desc: Bitfield for Xon/Xoff in TTC frame
+        - range: 47..47
+          type: W
+          name: EMU_START
+          default: 0
+          desc: Start emulator functionality
+        - range: 46..46
+          type: W
+          name: TTC_MODE
+          default: 0
+          desc: Control the emulator by TTC input or by RegMap (1/0)
+        - range: 45..45
+          type: W
+          name: XONXOFF
+          default: 0
+          desc: Debug Xon/Xoff functionality (1/0)
+        - range: 44..44
+          type: W
+          name: INLC_CRC32
+          default: 0
+          desc: |
+            0: No checksum
+            1: Append the data with a CRC32
+        - range: 43..43
+          type: W
+          name: BCR
+          default: 0
+          desc: Reset BCID to 0
+        - range: 42..42
+          type: W
+          name: ECR
+          default: 0
+          desc: Reset L1ID to 0
+        - range: 41..41
+          type: W
+          name: DATA_SRC_SEL
+          default: 0
+          desc: | 
+            Data source select
+            0: Data input comes from EMURAM
+            1: Data input comes from PCIe
+        - range: 40..32
+          type: R
+          name: INT_STATUS_EMU
+          default: 0
+          desc: Read internal status emulator
+        - range: 31..16
+          type: W
+          name: FFU_FM_EMU_T
+          default: 0
+          desc: For Future Use (trigger registers)
+        - range: 15..0
+          type: W
+          name: FFU_FM_EMU_W
+          default: 0
+          desc: For Future Use (write registers)
+    
+    - name: FMEMU_RANDOM_RAM_ADDR
+      type: W
+      desc: Controls the address of the ramblock for the random number generator
+      bitfield:
+        - range: 9..0 
+    - name: FMEMU_RANDOM_RAM
+      type: W
+      bitfield:
+        - range: any 
+          type: T 
+          name: WE
+          value: 1
+          desc: Any write to this register (DATA) triggers a write to the ramblock
+        - range: 39..16
+          name: CHANNEL_SELECT
+          value: 0xFFFFFF
+          desc: Enable write enable only for the selected channel
+        - range: 15..0
+          name: DATA
+          type: W
+          desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+    - name: FMEMU_RANDOM_CONTROL
+      type: W
+      desc: Controls the random chunk length generator
+      bitfield:
+        - name: SELECT_RANDOM
+          range: 20
+          desc: 1 enables the random chunk length, 0 uses a constant chunk length
+          default: 0
+        - name: SEED
+          range: 19..10
+          desc: Seed for the random number generator, should not be 0
+          default: 0x200
+        - name: POLYNOMIAL
+          range: 9..0
+          desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
+          default: 0x240
+         
+    
+#Registers that are replicated 24 times under Generators:
+FELIG_DATA_GEN_CONFIG_ARR:
+  number: 24
+  type: W
+  entries:
+    - name: FELIG_DATA_GEN_CONFIG
+      format_name: FELIG_DATA_GEN_CONFIG_{index:02}
+      type_name: FELIG_DATA_GEN_CONFIG
+      desc: FELIG specific configuration test registers
+      bitfield:
+        - name: USERDATA
+          range: 63..48
+          default: 0
+          desc: Sets static payload word. When PATTERN_SEL=1.
+        - name: CHUNK_LENGTH
+          range: 47..32
+          default: 0
+          desc: FELIG data generator chunk-length in bytes.
+        - name: RESET
+          range: 19..15
+          default: 0
+          desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+        - name: SW_BUSY
+          range: 14..10
+          default: 0
+          desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+        - name: DATA_FORMAT
+          range: 9..5
+          default: 0
+          desc: FELIG data generator format. 0:8b10b, 1:direct.
+        - name: PATTERN_SEL
+          range: 4..0
+          default: 0
+          desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+    
+FELIG_ELINK_CONFIG_ARR:
+  number: 24
+  type: W
+  entries:
+    - name: FELIG_ELINK_CONFIG
+      format_name: FELIG_ELINK_CONFIG_{index:02}
+      type_name: FELIG_ELINK_CONFIG
+      desc: FELIG specific configuration test registers
+      bitfield:
+        - name: ENDIAN_MOD
+          range: 39..35
+          default: 0
+          desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+        - name: INPUT_WIDTH
+          range: 34..30
+          default: 0
+          desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+        - name: OUTPUT_WIDTH
+          range: 9..0
+          default: 0
+          desc: FELIG elink data output width.
+          
+FELIG_ELINK_ENABLE_ARR:
+  number: 24
+  type: W
+  entries:
+    - name: FELIG_ELINK_ENABLE
+      format_name: FELIG_ELINK_ENABLE_{index:02}
+      type_name: FELIG_ELINK_ENABLE
+      desc: FELIG specific configuration registers
+      bitfield:
+        - range: 39..0
+          default: 0
+          desc: FELIG elink enable.  One bit per elink. 0:disabled, 1:enabled.
+    
+FELIG_LANE_CONFIG_ARR:
+  number: 24
+  type: W
+  entries:
+    - name: FELIG_LANE_CONFIG
+      format_name: FELIG_LANE_CONFIG_{index:02}
+      type_name: FELIG_LANE_CONFIG
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: B_CH_BIT_SEL
+          range: 63..42
+          default: 0
+          desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+        - name: A_CH_BIT_SEL
+          range: 41..35
+          default: 0
+          desc: Selects the bit from the received FELIX data from which to extract the L1A.
+        - name: LB_FIFO_DELAY
+          range: 34..30
+          default: 0
+          desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+        - name: ELINK_SYNC
+          range: 7..7
+          default: 0
+          desc: When set, synchronizes the elink word boundaries.  Must be set back to 0 to resume normal operation.
+        - name: PICXO_OFFEST_EN
+          range: 6..6
+          default: 0
+          desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+        - name: PI_HOLD
+          range: 5..5
+          default: 0
+          desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+        - name: GBT_LB_ENABLE
+          range: 4..4
+          default: 0
+          desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+        - name: GBH_LB_ENABLE
+          range: 3..3
+          default: 0
+          desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+        - name: L1A_SOURCE
+          range: 2..2
+          default: 0
+          desc: FELIG L1A data source select.  0:from local counter, 1:from FELIX.
+        - name: GBT_EMU_SOURCE
+          range: 1..1
+          default: 0
+          desc: FELIG emulation data source select.  0:state-machine emulator, 1:ram-based emulator.
+        - name: FG_SOURCE
+          range: 0..0
+          default: 0
+          desc: FELIG link check data source selection control.  0:normal operation, 1:PRBS link checker (not elink emulation data) 
+    
+FELIG_MON_TTC_0_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_TTC_0
+      format_name: FELIG_MON_TTC_0_{index:02}
+      type_name: FELIG_MON_TTC_0
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: L1ID
+          range: 63..40
+          default: 0
+          desc: Live TTC data monitor.
+        - name: XL1ID
+          range: 39..32
+          default: 0
+          desc: Live TTC data monitor.
+        - name: BCID
+          range: 31..20
+          default: 0
+          desc: Live TTC data monitor.
+        - name: RESERVED0
+          range: 19..16
+          default: 0
+          desc: Live TTC data monitor.
+        - name: LEN
+          range: 15..8
+          default: 0
+          desc: Live TTC data monitor.
+        - name: FMT
+          range: 7..0
+          default: 0
+          desc: Live TTC data monitor.
+    
+FELIG_MON_TTC_1_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_TTC_1
+      format_name: FELIG_MON_TTC_1_{index:02}
+      type_name: FELIG_MON_TTC_1
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: RESERVED1
+          range: 63..48
+          default: 0
+          desc: Live TTC data monitor.
+        - name: TRIGGER_TYPE
+          range: 47..32
+          default: 0
+          desc: Live TTC data monitor.
+        - name: ORBIT
+          range: 31..0
+          default: 0
+          desc: Live TTC data monitor.
+    
+FELIG_MON_COUNTERS_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_COUNTERS
+      format_name: FELIG_MON_COUNTERS_{index:02}
+      type_name: FELIG_MON_COUNTERS
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: SLIDE_COUNT
+          range: 63..32
+          default: 0
+          desc: Counts the number of rx slides commanded by the GBT logic.  Should be static once a link is established.
+        - name: FC_ERROR_COUNT
+          range: 31..0
+          default: 
+          desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+    
+FELIG_MON_FREQ_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_FREQ
+      format_name: FELIG_MON_FREQ_{index:02}
+      type_name: FELIG_MON_FREQ
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: TX
+          range: 63..32
+          default: 0
+          desc: FELIG regenerated TX clock frequency[Hz].
+        - name: RX
+          range: 31..0
+          default: 0
+          desc: FELIG recovered RX clock frequency[Hz].
+    
+FELIG_MON_L1A_ID_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_L1A_ID
+      format_name: FELIG_MON_L1A_ID_{index:02}
+      type_name: FELIG_MON_L1A_ID
+      desc: FELIG specific configuration registers
+      bitfield:
+        - range: 31..0
+          default: 0
+          desc: FELIG's last L1 ID.
+    
+FELIG_MON_PICXO_ARR:
+  number: 24
+  type: R
+  entries:
+    - name: FELIG_MON_PICXO
+      format_name: FELIG_MON_PICXO_{index:02}
+      type_name: FELIG_MON_PICXO
+      desc: FELIG specific configuration registers
+      bitfield:
+        - name: VLOT
+          range: 53..32
+          default: 0
+          desc: Value indicates TX clock (recovered RX clock)  to RX reference clock frequency offset.
+        - name: ERROR
+          range: 20..0
+          default: 0
+          desc: Value indicates RX to TX frequency tracking error.
+
diff --git a/sources/templates/registers.pdf b/sources/templates/registers.pdf
index 7f18b070c1798ea358b4e8bc6966a46ccdafb2cf..55edfea6510cf3ba8ee3804db493411615b44a78 100644
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diff --git a/sources/templates/version.txt b/sources/templates/version.txt
deleted file mode 100644
index 07de8fc4ee1aa6b1e8b7d612733e7b4d49e888ef..0000000000000000000000000000000000000000
--- a/sources/templates/version.txt
+++ /dev/null
@@ -1 +0,0 @@
-0406
\ No newline at end of file
diff --git a/sources/templates/version.txt.template b/sources/templates/version.txt.template
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@@ -1 +0,0 @@
-{{ tree.version|version|hex }}