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Created date
Added additional FullToAxis in decoding / FullmodeEmulator and another fanout...
!306
· created
Nov 25, 2021
by
Frans Schreuder
Merged
0
updated
Dec 08, 2021
Fix for FLX-1758. Workaround tested in simulation
!305
· created
Nov 24, 2021
by
Frans Schreuder
release-4.10
Merged
0
updated
Dec 22, 2021
Fixed uncontrained internal endpoints in FELIG's gbt printer. FLX-1691
!304
· created
Nov 19, 2021
by
Frans Schreuder
master
Merged
0
updated
Nov 24, 2021
FLX-1631 phase2 RegMap optimization
!303
· created
Nov 17, 2021
by
Filiberto Bonini
Closed
1
updated
Mar 11, 2022
Resolve FLX-1736 "Irq async reg"
!302
· created
Nov 08, 2021
by
Frans Schreuder
master
Merged
0
updated
Nov 24, 2021
Removed some statements that were previously in a dead "else" statement and...
!301
· created
Oct 15, 2021
by
Frans Schreuder
FLX-1697_TTC_Emulator_LongB_OCR_support
Closed
Approved
4
updated
Oct 23, 2021
Resolve FLX-1697 "Ttc emulator longb ocr support"
!300
· created
Oct 11, 2021
by
Frans Schreuder
master
Merged
Approved
4
updated
Nov 12, 2021
FLX-1720: Added WupperCodeGen as a submodule
!299
· created
Oct 08, 2021
by
Frans Schreuder
Merged
0
updated
Oct 09, 2021
Release 4.10
!298
· created
Oct 06, 2021
by
Frans Schreuder
master
Merged
0
updated
Nov 24, 2021
This should fix FLX-1716
!297
· created
Oct 05, 2021
by
Frans Schreuder
master
Merged
0
updated
Oct 06, 2021
Fix for FLX-1715: DATA_WIDTH dependency for sorting memory mem_addra calculation
!296
· created
Sep 29, 2021
by
Frans Schreuder
master
Merged
0
updated
Oct 11, 2021
Fix for FLX-1715: DATA_WIDTH dependency for sorting memory mem_addra calculation
!295
· created
Sep 29, 2021
by
Frans Schreuder
Merged
0
updated
Oct 05, 2021
The toplevel VHDL files for BNL712 did not have the Si5345_RSTN pin, this was...
!294
· created
Sep 23, 2021
by
Frans Schreuder
master
Merged
0
updated
Oct 05, 2021
fixed pin for SI5345 reset register as per BNL712 schematics
!293
· created
Sep 23, 2021
by
Marco Trovato
Merged
0
updated
Sep 24, 2021
WIP: Preliminary instantiation of core1990 in link wrapper. There is no support yet...
!292
· created
Sep 20, 2021
by
Frans Schreuder
Closed
1
updated
Mar 02, 2022
Pixel Flavor builds with 24 channels
!291
· created
Sep 20, 2021
by
Marco Trovato
Merged
3
updated
Sep 21, 2021
Resolve FLX-1669 "Phase2/ fmemuramtoxpm"
!290
· created
Sep 20, 2021
by
Frans Schreuder
Merged
0
updated
Sep 21, 2021
Resolve FLX-1705 "Phase2/ yarr debug register split"
!289
· created
Sep 20, 2021
by
Frans Schreuder
Merged
0
updated
Sep 21, 2021
Resolve FLX-1704 "Addbcrcounter"
!288
· created
Sep 20, 2021
by
Frans Schreuder
master
Merged
0
updated
Oct 06, 2021
Added sys clock 1 (pcie refclk) for endpoint 1 to constraints for BNL711
!287
· created
Sep 20, 2021
by
Frans Schreuder
master
Merged
0
updated
Sep 20, 2021
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