Skip to content
GitLab
Explore
Sign in
Open
8
Merged
472
Closed
97
All
577
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Created date
Resolve FLX-2072 "Emptysuppress"
!416
· created
Dec 21, 2022
by
Frans Schreuder
master
Merged
updated
Jan 19, 2023
LTITTC Link Wrapper moved from link wrapper to LTITTC Wrapper. Same MGT bank...
!420
· created
Jan 19, 2023
by
Frans Schreuder
Merged
10
updated
Feb 06, 2023
Deinit submodules after simulation and publish script
!421
· created
Jan 19, 2023
by
Frans Schreuder
Merged
updated
Jan 20, 2023
Set default NUMBER_OF_DESCRIPTORS to 6 (5 tohost + 1 fromhost), see FLX-2098
!422
· created
Jan 19, 2023
by
Frans Schreuder
Merged
updated
Jan 27, 2023
Imlemented LTI transmitter and Interlaken receiver on FLX182
!423
· created
Jan 25, 2023
by
Frans Schreuder
Merged
updated
Mar 02, 2023
Resolve FLX-2087 "FELIG L1A reset"
!424
· created
Jan 26, 2023
by
Ricardo Luz
master
Merged
updated
Jan 27, 2023
Upgraded VMK180 block designs to Vivado 2022.2 (non engineering sample)
!425
· created
Jan 27, 2023
by
Frans Schreuder
Merged
updated
Jan 31, 2023
Use Vivado 2021.2 for VCU128 ci script
!426
· created
Jan 30, 2023
by
Frans Schreuder
Merged
updated
Feb 01, 2023
64b66b module translated to VDHL and UVVM/Modelsim testbench
!428
· created
Feb 04, 2023
by
Marco Trovato
Merged
3
updated
Feb 28, 2023
renaming LTITTC R/W colliding registers
!429
· created
Feb 08, 2023
by
Marco Trovato
Merged
updated
Feb 15, 2023
FLX-2115 BUFG
!430
· created
Feb 10, 2023
by
Ricardo Luz
Merged
updated
Feb 11, 2023
pixel decoding aclk at 160 MHz to avoid data losses
!431
· created
Feb 14, 2023
by
Marco Trovato
Merged
updated
Feb 15, 2023
Combined registers from phase2/master_FLX-2106_64b66bsimu and...
!432
· created
Feb 15, 2023
by
Frans Schreuder
Merged
2
updated
Feb 17, 2023
Resolve FLX-2118
!433
· created
Feb 16, 2023
by
Marius Wensing
Merged
updated
Feb 22, 2023
Replaced \= in comment by /= to aviod unknown escape character in c...
!434
· created
Feb 17, 2023
by
Frans Schreuder
Merged
updated
Feb 18, 2023
ToHostAxiStreamController was rewritten (toblock process divided into multiple...
!435
· created
Feb 22, 2023
by
Frans Schreuder
Merged
updated
Mar 01, 2023
Resolve open issues from FLX-1826 and FLX-2135
!436
· created
Mar 02, 2023
by
Marius Wensing
Merged
2
updated
May 10, 2023
Added a rule to execute VSG, compile_simlib and simulation for either pushes...
!438
· created
Mar 06, 2023
by
Frans Schreuder
Merged
updated
Mar 07, 2023
Implemented AUTO RX Reset counters for FULL, GBT and lpGBT in phase2
!439
· created
Mar 06, 2023
by
Frans Schreuder
Merged
updated
Mar 20, 2023
Resolve FLX-2045 "Auto rx reset counter"
!440
· created
Mar 07, 2023
by
Frans Schreuder
master
Merged
updated
Mar 20, 2023
Prev
1
…
14
15
16
17
18
19
20
21
22
…
24
Next