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Created date
Added hgtd testbench to encoding_fileset
!362
· created
May 10, 2022
by
Frans Schreuder
Merged
updated
Jun 09, 2022
WIP: Add an ILA like debug using the register map to the output of GBT 8b10b decoders.
!363
· created
May 11, 2022
by
Frans Schreuder
master
Closed
updated
Jul 05, 2022
Resolve FLX-1892 "Ttc emulator debug"
!364
· created
Jun 07, 2022
by
Frans Schreuder
master
Merged
updated
Jul 06, 2022
Add ila (debug_bridge) support through the PCIe configuration space
!365
· created
Jun 07, 2022
by
Frans Schreuder
master
Merged
updated
Sep 17, 2022
Reverted Versal IP
!366
· created
Jun 08, 2022
by
Frans Schreuder
phase2/FLX-1769_AddGBTForVCU128
Merged
updated
Jun 09, 2022
Added XVC over PCIe for phase2 (Kintex Ultrascale only)
!367
· created
Jun 10, 2022
by
Frans Schreuder
Merged
updated
Jul 01, 2022
Added new registers and extended bitfields for FELIG as requested by @riluz in FLX-1428
!368
· created
Jun 15, 2022
by
Frans Schreuder
Closed
updated
Jul 01, 2022
Added a register to make the HDLC flag for EC E-Links configurable, default:...
!369
· created
Jun 24, 2022
by
Frans Schreuder
Closed
1
updated
Jul 01, 2022
Fixed a typo in the evencycle_dma bit for DMA_STATUS 3 (the bit from descriptor 2 was assigned)
!370
· created
Jun 28, 2022
by
Frans Schreuder
Merged
updated
Jun 30, 2022
changes to laneregistermap. added ila for registers (still need to add .xci to...
!371
· created
Jul 01, 2022
by
Frans Schreuder
Merged
updated
Jul 06, 2022
Added a register to make the HDLC flag for EC E-Links configurable, default:...
!372
· created
Jul 01, 2022
by
Frans Schreuder
Merged
updated
Jul 02, 2022
Send double BCR immediately on OCR
!373
· created
Jul 04, 2022
by
Frans Schreuder
master
Merged
updated
Jul 06, 2022
Ported changes for FLX-1892 and FLX-1946 to phase2/master
!374
· created
Jul 05, 2022
by
Frans Schreuder
Merged
updated
Jul 07, 2022
FLX-1937: Implemented instant timeout mechanism
!375
· created
Jul 08, 2022
by
Frans Schreuder
Merged
updated
Jul 12, 2022
Resolve FLX-1676 "Phase2/ itkpixv1 1 merged"
!376
· created
Jul 11, 2022
by
Frans Schreuder
phase2/FLX-1676_ITkPixV1_1
Closed
5
updated
Aug 30, 2022
Improve timing constraints (and fix reset for 240MHz clock domain) for GBT mode FLX712
!377
· created
Jul 11, 2022
by
Frans Schreuder
master
Closed
1
updated
Aug 30, 2022
Output the OCR half way the BCR period from the TTC emulator
!378
· created
Jul 12, 2022
by
Frans Schreuder
Merged
updated
Aug 01, 2022
Output the OCR half way the BCR period from the TTC emulator
!379
· created
Jul 12, 2022
by
Frans Schreuder
master
Merged
updated
Aug 05, 2022
Connected LMK reference clocks and added them to timing constraints
!380
· created
Jul 13, 2022
by
Frans Schreuder
Merged
updated
Jul 14, 2022
Resolve FLX-1954 "Phase2/ prbs lpgbt"
!381
· created
Jul 15, 2022
by
Frans Schreuder
Closed
4
updated
Aug 04, 2022
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