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Created date
Draft: Resolve FLX-2503 "Phase2/ wupper bar3 250mhz"
!598
· created
Dec 10, 2024
by
Frans Schreuder
updated
Dec 12, 2024
Draft: Initial implementation of phase2 TTCToHost virtual e-link:
!597
· created
Dec 09, 2024
by
Frans Schreuder
updated
Dec 10, 2024
Draft: adding test cases to debug data emulator
!592
· created
Nov 29, 2024
by
Davide Finazzi
updated
Dec 03, 2024
lots of cleanup, and removed some registers for Linkwrapper
!580
· created
Sep 26, 2024
by
Frans Schreuder
updated
Dec 04, 2024
Add new features to direct mode (FLX-2455) and push register map to 5.3
!579
· created
Sep 25, 2024
by
Frans Schreuder
updated
Nov 07, 2024
Added condition for GBT_CHANNEL_DISABLE in lpgbt wrapper and decoding gearbox
!578
· created
Sep 06, 2024
by
Frans Schreuder
updated
Sep 06, 2024
Draft: TB skips BC-gating and ASIC reg RW masking checks when not included in the...
!575
· created
Jul 31, 2024
by
Frans Schreuder
updated
Jul 31, 2024
Draft: Resolve FLX-2417 "Phase2/ linksharingmultiplexing"
!572
· created
Jul 18, 2024
by
Marius Wensing
updated
Jul 24, 2024
Draft: phase2/FLX-1592_feligFLX712_ITkStripsEmu_2024
!539
· created
Mar 26, 2024
by
Frans Schreuder
2
updated
Dec 07, 2024
Draft: Implemented a very simple IDLE detection circuit to see whether a HDLC e-link is aligned.
!516
· created
Nov 16, 2023
by
Frans Schreuder
updated
Nov 16, 2023
