Readme for developers
Point of contact: Frans Schreuder f.schreuder@nikhef.nl
Cloning the repository
This FELIX firmware repository can be cloned on it's own, and contains all the necessary files to generate a bitfile or run a simulation. FELIX is however not complete with firmware alone, and for working with the register map (WupperCodeGen) a part of the software tree is needed. It is therefore recommended to clone the complete FELIX project as follows:
#First clone the toplevel FELIX repository, which is an empty placeholder
#with only some scripts.
git clone ssh://git@gitlab.cern.ch:7999/atlas-tdaq-felix/felix.git
cd felix
#Clone the subrepositories, software, firmware, documents, hardware
./clone_all.sh ssh
#Clone the software subrepositories
cd software
./clone_all.sh ssh
#Now you have a complete FELIX directory treeBuilding firmware
Vivado 2020.2 is recommended for building the firmware.
To create a bitfile from the sources in this repository, two steps are required, but first Vivado and the Xilinx licenses must be available. At Cern, Vivado is installed on the following path:
/afs/cern.ch/work/f/fschreud/public/Xilinx/Vivado/2018.1/
To use Vivado at Cern, one can issue the following commands:
export XILINXD_LICENSE_FILE="2112@lxlicen01.cern.ch,2112@lxlicen02.cern.ch,2112@lxlicen03.cern.ch"
source /afs/cern.ch/work/f/fschreud/public/Xilinx/Vivado/2018.1/settings64.sh
vivadoCreating the project for branches based on master
There are two flavours (GBT mode and lpGBT mode) in Phase 1. To build the flavour of choice, one must start from the corresponding script directory. There is technically also FULL mode, but I never build it with strips. For GBT mode:
cd felix/firmware/scripts/FELIX_top
vivadoThen from the Vivado tcl console:
#To create the project, replace FLX712 with FLX709 when building for the VC709 card
source ./FLX712_GBT_import_vivado.tcl
#To run synthesis, implementation and create a bitstream in felix/firmware/output for Strips build:
# (other scripts which have lpgbt in their name will also work)
source ./do_implementation_BNL712_4ch_strips_vldb.tcl
For lpGBT mode:
cd felix/firmware/scripts/FELIX_top
vivadoThen from the Vivado tcl console:
# lpGBT mode is only supported for FLX712, vc709 will not work!
source ./FLX712_GBT_import_vivado.tcl
#To run synthesis, implementation and create a bitstream in felix/firmware/output for Strips build:
# (other scripts which don't have lpgbt in their name will also work)
source ./do_implementation_BNL712_4ch_strips_lpgbt_starchip_stave.tclCreating a project for branches based on phase2/master
In Phase 2 the different flavours are generated from the same project and the same toplevel VHDL file. Therefore the different flavours are built using different do_implementation*.tcl scripts. For all flavours
cd felix/firmware/scripts/FELIX_top
vivadoThen from the Vivado tcl console:
#To create the project, replace FLX712 with FLX709 when building for the VC709 card
source ./FLX712_FELIX_import_vivado.tcl
#To run synthesis, implementation and create a bitstream in felix/firmware/output
source ./do_implementation_BNL712_GBT.tcl #GBT mode
source ./do_implementation_BNL712_FULL.tcl #FULL mode
#There are more flavours in that directory that can be built with similar scriptsSharing bitfiles
Bitfiles may be uploaded to Sharepoint for testing and development purposes. These bitfiles will automatically be copied to the FELIX developers website