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IDR_2023_03_27e0254183 · ·
This is the post IDR version of SL firmware, compatible with V2 SL prototype
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PDR_2021_12_7dd0465ea · ·
This is the version referring to the preliminary design review. Base clock is 400MHz.
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This is the post IDR version of SL firmware, compatible with V2 SL prototype
Updated version of the readout firmware with RAMs.
This is the version referring to the preliminary design review. Base clock is 400MHz.