diff --git a/InnerDetector/InDetConditions/SCT_ConditionsAlgorithms/share/testRodVeto.py b/InnerDetector/InDetConditions/SCT_ConditionsAlgorithms/share/testRodVeto.py index f5b8129e9ef0eb1030a1ad65a44b0d75c71eec48..6f8f347ba68c5e1aaf6e1aae566886148d1936b1 100644 --- a/InnerDetector/InDetConditions/SCT_ConditionsAlgorithms/share/testRodVeto.py +++ b/InnerDetector/InDetConditions/SCT_ConditionsAlgorithms/share/testRodVeto.py @@ -69,11 +69,6 @@ from AthenaCommon.AlgSequence import AlgSequence job = AlgSequence() - -from SCT_Cabling.SCT_CablingConf import SCT_CablingSvc -ToolSvc = ServiceMgr.ToolSvc -ServiceMgr+=SCT_CablingSvc() - #-------------------------------------------------------------- # Load IOVDbSvc #-------------------------------------------------------------- @@ -97,7 +92,6 @@ job+= SCT_RODVetoTestAlg() import AthenaCommon.AtlasUnixGeneratorJob -ServiceMgr.SCT_CablingSvc.OutputLevel = INFO ToolSvc.SCT_RODVetoTool.OutputLevel=VERBOSE ServiceMgr.EventSelector.InitialTimeStamp = 1500000000 ServiceMgr.EventSelector.RunNumber = 300000 # MC16c 2017 run number diff --git a/InnerDetector/InDetExample/InDetRecExample/share/InDetWriteBS_jobOptions.py b/InnerDetector/InDetExample/InDetRecExample/share/InDetWriteBS_jobOptions.py index bf071827f6cfd73e5b4415d2a80223a793fc75dd..0e45083cc3dbbf17561529ec79d74f27bd9b0d44 100755 --- a/InnerDetector/InDetExample/InDetRecExample/share/InDetWriteBS_jobOptions.py +++ b/InnerDetector/InDetExample/InDetRecExample/share/InDetWriteBS_jobOptions.py @@ -22,19 +22,7 @@ ByteStreamCnvSvc = svcMgr.ByteStreamCnvSvc ByteStreamCnvSvc.IsSimulation = True ByteStreamCnvSvc.ByteStreamOutputSvc ="ByteStreamEventStorageOutputSvc" -# SCT cabling -from SCT_Cabling.SCT_CablingConf import SCT_CablingSvc -ServiceMgr+=SCT_CablingSvc() -IOVDbSvc = Service("IOVDbSvc") -from IOVDbSvc.CondDB import conddb -conddb.addFolderSplitMC("SCT","/SCT/DAQ/Configuration/ROD","/SCT/DAQ/Configuration/ROD") -conddb.addFolderSplitMC("SCT","/SCT/DAQ/Configuration/MUR","/SCT/DAQ/Configuration/MUR") -conddb.addFolderSplitMC("SCT","/SCT/DAQ/Configuration/RODMUR","/SCT/DAQ/Configuration/RODMUR") -conddb.addFolderSplitMC("SCT","/SCT/DAQ/Configuration/Geog","/SCT/DAQ/Configuration/Geog") -ServiceMgr.SCT_CablingSvc.DataSource = "CORACOOL" -# hack to force MC calbing loading for FDR2 -#if svcMgr.ByteStreamCnvSvc.IsSimulation: -# ServiceMgr.SCT_CablingSvc.DataSource = "SCT_MC_FullCabling_svc.dat" +include("InDetRecExample/InDetRecCabling.py") if DetFlags.haveRIO.pixel_on(): ByteStreamCnvSvc.InitCnvs += ["PixelRDO_Container"] diff --git a/InnerDetector/InDetExample/InDetTrigRecExample/share/testEFID_basic.py b/InnerDetector/InDetExample/InDetTrigRecExample/share/testEFID_basic.py index dba3518807b77b1d815b543655da5cd21706e838..92345115e9dafe47fd6d1492f619dd096ea1c92f 100644 --- a/InnerDetector/InDetExample/InDetTrigRecExample/share/testEFID_basic.py +++ b/InnerDetector/InDetExample/InDetTrigRecExample/share/testEFID_basic.py @@ -225,12 +225,3 @@ steeringEF = job.TrigSteer_EF # if 0 and doReadBS: ServiceMgr.ByteStreamCnvSvc.IsSimulation = True - - # hack to force MC calbing loading for FDR2 - if ServiceMgr.ByteStreamCnvSvc.IsSimulation: - from InDetCabling.InDetCablingConf import SCT_CablingSelector - SCT_CablingSelector = SCT_CablingSelector(Method = "MANUAL", Layout ="FromTextFile", Filename = "SCT_MC_FullCabling.dat") - ToolSvc += SCT_CablingSelector - - - diff --git a/Reconstruction/RecExample/RecExCommon/share/RecExCommon_topOptions.py b/Reconstruction/RecExample/RecExCommon/share/RecExCommon_topOptions.py index 7a6441c8fc8d6f46f6b601a459f3c12f2b9b1bf5..79d3683e4a0c256f0cf9bf807cbe78a7738eaa1b 100644 --- a/Reconstruction/RecExample/RecExCommon/share/RecExCommon_topOptions.py +++ b/Reconstruction/RecExample/RecExCommon/share/RecExCommon_topOptions.py @@ -1581,13 +1581,6 @@ if rec.doWriteBS(): StreamBSFileOutput.ItemList += ["LUCID_DigitContainer#Lucid_Digits"] - # special SCT CABLING (ONLY FOR OLD FDR DATA) - #from InDetCabling.InDetCablingConf import SCT_CablingSelector - #SCT_CablingSelector = SCT_CablingSelector(Method = "MANUAL", Layout = "FromTextFile", Filename = "SCT_MC_FullCabling.dat") - #ToolSvc += SCT_CablingSelector - - - # LAr # StreamBS.ItemList +=["LArRawChannels#*"] StreamBSFileOutput.ItemList +=["2721#*"] diff --git a/Trigger/TrigValidation/TrigEgammaValidation/share/generalJobOption.py b/Trigger/TrigValidation/TrigEgammaValidation/share/generalJobOption.py index e23a1353b631770ca97b094d56e58c34f7155616..79945d20a8648a5a92577e79f392ce331b04b994 100644 --- a/Trigger/TrigValidation/TrigEgammaValidation/share/generalJobOption.py +++ b/Trigger/TrigValidation/TrigEgammaValidation/share/generalJobOption.py @@ -213,9 +213,6 @@ elif (WhichInput == "BS"): #if hasattr(ToolSvc,"TRT_FillCablingData_DC3"): # ToolSvc.TRT_FillCablingData_DC3.RealData=False - #if hasattr(ToolSvc,"SCT_CablingSelector"): - # ToolSvc.SCT_CablingSelector.Filename = "SCT_Jan08Cabling.dat" - jobproperties.PerfMonFlags.doMonitoring = True print ">>>>>>>>== generalJobOption.py DEBUG ==<<<<<<<<<" diff --git a/Trigger/TrigValidation/TrigP1Test/share/TopOptions_WriteBS_LVL1sim_fromAthena.py b/Trigger/TrigValidation/TrigP1Test/share/TopOptions_WriteBS_LVL1sim_fromAthena.py index fe192170459492275e51d807214c032902229633..bab3d27d0e8181f103500247e157817e18047e2b 100644 --- a/Trigger/TrigValidation/TrigP1Test/share/TopOptions_WriteBS_LVL1sim_fromAthena.py +++ b/Trigger/TrigValidation/TrigP1Test/share/TopOptions_WriteBS_LVL1sim_fromAthena.py @@ -130,12 +130,6 @@ from LArByteStream.LArByteStreamConf import LArRawDataContByteStreamTool ToolSvc+=LArRawDataContByteStreamTool() ToolSvc.LArRawDataContByteStreamTool.InitializeForWriting=True -# ------------------------------------------------------------- -# SCT Cablings -# ------------------------------------------------------------- -if hasattr(ToolSvc,"SCT_CablingSelector"): - ToolSvc.SCT_CablingSelector.Filename = "SCT_Jan08Cabling.dat" - theApp.CreateSvc += ["StoreGateSvc/StoreGateSvc" ] ByteStreamAddressProviderSvc = Service( "ByteStreamAddressProviderSvc" ) ByteStreamAddressProviderSvc.TypeNames += [