diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
index 05e8c3eb8d86bbdef3f5c4d6c053e1c60c371aac..a767f4102ada9350ca29951ee5345b21f97adb0a 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
@@ -52,7 +52,7 @@ namespace LVL1 {
virtual int getID() override {return m_id;}
virtual void SetTowersAndCells_SG( int [][6] ) override ;
- virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &) override ;
+ virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &, unsigned int &) override ;
virtual std::vector <uint32_t> getEmTOBs() override ;
virtual std::vector <uint32_t> getTauTOBs() override ;
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
index 6fcd651df0e0c08567006f01ba8500547b5457b5..192414cfef5d6feef76711b582372e272d8462ab 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
@@ -29,7 +29,7 @@
#include "StoreGate/ReadHandle.h"
#include "SGTools/TestStore.h"
#include "TrigConfData/L1Menu.h"
-
+#include <unordered_map>
#include <iostream>
#include <fstream>
@@ -165,9 +165,15 @@ StatusCode eFEXFPGA::execute(eFEXOutputCollection* inputOutputCollection){
unsigned int RetaWP = 0;
unsigned int RhadWP = 0;
unsigned int WstotWP = 0;
- SetIsoWP(RetaCoreEnv,threshReta,RetaWP);
- SetIsoWP(RhadCoreEnv,threshRhad,RhadWP);
- SetIsoWP(WstotCoreEnv,threshWstot,WstotWP);
+
+ // bitshifts for the different iso vars
+ unsigned int RetaBitS = 3;
+ unsigned int RhadBitS = 3;
+ unsigned int WstotBitS = 5;
+
+ SetIsoWP(RetaCoreEnv,threshReta,RetaWP,RetaBitS);
+ SetIsoWP(RhadCoreEnv,threshRhad,RhadWP,RhadBitS);
+ SetIsoWP(WstotCoreEnv,threshWstot,WstotWP,WstotBitS);
int eta_ind = ieta; // No need to offset eta index with new 0-5 convention
int phi_ind = iphi - 1;
@@ -340,7 +346,8 @@ void eFEXFPGA::SetTowersAndCells_SG(int tmp_eTowersIDs_subset[][6]){
}
-void eFEXFPGA::SetIsoWP(std::vector<unsigned int> & CoreEnv, std::vector<unsigned int> & thresholds, unsigned int & workingPoint) {
+void eFEXFPGA::SetIsoWP(std::vector<unsigned int> & CoreEnv, std::vector<unsigned int> & thresholds, unsigned int & workingPoint, unsigned int & bitshift) {
+ // Working point evaluted by Core * 2^bitshift > Threshold * Environment conditions
bool CoreOverflow = false;
bool EnvOverflow = false;
@@ -348,7 +355,9 @@ void eFEXFPGA::SetIsoWP(std::vector<unsigned int> & CoreEnv, std::vector<unsigne
bool ThrEnvOverflowM = false;
bool ThrEnvOverflowT = false;
- if (CoreEnv[0] > 0xffff) CoreOverflow = true;
+ std::unordered_map<unsigned int, unsigned int> bsmap { {3, 8}, {5, 32}};
+
+ if (CoreEnv[0]*bsmap[bitshift] > 0xffff) CoreOverflow = true;
if (CoreEnv[1] > 0xffff) EnvOverflow = true;
if (CoreEnv[1]*thresholds[0] > 0xffff) ThrEnvOverflowL = true;
if (CoreEnv[1]*thresholds[1] > 0xffff) ThrEnvOverflowM = true;
@@ -356,13 +365,13 @@ void eFEXFPGA::SetIsoWP(std::vector<unsigned int> & CoreEnv, std::vector<unsigne
if (CoreOverflow == false) {
if (EnvOverflow == false) {
- if ( (CoreEnv[0] > (thresholds[0]*CoreEnv[1])) && ThrEnvOverflowL == false ) {
+ if ( (CoreEnv[0]*bsmap[bitshift] > (thresholds[0]*CoreEnv[1])) && ThrEnvOverflowL == false ) {
workingPoint = 1;
}
- else if ( (CoreEnv[0] > (thresholds[1]*CoreEnv[1])) && ThrEnvOverflowM == false ) {
+ else if ( (CoreEnv[0]*bsmap[bitshift] > (thresholds[1]*CoreEnv[1])) && ThrEnvOverflowM == false ) {
workingPoint = 2;
}
- else if ( (CoreEnv[0] > (thresholds[2]*CoreEnv[1])) && ThrEnvOverflowT == false ) {
+ else if ( (CoreEnv[0]*bsmap[bitshift] > (thresholds[2]*CoreEnv[1])) && ThrEnvOverflowT == false ) {
workingPoint = 3;
}
else {
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
index ca3280d2656d5a91ce71665741b00ce6b3152b71..06c2a51a6bd9b22534ca1c25676b7344cb7ff8c9 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
@@ -202,8 +202,8 @@ void LVL1::eFEXegAlgo::getWstot(std::vector<unsigned int> & output){
}
}
- output.push_back(numer);
output.push_back(den);
+ output.push_back(numer);
}
@@ -239,8 +239,8 @@ std::unique_ptr<eFEXegTOB> LVL1::eFEXegAlgo::geteFEXegTOB() {
std::vector<unsigned int> temvector;
getWstot(temvector);
- out->setWstotNum(temvector[0]);
- out->setWstotDen(temvector[1]);
+ out->setWstotNum(temvector[1]);
+ out->setWstotDen(temvector[0]);
getRhad(temvector);
out->setRhadNum(temvector[1]);
out->setRhadDen(temvector[0] + temvector[1]);
diff --git a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
index e22a29464c4602f8eb51eae735fb56b015b495b7..cca69deb7e572fa80ddecb82e267cf47d3a4be06 100644
--- a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
+++ b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
@@ -39,7 +39,7 @@ Interface definition for eFEXFPGA
virtual void SetTowersAndCells_SG(int [][6]) = 0;
- virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &) = 0;
+ virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &, unsigned int &) = 0;
virtual std::vector<uint32_t> getEmTOBs() = 0;
diff --git a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
index 59d441b655466015b3dfe4ac443f2dccd4fda548..9cdccab16e73abf03ed215ca31a9dd8ffb56be14 100644
--- a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
+++ b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
@@ -3335,7 +3335,17 @@ HLT_e300_etcut_L1EM22VHI:
2: 1
3: 1
HLT_e300_etcut_L1eEM22M:
- eventCount: 0
+ eventCount: 1
+ stepCounts:
+ 0: 1
+ 1: 1
+ 2: 1
+ 3: 1
+ stepFeatures:
+ 0: 1
+ 1: 13
+ 2: 1
+ 3: 1
HLT_e30_lhvloose_L1EM22VHI:
eventCount: 5
stepCounts:
@@ -9684,27 +9694,27 @@ HLT_noalg_L1cTAU20M:
HLT_noalg_L1cTAU25M:
eventCount: 0
HLT_noalg_L1eEM10L:
- eventCount: 0
+ eventCount: 7
HLT_noalg_L1eEM15:
eventCount: 16
HLT_noalg_L1eEM15L:
- eventCount: 0
+ eventCount: 6
HLT_noalg_L1eEM15M:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM20:
eventCount: 14
HLT_noalg_L1eEM20L:
- eventCount: 0
+ eventCount: 6
HLT_noalg_L1eEM20M:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM22:
eventCount: 14
HLT_noalg_L1eEM22L:
- eventCount: 0
+ eventCount: 5
HLT_noalg_L1eEM22M:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM22T:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM3:
eventCount: 20
HLT_noalg_L1eEM5:
@@ -9712,9 +9722,9 @@ HLT_noalg_L1eEM5:
HLT_noalg_L1eEM8:
eventCount: 18
HLT_noalg_L1eEM8L:
- eventCount: 0
+ eventCount: 7
HLT_noalg_L1eEM8M:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eTAU100:
eventCount: 0
HLT_noalg_L1eTAU12:
diff --git a/Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref b/Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref
index 08f501b6807f63993ff3b733c1903d7cf8a5a256..679805d1ced40ee757ab54b22255fdc0a5b60cb6 100644
--- a/Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref
+++ b/Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref
@@ -3862,23 +3862,23 @@ HLT_noalg_L1cTAU20M:
HLT_noalg_L1cTAU25M:
eventCount: 0
HLT_noalg_L1eEM10L:
- eventCount: 0
+ eventCount: 2
HLT_noalg_L1eEM15:
eventCount: 11
HLT_noalg_L1eEM15L:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM15M:
eventCount: 0
HLT_noalg_L1eEM20:
eventCount: 7
HLT_noalg_L1eEM20L:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM20M:
eventCount: 0
HLT_noalg_L1eEM22:
eventCount: 7
HLT_noalg_L1eEM22L:
- eventCount: 0
+ eventCount: 1
HLT_noalg_L1eEM22M:
eventCount: 0
HLT_noalg_L1eEM22T:
@@ -3890,7 +3890,7 @@ HLT_noalg_L1eEM5:
HLT_noalg_L1eEM8:
eventCount: 23
HLT_noalg_L1eEM8L:
- eventCount: 0
+ eventCount: 3
HLT_noalg_L1eEM8M:
eventCount: 0
HLT_noalg_L1eTAU100: