Commit b1f42ea7 authored by Joerg Stelzer's avatar Joerg Stelzer
Browse files

When not reading the prescales from COOL, folder will not be available

parent f0f10eb3
...@@ -187,13 +187,14 @@ def setupHLTPrescaleCondAlg( flags = None ): ...@@ -187,13 +187,14 @@ def setupHLTPrescaleCondAlg( flags = None ):
else: else:
raise RuntimeError("trigger configuration flag 'trigConfig' starts with %s, which is not understood" % tc["source"]) raise RuntimeError("trigger configuration flag 'trigConfig' starts with %s, which is not understood" % tc["source"])
if flags is None: # old style config if tc["source"] == "COOL":
from AthenaCommon.AlgSequence import AthSequencer if flags is None: # old style config
condSequence = AthSequencer("AthCondSeq") from AthenaCommon.AlgSequence import AthSequencer
condSequence += hltPrescaleCondAlg condSequence = AthSequencer("AthCondSeq")
from IOVDbSvc.CondDB import conddb condSequence += hltPrescaleCondAlg
conddb.addFolder( "TRIGGER", getHLTPrescaleFolderName(), className="AthenaAttributeList" ) from IOVDbSvc.CondDB import conddb
log.info("Adding folder %s to conddb", getHLTPrescaleFolderName() ) conddb.addFolder( "TRIGGER", getHLTPrescaleFolderName(), className="AthenaAttributeList" )
log.info("Adding folder %s to conddb", getHLTPrescaleFolderName() )
return hltPrescaleCondAlg return hltPrescaleCondAlg
...@@ -223,11 +224,13 @@ def TrigConfigSvcCfg( flags ): ...@@ -223,11 +224,13 @@ def TrigConfigSvcCfg( flags ):
def HLTPrescaleCondAlgCfg( flags ): def HLTPrescaleCondAlgCfg( flags ):
log = logging.getLogger('TrigConfigSvcCfg') log = logging.getLogger('TrigConfigSvcCfg')
from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
from IOVDbSvc.IOVDbSvcConfig import addFolders
acc = ComponentAccumulator() acc = ComponentAccumulator()
acc.addCondAlgo( setupHLTPrescaleCondAlg( flags ) ) acc.addCondAlgo( setupHLTPrescaleCondAlg( flags ) )
acc.merge(addFolders(flags, getHLTPrescaleFolderName(), "TRIGGER_ONL", className="AthenaAttributeList")) tc = getTrigConfigFromFlag( flags )
log.info("Adding folder %s to CompAcc", getHLTPrescaleFolderName() ) if tc["source"] == "COOL":
from IOVDbSvc.IOVDbSvcConfig import addFolders
acc.merge(addFolders(flags, getHLTPrescaleFolderName(), "TRIGGER_ONL", className="AthenaAttributeList"))
log.info("Adding folder %s to CompAcc", getHLTPrescaleFolderName() )
return acc return acc
......
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