Commit b1f42ea7 authored by Joerg Stelzer's avatar Joerg Stelzer
Browse files

When not reading the prescales from COOL, folder will not be available

parent f0f10eb3
......@@ -187,6 +187,7 @@ def setupHLTPrescaleCondAlg( flags = None ):
raise RuntimeError("trigger configuration flag 'trigConfig' starts with %s, which is not understood" % tc["source"])
if tc["source"] == "COOL":
if flags is None: # old style config
from AthenaCommon.AlgSequence import AthSequencer
condSequence = AthSequencer("AthCondSeq")
......@@ -223,9 +224,11 @@ def TrigConfigSvcCfg( flags ):
def HLTPrescaleCondAlgCfg( flags ):
log = logging.getLogger('TrigConfigSvcCfg')
from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
from IOVDbSvc.IOVDbSvcConfig import addFolders
acc = ComponentAccumulator()
acc.addCondAlgo( setupHLTPrescaleCondAlg( flags ) )
tc = getTrigConfigFromFlag( flags )
if tc["source"] == "COOL":
from IOVDbSvc.IOVDbSvcConfig import addFolders
acc.merge(addFolders(flags, getHLTPrescaleFolderName(), "TRIGGER_ONL", className="AthenaAttributeList"))"Adding folder %s to CompAcc", getHLTPrescaleFolderName() )
return acc
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