From 46fdeef68cad8175bea80bf504f5306ddb353aa5 Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Thu, 22 Oct 2020 19:59:47 +0200
Subject: [PATCH 1/3] Add eFEXDriver

---
 .../TriggerJobOpts/python/Lvl1SimulationConfig.py             | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py b/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
index 87f82bf65fce..ffc5f2e27fd4 100644
--- a/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
+++ b/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
@@ -87,6 +87,10 @@ def Lvl1SimulationSequence( flags = None ):
             #conddb.addFolderWithTag("TRIGGER_OFL", l1calofolder, "HEAD")
             conddb.addFolder( "TRIGGER_OFL", l1calofolder )
 
+    if flags.Trigger.enableL1Phase1:
+        from AthenaCommon import CfgMgr
+        l1CaloSim += CfgMgr.LVL1__eFEXDriver('MyeFEXDriver')
+
     ##################################################
     # Muons
     ##################################################
-- 
GitLab


From 70be6106b0a400b326224cab2d299a351a6e9343 Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Thu, 22 Oct 2020 20:00:08 +0200
Subject: [PATCH 2/3] Move to input file with supercells

---
 .../test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py           | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py b/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
index 6acd4e74a860..1ed367e1b8f3 100755
--- a/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
+++ b/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
@@ -12,7 +12,7 @@ from TrigValTools.TrigValSteering import Test, ExecStep, CheckSteps
 ex = ExecStep.ExecStep()
 ex.type = 'athena'
 ex.job_options = 'TriggerJobOpts/runHLT_standalone.py'
-ex.input = 'ttbar'
+ex.input = '/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_d1536_tid18795273_00/RDO.18795273._000063.pool.root.1'
 ex.threads = 1
 precommand = ''.join([
   "setMenu='LS2_v1';",  # LS2_v1 soon to be renamed to Dev_pp_run3_v1
-- 
GitLab


From ad94bf13fde42a319ee6cc84c5af4380de5a3e3e Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Fri, 23 Oct 2020 14:09:26 +0200
Subject: [PATCH 3/3] alias for phase-1 sample

---
 .../TrigValidation/TrigValTools/share/TrigValInputs.json   | 7 +++++++
 .../test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py      | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Trigger/TrigValidation/TrigValTools/share/TrigValInputs.json b/Trigger/TrigValidation/TrigValTools/share/TrigValInputs.json
index 052c31a0e369..8a0261189f7b 100644
--- a/Trigger/TrigValidation/TrigValTools/share/TrigValInputs.json
+++ b/Trigger/TrigValidation/TrigValTools/share/TrigValInputs.json
@@ -56,6 +56,13 @@
             "/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_r11315/RDO.17533168._000002.pool.root.1"
         ]
     },
+    "ttbar_phase1": {
+        "source": "mc",
+        "format": "RDO",
+        "paths": [
+            "/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_d1536_tid18795273_00/RDO.18795273._000063.pool.root.1"
+        ]
+    },
     "ttbar_pu80": {
         "source": "mc",
         "format": "RDO",
diff --git a/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py b/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
index 1ed367e1b8f3..f347c93b6822 100755
--- a/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
+++ b/Trigger/TrigValidation/TriggerTest/test/test_trig_mc_v1Dev_L1SimOnly_phase1_build.py
@@ -12,7 +12,7 @@ from TrigValTools.TrigValSteering import Test, ExecStep, CheckSteps
 ex = ExecStep.ExecStep()
 ex.type = 'athena'
 ex.job_options = 'TriggerJobOpts/runHLT_standalone.py'
-ex.input = '/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_d1536_tid18795273_00/RDO.18795273._000063.pool.root.1'
+ex.input = 'ttbar_phase1'
 ex.threads = 1
 precommand = ''.join([
   "setMenu='LS2_v1';",  # LS2_v1 soon to be renamed to Dev_pp_run3_v1
-- 
GitLab