From 90b4713acca3e9ffea0e920e22888f704e75240c Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Wed, 17 Nov 2021 19:58:46 +0100
Subject: [PATCH 1/4] Set up emulation in L1CaloFEXSimCfg
---
.../L1CaloFEXSim/python/L1CaloFEXSimCfg.py | 10 ++++-
.../python/EmulationConfig.py | 41 +++++++++++++++++++
.../python/Lvl1SimulationConfig.py | 8 ++--
.../TriggerJobOpts/share/runHLT_standalone.py | 8 ++--
4 files changed, 59 insertions(+), 8 deletions(-)
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
index feeb56db43dc..41b084c741ad 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
@@ -10,11 +10,14 @@ def L1CaloFEXSimCfg(flags):
if flags.Input.isMC:
SCellType = "SCell"
else:
- SCellType = simflags.Calo.SCellType()
+ SCellType = "EmulatedSCell"
eFEX = CompFactory.LVL1.eFEXDriver('eFEXDriver',
SCell=SCellType )
eFEX.eSuperCellTowerMapperTool.SCell=SCellType
eFEX.eFEXSysSimTool.SCell=SCellType
+ print(eFEX.SCell)
+ print(eFEX.eSuperCellTowerMapperTool.SCell)
+ print(eFEX.eFEXSysSimTool.SCell)
acc.addEventAlgo(eFEX)
# jFEX part
@@ -30,6 +33,11 @@ def L1CaloFEXSimCfg(flags):
gFEX.gFEXSysSimTool.SCell=SCellType
acc.addEventAlgo(gFEX)
+ from TrigT1CaloFexPerf.EmulationConfig import emulateSC_Cfg
+
+ print("SCellType= ", SCellType)
+ acc.merge(emulateSC_Cfg(flags,SCOut=SCellType))
+
return acc
if __name__ == '__main__':
diff --git a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
index c486bbabc8f0..57a9a8331bc9 100644
--- a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
+++ b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
@@ -56,3 +56,44 @@ def emulateSC(sCell_sequence, CellsIn="SeedLessFS", SCOut="EmulatedSCell"):
if(perfFlags.Calo.ApplyEmulatedPedestal()):
#Apply the pedestal correction. There may be cases we do not want this.
sCell_sequence+=larscbea
+
+def emulateSC_Cfg(flags, CellsIn="SeedLessFS", SCOut="EmulatedSCell"):
+
+ from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
+ from AthenaConfiguration.ComponentFactory import CompFactory
+ acc = ComponentAccumulator()
+ if flags.Input.isMC:
+ from LArCabling.LArCablingConfig import LArFebRodMappingCfg
+ acc.merge(LArFebRodMappingCfg(flags))
+
+ from TrigCaloRec.TrigCaloRecConfig import HLTCaloCellSeedLessMaker
+
+ from LArROD.LArSCSimpleMakerConfig import LArSuperCellBCIDEmAlgCfg
+
+ larSCargs = {}
+ larSCargs["SCellContainerIn"] = "EmulatedSCellNoBCID"
+ larSCargs["SCellContainerOut"] = SCOut
+
+ if(perfFlags.Calo.ApplyEmulatedPedestal()):
+ #Apply the pedestal correction. There may be cases we do not want this.
+ #The default input to LARSuperCellBCIDEmAlg (which applies the BCID correction) is the same: SCellContainer
+ acc.merge(LArSuperCellBCIDEmAlgCfg(flags, **larSCargs))
+
+
+ HLTCaloCellSeedLessMaker = CompFactory.HLTCaloCellMaker(ExtraInputs=[('TileEMScale','ConditionStore+TileEMScale'),('TileBadChannels','ConditionStore+TileBadChannels'),
+ ('IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTEM' ),
+ ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTHEC' ),
+ ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TILE' ),
+ ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALEM' ),
+ ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALHAD' ),
+ ( 'LArBadChannelCont', 'ConditionStore+LArBadChannel'),
+ ( 'LArMCSym', 'ConditionStore+LArMCSym'), ('LArOnOffIdMapping' , 'ConditionStore+LArOnOffIdMap' ),
+ ('LArFebRodMapping' , 'ConditionStore+LArFebRodMap' ),('CaloDetDescrManager', 'ConditionStore+CaloDetDescrManager') ],
+ RoIs="",
+ CellsName="SeedLessFS")
+
+ acc.addEventAlgo(HLTCaloCellSeedLessMaker)
+ #Use SCEmulation tool that randomly samples time histograms to estimate time for low energy and negative cells forming a supercell
+ acc.addEventAlgo(CompFactory.LVL1.SCEmulation(InputCells=CellsIn, OutputSuperCells = "EmulatedSCellNoBCID"))
+
+ return acc
diff --git a/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py b/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
index e113c6211e25..8e8aa612b3e7 100644
--- a/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
+++ b/Trigger/TriggerCommon/TriggerJobOpts/python/Lvl1SimulationConfig.py
@@ -205,9 +205,11 @@ def Lvl1SimulationCfg(flags, seqName = None):
from TrigT1CaloSim.TrigT1CaloSimRun2Config import L1CaloLegacySimCfg
acc.merge(L1CaloLegacySimCfg(flags), sequenceName='L1CaloLegacySimSeq')
- #acc.addSequence(seqAND('L1CaloSimSeq'), parentName='L1SimSeq')
- #from TrigT1CaloSim.TrigT1CaloSimRun2Config import L1CaloSimCfg
- #acc.merge(L1CaloSimCfg(flags), sequenceName='L1CaloSimSeq')
+ acc.addSequence(seqAND('L1CaloSimSeq'), parentName='L1SimSeq')
+
+ if flags.Trigger.enableL1CaloPhase1:
+ from L1CaloFEXSim.L1CaloFEXSimCfg import L1CaloFEXSimCfg
+ acc.merge(L1CaloFEXSimCfg(flags), sequenceName = 'L1CaloSimSeq')
acc.addSequence(seqAND('L1MuonSimSeq'), parentName='L1SimSeq')
from TriggerJobOpts.Lvl1MuonSimulationConfig import Lvl1MuonSimulationCfg
diff --git a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
index 93bc824cf194..40df177d6cd1 100644
--- a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
+++ b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
@@ -479,10 +479,10 @@ LumiBlockMuWriterDefault(sequence=hltBeginSeq)
# Level 1 simulation
# ---------------------------------------------------------------
if opt.doL1Sim:
- from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationSequence
- hltBeginSeq += Lvl1SimulationSequence(ConfigFlags)
- #from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationCfg
- #CAtoGlobalWrapper(Lvl1SimulationCfg, ConfigFlags, seqName="HLTBeginSeq")
+ #from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationSequence
+ #hltBeginSeq += Lvl1SimulationSequence(ConfigFlags)
+ from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationCfg
+ CAtoGlobalWrapper(Lvl1SimulationCfg, ConfigFlags, seqName="HLTBeginSeq")
# ---------------------------------------------------------------
# Add HLTSeeding providing inputs to HLT
--
GitLab
From 343c2f0594980e5e0e9963ed56fca4388c8286e6 Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Mon, 22 Nov 2021 11:30:22 +0100
Subject: [PATCH 2/4] Don't retrieve run number for online running
---
.../python/TileCablingSvcConfig.py | 49 ++++++++++++-------
.../python/TileConfigFlags.py | 7 +++
2 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/TileCalorimeter/TileConditions/python/TileCablingSvcConfig.py b/TileCalorimeter/TileConditions/python/TileCablingSvcConfig.py
index 66ab034a0869..c3994d4dc377 100644
--- a/TileCalorimeter/TileConditions/python/TileCablingSvcConfig.py
+++ b/TileCalorimeter/TileConditions/python/TileCablingSvcConfig.py
@@ -25,26 +25,37 @@ def TileCablingSvcCfg(flags):
tileCablingSvc = CompFactory.TileCablingSvc()
geometry = flags.GeoModel.AtlasVersion
- runNumber = flags.Input.RunNumber[0]
run = flags.GeoModel.Run
- if run == 'RUN1':
- if runNumber > 219651:
- # Choose RUN2 cabling for old geometry tags starting from 26-MAR-2013
- tileCablingSvc.CablingType = 4
- msg.warning("Forcing RUN2 cabling for run %s with geometry %s", runNumber, geometry)
-
- elif run == 'RUN2':
- if (flags.Input.isMC and runNumber >= 310000) or runNumber >= 343000 or runNumber < 1:
- # Choose RUN2a cabling for R2 geometry tags starting from 31-Jan-2018
- tileCablingSvc.CablingType = 5
- msg.info("Forcing RUN2a (2018) cabling for run %s with geometry %s", runNumber, geometry)
-
- else:
- tileCablingSvc.CablingType = 4
- msg.info("Forcing RUN2 (2014-2017) cabling for run %s with geometry %s", runNumber, geometry)
- elif run == 'RUN3':
- tileCablingSvc.CablingType = 6
- msg.info("Forcing RUN3 cabling for run %s with geometry %s", run, geometry)
+
+ if not flags.Common.isOnline:
+ runNumber = flags.Input.RunNumber[0]
+ if run == 'RUN1':
+ if runNumber > 219651:
+ # Choose RUN2 cabling for old geometry tags starting from 26-MAR-2013
+ tileCablingSvc.CablingType = 4
+ msg.warning("Forcing RUN2 cabling for run %s with geometry %s", runNumber, geometry)
+
+ elif run == 'RUN2':
+ if (flags.Input.isMC and runNumber >= 310000) or runNumber >= 343000 or runNumber < 1:
+ # Choose RUN2a cabling for R2 geometry tags starting from 31-Jan-2018
+ tileCablingSvc.CablingType = 5
+ msg.info("Forcing RUN2a (2018) cabling for run %s with geometry %s", runNumber, geometry)
+
+ else:
+ tileCablingSvc.CablingType = 4
+ msg.info("Forcing RUN2 (2014-2017) cabling for run %s with geometry %s", runNumber, geometry)
+ elif run == 'RUN3':
+ tileCablingSvc.CablingType = 6
+ msg.info("Forcing RUN3 cabling for run %s with geometry %s", run, geometry)
+ else: #Running online or simulating running online: either way, do not access run number
+ if run == 'RUN2':
+ tileCablingSvc.CablingType = 5
+ msg.info("Forcing RUN2a (2018) cabling for online run with geometry %s", geometry)
+ elif run == 'RUN3':
+ tileCablingSvc.CablingType = 6
+ msg.info("Forcing RUN3 cabling for online run with geometry %s", geometry)
+ else:
+ log.error("CablingType only defined for Run 2 and Run 3 geometries")
acc.addService(tileCablingSvc, primary = True)
diff --git a/TileCalorimeter/TileConfiguration/python/TileConfigFlags.py b/TileCalorimeter/TileConfiguration/python/TileConfigFlags.py
index 07368f70b3bc..46865d9d5d7f 100644
--- a/TileCalorimeter/TileConfiguration/python/TileConfigFlags.py
+++ b/TileCalorimeter/TileConfiguration/python/TileConfigFlags.py
@@ -39,6 +39,13 @@ def createTileConfigFlags():
def _doOpt2ByDefault(prevFlags):
+ #For online operation don't check run number
+ if prevFlags.Common.isOnline:
+ if 'collisions' in prevFlags.Beam.Type:
+ return False # Use OF without iterations for collisions
+ else:
+ return True
+
runNumber = prevFlags.Input.RunNumber[0]
# Run Optimal Filter with iterations (Opt2) by default,
# both for cosmics and collisions data before 2011
--
GitLab
From 4bfa7789ab6f678dba0924c5ccf43f080b59b9dc Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Mon, 22 Nov 2021 12:13:27 +0100
Subject: [PATCH 3/4] CA implementation of supercell emulation
---
.../TrigCaloRec/python/TrigCaloRecConfig.py | 17 +++++++++
.../L1CaloFEXSim/python/L1CaloFEXSimCfg.py | 35 ++++++++-----------
.../python/EmulationConfig.py | 24 ++++---------
3 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py b/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
index 886c27a3c641..39a03868cfe4 100755
--- a/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
+++ b/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
@@ -707,6 +707,23 @@ def hltCaloCellMakerCfg(flags, name=None, roisKey='UNSPECIFIED'):
acc.addEventAlgo(cellMaker, primary=True)
return acc
+def hltCaloCellSeedlessMakerCfg(flags, roisKey='UNSPECIFIED'):
+ acc = ComponentAccumulator()
+ from TrigT2CaloCommon.TrigCaloDataAccessConfig import trigCaloDataAccessSvcCfg, CaloDataAccessSvcDependencies
+ acc.merge(trigCaloDataAccessSvcCfg(flags))
+
+ hltCaloCellSeedLessMaker = CompFactory.HLTCaloCellMaker("CaloCellSeedLessFS", ExtraInputs = CaloDataAccessSvcDependencies,
+ RoIs = roisKey,
+ CellsName ="SeedLessFS")
+
+ acc.addEventAlgo(hltCaloCellSeedLessMaker, primary=True)
+
+ from CaloTools.CaloNoiseCondAlgConfig import CaloNoiseCondAlgCfg
+ acc.merge(CaloNoiseCondAlgCfg(flags, noisetype="electronicNoise"))
+ acc.addCondAlgo(CompFactory.CaloNoiseSigmaDiffCondAlg())
+
+ return acc
+
def hltTopoClusterMakerCfg(flags, name, clustersKey, cellsKey="CaloCells"):
acc = ComponentAccumulator()
from CaloRec.CaloTopoClusterConfig import (
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
index 41b084c741ad..b0baeff31ae3 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/python/L1CaloFEXSimCfg.py
@@ -6,38 +6,33 @@ def L1CaloFEXSimCfg(flags):
from AthenaConfiguration.ComponentFactory import CompFactory
acc = ComponentAccumulator()
- from TrigT1CaloFexPerf.L1PerfControlFlags import L1Phase1PerfFlags as simflags
if flags.Input.isMC:
- SCellType = "SCell"
+ sCellType = "SCell"
else:
- SCellType = "EmulatedSCell"
+ sCellType = "EmulatedSCell"
+ from TrigT1CaloFexPerf.EmulationConfig import emulateSC_Cfg
+ acc.merge(emulateSC_Cfg(flags,SCOut=sCellType))
+
+
eFEX = CompFactory.LVL1.eFEXDriver('eFEXDriver',
- SCell=SCellType )
- eFEX.eSuperCellTowerMapperTool.SCell=SCellType
- eFEX.eFEXSysSimTool.SCell=SCellType
- print(eFEX.SCell)
- print(eFEX.eSuperCellTowerMapperTool.SCell)
- print(eFEX.eFEXSysSimTool.SCell)
+ SCell=sCellType )
+ eFEX.eSuperCellTowerMapperTool = CompFactory.LVL1.eSuperCellTowerMapper('eSuperCellTowerMapper', SCell=sCellType)
+ eFEX.eFEXSysSimTool = CompFactory.LVL1.eFEXSysSim('eFEXSysSimTool', SCell=sCellType)
acc.addEventAlgo(eFEX)
# jFEX part
jFEX = CompFactory.LVL1.jFEXDriver('jFEXDriver',
- SCell=SCellType )
- jFEX.jSuperCellTowerMapperTool.SCell=SCellType
- jFEX.jFEXSysSimTool.SCell=SCellType
+ SCell=sCellType )
+ jFEX.jSuperCellTowerMapperTool = CompFactory.LVL1.jSuperCellTowerMapper('jSuperCellTowerMapper', SCell=sCellType)
+ jFEX.jFEXSysSimTool = CompFactory.LVL1.jFEXSysSim('jFEXSysSimTool', SCell=sCellType)
acc.addEventAlgo(jFEX)
gFEX = CompFactory.LVL1.gFEXDriver('gFEXDriver',
- SCell=SCellType )
- gFEX.gSuperCellTowerMapperTool.SCell=SCellType
- gFEX.gFEXSysSimTool.SCell=SCellType
+ SCell=sCellType )
+ gFEX.gSuperCellTowerMapperTool = CompFactory.LVL1.gSuperCellTowerMapper('gSuperCellTowerMapper', SCell=sCellType)
+ gFEX.gFEXSysSimTool = CompFactory.LVL1.gFEXSysSim('gFEXSysSimTool', SCell=sCellType)
acc.addEventAlgo(gFEX)
- from TrigT1CaloFexPerf.EmulationConfig import emulateSC_Cfg
-
- print("SCellType= ", SCellType)
- acc.merge(emulateSC_Cfg(flags,SCOut=SCellType))
-
return acc
if __name__ == '__main__':
diff --git a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
index 57a9a8331bc9..6e2dfb28ec06 100644
--- a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
+++ b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
@@ -66,7 +66,12 @@ def emulateSC_Cfg(flags, CellsIn="SeedLessFS", SCOut="EmulatedSCell"):
from LArCabling.LArCablingConfig import LArFebRodMappingCfg
acc.merge(LArFebRodMappingCfg(flags))
- from TrigCaloRec.TrigCaloRecConfig import HLTCaloCellSeedLessMaker
+ from TrigCaloRec.TrigCaloRecConfig import hltCaloCellSeedlessMakerCfg
+ acc.merge(hltCaloCellSeedlessMakerCfg(flags, roisKey = ""))
+
+
+ #Use SCEmulation tool that randomly samples time histograms to estimate time for low energy and negative cells forming a supercell
+ acc.addEventAlgo(CompFactory.LVL1.SCEmulation(InputCells=CellsIn, OutputSuperCells = "EmulatedSCellNoBCID"))
from LArROD.LArSCSimpleMakerConfig import LArSuperCellBCIDEmAlgCfg
@@ -79,21 +84,4 @@ def emulateSC_Cfg(flags, CellsIn="SeedLessFS", SCOut="EmulatedSCell"):
#The default input to LARSuperCellBCIDEmAlg (which applies the BCID correction) is the same: SCellContainer
acc.merge(LArSuperCellBCIDEmAlgCfg(flags, **larSCargs))
-
- HLTCaloCellSeedLessMaker = CompFactory.HLTCaloCellMaker(ExtraInputs=[('TileEMScale','ConditionStore+TileEMScale'),('TileBadChannels','ConditionStore+TileBadChannels'),
- ('IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTEM' ),
- ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTHEC' ),
- ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TILE' ),
- ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALEM' ),
- ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALHAD' ),
- ( 'LArBadChannelCont', 'ConditionStore+LArBadChannel'),
- ( 'LArMCSym', 'ConditionStore+LArMCSym'), ('LArOnOffIdMapping' , 'ConditionStore+LArOnOffIdMap' ),
- ('LArFebRodMapping' , 'ConditionStore+LArFebRodMap' ),('CaloDetDescrManager', 'ConditionStore+CaloDetDescrManager') ],
- RoIs="",
- CellsName="SeedLessFS")
-
- acc.addEventAlgo(HLTCaloCellSeedLessMaker)
- #Use SCEmulation tool that randomly samples time histograms to estimate time for low energy and negative cells forming a supercell
- acc.addEventAlgo(CompFactory.LVL1.SCEmulation(InputCells=CellsIn, OutputSuperCells = "EmulatedSCellNoBCID"))
-
return acc
--
GitLab
From cc7377e1a9e82eb9981dc11a62960c5e30701293 Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Mon, 22 Nov 2021 15:23:42 +0100
Subject: [PATCH 4/4] Revert setting up L1 simulation sequence
---
.../TriggerJobOpts/share/runHLT_standalone.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
index 40df177d6cd1..93bc824cf194 100644
--- a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
+++ b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
@@ -479,10 +479,10 @@ LumiBlockMuWriterDefault(sequence=hltBeginSeq)
# Level 1 simulation
# ---------------------------------------------------------------
if opt.doL1Sim:
- #from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationSequence
- #hltBeginSeq += Lvl1SimulationSequence(ConfigFlags)
- from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationCfg
- CAtoGlobalWrapper(Lvl1SimulationCfg, ConfigFlags, seqName="HLTBeginSeq")
+ from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationSequence
+ hltBeginSeq += Lvl1SimulationSequence(ConfigFlags)
+ #from TriggerJobOpts.Lvl1SimulationConfig import Lvl1SimulationCfg
+ #CAtoGlobalWrapper(Lvl1SimulationCfg, ConfigFlags, seqName="HLTBeginSeq")
# ---------------------------------------------------------------
# Add HLTSeeding providing inputs to HLT
--
GitLab