From 089e0aa644742dec83ac965f9ede8fe16d5585d2 Mon Sep 17 00:00:00 2001
From: John Chapman <jchapman@cern.ch>
Date: Thu, 24 Mar 2022 14:18:57 +0100
Subject: [PATCH] Add art-architecture to DigitizationTests and
 DigitizationTestsMT ART scripts

---
 .../test/test_Digi_tf_RUN4_presampling_mu140.sh                  | 1 +
 .../test/test_Digi_tf_RUN4_presampling_mu200.sh                  | 1 +
 .../DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu60.sh | 1 +
 .../test/test_Digi_tf_RUN4_single_muon_no_pileup.sh              | 1 +
 .../DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu140.sh      | 1 +
 .../DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu200.sh      | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu60.sh | 1 +
 .../DigitizationTests/test/test_Digi_tf_RUN4_ttbar_no_pileup.sh  | 1 +
 .../test/test_Digi_tf_mc15_2010_ttbar_no_pileup.sh               | 1 +
 .../test/test_Digi_tf_mc15_2011_ttbar_no_pileup.sh               | 1 +
 .../test/test_Digi_tf_mc15_2012_ttbar_no_pileup.sh               | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc15_2015_cosmics.sh     | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc15_2015_heavy_ion.sh   | 1 +
 .../test/test_Digi_tf_mc15_2015_ttbar_25ns_pileup_noNoise.sh     | 1 +
 .../test/test_Digi_tf_mc16_CA_vs_CG_no_pileup.sh                 | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16a_CA_vs_CG.sh  | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16a_qballs.sh    | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar.sh     | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc16a_ttbar_algs.sh      | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16d_CA_vs_CG.sh  | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16d_ttbar.sh     | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16e_CA_vs_CG.sh  | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar.sh     | 1 +
 .../test/test_Digi_tf_mc16e_ttbar_beamspotsizereweight.sh        | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG.sh  | 1 +
 .../test/test_Digi_tf_mc20a_CA_vs_CG_no_minbias.sh               | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc20a_presampling.sh     | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc20d_CA_vs_CG.sh  | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc20d_presampling.sh     | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG.sh  | 1 +
 .../test/test_Digi_tf_mc20e_CA_vs_CG_no_minbias.sh               | 1 +
 .../test/test_Digi_tf_mc20e_CA_vs_CG_presampling_custom.sh       | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc20e_presampling.sh     | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh     | 1 +
 .../Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh     | 1 +
 .../DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh | 1 +
 .../test/test_Digi_tf_multistep_presampling_CA_vs_CG.sh          | 1 +
 .../test/test_Digi_tf_RUN4_MP_presampling_reproducibility.sh     | 1 +
 .../test/test_Digi_tf_RUN4_MP_ttbar_reproducibility.sh           | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT.sh          | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_1thread.sh  | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_LAr.sh      | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Muon.sh     | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_SCT.sh      | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_TRT.sh      | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Tile.sh     | 1 +
 .../test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_pixel.sh    | 1 +
 .../test/test_Digi_tf_mc16d_premixing_for_MT_AthenaMP.sh         | 1 +
 .../test/test_Digi_tf_mc16d_ttbar_AthenaMP.sh                    | 1 +
 .../test/test_Digi_tf_mc20_ttbar_no_pileup_MT.sh                 | 1 +
 .../test/test_Digi_tf_mc20_ttbar_no_pileup_MT_1thread.sh         | 1 +
 ...gi_tf_mc20e_MP_SharedWriter_NoParallelComp_reproducibility.sh | 1 +
 .../test/test_Digi_tf_mc20e_MP_SharedWriter_reproducibility.sh   | 1 +
 .../test/test_Digi_tf_mc20e_MP_presampling_reproducibility.sh    | 1 +
 .../test/test_Digi_tf_mc20e_MP_reproducibility.sh                | 1 +
 .../test_Digi_tf_multistep_MP_presampling_reproducibility.sh     | 1 +
 56 files changed, 56 insertions(+)

diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu140.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu140.sh
index 6a4649e1038b..d35bd5cc5f01 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu140.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu140.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 pile-up presampling
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_presampling.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu200.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu200.sh
index 4e0cfb9fdf66..5e5cb385cd0e 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu200.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu200.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 pile-up presampling
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_presampling.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu60.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu60.sh
index 1bfe9372ee22..7c610b7a92bb 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu60.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_presampling_mu60.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 pile-up presampling
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_presampling.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_single_muon_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_single_muon_no_pileup.sh
index aa16d3d0685a..f3c80ec94cd8 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_single_muon_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_single_muon_no_pileup.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 digitization of a single muon sample without pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_muons.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu140.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu140.sh
index 33101ac64aaf..878439a6a25a 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu140.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu140.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 digitization of a ttbar sample with pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_ttbar.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu200.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu200.sh
index f506b9619275..e7a8c63d925c 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu200.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu200.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 digitization of a ttbar sample with pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_ttbar.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu60.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu60.sh
index bfb15eb08142..be3ea78c8656 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu60.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_mu60.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 digitization of a ttbar sample with pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_ttbar.mu200.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_no_pileup.sh
index fe22094555e1..e677b0742d8d 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_RUN4_ttbar_no_pileup.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 digitization of a ttbar sample without pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: RUN4_ttbar.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2010_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2010_ttbar_no_pileup.sh
index 39381d278d14..bc43e860b4f1 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2010_ttbar_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2010_ttbar_no_pileup.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2010_ttbar_no_pileup.RDO.pool.root
 
 DigiOutFileName="mc15_2010_ttbar_no_pileup.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2011_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2011_ttbar_no_pileup.sh
index b9488f17fe09..4e3a71c5ffd0 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2011_ttbar_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2011_ttbar_no_pileup.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2011_ttbar_no_pileup.RDO.pool.root
 
 DigiOutFileName="mc15_2011_ttbar_no_pileup.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2012_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2012_ttbar_no_pileup.sh
index 46f81e43f06b..659694199d14 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2012_ttbar_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2012_ttbar_no_pileup.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2012_ttbar_no_pileup.RDO.pool.root
 
 DigiOutFileName="mc15_2012_ttbar_no_pileup.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_cosmics.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_cosmics.sh
index 79dea62ad014..1ec09838e6ac 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_cosmics.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_cosmics.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2015_cosmics.RDO.pool.root
 
 DigiOutFileName="mc15_2015_cosmics.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_heavy_ion.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_heavy_ion.sh
index 3464cad71d8f..fd253f2bbcb5 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_heavy_ion.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_heavy_ion.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2015_heavyIon.RDO.pool.root
 
 DigiOutFileName="mc15_2015_heavyIon.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_ttbar_25ns_pileup_noNoise.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_ttbar_25ns_pileup_noNoise.sh
index 661dec0f7353..7be6b8768654 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_ttbar_25ns_pileup_noNoise.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc15_2015_ttbar_25ns_pileup_noNoise.sh
@@ -6,6 +6,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-output: mc15_2015_ttbar_25ns_pileup_noNoise.RDO.pool.root
 
 DigiOutFileName="mc15_2015_ttbar_25ns_pileup_noNoise.RDO.pool.root"
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16_CA_vs_CG_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16_CA_vs_CG_no_pileup.sh
index cf4eb0f698f8..62863f7c57c0 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16_CA_vs_CG_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16_CA_vs_CG_no_pileup.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc16a_ttbar.CG.RDO.pool.root
 # art-output: mc16a_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_CA_vs_CG.sh
index c799a06cb411..5cb3d072c1bb 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc16a_ttbar.CG.RDO.pool.root
 # art-output: mc16a_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_qballs.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_qballs.sh
index 483e037bf4b4..f3543e30b1e6 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_qballs.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_qballs.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC16a qball sample with 2016a geometry and conditions, 25ns pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar.sh
index 90959f7b3dee..f2a81fc0b639 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC16a ttbar sample with 2016a geometry and conditions, 25ns pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar_algs.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar_algs.sh
index 052cb08f768e..b6298257a1f9 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar_algs.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16a_ttbar_algs.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC16a ttbar sample with 2016a geometry and conditions, 25ns pile-up and using digitizationFlags.doXingByXingPileUp=False
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc16a_ttbar_algs.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_CA_vs_CG.sh
index 49172af5b702..1063a2f1b1fe 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc16d_ttbar.CG.RDO.pool.root
 # art-output: mc16d_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_ttbar.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_ttbar.sh
index 0886eba9fcc5..2321bef6fe21 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_ttbar.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16d_ttbar.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an mc16d ttbar sample with 2016d geometry and conditions, 25ns pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_CA_vs_CG.sh
index 4aeeb93e5ca1..49051a7abf4d 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc16e_ttbar.CG.RDO.pool.root
 # art-output: mc16e_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar.sh
index bc4482398fa0..063954275a95 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an mc16e ttbar sample with 2018 geometry and conditions, 25ns pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar_beamspotsizereweight.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar_beamspotsizereweight.sh
index 5a87fa079dc8..48102e635eba 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar_beamspotsizereweight.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc16e_ttbar_beamspotsizereweight.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an mc16e ttbar sample with 2018 geometry and conditions, 25ns pile-up
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG.sh
index e4d21e799700..0914a5a9bf7f 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20a_ttbar.CG.RDO.pool.root
 # art-output: mc20a_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG_no_minbias.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG_no_minbias.sh
index 2fd91612c130..71d1bdb299b0 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG_no_minbias.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_CA_vs_CG_no_minbias.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20a_ttbar.CG.RDO.pool.root
 # art-output: mc20a_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_presampling.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_presampling.sh
index e95f2750d7a6..1c146379a304 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_presampling.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20a_presampling.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20a pile-up presamling with 2015/2016 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
 # art-output: mc20a_presampling.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_CA_vs_CG.sh
index af766879b480..621c3d1fbff3 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20d_ttbar.CG.RDO.pool.root
 # art-output: mc20d_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_presampling.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_presampling.sh
index aaa762050372..2813714d26df 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_presampling.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20d_presampling.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20d pile-up presamling with 2017 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
 # art-output: mc20d_presampling.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG.sh
index 1bf54427f0ad..4fbb0c62bae6 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20e_ttbar.CG.RDO.pool.root
 # art-output: mc20e_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_no_minbias.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_no_minbias.sh
index 8e07c012fddb..a0850772057e 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_no_minbias.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_no_minbias.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20e_ttbar.CG.RDO.pool.root
 # art-output: mc20e_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_presampling_custom.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_presampling_custom.sh
index 99d9756a1b62..75dcf3882bbf 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_presampling_custom.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_CA_vs_CG_presampling_custom.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc20e_presampling.CG.RDO.pool.root
 # art-output: mc20e_presampling.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_presampling.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_presampling.sh
index bc729764e4f3..06d437838d83 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_presampling.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc20e_presampling.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20e pile-up presamling with 2018 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
 # art-output: mc20e_presampling.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh
index 40633e838d44..dc22005ddb70 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc21a_presampling.CG.RDO.pool.root
 # art-output: mc21a_presampling.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh
index 730a13e42747..50337a823166 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc21a_ttbar.CG.RDO.pool.root
 # art-output: mc21a_ttbar.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh
index 406357dd525a..ac96f39163d3 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: mc21a.ttbar.nopileup.CG.RDO.pool.root
 # art-output: mc21a.ttbar.nopileup.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_multistep_presampling_CA_vs_CG.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_multistep_presampling_CA_vs_CG.sh
index 914f78d0dde8..3cda34ceaa73 100755
--- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_multistep_presampling_CA_vs_CG.sh
+++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_multistep_presampling_CA_vs_CG.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach.
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: master/Athena
 # art-output: multistep_presampling.CG.RDO.pool.root
 # art-output: multistep_presampling.CA.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_presampling_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_presampling_reproducibility.sh
index 9dc9d2e21211..bf475baadd95 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_presampling_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_presampling_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 pile-up pre-mixing MP tests
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: RUN4_presampling_SP.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_ttbar_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_ttbar_reproducibility.sh
index 3be16d985dc7..8933334d3bbf 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_ttbar_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_RUN4_MP_ttbar_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run 4 pile-up ttbar MP tests
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: RUN4_ttbar_SP.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT.sh
index ef6ca0798550..181e5d3c4a91 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_1thread.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_1thread.sh
index 2715629cf2e3..9a68b6556109 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_1thread.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_1thread.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT with one thread
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_LAr.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_LAr.sh
index ac9c9ee90e48..fd43592a2257 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_LAr.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_LAr.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run LAr digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Muon.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Muon.sh
index 010358461244..cec61811235d 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Muon.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Muon.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run Muon digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_SCT.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_SCT.sh
index c793d9b0c92a..f49c233e3f04 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_SCT.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_SCT.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run SCT digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_TRT.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_TRT.sh
index 0b54ec26bd5d..52e853f20d75 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_TRT.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_TRT.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run TRT digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Tile.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Tile.sh
index fbb535631b36..bdfd994ee801 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Tile.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_Tile.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run Tile digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_pixel.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_pixel.sh
index 3933859d29cd..3d0e55be8296 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_pixel.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16a_ttbar_no_pileup_ST_vs_MT_pixel.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run Pixel digitization of an MC16a ttbar sample with 2016 geometry and conditions, without pile-up using Athena and AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc16a_ttbar.ST.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_premixing_for_MT_AthenaMP.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_premixing_for_MT_AthenaMP.sh
index b05dd41ec087..fbfee83b5261 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_premixing_for_MT_AthenaMP.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_premixing_for_MT_AthenaMP.sh
@@ -3,6 +3,7 @@
 # art-description: Run MC16 pile-up pre-mixing with 2016d geometry and conditions, 25ns pile-up, MT output containers in AthenaMP
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-output: mc16d_premixing_MT.MP.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_ttbar_AthenaMP.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_ttbar_AthenaMP.sh
index 3d5c1ed4bb3e..088c05ce154a 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_ttbar_AthenaMP.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc16d_ttbar_AthenaMP.sh
@@ -3,6 +3,7 @@
 # art-description: Run digitization of an mc16d ttbar sample with 2016d geometry and conditions, 25ns pile-up in AthenaMP
 # art-include: master/Athena
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-output: mc16d_ttbar.MP.RDO.pool.root
 
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT.sh
index 71327935e364..8b703bd6c0a3 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC20 ttbar sample with 2018 geometry and conditions, without pile-up using AthenaMT
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT_1thread.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT_1thread.sh
index 395f510acc06..b01d0a22b8bc 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT_1thread.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20_ttbar_no_pileup_MT_1thread.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run digitization of an MC20 ttbar sample with 2018 geometry and conditions, without pile-up using AthenaMT with one thread
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_NoParallelComp_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_NoParallelComp_reproducibility.sh
index fb37ed2ca462..f77f47e7692f 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_NoParallelComp_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_NoParallelComp_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20e pile-up pre-mixing with 2018 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc20e_SP.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_reproducibility.sh
index bd5f55f24650..9cec190b3ae1 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_SharedWriter_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20e pile-up pre-mixing with 2018 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: mc20e_SP.RDO.pool.root
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_presampling_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_presampling_reproducibility.sh
index 3c9018571428..5e557eeebe29 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_presampling_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_presampling_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20e pile-up pre-mixing with 2018 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_reproducibility.sh
index 50e6232f8b8b..63527ae1275e 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc20e_MP_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run MC20e pile-up pre-mixing with 2018 geometry and conditions, 25ns pile-up, MT output containers
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: 22.0-mc20/Athena
 # art-include: master/Athena
diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_multistep_MP_presampling_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_multistep_MP_presampling_reproducibility.sh
index 29886212bf04..7bead3fa8f6e 100755
--- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_multistep_MP_presampling_reproducibility.sh
+++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_multistep_MP_presampling_reproducibility.sh
@@ -2,6 +2,7 @@
 #
 # art-description: Run multistep pile-up presampling
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-athena-mt: 8
 # art-include: master/Athena
 # art-output: multistep_presampling_SP.RDO.pool.root
-- 
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