diff --git a/Simulation/SimuJobTransforms/share/skeleton.HITtoRDO.py b/Simulation/SimuJobTransforms/share/skeleton.HITtoRDO.py
index 747d99d92bcaae3df8a0686f03a960eb32a76e58..b28f3f6ff9d7b2c912acdb5cfce520ddadf243a3 100644
--- a/Simulation/SimuJobTransforms/share/skeleton.HITtoRDO.py
+++ b/Simulation/SimuJobTransforms/share/skeleton.HITtoRDO.py
@@ -398,16 +398,20 @@ topSeq = AlgSequence()
 ## Set Overall per-Algorithm time-limit on the AlgSequence
 topSeq.TimeOut = 43200 * Units.s
 
-try:
-    timingOutput = "HITStoRDO_timings"
-    if digitizationFlags.PileUpPresampling and 'LegacyOverlay' not in digitizationFlags.experimentalDigi():
-        from OverlayCommonAlgs.OverlayFlags import overlayFlags
-        timingOutput = overlayFlags.bkgPrefix() + timingOutput
-
-    from RecAlgs.RecAlgsConf import TimingAlg
-    topSeq += TimingAlg("DigiTimerBegin", TimingObjOutputName = timingOutput)
-except:
-    digilog.warning('Could not add TimingAlg, no timing info will be written out.')
+
+if jobproperties.ConcurrencyFlags.NumThreads() == 0:
+    try:
+        timingOutput = "HITStoRDO_timings"
+        if digitizationFlags.PileUpPresampling and 'LegacyOverlay' not in digitizationFlags.experimentalDigi():
+            from OverlayCommonAlgs.OverlayFlags import overlayFlags
+            timingOutput = overlayFlags.bkgPrefix() + timingOutput
+
+        from RecAlgs.RecAlgsConf import TimingAlg
+        topSeq += TimingAlg("DigiTimerBegin", TimingObjOutputName = timingOutput)
+    except:
+        digilog.warning('Could not add TimingAlg, no timing info will be written out.')
+else:
+    digilog.info("MT mode, not scheduling TimingAlg")
 
 include ("Digitization/Digitization.py")