diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh index dc22005ddb7056f34bb7b166eed20fbb5dee3a09..48f8ab287499500024a18b551ac1f47cdfd50e2b 100755 --- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh +++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling.sh @@ -3,6 +3,7 @@ # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach. # art-type: grid # art-architecture: '#x86_64-intel' +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a_presampling.CG.RDO.pool.root # art-output: mc21a_presampling.CA.RDO.pool.root diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable.sh index 6c23332890d52b0405e4836f0b4b953de8d8dbcc..36e813f2ae087257281d116f1f2c782038e0ffc9 100755 --- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable.sh +++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable.sh @@ -3,6 +3,7 @@ # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach. # art-type: grid # art-architecture: '#x86_64-intel' +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a_presampling.VarBS.CG.RDO.pool.root # art-output: mc21a_presampling.VarBS.CA.RDO.pool.root diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable_TruthOnly.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable_TruthOnly.sh index e2f4f254b752835a1146bd0596c2cd48fd25a299..1efc52eaf4726661b5f0112387fde13f128724c7 100755 --- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable_TruthOnly.sh +++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_presampling_variable_TruthOnly.sh @@ -3,6 +3,7 @@ # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach. # art-type: grid # art-architecture: '#x86_64-intel' +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a_presampling.VarBSTruth.CG.RDO.pool.root # art-output: mc21a_presampling.VarBSTruth.CA.RDO.pool.root diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh index 50337a823166d3a74f8e5d40b55dbb0fec6b2950..e4b9a743216d07e90b84e3d6549984ec4b39ab7a 100755 --- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh +++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar.sh @@ -3,6 +3,7 @@ # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach. # art-type: grid # art-architecture: '#x86_64-intel' +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a_ttbar.CG.RDO.pool.root # art-output: mc21a_ttbar.CA.RDO.pool.root diff --git a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh index ac96f39163d365aaa31afc49b7ed24eba6cf9bc6..1b1f03395c2481406651d3c0ab1f6ceb2b9fbca4 100755 --- a/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh +++ b/Simulation/Tests/DigitizationTests/test/test_Digi_tf_mc21a_ttbar_no_pileup.sh @@ -3,6 +3,7 @@ # art-description: Run a digitization example to compare configuration between ConfGetter and the new ComponentAccumulator approach. # art-type: grid # art-architecture: '#x86_64-intel' +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a.ttbar.nopileup.CG.RDO.pool.root # art-output: mc21a.ttbar.nopileup.CA.RDO.pool.root diff --git a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc21a_MP_presampling_reproducibility.sh b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc21a_MP_presampling_reproducibility.sh index 71e86155584aafbc4dd9709267e0a6f0052e3c58..5ece773f34fb108447c2fea515e6e3427feff589 100755 --- a/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc21a_MP_presampling_reproducibility.sh +++ b/Simulation/Tests/DigitizationTestsMT/test/test_Digi_tf_mc21a_MP_presampling_reproducibility.sh @@ -4,6 +4,7 @@ # art-type: grid # art-architecture: '#x86_64-intel' # art-athena-mt: 8 +# art-include: 22.0/Athena # art-include: master/Athena # art-output: mc21a_presampling_SP.RDO.pool.root # art-output: mc21a_presampling_MP_fork_evt0.RDO.pool.root diff --git a/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar.sh b/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar.sh index 8264041af00e8cd23f9dcffbccab63f676f70abc..83be46f11d16352e67a46127947ebd802ccf17ec 100755 --- a/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar.sh +++ b/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: Run simulation using ISF with the FullG4MT_QS simulator, reading 13 TeV ttbar events, writing HITS, using 2021 geometry and MC21 conditions +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar_VarBS.sh b/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar_VarBS.sh index b348eef9555f47db4c657086b398890e69aac4d8..f553998e101bd8a8f5f2879485ec508a46fbc407 100755 --- a/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar_VarBS.sh +++ b/Simulation/Tests/ISF_Validation/test/test_MC21_FullG4MT_QS_ttbar_VarBS.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: Run simulation using ISF with the FullG4MT_QS simulator, reading 13 TeV ttbar events, writing HITS, using 2021 geometry and MC21 conditions +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_AF3InputParamFiles.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_AF3InputParamFiles.sh index 761d5e259c9b1ec4bc23487d3fcf476f364894dd..1a3093d877680c0916d09c7be17dc6c23c23c20b 100644 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_AF3InputParamFiles.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_AF3InputParamFiles.sh @@ -2,6 +2,7 @@ # # art-description: MC21-style simulation using FullG4 for producing input samples needed for the Fast Calorimeter Simulation parametrisation # art-type: build +# art-include: 22.0/Athena # art-include: master/Athena # Full chain with special flags @@ -39,4 +40,4 @@ FCS_Ntup_tf.py --inputESDFile 'ESD.pool.root' \ --outputNTUP_FCSFile 'calohit.root' \ --doG4Hits true -echo "art-result: $? fcs_ntup step" \ No newline at end of file +echo "art-result: $? fcs_ntup step" diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime.sh index 664a3e5009bd4b44c5cc32ccd422f464637fb0ca..bdf73b6b88d123046502aaf9c482d8efa24d4440 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime.sh @@ -1,6 +1,8 @@ #!/bin/sh # # art-description: MC21-style simulation using FullG4_QS (13 TeV Zprime input - needs updating) +# art-include: 22.0/Athena +# art-include: 22.0/AthSimulation # art-include: master/Athena # art-include: master/AthSimulation # art-type: grid diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime_2evts.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime_2evts.sh index 4af51d60c19730b264e776d19f9d5de995758a00..8eeafb1a7b5359f06b6b65a2699c8a9033ccc6ce 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime_2evts.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ZPrime_2evts.sh @@ -2,6 +2,8 @@ # # art-description: MC21-style simulation using FullG4_QS (13 TeV Zprime input - needs updating) # art-type: build +# art-include: 22.0/Athena +# art-include: 22.0/AthSimulation # art-include: master/Athena # art-include: master/AthSimulation diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ttbar.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ttbar.sh index 253d6d200ab5d3adaf0ade2c55dd7bb0828650a8..733c62c76c6df0b7d6a0011d1bc4dc5ab3d81445 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ttbar.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_QS_ttbar.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using FullG4MT_QS (13 TeV ttbar input - needs updating) +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ReproducibilityTest.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ReproducibilityTest.sh index 72de610d1b332bf581e73ddde85810b1d5efe7b8..3c6326a128266e6181e5649908cfbba581994b17 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ReproducibilityTest.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ReproducibilityTest.sh @@ -1,6 +1,8 @@ #!/bin/sh # # art-description: MC21-style simulation using FullG4, checking that the SkipEvents argument works (7 TeV ttbar input - needs updating) +# art-include: 22.0/Athena +# art-include: 22.0/AthSimulation # art-include: master/Athena # art-include: master/AthSimulation # art-type: grid diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_minbias.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_minbias.sh index 0275640bfd74a987931619729da192f69216000c..6197db1a81100f7deffad7d15a35c8b5033475b9 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_minbias.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_minbias.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using FullG4 (7 TeV minbias input - needs updating) +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ttbar_2evts.sh b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ttbar_2evts.sh index b1ad009ea05fcbdbee955ed25036fc3f7041c6fa..8c5edc6ff5cb5b11da0601a52ab9bf90e71f9b3a 100755 --- a/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ttbar_2evts.sh +++ b/Simulation/Tests/ISF_Validation/test/test_RUN3_FullG4_ttbar_2evts.sh @@ -2,6 +2,8 @@ # # art-description: MC21-style simulation using FullG4 (13 TeV ttbar input - needs updating) # art-type: build +# art-include: 22.0/Athena +# art-include: 22.0/AthSimulation # art-include: master/Athena # art-include: master/AthSimulation diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3F_G4MS_ttbar_CAvsCG.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3F_G4MS_ttbar_CAvsCG.sh index 34cb17bcad6935abc4cf8b5c6c60bc436bc90abe..3ee09a0530d7a37fa7f455bc5ad3389fc03a445c 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3F_G4MS_ttbar_CAvsCG.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3F_G4MS_ttbar_CAvsCG.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using ATLFAST3F_G4MS +# art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' # art-output: test.*.HITS.pool.root diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_QS_ttbar_CAvsCG.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_QS_ttbar_CAvsCG.sh index 2c484311dfa64054d07d226b83f5dbf83e15dacb..280690525dcac22ebcdd72399c5b46d73fb486aa 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_QS_ttbar_CAvsCG.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_QS_ttbar_CAvsCG.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using ATLFAST3MT_QS +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_ttbar_CAvsCG.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_ttbar_CAvsCG.sh index cd84bdb14eebaf7d0fcb7c34e9a5584b1636f675..65f3e2d18659e652c085821a5e7223ead514948f 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_ttbar_CAvsCG.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFAST3MT_ttbar_CAvsCG.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using ATLFAST3MT +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFASTIIF_G4MS_ttbar_CAvsCG.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFASTIIF_G4MS_ttbar_CAvsCG.sh index 061bf83e4c826a80823febee99e40189b513de0e..2f69963c1f23c6b6bb27086685a89ecb337ab7c0 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFASTIIF_G4MS_ttbar_CAvsCG.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_ATLFASTIIF_G4MS_ttbar_CAvsCG.sh @@ -2,6 +2,7 @@ # # art-description: MC21-style simulation using ATLFASTIIF_G4MS # art-type: grid +# art-include: master/Athena # art-architecture: '#x86_64-intel' # art-output: test.*.HITS.pool.root # art-output: log.* diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_FullG4MT_QS_ttbar_CAvsCG.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_FullG4MT_QS_ttbar_CAvsCG.sh index a7df8660cbb900d8404c377bce115e9c0f9cce1a..be22737752fe33cb05fec5dca659085018adc444 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_FullG4MT_QS_ttbar_CAvsCG.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3Sym_FullG4MT_QS_ttbar_CAvsCG.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using FullG4MT_QS +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3_ATLFAST3_ttbar_MP.sh b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3_ATLFAST3_ttbar_MP.sh index f320ad0651c93b7411dadef770ec1181b34f3d3b..d2057016bb45d647e66cd46491de51c031df50ab 100755 --- a/Simulation/Tests/ISF_ValidationMT/test/test_RUN3_ATLFAST3_ttbar_MP.sh +++ b/Simulation/Tests/ISF_ValidationMT/test/test_RUN3_ATLFAST3_ttbar_MP.sh @@ -1,6 +1,7 @@ #!/bin/sh # # art-description: MC21-style simulation using ATLFAST3MT in AthenaMP +# art-include: 22.0/Athena # art-include: master/Athena # art-type: grid # art-architecture: '#x86_64-intel' diff --git a/Simulation/Tests/OverlayTests/test/test_MCOverlay_MC21a_ttbar.sh b/Simulation/Tests/OverlayTests/test/test_MCOverlay_MC21a_ttbar.sh index ce32e43500bac93de67874d3e4eb0cbd04479826..4b166ba6d48272585d5b2147e04cf41defa42bc2 100755 --- a/Simulation/Tests/OverlayTests/test/test_MCOverlay_MC21a_ttbar.sh +++ b/Simulation/Tests/OverlayTests/test/test_MCOverlay_MC21a_ttbar.sh @@ -3,7 +3,7 @@ # art-description: MC+MC Overlay without reco for MC21a, ttbar # art-type: grid # art-architecture: '#x86_64-intel' -# art-include: 22.0-mc20/Athena +# art-include: 22.0/Athena # art-include: master/Athena # art-output: *.root