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Alexander Undrus
athena
Commits
51892f33
Commit
51892f33
authored
Sep 29, 2021
by
Frank Winklmeier
Browse files
Merge branch 'newBranch.1632380948' into 'master'
Re-inclusion of bad channel masking in the HLTCalo See merge request
atlas/athena!46736
parents
4c8bdedb
010c9308
Changes
15
Hide whitespace changes
Inline
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LArCalorimeter/LArBadChannelTool/python/LArBadChannelAccess.py
View file @
51892f33
...
...
@@ -7,7 +7,7 @@ def LArBadChannelAccess(algname="LArBadChannelCondAlg",dbString=None):
condSeq
=
AthSequencer
(
"AthCondSeq"
)
if
hasattr
(
condSeq
,
algname
):
print
(
"Access to bad
Feb
info already set up"
)
print
(
"Access to bad
Cell
info already set up"
)
return
...
...
@@ -22,10 +22,12 @@ def LArBadChannelAccess(algname="LArBadChannelCondAlg",dbString=None):
else
:
if
conddb
.
isOnline
:
foldername
=
"/LAR/BadChannels/BadChannels"
conddb
.
addFolder
(
"LAR"
,
foldername
,
className
=
"CondAttrListCollection"
)
if
not
conddb
.
folderRequested
(
foldername
):
conddb
.
addFolder
(
"LAR"
,
foldername
,
className
=
"CondAttrListCollection"
)
else
:
foldername
=
"/LAR/BadChannelsOfl/BadChannels"
conddb
.
addFolder
(
"LAR_OFL"
,
foldername
,
className
=
"CondAttrListCollection"
)
if
not
conddb
.
folderRequested
(
foldername
):
conddb
.
addFolder
(
"LAR_OFL"
,
foldername
,
className
=
"CondAttrListCollection"
)
pass
pass
...
...
LArCalorimeter/LArExample/LArConditionsCommon/share/LArConditionsCommon_MC_jobOptions.py
View file @
51892f33
...
...
@@ -91,11 +91,13 @@ if LArDBConnection != "" and 'InputDBConnectionBadChannel' not in dir():
from
LArBadChannelTool.LArBadChannelToolConf
import
LArBadChannelCondAlg
,
LArBadFebCondAlg
if
LArDBConnection
!=
""
:
conddb
.
addFolder
(
""
,
BadChannelsFolder
+
"<dbConnection>"
+
InputDBConnectionBadChannel
+
"</dbConnection>"
,
className
=
"CondAttrListCollection"
)
else
:
conddb
.
addFolder
(
LArDB
,
BadChannelsFolder
,
className
=
"CondAttrListCollection"
)
condSeq
+=
LArBadChannelCondAlg
(
ReadKey
=
BadChannelsFolder
)
if
not
conddb
.
folderRequested
(
BadChannelsFolder
):
if
LArDBConnection
!=
""
:
conddb
.
addFolder
(
""
,
BadChannelsFolder
+
"<dbConnection>"
+
InputDBConnectionBadChannel
+
"</dbConnection>"
,
className
=
"CondAttrListCollection"
)
else
:
conddb
.
addFolder
(
LArDB
,
BadChannelsFolder
,
className
=
"CondAttrListCollection"
)
if
not
hasattr
(
condSeq
,
"LArBadChannelCondAlg"
):
condSeq
+=
LArBadChannelCondAlg
(
ReadKey
=
BadChannelsFolder
)
if
LArDBConnection
!=
""
:
conddb
.
addFolder
(
""
,
MissingFEBsFolder
+
"<dbConnection>"
+
InputDBConnectionBadChannel
+
"</dbConnection>"
,
className
=
'AthenaAttributeList'
)
else
:
...
...
LArCalorimeter/LArExample/LArConditionsCommon/share/LArConditionsCommon_comm_jobOptions.py
View file @
51892f33
...
...
@@ -52,11 +52,13 @@ rekeyBC="<key>/LAR/BadChannels/BadChannels</key>"
rekeyMF
=
"<key>/LAR/BadChannels/MissingFEBs</key>"
conddb
.
addFolderSplitOnline
(
"LAR"
,
"/LAR/BadChannels/BadChannels"
,
"/LAR/BadChannelsOfl/BadChannels"
+
forceRN
+
rekeyBC
,
className
=
"CondAttrListCollection"
)
from
LArBadChannelTool.LArBadChannelToolConf
import
LArBadChannelCondAlg
condSeq
+=
LArBadChannelCondAlg
(
ReadKey
=
"/LAR/BadChannels/BadChannels"
)
if
not
hasattr
(
condSeq
,
"LArBadChannelCondAlg"
):
condSeq
+=
LArBadChannelCondAlg
(
ReadKey
=
"/LAR/BadChannels/BadChannels"
)
conddb
.
addFolderSplitOnline
(
"LAR"
,
"/LAR/BadChannels/MissingFEBs"
,
"/LAR/BadChannelsOfl/MissingFEBs"
+
forceRN
+
rekeyMF
,
className
=
'AthenaAttributeList'
)
from
LArBadChannelTool.LArBadChannelToolConf
import
LArBadFebCondAlg
condSeq
+=
LArBadFebCondAlg
(
ReadKey
=
"/LAR/BadChannels/MissingFEBs"
)
if
not
hasattr
(
condSeq
,
"LArBadFebCondAlg"
):
condSeq
+=
LArBadFebCondAlg
(
ReadKey
=
"/LAR/BadChannels/MissingFEBs"
)
if
(
rec
.
doESD
()
or
rec
.
doRDOTrigger
()):
if
'COMP200'
not
in
conddb
.
GetInstance
():
...
...
Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
View file @
51892f33
...
...
@@ -574,7 +574,7 @@ class HLTCaloCellSeedLessMaker (_HLTCaloCellMaker):
setMinimalCaloSetup
()
from
AthenaCommon.AppMgr
import
ServiceMgr
as
svcMgr
self
.
ExtraInputs
=
[(
'TileEMScale'
,
'ConditionStore+TileEMScale'
),(
'TileBadChannels'
,
'ConditionStore+TileBadChannels'
)]
self
.
ExtraInputs
+=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
self
.
ExtraInputs
+=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
),
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
self
.
CellsName
=
"SeedLessFS"
self
.
RoIs
=
''
self
.
TrigDataAccessMT
=
svcMgr
.
TrigCaloDataAccessSvc
...
...
@@ -584,7 +584,7 @@ class HLTCaloCellMaker (_HLTCaloCellMaker):
def
__init__
(
self
,
name
):
super
(
HLTCaloCellMaker
,
self
).
__init__
(
name
)
self
.
ExtraInputs
=
[(
'TileEMScale'
,
'ConditionStore+TileEMScale'
),(
'TileBadChannels'
,
'ConditionStore+TileBadChannels'
)]
self
.
ExtraInputs
+=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
self
.
ExtraInputs
+=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
),
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
from
AthenaMonitoringKernel.GenericMonitoringTool
import
GenericMonitoringTool
monTool
=
GenericMonitoringTool
(
'MonTool'
)
maxNumberOfCells
=
1600.0
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/TrigT2CaloCommon/LArCellCont.h
View file @
51892f33
...
...
@@ -25,6 +25,7 @@
#include "LArRawConditions/LArMCSym.h"
#include "LArRecConditions/LArFebRodMapping.h"
#include "LArCabling/LArOnOffIdMapping.h"
#include "LArRecConditions/LArBadChannelCont.h"
#include <vector>
...
...
@@ -69,7 +70,7 @@ class LArCellCont : public std::vector<LArCellCollection*>
virtual
~
LArCellCont
()
{
};
/** initialize method. Builds all cells and collections. */
StatusCode
initialize
(
const
LArMCSym
&
mcsym
,
const
LArFebRodMapping
&
febrod
)
;
StatusCode
initialize
(
const
LArMCSym
&
mcsym
,
const
LArFebRodMapping
&
febrod
,
const
LArBadChannelCont
&
badchannel
)
;
/** finalize method. Destroys all cells and collections. */
StatusCode
finalize
(
void
)
;
/** sets Event Number */
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/python/CaloDef.py
View file @
51892f33
...
...
@@ -27,7 +27,7 @@ def _algoHLTCaloCell(name="HLTCaloCellMaker", inputEDM='', outputEDM='CellsClust
algo
.
RoIs
=
inputEDM
algo
.
TrigDataAccessMT
=
svcMgr
.
TrigCaloDataAccessSvc
algo
.
CellsName
=
outputEDM
algo
.
ExtraInputs
+=
[
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
algo
.
ExtraInputs
+=
[
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
return
algo
def
_algoHLTHIEventShape
(
name
=
'HLTEventShapeMaker'
,
inputEDM
=
'CellsClusters'
,
outputEDM
=
'HIEventShape'
):
...
...
@@ -95,7 +95,7 @@ def _algoL2Egamma(inputEDM="", doRinger=False, ClustersName="HLT_FastCaloEMClust
from
TrigT2CaloEgamma.TrigT2CaloEgammaConfig
import
T2CaloEgamma_All
algo
=
T2CaloEgamma_All
(
"L2CaloLayersFex"
)
algo
.
RoIs
=
inputEDM
algo
.
ExtraInputs
+=
[
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
algo
.
ExtraInputs
+=
[
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
)
]
from
TrigEDMConfig.TriggerEDMRun3
import
recordable
algo
.
ClustersName
=
recordable
(
ClustersName
)
return
algo
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/python/TrigCaloDataAccessConfig.py
View file @
51892f33
...
...
@@ -36,7 +36,8 @@ CaloDataAccessSvcDependencies = [('TileEMScale' , 'ConditionStore+TileEMSc
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
),
(
'LArOnOffIdMapping'
,
'ConditionStore+LArOnOffIdMap'
),
(
'LArFebRodMapping'
,
'ConditionStore+LArFebRodMap'
),
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
)]
(
'LArMCSym'
,
'ConditionStore+LArMCSym'
),
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
)]
def
CaloOffsetCorrectionCfg
(
flags
):
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/python/TrigT2CaloCommonConfig.py
View file @
51892f33
...
...
@@ -27,6 +27,12 @@ class TrigCaloDataAccessSvc(_TrigCaloDataAccessSvc):
self
.
RegSelToolTILE
=
makeRegSelTool_TILE
()
condseq
=
AthSequencer
(
'AthCondSeq'
)
condseq
.
RegSelCondAlg_TTEM
.
RegSelLUT
=
"ConditionStore+RegSelLUTCondData_TTEM"
from
IOVDbSvc.CondDB
import
conddb
from
LArBadChannelTool.LArBadChannelAccess
import
LArBadChannelAccess
if
conddb
.
isMC
:
LArBadChannelAccess
(
dbString
=
"<db>COOLOFL_LAR/OFLP200</db>/LAR/BadChannels/BadChannels"
)
else
:
LArBadChannelAccess
(
dbString
=
"<db>COOLONL_LAR/CONDBR2</db>/LAR/BadChannels/BadChannels"
)
if
(
globalflags
.
DatabaseInstance
==
"COMP200"
and
ConfigFlags
.
Trigger
.
calo
.
doOffsetCorrection
)
:
log
.
warning
(
"Not possible to run BCID offset correction with COMP200"
)
...
...
@@ -34,7 +40,6 @@ class TrigCaloDataAccessSvc(_TrigCaloDataAccessSvc):
if
ConfigFlags
.
Trigger
.
calo
.
doOffsetCorrection
:
if
globalflags
.
DataSource
()
==
'data'
and
athenaCommonFlags
.
isOnline
():
log
.
info
(
'Enable HLT calo offset correction for data'
)
from
IOVDbSvc.CondDB
import
conddb
conddb
.
addFolder
(
"LAR_ONL"
,
"/LAR/ElecCalibFlat/OFC"
)
from
LArRecUtils.LArRecUtilsConf
import
LArFlatConditionSvc
svcMgr
+=
LArFlatConditionSvc
()
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/share/Calo.py
View file @
51892f33
...
...
@@ -48,6 +48,8 @@ if ConfigFlags.Trigger.doCalo:
if
(
True
):
from
LArRecUtils.LArMCSymCondAlg
import
LArMCSymCondAlgDefault
LArMCSymCondAlgDefault
()
from
LArBadChannelTool.LArBadChannelAccess
import
LArBadChannelAccess
LArBadChannelAccess
()
from
TrigMinBias.TrigMinBiasConf
import
MbtsFex
alg
=
MbtsFex
()
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/src/LArCellCont.cxx
View file @
51892f33
...
...
@@ -12,13 +12,14 @@
#include "CaloUtils/CaloCellCorrection.h"
#include "GaudiKernel/EventContext.h"
#include "CaloEvent/CaloBCIDAverage.h"
#include "LArRecConditions/LArBadChanBitPacking.h"
#include <iostream>
LArCellCont
::
LArCellCont
()
:
m_event
(
0
),
m_lumi_block
(
0
),
m_bcid
(
5000
),
m_bcidEvt
(
5000
),
m_BCIDcache
(
false
)
{}
StatusCode
LArCellCont
::
initialize
(
const
LArMCSym
&
mcsym
,
const
LArFebRodMapping
&
febrod
)
{
LArCellCont
::
initialize
(
const
LArMCSym
&
mcsym
,
const
LArFebRodMapping
&
febrod
,
const
LArBadChannelCont
&
badchannel
)
{
#ifdef TRIGLARCELLDEBUG
std
::
cout
<<
"LArCellCont
\t\t
DEBUG
\t
in initialize"
<<
std
::
endl
;
...
...
@@ -144,11 +145,22 @@ m_hashSym.resize(onlineId->febHashMax());
for
(
int
ch
=
0
;
ch
<
128
;
ch
++
){
LArRoI_Map
::
TT_ID
ttId
;
LArCell
*
larcell
=
makeCell
.
getLArCell
(
febidcomp
,
ch
,
0
,
0
,
0
,
ttId
);
const
LArBadChanBitPacking
packing
;
if
(
larcell
)
{
// if it is a good cell
// Fixes default value
larcell
->
setGain
(
CaloGain
::
LARHIGHGAIN
);
(
*
this
)[
idx
]
->
push_back
(
larcell
);
collMap
[
ttId
].
push_back
(
larcell
);
LArBadChannel
bc
=
badchannel
.
offlineStatus
(
larcell
->
ID
());
bool
good
(
true
);
if
(
!
bc
.
good
()
){
// cell has some specific problems
if
(
bc
.
unstable
()
)
good
=
false
;
if
(
bc
.
highNoiseHG
()
)
good
=
false
;
if
(
bc
.
highNoiseMG
()
)
good
=
false
;
if
(
bc
.
highNoiseLG
()
)
good
=
false
;
if
(
bc
.
problematicForUnknownReason
()
)
good
=
false
;
}
if
(
good
)
collMap
[
ttId
].
push_back
(
larcell
);
// cell masked if not know to be good
HWIdentifier
hwsym
=
mcsym
.
ZPhiSymOnl
(
onlineId
->
channel_Id
(
febid
,
ch
));
if
(
m_indexset
.
find
(
hwsym
)
!=
m_indexset
.
end
()
){
int
index
=
(
m_indexset
.
find
(
hwsym
))
->
second
;
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/src/TrigCaloDataAccessSvc.cxx
View file @
51892f33
...
...
@@ -30,6 +30,7 @@ StatusCode TrigCaloDataAccessSvc::initialize() {
CHECK
(
m_febRodMappingKey
.
initialize
()
);
CHECK
(
m_regionSelector_TTEM
.
retrieve
()
);
CHECK
(
m_mcsymKey
.
initialize
()
);
CHECK
(
m_bcContKey
.
initialize
()
);
CHECK
(
m_regionSelector_TTHEC
.
retrieve
()
);
CHECK
(
m_regionSelector_FCALEM
.
retrieve
()
);
CHECK
(
m_regionSelector_FCALHAD
.
retrieve
()
);
...
...
@@ -335,6 +336,7 @@ unsigned int TrigCaloDataAccessSvc::lateInit(const EventContext& context) { // n
SG
::
ReadCondHandle
<
LArMCSym
>
mcsym
(
m_mcsymKey
,
context
);
SG
::
ReadCondHandle
<
LArFebRodMapping
>
febrod
(
m_febRodMappingKey
,
context
);
SG
::
ReadCondHandle
<
LArBadChannelCont
>
larBadChan
{
m_bcContKey
,
context
};
unsigned
int
nFebs
=
70
;
unsigned
int
high_granu
=
(
unsigned
int
)
ceilf
(
m_vrodid32fullDet
.
size
()
/
((
float
)
nFebs
)
);
...
...
@@ -360,7 +362,7 @@ unsigned int TrigCaloDataAccessSvc::lateInit(const EventContext& context) { // n
ec
.
setSlot
(
slot
);
HLTCaloEventCache
*
cache
=
m_hLTCaloSlot
.
get
(
ec
);
cache
->
larContainer
=
new
LArCellCont
();
if
(
cache
->
larContainer
->
initialize
(
**
mcsym
,
**
febrod
).
isFailure
()
)
if
(
cache
->
larContainer
->
initialize
(
**
mcsym
,
**
febrod
,
**
larBadChan
).
isFailure
()
)
return
0x1
;
// dummy code
std
::
vector
<
CaloCell
*>
local_cell_copy
;
local_cell_copy
.
reserve
(
200000
);
...
...
Trigger/TrigAlgorithms/TrigT2CaloCommon/src/TrigCaloDataAccessSvc.h
View file @
51892f33
...
...
@@ -27,6 +27,7 @@
#include "LArRawConditions/LArMCSym.h"
#include "LArCabling/LArOnOffIdMapping.h"
#include "LArRecConditions/LArFebRodMapping.h"
#include "LArRecConditions/LArBadChannelCont.h"
class
TrigCaloDataAccessSvc
:
public
extends
<
AthService
,
ITrigCaloDataAccessSvc
>
{
public:
...
...
@@ -82,6 +83,8 @@ class TrigCaloDataAccessSvc : public extends<AthService, ITrigCaloDataAccessSvc>
{
this
,
"CablingKey"
,
"LArOnOffIdMap"
,
"SG Key for LArOnOffIdMapping"
}
;
SG
::
ReadCondHandleKey
<
LArFebRodMapping
>
m_febRodMappingKey
{
this
,
"RodFebKey"
,
"LArFebRodMap"
,
"SG Key for LArFebRodMapping"
}
;
SG
::
ReadCondHandleKey
<
LArBadChannelCont
>
m_bcContKey
{
this
,
"LArBadChannelKey"
,
"LArBadChannel"
,
"Key of the LArBadChannelCont CDO"
};
void
reset_LArCol
(
LArCellCollection
*
coll
){
for
(
LArCellCollection
::
iterator
ii
=
coll
->
begin
();
ii
!=
coll
->
end
();
++
ii
)
...
...
Trigger/TrigAlgorithms/TrigT2CaloEgamma/python/TrigT2CaloEgammaConfig.py
View file @
51892f33
...
...
@@ -124,7 +124,7 @@ class T2CaloEgamma_All (CompFactory.T2CaloEgammaReFastAlgo):
self
.
PhiWidth
=
0.1
self
.
ExtraInputs
=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
]
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
,
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
)
]
#=======================================================================
...
...
@@ -144,7 +144,7 @@ class T2CaloEgamma_AllEm (CompFactory.T2CaloEgammaReFastAlgo):
self
.
PhiWidth
=
0.1
self
.
ExtraInputs
=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
]
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
,
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
)
]
#=======================================================================
...
...
@@ -168,7 +168,7 @@ class T2CaloEgamma_ReFastAlgo (CompFactory.T2CaloEgammaReFastAlgo):
self
.
IReAlgToolList
=
[
samp2
,
samp1
,
sampe
,
samph
]
self
.
ExtraInputs
=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
]
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
,
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
)
]
if
doRinger
:
from
TrigT2CaloEgamma.TrigT2CaloEgammaConfig
import
RingerReFexConfig
...
...
@@ -223,7 +223,7 @@ class T2CaloEgamma_ReFastFWDAlgo (CompFactory.T2CaloEgammaForwardReFastAlgo):
self
.
IReAlgToolList
=
[]
self
.
ExtraInputs
=
[(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TTHEC'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_TILE'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALEM'
),
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
]
(
'IRegSelLUTCondData'
,
'ConditionStore+RegSelLUTCondData_FCALHAD'
)
,
(
'LArBadChannelCont'
,
'ConditionStore+LArBadChannel'
)
]
self
.
EtaWidth
=
0.2
self
.
PhiWidth
=
0.2
...
...
Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
View file @
51892f33
...
...
@@ -82,8 +82,8 @@ HLT_2e5_lhvloose_bBeeM6000_L12EM3:
2: 4
3: 4
stepFeatures:
0: 5
0
1: 10
4
0: 5
1
1: 10
9
2: 14
3: 25
4: 3
...
...
@@ -2339,7 +2339,7 @@ HLT_e26_idperf_loose_lrtloose_L1EM22VHI:
0: 6
1: 6
2: 5
3: 2
5
3: 2
4
4: 5
HLT_e26_idperf_tight_L1EM22VHI:
eventCount: 5
...
...
@@ -2919,9 +2919,9 @@ HLT_e26_lhtight_ivarloose_e5_lhvloose_nopix_lrtloose_idperf_probe_L1EM22VHI:
4: 5
5: 19
6: 19
7: 1
1
8:
59
9: 1
1
7: 1
2
8:
63
9: 1
2
HLT_e26_lhtight_ivarloose_e9_etcut_probe_L1EM22VHI:
eventCount: 5
stepCounts:
...
...
@@ -3558,8 +3558,8 @@ HLT_e5_dnnloose_L1EM3:
3: 13
4: 7
stepFeatures:
0: 4
8
1: 9
2
0: 4
9
1: 9
7
2: 25
3: 54
4: 7
...
...
@@ -3599,10 +3599,10 @@ HLT_e5_etcut_L1eEM3:
2: 19
3: 19
stepFeatures:
0: 25
2
1: 66
4
2: 30
8
3: 41
9
0: 25
1
1: 66
3
2: 30
7
3: 41
6
HLT_e5_idperf_gsf_tight_L1EM3:
eventCount: 13
stepCounts:
...
...
@@ -3626,8 +3626,8 @@ HLT_e5_idperf_loose_L1EM3:
3: 13
4: 13
stepFeatures:
0: 4
8
1: 4
3
0: 4
9
1: 4
4
2: 25
3: 54
4: 23
...
...
@@ -3640,11 +3640,11 @@ HLT_e5_idperf_loose_lrtloose_L1EM3:
3: 15
4: 15
stepFeatures:
0: 4
8
1: 4
8
2: 2
5
3: 15
0
4: 2
4
0: 4
9
1: 4
9
2: 2
6
3: 15
4
4: 2
5
HLT_e5_idperf_medium_L1EM3:
eventCount: 13
stepCounts:
...
...
@@ -3758,8 +3758,8 @@ HLT_e5_lhvloose_j70_0eta320_j50_0eta490_j0_DJMASS1000j50_xe50_tcpufit_L1MJJ-500-
3: 2
4: 1
stepFeatures:
0:
9
1: 2
2
0:
10
1: 2
7
2: 5
3: 10
4: 2
...
...
@@ -3975,7 +3975,7 @@ HLT_e9_lhvloose_e5_lhvloose_bBeeM6000_L1BPH-0M9-EM7-EM5:
stepCounts:
0: 3
stepFeatures:
0: 2
1
0: 2
2
1: 52
2: 3
HLT_e9_lhvloose_mu20_mu8noL1_L1MU14FCH:
...
...
@@ -10531,7 +10531,7 @@ HLT_tau25_looseRNN_tracktwoLLP_L1TAU12IM:
1: 30
2: 30
3: 30
4: 1
3
4: 1
4
HLT_tau25_looseRNN_tracktwoMVABDT_L1TAU12IM:
eventCount: 8
stepCounts:
...
...
Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref
View file @
51892f33
...
...
@@ -34,7 +34,7 @@ HLT_2e5_lhvloose_bBeeM6000_L12EM3:
2: 2
3: 2
stepFeatures:
0: 4
7
0: 4
8
1: 49
2: 4
3: 5
...
...
@@ -950,7 +950,7 @@ HLT_e5_dnnloose_L1EM3:
2: 10
3: 10
stepFeatures:
0: 4
7
0: 4
6
1: 62
2: 13
3: 16
...
...
@@ -1013,8 +1013,8 @@ HLT_e5_idperf_loose_L1EM3:
3: 13
4: 13
stepFeatures:
0: 4
7
1: 3
5
0: 4
6
1: 3
4
2: 17
3: 22
4: 16
...
...
@@ -1027,8 +1027,8 @@ HLT_e5_idperf_loose_lrtloose_L1EM3:
3: 15
4: 15
stepFeatures:
0: 4
7
1: 4
6
0: 4
6
1: 4
5
2: 21
3: 86
4: 20
...
...
@@ -4224,136 +4224,136 @@ HLT_tau20_mediumRNN_tracktwoMVABDT_probe_xe110_pfsum_vssk_L1XE50:
HLT_tau20_mediumRNN_tracktwoMVA_probe_xe110_pfsum_vssk_L1XE50:
eventCount: 0
HLT_tau25_idperf_tracktwoMVABDT_L1TAU12IM:
eventCount:
10
eventCount:
9
stepCounts:
0: 11
1: 9
2: 9
3: 9
4: 9
stepFeatures:
0: 13
1: 10
2: 10
3: 10
4: 10
stepFeatures:
0: 13
1: 11
2: 11
3: 11
4: 11
HLT_tau25_idperf_tracktwoMVA_L1TAU12IM:
eventCount:
10
eventCount:
9
stepCounts:
0: 11
1: 9
2: 9
3: 9
4: 9
stepFeatures:
0: 13
1: 10
2: 10
3: 10
4: 10
stepFeatures:
0: 13
1: 11
2: 11
3: 11
4: 11
HLT_tau25_idperf_tracktwo_L1TAU12IM:
eventCount:
9
eventCount:
8
stepCounts:
0: 10
1: 8
2: 8
3: 8
4: 8
5: 8
stepFeatures:
0: 12
1: 9
2: 9
3: 9
4: 9
5: 9
stepFeatures:
0: 12
1: 10
2: 10
3: 10
4: 10
5: 10
HLT_tau25_looseRNN_tracktwoLLP_L1TAU12IM:
eventCount:
7
eventCount:
6
stepCounts:
0: 11
1: 9
2: 9
3: 9
4: 6
stepFeatures:
0: 13
1: 10
2: 10
3: 10
4: 7
stepFeatures:
0: 13
1: 11
2: 11
3: 11
4: 7
4: 6
HLT_tau25_looseRNN_tracktwoMVABDT_L1TAU12IM:
eventCount: 6
stepCounts:
0: 11
1:
10
2:
10
3:
10
1:
9
2:
9
3:
9
4: 6
stepFeatures:
0: 13
1: 1
1
2: 1
1
3: 1
1
1: 1
0
2: 1
0
3: 1
0
4: 6
HLT_tau25_looseRNN_tracktwoMVA_L1TAU12IM:
eventCount: 6
stepCounts:
0: 11
1:
10
2:
10
3:
10
1:
9
2:
9
3:
9
4: 6
stepFeatures:
0: 13
1: 1
1
2: 1
1
3: 1
1
1: 1
0
2: 1
0
3: 1
0
4: 6
HLT_tau25_medium1_tracktwo_L1TAU12IM:
eventCount: 4
stepCounts:
0: 10
1: 8
2: 8
3: 7
4: 7
5: 4
stepFeatures:
0: 12
1: 9
2: 9
3: 8
4: 8
5: 4
stepFeatures:
0: 12
1: 10
2: 10
3: 9
4: 9
5: 4
HLT_tau25_medium1_tracktwo_probe_xe110_pfsum_vssk_L1XE50:
eventCount: 0
HLT_tau25_mediumRNN_tracktwoLLP_L1TAU12IM:
eventCount: 6
stepCounts: