VME: feedback from Harvey
- spacing of clk to data on buses spread out a bit? e.g F_WRCLK_SPI_SCK, F_WR_DAC_SCLK. Long runs next to data lines could cause clk to couple to data on clk edges
- add pulldown to WR_CLK.RSTN
- VME_p1_p2 page, P1 pins A31, B31, C31 have both no connect and power symbols. Which one should it be? (Assuming is the power nets as these are on the layout)
- Extra/unused vias on JTAG connector J7. e.g P14
- WR_HELPER_P/N diff pair to FPGA pins polarity inverted. Obviously not major (is a diff pair...) but worth noting when connecting io buff in FPGA
- also on this net could R65 move closer to reduce stub length
I also have another question (well I have plenty questions about the board and what its doing, but that's not relevant to the review). There are some instances of diff pairs changing layers multiple times in a run e.g. PCIE.REFCLK_P/N. In my last place, when this happened we would add GND stitching vias either side of the diff pair vias, to provide a return path between the different reference planes at the point at which the pair is crossing them. Is this something worth adding, or do you never do this kind of thing?