Skip to content

HDL: Initialize signals with preset value if it exists

This MR fixes GitHub issue 52 (sorry for the cross-platform gymnastics).

  • In HDL tree synthesis, preset is not added to signal attributes.
  • In VHDL and Verilog code generation, the preset is written in binary format if it exists.
  • I updated existing generated golden files in testfiles/ and testfiles/tb.

Merge request reports

Loading