Automatically generating code from a description is certainly not a new idea and there are many existing tools with similar features. Here is a non-exhaustive list.
* wbgen (from CERN BE-CO-HT). One of the predecessor of Cheby. It can directly generate cross clock-domain logic, FIFOs and an interrupt controller. But it was limited to WB bus and cannot handle hierarchy of designs.
* Cheburashka + Gena (from CERN BE-RF and CERN BE-BI). Also a predecessor of Cheby. The input file is XML, which is seen as difficult to write by hand and to read; this was mitigated by a graphical editor. It supports many features commonly used at CERN (but not outside), including its non-standard bus.
*[bitvis.no Register Wizard](https://www.bitvis.no/media/register_wizard). A commercial (and non open source) tool with a JSON input.
*[IP-xact](https://www.accellera.org/downloads/standards/ip-xact). A standard using XML files to describe interface, including the registers. Not widely used or used with many private extensions.
*[SystemRDL](https://www.accellera.org/downloads/standards/systemrdl). Register Description Language. A standard that is apparently not used.
*[airhdl](https://airhdl.com/index.jsp). A nice web site that can generate hdl and doc, but closed-source.
