diff --git a/hdl/rtl/mqueue/mt_rmq_rx.vhd b/hdl/rtl/mqueue/mt_rmq_rx.vhd
index 734be3b7f7ca9400ffc0dc5606f838bdabc85ee1..b6591008876e51e47c08bfabe3c5aa94eadeabff 100644
--- a/hdl/rtl/mqueue/mt_rmq_rx.vhd
+++ b/hdl/rtl/mqueue/mt_rmq_rx.vhd
@@ -138,33 +138,30 @@ begin
             elsif snk_i.last = '1' then
               --  End of payload.
               n_state.state <= WRITE_SIZE;
+            end if; -- snk_i.error
+
+            if (state.is_hdr_d = '1' and snk_i.hdr = '0') then
+              -- end of header
+              outb_o.adr           <= c_mqueue_addr_payload;
+              outb_o.wmask         <= "1100";
+              n_state.addr         <= unsigned(c_mqueue_addr_payload);
+              n_state.is_even      <= '0';
+              n_state.payload_size <= to_unsigned(2, 13);
+              n_state.is_hdr_d     <= '0';
             else
+              n_state.is_hdr_d <= snk_i.hdr;
+              n_state.is_even  <= not state.is_even;
 
-              if (state.is_hdr_d = '1' and snk_i.hdr = '0') then
-                -- end of header
-                outb_o.adr           <= c_mqueue_addr_payload;
-                outb_o.wmask <= "1100";
-                n_state.addr         <= unsigned(c_mqueue_addr_payload);
-                n_state.state        <= CLAIM;
-                n_state.is_even      <= '0';
-                n_state.payload_size <= to_unsigned(2, 13);
-                n_state.is_hdr_d     <= '0';
+              if(snk_i.hdr = '0') then
+                n_state.payload_size <= state.payload_size + 2;
+              end if;
+
+              if state.is_even = '1' then
+                n_state.addr <= state.addr;
               else
-                n_state.state <= CLAIM;
-                n_state.is_hdr_d <= snk_i.hdr;
-                n_state.is_even <= not state.is_even;
-
-                if(snk_i.hdr = '0') then
-                  n_state.payload_size <= state.payload_size + 2;
-                end if;
-
-                if state.is_even = '1' then
-                  n_state.addr <= state.addr;
-                else
-                  n_state.addr <= state.addr + 4;
-                end if;  -- even
-              end if;  -- hdr
-            end if;
+                n_state.addr <= state.addr + 4;
+              end if;  -- even
+            end if;  -- hdr
 
           else
             outb_o <= (sel   => '0',
@@ -172,8 +169,7 @@ begin
                        dat   => (others => 'X'),
                        we    => '0',
                        wmask => "XXXX");
-            n_state <= state;
-          end if;
+          end if; -- snk_i.valid
 
         when WRITE_SIZE =>
           --  Make the slot ready.