Project 'be-cem-edl/diot/FMC-nanoFIP/fmc-nanofip-pcb' was moved to 'be-cem-edl/diot/worldfip/fmc-nanofip/fmc-nanofip-pcb'. Please update any links and bookmarks that may still have the old path.
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Milestone
sch-v3.1
All issues for this milestone are closed. You may close this milestone now.
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
14
- Replace TPS7A4901DGNT with TPS7A4901DRB
- Configuration pull-ups powered by P3V3, the I/O banks are on Vadj
- FIP signal bank powered by VBUS
- settings.sch: update hw revision
- Unused FMC pins
- VBUS connected to JTAG (J1)?
- FPGA I/O bank decoupling capacitors are still on P3V3
- ESD protection
- Vadj is declared as "not used"
- Level translator using Vadj
- Change SW2 connector variant
- Separate JTAG chains or lower TRST pull-down resistor value
- FieldTR zener diodes are difficult to source
- Change the FIP connector (DB9)
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