diff --git a/DIOT-bPOL12V/.gitignore b/DIOT-bPOL12V/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..6a055077a4797eab0e49aa6586080dcdc78837eb
--- /dev/null
+++ b/DIOT-bPOL12V/.gitignore
@@ -0,0 +1,5 @@
+**/__Previews
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+Project Logs*/
+IbisReport.txt
+IbisErrors.txt
diff --git a/DIOT-bPOL12V/DIOT_bPOL12V.PrjPcb b/DIOT-bPOL12V/DIOT_bPOL12V.PrjPcb
new file mode 100644
index 0000000000000000000000000000000000000000..2cd595739e67f1677dd710de6f74cad3df5b7710
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+
+[OutputGroup4]
+Name=Assembly Outputs
+Description=
+TargetPrinter=Microsoft Print to PDF
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Assembly
+OutputName1=Assembly Drawings
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType2=Pick Place
+OutputName2=Generates pick and place files
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+OutputType3=Test Points For Assembly
+OutputName3=Test Point Report
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+
+[OutputGroup5]
+Name=Fabrication Outputs
+Description=
+TargetPrinter=Microsoft Print to PDF
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=CompositeDrill
+OutputName1=Composite Drill Drawing
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType2=Drill
+OutputName2=Drill Drawing/Guides
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=4.62|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+Configuration2_Name1=ForceUpdateSettings
+Configuration2_Item1=False
+Configuration2_Name2=OutputConfigurationParameter1
+Configuration2_Item2=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name3=OutputConfigurationParameter2
+Configuration2_Item3=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Drill Drawing For (Top Layer - Bottom Layer)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name4=OutputConfigurationParameter3
+Configuration2_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=DrillDrawing|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name5=OutputConfigurationParameter4
+Configuration2_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical8|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name6=OutputConfigurationParameter5
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+Configuration2_Name7=OutputConfigurationParameter6
+Configuration2_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name8=OutputConfigurationParameter7
+Configuration2_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name9=OutputConfigurationParameter8
+Configuration2_Item9=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=1|Mirror=False|Name=Drill Drawing For (L2GND - L11GND)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name10=OutputConfigurationParameter9
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+Configuration2_Name11=OutputConfigurationParameter10
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+Configuration2_Name12=OutputConfigurationParameter11
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+Configuration2_Name13=OutputConfigurationParameter12
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+Configuration2_Name14=OutputConfigurationParameter13
+Configuration2_Item14=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name15=OutputConfigurationParameter14
+Configuration2_Item15=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=2|Mirror=False|Name=Drill Drawing For (Top Layer - L2GND)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\gdaniluk\cernbox\windows_shared\DIOT-bpol12\diot-sb-igl-master\diot-sb-igl-master\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration2_Name16=OutputConfigurationParameter15
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+Configuration2_Name17=OutputConfigurationParameter16
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+Configuration2_Name18=OutputConfigurationParameter17
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+Configuration2_Name19=OutputConfigurationParameter18
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+Configuration2_Name20=OutputConfigurationParameter19
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+Configuration2_Name25=OutputConfigurationParameter24
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+Configuration2_Name26=OutputConfigurationParameter25
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+Configuration2_Name29=OutputConfigurationParameter28
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+Configuration2_Name30=OutputConfigurationParameter29
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+Configuration2_Name37=OutputConfigurationParameter36
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+Configuration2_Name38=OutputConfigurationParameter37
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+Configuration2_Name39=OutputConfigurationParameter38
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+Configuration2_Name40=OutputConfigurationParameter39
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+Configuration2_Name41=OutputConfigurationParameter40
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+Configuration2_Name43=OutputConfigurationParameter42
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+Configuration2_Name44=OutputConfigurationParameter43
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+Configuration2_Name45=OutputConfigurationParameter44
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+
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+Configuration1_Name6=VisibleOrder
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+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType8=Text Print
+OutputName8=Text Print
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType9=Text Print
+OutputName9=Text Print
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType10=Text Print
+OutputName10=Text Print
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType11=Text Print
+OutputName11=Text Print
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType12=Text Print
+OutputName12=Text Print
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType13=Text Print
+OutputName13=Text Print
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
+PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType14=Text Print
+OutputName14=Text Print
+OutputDocumentPath14=
+OutputVariantName14=
+OutputDefault14=0
+PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType15=Text Print
+OutputName15=Text Print
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType16=Text Print
+OutputName16=Text Print
+OutputDocumentPath16=
+OutputVariantName16=
+OutputDefault16=0
+PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType17=Text Print
+OutputName17=Text Print
+OutputDocumentPath17=
+OutputVariantName17=
+OutputDefault17=0
+PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+
+[OutputGroup8]
+Name=Validation Outputs
+Description=
+TargetPrinter=Microsoft Print to PDF
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=BOM_Violations
+OutputName1=BOM Checks Report
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=Component states check
+OutputName2=Server's components states check
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=Configuration compliance
+OutputName3=Environment configuration compliance check
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+OutputType4=Design Rules Check
+OutputName4=Design Rules Check
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType5=Differences Report
+OutputName5=Differences Report
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType6=Electrical Rules Check
+OutputName6=Electrical Rules Check
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+OutputType7=Footprint Comparison Report
+OutputName7=Footprint Comparison Report
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+
+[OutputGroup9]
+Name=Export Outputs
+Description=
+TargetPrinter=Microsoft Print to PDF
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=AutoCAD dwg/dxf PCB
+OutputName1=AutoCAD dwg/dxf File PCB
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=AutoCAD dwg/dxf Schematic
+OutputName2=AutoCAD dwg/dxf File Schematic
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=ExportIDF
+OutputName3=Export IDF
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+OutputType4=ExportPARASOLID
+OutputName4=Export PARASOLID
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+OutputType5=ExportSTEP
+OutputName5=Export STEP
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=ExportVRML
+OutputName6=Export VRML
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+OutputType7=MBAExportPARASOLID
+OutputName7=Export PARASOLID
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+OutputType8=MBAExportSTEP
+OutputName8=Export STEP
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+OutputType9=Save As/Export PCB
+OutputName9=Save As/Export PCB
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+OutputType10=Save As/Export Schematic
+OutputName10=Save As/Export Schematic
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+OutputType11=Specctra Design PCB
+OutputName11=Specctra Design PCB
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=AnsysEDB
+OutputName12=Ansys EDB
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+
+[OutputGroup10]
+Name=PostProcess Outputs
+Description=
+TargetPrinter=Microsoft Print to PDF
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Copy Files
+OutputName1=Copy Files
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+
+[Modification Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+Type50=1
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=1
+Type57=1
+Type58=1
+Type59=1
+Type60=1
+Type61=1
+Type62=1
+Type63=1
+Type64=1
+Type65=1
+Type66=1
+Type67=1
+Type68=1
+Type69=1
+Type70=1
+Type71=1
+Type72=1
+Type73=1
+Type74=1
+Type75=1
+Type76=1
+Type77=1
+Type78=1
+Type79=1
+Type80=1
+Type81=1
+Type82=1
+Type83=1
+Type84=1
+Type85=1
+Type86=1
+Type87=1
+Type88=1
+Type89=1
+Type90=1
+Type91=1
+Type92=1
+Type93=1
+Type94=1
+Type95=1
+Type96=1
+Type97=1
+Type98=1
+Type99=1
+Type100=1
+Type101=1
+Type102=1
+Type103=1
+Type104=1
+Type105=1
+Type106=1
+Type107=1
+Type108=1
+Type109=1
+Type110=1
+Type111=1
+Type112=1
+Type113=1
+Type114=1
+Type115=1
+Type116=1
+Type117=1
+Type118=1
+Type119=1
+
+[Difference Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+Type50=1
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=1
+Type57=1
+Type58=1
+Type59=1
+Type60=1
+Type61=1
+Type62=1
+Type63=1
+Type64=1
+Type65=1
+Type66=1
+Type67=1
+Type68=1
+
+[Electrical Rules Check]
+Type1=1
+Type2=1
+Type3=2
+Type4=1
+Type5=2
+Type6=2
+Type7=0
+Type8=1
+Type9=1
+Type10=1
+Type11=2
+Type12=2
+Type13=2
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=0
+Type21=0
+Type22=0
+Type23=0
+Type24=1
+Type25=2
+Type26=0
+Type27=2
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=2
+Type33=0
+Type34=2
+Type35=1
+Type36=2
+Type37=1
+Type38=2
+Type39=2
+Type40=2
+Type41=0
+Type42=2
+Type43=1
+Type44=0
+Type45=0
+Type46=0
+Type47=0
+Type48=0
+Type49=0
+Type50=2
+Type51=0
+Type52=0
+Type53=1
+Type54=1
+Type55=1
+Type56=2
+Type57=1
+Type58=1
+Type59=2
+Type60=0
+Type61=0
+Type62=0
+Type63=0
+Type64=0
+Type65=2
+Type66=3
+Type67=2
+Type68=2
+Type69=0
+Type70=2
+Type71=2
+Type72=2
+Type73=2
+Type74=1
+Type75=2
+Type76=1
+Type77=1
+Type78=1
+Type79=1
+Type80=2
+Type81=3
+Type82=3
+Type83=3
+Type84=3
+Type85=3
+Type86=2
+Type87=2
+Type88=2
+Type89=1
+Type90=1
+Type91=3
+Type92=3
+Type93=2
+Type94=2
+Type95=2
+Type96=2
+Type97=2
+Type98=0
+Type99=1
+Type100=2
+Type101=0
+Type102=2
+Type103=2
+Type104=1
+Type105=2
+Type106=2
+Type107=2
+Type108=2
+Type109=1
+Type110=1
+Type111=1
+Type112=1
+Type113=1
+Type114=2
+Type115=2
+Type116=2
+Type117=3
+Type118=3
+Type119=3
+MultiChannelAlternate=2
+AlternateItemFail=3
+Type122=2
+Type123=1
+Type124=1
+Type125=1
+
+[ERC Connection Matrix]
+L1=NNNNNNNNNNNWNNNWW
+L2=NNWNNNNWWWNWNWNWN
+L3=NWEENEEEENEWNEEWN
+L4=NNENNNWEENNWNENWN
+L5=NNNNNNNNNNNNNNNNN
+L6=NNENNNNEENNWNENWN
+L7=NNEWNNWEENNWNENWN
+L8=NWEENEENEEENNEENN
+L9=NWEENEEEENEWNEEWW
+L10=NWNNNNNENNEWNNEWN
+L11=NNENNNNEEENWNENWN
+L12=WWWWNWWNWWWNWWWNN
+L13=NNNNNNNNNNNWNNNWW
+L14=NWEENEEEENEWNEEWW
+L15=NNENNNNEEENWNENWW
+L16=WWWWNWWNWWWNWWWNW
+L17=WNNNNNNNWNNNWWWWN
+
+[Annotate]
+SortOrder=3
+SortLocation=0
+ReplaceSubparts=0
+MatchParameter1=Comment
+MatchStrictly1=1
+MatchParameter2=Library Reference
+MatchStrictly2=1
+PhysicalNamingFormat=$Component_$RoomName
+GlobalIndexSortOrder=3
+GlobalIndexSortLocation=0
+
+[PrjClassGen]
+CompClassManualEnabled=0
+CompClassManualRoomEnabled=0
+NetClassAutoBusEnabled=1
+NetClassAutoCompEnabled=0
+NetClassAutoNamedHarnessEnabled=0
+NetClassManualEnabled=1
+NetClassSeparateForBusSections=0
+
+[LibraryUpdateOptions]
+SelectedOnly=0
+UpdateVariants=1
+UpdateToLatestRevision=1
+PartTypes=0
+FullReplace=1
+UpdateDesignatorLock=1
+UpdatePartIDLock=1
+PreserveParameterLocations=1
+PreserveParameterVisibility=1
+DoGraphics=1
+DoParameters=1
+DoModels=1
+AddParameters=0
+RemoveParameters=0
+AddModels=1
+RemoveModels=1
+UpdateCurrentModels=1
+
+[DatabaseUpdateOptions]
+SelectedOnly=0
+UpdateVariants=1
+UpdateToLatestRevision=1
+PartTypes=0
+
+[Comparison Options]
+ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0
+ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+
+[SmartPDF]
+PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
+Configuration_Name1=OutputConfigurationParameter1
+Configuration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name2=OutputConfigurationParameter2
+Configuration_Item2=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name3=OutputConfigurationParameter3
+Configuration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name4=OutputConfigurationParameter4
+Configuration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name5=OutputConfigurationParameter5
+Configuration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name6=OutputConfigurationParameter6
+Configuration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name7=OutputConfigurationParameter7
+Configuration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name8=OutputConfigurationParameter8
+Configuration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name9=OutputConfigurationParameter9
+Configuration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical8|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name10=OutputConfigurationParameter10
+Configuration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name11=OutputConfigurationParameter11
+Configuration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+Configuration_Name12=OutputConfigurationParameter12
+Configuration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+
diff --git a/DIOT-bPOL12V/DIOT_bPOL12V.PrjPcbStructure b/DIOT-bPOL12V/DIOT_bPOL12V.PrjPcbStructure
new file mode 100644
index 0000000000000000000000000000000000000000..29d723407809712572014ae6f692361b5eb4efcf
--- /dev/null
+++ b/DIOT-bPOL12V/DIOT_bPOL12V.PrjPcbStructure
@@ -0,0 +1,3 @@
+Record=TopLevelDocument|FileName=DIOT_bPOL12V_1V2.SchDoc|SheetNumber=1
+Record=NoMainPathDocument|SourceDocument=DIOT_bPOL12V_1V2.SchDoc|FileName=DIOT_bPOL12V_2V5.SchDoc|SheetNumber=3
+Record=NoMainPathDocument|SourceDocument=DIOT_bPOL12V_1V2.SchDoc|FileName=DIOT_bPOL12V_3V3.SchDoc|SheetNumber=2
diff --git a/DIOT-bPOL12V/DIOT_bPOL12V.pdf b/DIOT-bPOL12V/DIOT_bPOL12V.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..9a9f00760b2333d090ffb48da24a3eed0db77f2e
Binary files /dev/null and b/DIOT-bPOL12V/DIOT_bPOL12V.pdf differ
diff --git a/DIOT-bPOL12V/Fabrication/DIOT-bPOL12V.Cam b/DIOT-bPOL12V/Fabrication/DIOT-bPOL12V.Cam
new file mode 100644
index 0000000000000000000000000000000000000000..3212d46bf697bf2f8d27caeaf7a8cfd11d5f376a
Binary files /dev/null and b/DIOT-bPOL12V/Fabrication/DIOT-bPOL12V.Cam differ
diff --git a/DIOT-bPOL12V/Layout/DIOT_bPOL12V.PcbDoc b/DIOT-bPOL12V/Layout/DIOT_bPOL12V.PcbDoc
new file mode 100644
index 0000000000000000000000000000000000000000..f6ad2261021d273797d225685f47b6123249836b
Binary files /dev/null and b/DIOT-bPOL12V/Layout/DIOT_bPOL12V.PcbDoc differ
diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V-macro.APR_LIB b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V-macro.APR_LIB
new file mode 100644
index 0000000000000000000000000000000000000000..9fca5fe2bd1a676e525b9ef90d610f2c8fa7e191
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V-macro.APR_LIB	
@@ -0,0 +1,27 @@
+G04:AMPARAMS|DCode=11|XSize=27.559mil|YSize=9.842mil|CornerRadius=1.476mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD11*
+21,1,0.027559,0.006890,0,0,180.0*
+21,1,0.024606,0.009842,0,0,180.0*
+1,1,0.002953,-0.012303,0.003445*
+1,1,0.002953,0.012303,0.003445*
+1,1,0.002953,0.012303,-0.003445*
+1,1,0.002953,-0.012303,-0.003445*
+%
+G04:AMPARAMS|DCode=12|XSize=27.559mil|YSize=9.842mil|CornerRadius=1.476mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD12*
+21,1,0.027559,0.006890,0,0,90.0*
+21,1,0.024606,0.009842,0,0,90.0*
+1,1,0.002953,0.003445,0.012303*
+1,1,0.002953,0.003445,-0.012303*
+1,1,0.002953,-0.003445,-0.012303*
+1,1,0.002953,-0.003445,0.012303*
+%
+G04:AMPARAMS|DCode=39|XSize=41.339mil|YSize=41.339mil|CornerRadius=10.335mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD39*
+21,1,0.041339,0.020669,0,0,270.0*
+21,1,0.020669,0.041339,0,0,270.0*
+1,1,0.020669,-0.010335,-0.010335*
+1,1,0.020669,-0.010335,0.010335*
+1,1,0.020669,0.010335,0.010335*
+1,1,0.020669,0.010335,-0.010335*
+%
diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.EXTREP b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.EXTREP
new file mode 100644
index 0000000000000000000000000000000000000000..aeac7faa9ea2b6edad32cb199cfdc2877fd0bbd4
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.EXTREP	
@@ -0,0 +1,43 @@
+------------------------------------------------------------------------------------------
+Gerber File Extension Report For: DIOT_bPOL12V.GBR   1/10/2023  11:42:44 AM
+------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------
+Layer Extension     Layer Description                      
+------------------------------------------------------------------------------------------
+.gbr                Top Layer                               
+.gbr                L2GND                                   
+.gbr                L3                                      
+.gbr                L4PWR                                   
+.gbr                L5                                      
+.gbr                L6PWR                                   
+.gbr                L7PWR                                   
+.gbr                L8                                      
+.gbr                L9PWR                                   
+.gbr                L10                                     
+.gbr                L11GND                                  
+.gbr                Bottom Layer                            
+.gbr                Bottom Pad Master                       
+.gbr                Top Pad Master                          
+.gbr                Bottom Paste                            
+.gbr                Bottom Overlay                          
+.gbr                Bottom Solder                           
+.gbr                Top Overlay                             
+.gbr                Top Paste                               
+.gbr                Top Solder                              
+.gbr                Keep-Out Layer                          
+.gbr                Mechanical 14                           
+.gbr                Mechanical 8                            
+.gbr                Mechanical 1                            
+.gbr                Mechanical 15                           
+.gbr                Mechanical 13                           
+.gbr                Profile                                 
+.gbr                Non-plated through-hole drill file      
+.gbr                Plated through-hole drill file          
+.gbr                Blind or buried via drill file for drill pairs
+.gbr                Blind or buried via drill file for drill pairs
+.gbr                Blind or buried via drill file for drill pairs
+.gbr                Drill Drawing                           
+.gbr                Drill Guide                             
+------------------------------------------------------------------------------------------
diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.REP b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.REP
new file mode 100644
index 0000000000000000000000000000000000000000..16f12cbc5891704fbb03cd397287689e45b0e9a7
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.REP	
@@ -0,0 +1,622 @@
+*************************************************************
+FileName = DIOT_bPOL12V.GBR
+AutoAperture = True
+*************************************************************
+Generating : Top Layer
+      File : DIOT_bPOL12V_Copper_Signal_Top.gbr
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D13
+    D14
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D32
+    D33
+    D34
+    D35
+    D36
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : L2GND
+      File : DIOT_bPOL12V_Copper_Plane_1.gbr
+
+    Adding Layer      : L2GND
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D47
+    D48
+    D49
+    D50
+    D51
+*************************************************************
+
+*************************************************************
+Generating : L3
+      File : DIOT_bPOL12V_Copper_Signal_1.gbr
+
+    Adding Layer      : L3
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : L4PWR
+      File : DIOT_bPOL12V_Copper_Plane_2.gbr
+
+    Adding Layer      : L4PWR
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D50
+    D51
+    D52
+    D53
+*************************************************************
+
+*************************************************************
+Generating : L5
+      File : DIOT_bPOL12V_Copper_Signal_2.gbr
+
+    Adding Layer      : L5
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : L6PWR
+      File : DIOT_bPOL12V_Copper_Plane_3.gbr
+
+    Adding Layer      : L6PWR
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D50
+    D51
+    D52
+    D53
+*************************************************************
+
+*************************************************************
+Generating : L7PWR
+      File : DIOT_bPOL12V_Copper_Plane_4.gbr
+
+    Adding Layer      : L7PWR
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D50
+    D51
+    D52
+    D53
+*************************************************************
+
+*************************************************************
+Generating : L8
+      File : DIOT_bPOL12V_Copper_Signal_3.gbr
+
+    Adding Layer      : L8
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : L9PWR
+      File : DIOT_bPOL12V_Copper_Plane_5.gbr
+
+    Adding Layer      : L9PWR
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D50
+    D51
+    D52
+    D53
+*************************************************************
+
+*************************************************************
+Generating : L10
+      File : DIOT_bPOL12V_Copper_Signal_4.gbr
+
+    Adding Layer      : L10
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : L11GND
+      File : DIOT_bPOL12V_Copper_Plane_6.gbr
+
+    Adding Layer      : L11GND
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D40
+    D45
+    D46
+    D47
+    D48
+    D49
+    D50
+    D51
+*************************************************************
+
+*************************************************************
+Generating : Bottom Layer
+      File : DIOT_bPOL12V_Copper_Signal_Bot.gbr
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D32
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+*************************************************************
+
+*************************************************************
+Generating : Bottom Pad Master
+      File : DIOT_bPOL12V_Pads_Bot.gbr
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D38
+    D39
+    D40
+    D41
+*************************************************************
+
+*************************************************************
+Generating : Top Pad Master
+      File : DIOT_bPOL12V_Pads_Top.gbr
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D13
+    D14
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D37
+    D38
+    D39
+    D40
+    D41
+*************************************************************
+
+*************************************************************
+Generating : Bottom Paste
+      File : DIOT_bPOL12V_Paste_Bot.gbr
+
+    Adding Layer      : Bottom Paste
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Bottom Overlay
+      File : DIOT_bPOL12V_Legend_Bot.gbr
+
+    Adding Layer      : Bottom Overlay
+
+
+Used DCodes :
+    D54
+    D55
+*************************************************************
+
+*************************************************************
+Generating : Bottom Solder
+      File : DIOT_bPOL12V_Soldermask_Bot.gbr
+
+    Adding Layer      : Bottom Solder
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D37
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+    D56
+*************************************************************
+
+*************************************************************
+Generating : Top Overlay
+      File : DIOT_bPOL12V_Legend_Top.gbr
+
+    Adding Layer      : Top Overlay
+
+
+Used DCodes :
+    D55
+    D57
+    D58
+*************************************************************
+
+*************************************************************
+Generating : Top Paste
+      File : DIOT_bPOL12V_Paste_Top.gbr
+
+    Adding Layer      : Top Paste
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D13
+    D14
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+*************************************************************
+
+*************************************************************
+Generating : Top Solder
+      File : DIOT_bPOL12V_Soldermask_Top.gbr
+
+    Adding Layer      : Top Solder
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D13
+    D14
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D37
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+    D56
+*************************************************************
+
+*************************************************************
+Generating : Keep-Out Layer
+      File : DIOT_bPOL12V_Keep-out.gbr
+
+    Adding Layer      : Keep-Out Layer
+
+
+Used DCodes :
+    D59
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 14
+      File : DIOT_bPOL12V_Mechanical_14.gbr
+
+    Adding Layer      : Mechanical 14
+
+
+Used DCodes :
+    D54
+    D55
+    D58
+    D60
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 8
+      File : DIOT_bPOL12V_Mechanical_8.gbr
+
+    Adding Layer      : Mechanical 8
+
+
+Used DCodes :
+    D60
+    D61
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 1
+      File : DIOT_bPOL12V_Mechanical_1.gbr
+
+    Adding Layer      : Mechanical 1
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 15
+      File : DIOT_bPOL12V_Mechanical_15.gbr
+
+    Adding Layer      : Mechanical 15
+
+
+Used DCodes :
+    D61
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 13
+      File : DIOT_bPOL12V_Mechanical_13.gbr
+
+    Adding Layer      : Mechanical 13
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Profile
+      File : DIOT_bPOL12V_Profile.gbr
+
+
+Used DCodes :
+    D62
+*************************************************************
+
+*************************************************************
+Generating : Non-plated through-hole drill file
+      File : DIOT_bPOL12V_NPTH_Drill.gbr
+
+
+Used DCodes :
+    D63
+*************************************************************
+
+*************************************************************
+Generating : Plated through-hole drill file
+      File : DIOT_bPOL12V_PTH_Drill.gbr
+
+
+Used DCodes :
+    D64
+    D65
+    D66
+    D67
+    D68
+    D69
+    D70
+*************************************************************
+
+*************************************************************
+Generating : Blind or buried via drill file for drill pairs
+      File : DIOT_bPOL12V_Plated_Drill_1_2.gbr
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Blind or buried via drill file for drill pairs
+      File : DIOT_bPOL12V_Plated_Drill_1_11.gbr
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Blind or buried via drill file for drill pairs
+      File : DIOT_bPOL12V_Plated_Drill_2_11.gbr
+
+
+Used DCodes :
+*************************************************************
+
+*************************************************************
+Generating : Drill Drawing
+      File : DIOT_bPOL12V_Drawing_1.gbr
+
+    Adding Drill Pair : Top Layer-Bottom Layer
+
+    Adding Layer      : Drill Drawing
+
+
+Used DCodes :
+    D72
+    D73
+*************************************************************
+
+*************************************************************
+Generating : Drill Guide
+      File : DIOT_bPOL12V_Drillmap_1.gbr
+
+    Adding Drill Pair : Top Layer-Bottom Layer
+
+    Adding Layer      : Drill Guide
+
+
+Used DCodes :
+    D72
+*************************************************************
+
diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.RUL b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..5a68b7f3b8cf078e7289b150509475b8a84acb88
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.RUL	
@@ -0,0 +1,12 @@
+DRC Rules Export File for PCB: D:\Altium_projects\diot-sb-igl\DIOT-bPOL12V\Layout\DIOT_bPOL12V.PcbDoc
+RuleKind=MinimumAnnularRing|RuleName=MinimumAnnularRing|Scope=Board|Minimum=7.80
+RuleKind=MinimumAnnularRing|RuleName=MinimumAnnularRing_Via|Scope=Board|Minimum=4.72
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=0.00
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.15
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
+RuleKind=ShortCircuit|RuleName=ShortCircuit_NT|Scope=Board|Allowed=1
+RuleKind=ShortCircuit|RuleName=ShortCircuit_NetTie|Scope=Board|Allowed=1
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.54
+RuleKind=Clearance|RuleName=Clearance_Poly|Scope=Board|Minimum=7.09
+RuleKind=Clearance|RuleName=Clearance_Poly_Paires_Diff|Scope=Board|Minimum=15.00
+RuleKind=Clearance|RuleName=Clearance_NT|Scope=Board|Minimum=0.00
diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.apr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.apr
new file mode 100644
index 0000000000000000000000000000000000000000..aeed805fa32501a576f79d20670a8b1c1823b7b5
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V.apr	
@@ -0,0 +1,61 @@
+D10   RECTANGULAR        35.433      39.370       0.000 FLASH     270.000
+D13   RECTANGULAR       141.732     141.732       0.000 FLASH      90.000
+D14   RECTANGULAR        50.000     129.921       0.000 FLASH      90.000
+D15   RECTANGULAR        59.055      94.488       0.000 FLASH       0.000
+D16   RECTANGULAR        57.087      45.276       0.000 FLASH     270.000
+D17   RECTANGULAR        24.409      24.409       0.000 FLASH     180.000
+D18   RECTANGULAR        25.197     110.236       0.000 FLASH       0.000
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_1.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_1.gbr
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index 0000000000000000000000000000000000000000..93ec7b0d7e3975c06e93d739831d7786f3fe5b42
--- /dev/null
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_2.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_2.gbr
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_3.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_3.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..72bd9791278b29512e48937e0e7daf33522c1c45
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_3.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_4.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_4.gbr
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index 0000000000000000000000000000000000000000..1f10d9a5283cc387831c37f9d7d4e7782a56ff49
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_5.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_5.gbr
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index 0000000000000000000000000000000000000000..9f093a5a3f7797e5b1aac3cf5a24b0a300155292
--- /dev/null
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_6.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Plane_6.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..9c4118730c60d63450b660549dc38af8cdd957f3
--- /dev/null
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_1.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_1.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..4a47f52b1cf268ea569cae37d4cf03a736c2f147
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_1.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_2.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_2.gbr
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_3.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_3.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..8a722386597559e081d0b4789178e08b75c15867
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_3.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_4.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_4.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..7f037166235877b1a301c5b0e37a8e7293b4d871
--- /dev/null
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Bot.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Bot.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..976e9209994c275fdd1f4690572ea677c9ff14a2
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Bot.gbr	
@@ -0,0 +1,1002 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Top.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Top.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..1b989e50a29fa738bea2c212d7ac16d57b4d3ac0
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Copper_Signal_Top.gbr	
@@ -0,0 +1,5279 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drawing_1.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drawing_1.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..47dd99d55b60f093a2ef47132438e2aba2a0e97e
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drawing_1.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drillmap_1.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drillmap_1.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..3fabf7944054d097bf68daa3f096614f70af0e08
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Drillmap_1.gbr	
@@ -0,0 +1,951 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Keep-out.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Keep-out.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..605d46d94177d8ab5b14f75dc70d81178c771237
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Keep-out.gbr	
@@ -0,0 +1,23 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Bot.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Bot.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..88385163a174b178e42f97daded0c0b27332dfd2
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Bot.gbr	
@@ -0,0 +1,553 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Top.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Top.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..0163394b7b258da23808ef70c5d64cd6371bc4de
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Legend_Top.gbr	
@@ -0,0 +1,32310 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_15.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_15.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..b2d01216b565455b4e4621ff399f0c5e5fcfb101
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_15.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_8.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_8.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..b893e4cb81b9158e54a7fe8255e82bf9b0834c42
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Mechanical_8.gbr	
@@ -0,0 +1,1896 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_NPTH_Drill.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_NPTH_Drill.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..98917181ddb2d25143a9edbbdb9765e9dbfcb63e
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_NPTH_Drill.gbr	
@@ -0,0 +1,23 @@
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_PTH_Drill.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_PTH_Drill.gbr
new file mode 100644
index 0000000000000000000000000000000000000000..b1df3368c75871ea5e66a057e1d68c41cda27512
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_PTH_Drill.gbr	
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index 0000000000000000000000000000000000000000..d1bc89f87e673ab662133f069b34e1b363ad250e
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Pads_Bot.gbr	
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Pads_Top.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Pads_Top.gbr
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index 0000000000000000000000000000000000000000..49b6a26d8618336bbfb361f79c8a66dfc9c5bf96
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index 0000000000000000000000000000000000000000..aa9437bfeea21ac3385bea3327981ce10a2be910
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Paste_Top.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Paste_Top.gbr
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index 0000000000000000000000000000000000000000..2872b1cb65dc18046f9624323e9bf2201c867af2
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Soldermask_Top.gbr b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/DIOT_bPOL12V_Soldermask_Top.gbr
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index 0000000000000000000000000000000000000000..62fa3faf03edb1fb8e1705cbbe02cf8f8946e5af
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diff --git a/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/Status Report.Txt b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/Status Report.Txt
new file mode 100644
index 0000000000000000000000000000000000000000..cb2288b23f27f12796173ad9160ca59172f69864
--- /dev/null
+++ b/DIOT-bPOL12V/Project Outputs for DIOT_bPOL12V/Status Report.Txt	
@@ -0,0 +1,46 @@
+Output: Gerber X2 Files
+Type  : GerberX2
+From  : Project [DIOT_bPOL12V.PrjPcb]
+   Generated File[DIOT_bPOL12V_Copper_Signal_Top.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_1.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Signal_1.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_2.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Signal_2.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_3.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_4.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Signal_3.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_5.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Signal_4.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Plane_6.gbr]
+   Generated File[DIOT_bPOL12V_Copper_Signal_Bot.gbr]
+   Generated File[DIOT_bPOL12V_Pads_Bot.gbr]
+   Generated File[DIOT_bPOL12V_Pads_Top.gbr]
+   Generated File[DIOT_bPOL12V_Paste_Bot.gbr]
+   Generated File[DIOT_bPOL12V_Legend_Bot.gbr]
+   Generated File[DIOT_bPOL12V_Soldermask_Bot.gbr]
+   Generated File[DIOT_bPOL12V_Legend_Top.gbr]
+   Generated File[DIOT_bPOL12V_Paste_Top.gbr]
+   Generated File[DIOT_bPOL12V_Soldermask_Top.gbr]
+   Generated File[DIOT_bPOL12V_Keep-out.gbr]
+   Generated File[DIOT_bPOL12V_Mechanical_14.gbr]
+   Generated File[DIOT_bPOL12V_Mechanical_8.gbr]
+   Generated File[DIOT_bPOL12V_Mechanical_1.gbr]
+   Generated File[DIOT_bPOL12V_Mechanical_15.gbr]
+   Generated File[DIOT_bPOL12V_Mechanical_13.gbr]
+   Generated File[DIOT_bPOL12V_Profile.gbr]
+   Generated File[DIOT_bPOL12V_NPTH_Drill.gbr]
+   Generated File[DIOT_bPOL12V_PTH_Drill.gbr]
+   Generated File[DIOT_bPOL12V_Plated_Drill_1_2.gbr]
+   Generated File[DIOT_bPOL12V_Plated_Drill_1_11.gbr]
+   Generated File[DIOT_bPOL12V_Plated_Drill_2_11.gbr]
+   Generated File[DIOT_bPOL12V_Drawing_1.gbr]
+   Generated File[DIOT_bPOL12V_Drillmap_1.gbr]
+   Generated File[DIOT_bPOL12V.RUL]
+   Generated File[DIOT_bPOL12V.EXTREP]
+   Generated File[DIOT_bPOL12V.REP]
+
+
+Files Generated   : 37
+Documents Printed : 0
+
+Finished Output Generation At 11:42:52 AM On 1/10/2023
diff --git a/DIOT-bPOL12V/README.md b/DIOT-bPOL12V/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..f37054b9c2c7b84a852bbc99ce77a90d7416227b
--- /dev/null
+++ b/DIOT-bPOL12V/README.md
@@ -0,0 +1,3 @@
+# bPOL12V Test Board
+
+The board purpose is test the bPOL12V behaviour in a single pcb. If the first test go successful, it will be mounted afterwards in the system board for more testing. The board was designed mechanically compatible to replace the 2 pcbs base in FEASTMP.
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Electrical.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Electrical.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..a1c7ddde4b74f32dc37db53a0bca13f335289b84
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Electrical.RUL
@@ -0,0 +1,9 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('NT*')|SCOPE2EXPRESSION=All|NAME=Clearance_NT|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=DHGMROTW|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=0mil|GENERICCLEARANCE=0mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=TRUE|OBJECTCLEARANCES= ¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPoly and InNet('GND')|SCOPE2EXPRESSION=InAnyDifferentialPair|NAME=Clearance_Poly_Paires_Diff|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=JMONKYCV|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=15mil|GENERICCLEARANCE=15mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= ¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPoly|SCOPE2EXPRESSION=All|NAME=Clearance_Poly|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=OLTDBSPV|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=7.0866mil|GENERICCLEARANCE=7.0866mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= ¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=not HasFootprint('Net Tie')|NAME=Clearance|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=EOQHYDMT|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=3.5433mil|GENERICCLEARANCE=3.5433mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES=ClearanceObj_Arc-ClearanceObj_Hole:0;ClearanceObj_Track-ClearanceObj_Hole:0;ClearanceObj_SMDPad-ClearanceObj_Hole:0;ClearanceObj_THPad-ClearanceObj_Hole:0;ClearanceObj_Via-ClearanceObj_Hole:0;ClearanceObj_Fill-ClearanceObj_Hole:0;ClearanceObj_Poly-ClearanceObj_Hole:0;ClearanceObj_Region-ClearanceObj_Hole:0;ClearanceObj_Text-ClearanceObj_Hole:0¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ShortCircuit|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('NetTie')|SCOPE2EXPRESSION=InNet('SENSE.P12V0+')or InNet('SENSE.P12V0-')or InNet('SENSE.P1V2+')or InNet('SENSE.P1V2-') or InNet('SENSE.P3V3+') or InNet('SENSE.P3V3-') or InNet('SENSE.PPERIPH+') or InNet('SENSE.PPERIPH-')|NAME=ShortCircuit_NetTie|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CMONATKJ|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ShortCircuit|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('J34') or  InComponent('J31') or InComponent('J30') or InComponent('J29') or InComponent('J33') or InComponent('J26')|SCOPE2EXPRESSION=InComponent('NT*')|NAME=ShortCircuit_NT|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=PVSHXGSS|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ShortCircuit|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=ShortCircuit|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=WORVRETY|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnRoutedNet|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnRoutedNet|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=WRIQKVPH|DEFINEDBYLOGICALDOCUMENT=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnpouredPolygon|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnpouredPolygon|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=EMUSYJDB|DEFINEDBYLOGICALDOCUMENT=FALSE¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-High-Speed.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-High-Speed.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..2125bb9696318d97ab79f32afe69fecc3d493d43
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-High-Speed.RUL
@@ -0,0 +1,20 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Length|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('CPCIs2a') or InxSignalClass('CPCIs2 XS')|SCOPE2EXPRESSION=All|NAME=Length CPCIs2a + XS|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=OGNVHYBB|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=4960.6299mil|MINLIMIT=4763.7795mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Length|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('CPCIs5a')    or InxSignalClass('CPCIs5 XS')|SCOPE2EXPRESSION=All|NAME=Length CPCIs5a + XS|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=YBFFAJAY|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=6106.2992mil|MINLIMIT=5944.8819mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('MoniMod-I2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_6|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=SOVWFIIQ|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=984.252mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('PcbVer-I2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_1|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=DJCJVMMQ|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=984.252mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('Mon-P_SWD')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_23|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=BBLXRNPC|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('Mon-I2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_22|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=IONSLVXF|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FrontPanel-PossiblyI2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_21|ENABLED=TRUE|PRIORITY=5|COMMENT= |UNIQUEID=TCGGIBWX|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('Mon-F_SWD')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_20|ENABLED=TRUE|PRIORITY=6|COMMENT= |UNIQUEID=RYBCARYB|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('Backplane-I2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_19|ENABLED=TRUE|PRIORITY=7|COMMENT= |UNIQUEID=GYHWDPCM|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FMC-I2C')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_18|ENABLED=TRUE|PRIORITY=8|COMMENT= |UNIQUEID=JRHDKGYW|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=1968.5039mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FMC_DP')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_17|ENABLED=TRUE|PRIORITY=9|COMMENT= |UNIQUEID=BAACLURE|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=393.7008mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FMC_DP')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_16|ENABLED=TRUE|PRIORITY=10|COMMENT= |UNIQUEID=PPGNERSU|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=78.7402mil|CHECKNETSINDIFFPAIR=TRUE|CHECKDIFFPAIRVSDIFFPAIR=FALSE|CHECKXSIGNALS=FALSE|CHECKOTHERS=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('Periph_Clocks_Matched')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_15|ENABLED=TRUE|PRIORITY=11|COMMENT= |UNIQUEID=ESJZDATQ|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=393.7008mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('User_Flash')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_5|ENABLED=TRUE|PRIORITY=12|COMMENT= |UNIQUEID=KNXQYALR|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=787.4016mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FPGA-JTAG')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_4|ENABLED=TRUE|PRIORITY=13|COMMENT= |UNIQUEID=NADAJUOZ|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=393.7008mil|CHECKNETSINDIFFPAIR=FALSE|CHECKDIFFPAIRVSDIFFPAIR=TRUE|CHECKXSIGNALS=TRUE|CHECKOTHERS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('PERIPH_DP')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_3|ENABLED=TRUE|PRIORITY=14|COMMENT= |UNIQUEID=QZBXIELW|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=78.7402mil|CHECKNETSINDIFFPAIR=TRUE|CHECKDIFFPAIRVSDIFFPAIR=FALSE|CHECKXSIGNALS=FALSE|CHECKOTHERS=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FMC-CLK')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths_2|ENABLED=TRUE|PRIORITY=15|COMMENT= |UNIQUEID=EQPCYTSN|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=196.8504mil|CHECKNETSINDIFFPAIR=TRUE|CHECKDIFFPAIRVSDIFFPAIR=FALSE|CHECKXSIGNALS=FALSE|CHECKOTHERS=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MatchedLengths|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNetClass('FMC-MGT')|SCOPE2EXPRESSION=All|NAME=Schematic Matched Net Lengths|ENABLED=TRUE|PRIORITY=16|COMMENT= |UNIQUEID=MEJPAKOD|DEFINEDBYLOGICALDOCUMENT=TRUE|TOLERANCE=39.3701mil|CHECKNETSINDIFFPAIR=TRUE|CHECKDIFFPAIRVSDIFFPAIR=FALSE|CHECKXSIGNALS=FALSE|CHECKOTHERS=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ViasUnderSMD|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=HasFootprint ('CAPC0603X33N') or HasFootprint ('RESC1005X40N') or HasFootprint('CAPC1608X87N')   or HasFootprint('CAPC1005X55N') or  HasFootprint('Net Tie') or HasFootprint('STELVIO-KONTEK_3131730000400') or HasFootprint('TEXAS_DRB(S-PVSON-N8)') or HasFootprint('TO170P1394X457-6N-R900X1060')|SCOPE2EXPRESSION=All|NAME=ViasUnderSMD_Jumper|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=OHJWYKVY|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ViasUnderSMD|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=not InComponentClass('Overlapping')|SCOPE2EXPRESSION=All|NAME=ViasUnderSMD|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=IVJWWULE|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=FALSE¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Manufacturing.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Manufacturing.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..3114faf2f02e4a33efe3c90a099fb5f85b88381f
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Manufacturing.RUL
@@ -0,0 +1,10 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumAnnularRing|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia|SCOPE2EXPRESSION=All|NAME=MinimumAnnularRing_Via|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=YPKHJQES|DEFINEDBYLOGICALDOCUMENT=FALSE|MINIMUMRING=4.7244mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumAnnularRing|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=MinimumAnnularRing|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=VJALMFID|DEFINEDBYLOGICALDOCUMENT=FALSE|MINIMUMRING=7.7953mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=HoleSize|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=HoleSize|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=MIGWIUCM|DEFINEDBYLOGICALDOCUMENT=FALSE|ABSOLUTEVALUES=TRUE|MAXLIMIT=196.8504mil|MINLIMIT=7.874mil|MAXPERCENT=80.000|MINPERCENT=20.000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=LayerPairs|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=LayerPairs|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HJPBEFFM|DEFINEDBYLOGICALDOCUMENT=FALSE|ENFORCE=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=HoleToHoleClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=HoleToHoleClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LURSJIFO|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=7.874mil|ALLOWSTACKEDMICROVIAS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumSolderMaskSliver|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsThruPin|SCOPE2EXPRESSION=IsThruPin|NAME=MinimumSolderMaskSliver|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HFXTEAIU|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSOLDERMASKWIDTH=0mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSolderMaskClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsPad|SCOPE2EXPRESSION=All|NAME=SilkToSolderMaskClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=JJMBDHEW|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSILKSCREENTOMASKGAP=3.1496mil|CLEARANCETOEXPOSEDCOPPER=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSilkClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=HasFootprint('AMPHENOL_10052824-101LF')or HasFootprint('AMPHENOL_10052825-101LF')or HasFootprint('AMPHENOL_10052837-101LF')or HasFootprint('AMPHENOL_10052838-101LF')|SCOPE2EXPRESSION=HasFootprint('AMPHENOL_10052824-101LF')or HasFootprint('AMPHENOL_10052825-101LF')or HasFootprint('AMPHENOL_10052837-101LF')or HasFootprint('AMPHENOL_10052838-101LF')|NAME=SilkToSilkClearance_CPCIS|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=XOPFTIKA|DEFINEDBYLOGICALDOCUMENT=FALSE|SILKTOSILKCLEARANCE=0mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSilkClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SilkToSilkClearance|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=FHEMNMRI|DEFINEDBYLOGICALDOCUMENT=FALSE|SILKTOSILKCLEARANCE=1.9685mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=NetAntennae|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=NetAntennae|ENABLED=FALSE|PRIORITY=1|COMMENT= |UNIQUEID=LGNPSJYG|DEFINEDBYLOGICALDOCUMENT=FALSE|NETANTENNAETOLERANCE=0mil¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Mask.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Mask.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..4b8c021a106ecb6dc970905e869b6ff8c39ced19
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Mask.RUL
@@ -0,0 +1,2 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SolderMaskExpansion|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=DUPFVTDY|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=0mil|ISTENTINGTOP=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PasteMaskExpansion|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PasteMaskExpansion|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LYSDPRVW|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=0mil¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Plane.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Plane.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..5e0ca0311478ae2e7ec5c58b793affb4112d3819
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Plane.RUL
@@ -0,0 +1,14 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPadClass('ft_pcbm')|SCOPE2EXPRESSION=All|NAME=PlaneConnect_ft_pcbm|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=RBNDIMCV|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=9.8425mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=7.874mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia or InPadClass('Direct')|SCOPE2EXPRESSION=All|NAME=PlaneConnect_Vias|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=QVTYQBNS|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Direct|RELIEFEXPANSION=20mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=10mil|RELIEFAIRGAP=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=AsMM(HoleDiameter)<0.5|SCOPE2EXPRESSION=All|NAME=PlaneConnect_0 > 0.5|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=GVIBDKAG|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=11.811mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=7.874mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=0.5) and (AsMM(HoleDiameter)<1)|SCOPE2EXPRESSION=All|NAME=PlaneConnect_0.5 > 1|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=GVIBDKAG|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=11.811mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=9.8425mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=1) and (AsMM(HoleDiameter)<1.5)|SCOPE2EXPRESSION=All|NAME=PlaneConnect_1 > 1.5|ENABLED=TRUE|PRIORITY=5|COMMENT= |UNIQUEID=GVIBDKAG|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=11.811mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=11.811mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=1.5) and (AsMM(HoleDiameter)<2)|SCOPE2EXPRESSION=All|NAME=PlaneConnect_1.5 > 2|ENABLED=TRUE|PRIORITY=6|COMMENT= |UNIQUEID=GVIBDKAG|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=11.811mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=15.748mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneConnect|ENABLED=TRUE|PRIORITY=7|COMMENT= |UNIQUEID=UHQAWVKJ|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=11.811mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=19.685mil|RELIEFAIRGAP=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneClearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=JTGSGKFR|DEFINEDBYLOGICALDOCUMENT=FALSE|CLEARANCE=9.8425mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia or InPadClass('Direct') or InNetClass('ESD_STRIP')|SCOPE2EXPRESSION=All|NAME=PolygonConnect_Vias|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=BWMPFGLT|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Direct|RELIEFCONDUCTORWIDTH=10mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=AsMM(HoleDiameter)<0.5|SCOPE2EXPRESSION=All|NAME=PolygonConnect_0 > 0.5|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=MLKIDVVI|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=7.874mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=0.5) and (AsMM(HoleDiameter)<1)|SCOPE2EXPRESSION=All|NAME=PolygonConnect_0.5 > 1|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=MLKIDVVI|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=9.8425mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=1) and (AsMM(HoleDiameter)<1.5)|SCOPE2EXPRESSION=All|NAME=PolygonConnect_1 > 1.5|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=MLKIDVVI|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=11.811mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(AsMM(HoleDiameter)>=1.5) and (AsMM(HoleDiameter)<2)|SCOPE2EXPRESSION=All|NAME=PolygonConnect_1.5 > 2|ENABLED=TRUE|PRIORITY=5|COMMENT= |UNIQUEID=MLKIDVVI|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=15.748mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=7.874mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PolygonConnect|ENABLED=TRUE|PRIORITY=6|COMMENT= |UNIQUEID=MLKIDVVI|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=19.685mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=7.874mil¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Routing.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Routing.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..93fdb2c8398e9756ce65fd39e5d1200106dda0ac
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Routing.RUL
@@ -0,0 +1,12 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Width|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Width|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=OEFXSWDA|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=100mil|MINLIMIT=3.1496mil|PREFEREDWIDTH=3.1496mil|TOPLAYER_MINWIDTH=3.937mil|TOPLAYER_PREFWIDTH=3.937mil|MIDLAYER5_MINWIDTH=3.937mil|MIDLAYER5_PREFWIDTH=12mil|MIDLAYER6_MINWIDTH=3.937mil|MIDLAYER6_PREFWIDTH=12mil|MIDLAYER7_MINWIDTH=3.937mil|MIDLAYER7_PREFWIDTH=12mil|MIDLAYER8_MINWIDTH=3.937mil|MIDLAYER8_PREFWIDTH=12mil|MIDLAYER9_MINWIDTH=3.937mil|MIDLAYER9_PREFWIDTH=12mil|MIDLAYER10_MINWIDTH=3.937mil|MIDLAYER10_PREFWIDTH=12mil|MIDLAYER11_MINWIDTH=3.937mil|MIDLAYER11_PREFWIDTH=12mil|MIDLAYER12_MINWIDTH=3.937mil|MIDLAYER12_PREFWIDTH=12mil|MIDLAYER13_MINWIDTH=3.937mil|MIDLAYER13_PREFWIDTH=12mil|MIDLAYER14_MINWIDTH=3.937mil|MIDLAYER14_PREFWIDTH=12mil|MIDLAYER15_MINWIDTH=3.937mil|MIDLAYER15_PREFWIDTH=12mil|MIDLAYER16_MINWIDTH=3.937mil|MIDLAYER16_PREFWIDTH=12mil|MIDLAYER17_MINWIDTH=3.937mil|MIDLAYER17_PREFWIDTH=12mil|MIDLAYER18_MINWIDTH=3.937mil|MIDLAYER18_PREFWIDTH=12mil|MIDLAYER19_MINWIDTH=3.937mil|MIDLAYER19_PREFWIDTH=12mil|MIDLAYER20_MINWIDTH=3.937mil|MIDLAYER20_PREFWIDTH=12mil|MIDLAYER21_MINWIDTH=3.937mil|MIDLAYER21_PREFWIDTH=12mil|MIDLAYER22_MINWIDTH=3.937mil|MIDLAYER22_PREFWIDTH=12mil|MIDLAYER23_MINWIDTH=3.937mil|MIDLAYER23_PREFWIDTH=12mil|MIDLAYER24_MINWIDTH=3.937mil|MIDLAYER24_PREFWIDTH=12mil|MIDLAYER25_MINWIDTH=3.937mil|MIDLAYER25_PREFWIDTH=12mil|MIDLAYER26_MINWIDTH=3.937mil|MIDLAYER26_PREFWIDTH=12mil|MIDLAYER27_MINWIDTH=3.937mil|MIDLAYER27_PREFWIDTH=12mil|MIDLAYER28_MINWIDTH=3.937mil|MIDLAYER28_PREFWIDTH=12mil|MIDLAYER29_MINWIDTH=3.937mil|MIDLAYER29_PREFWIDTH=12mil|MIDLAYER30_MINWIDTH=3.937mil|MIDLAYER30_PREFWIDTH=12mil|BOTTOMLAYER_MINWIDTH=3.937mil|BOTTOMLAYER_PREFWIDTH=3.937mil|MINIMP=50.000000|MAXIMP=50.000000|FAVIMP=50.000000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingTopology|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingTopology|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=ALODDUUP|DEFINEDBYLOGICALDOCUMENT=FALSE|TOPOLOGY=Shortest¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingPriority|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingPriority|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=BDLHMFKE|DEFINEDBYLOGICALDOCUMENT=FALSE|ROUTINGPRIORITY=0¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingLayers|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingLayers|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=UWKCAQDF|DEFINEDBYLOGICALDOCUMENT=FALSE|TOP LAYER_V5=TRUE|MID LAYER 1_V5=TRUE|MID LAYER 2_V5=TRUE|MID LAYER 3_V5=TRUE|MID LAYER 4_V5=TRUE|MID LAYER 5_V5=TRUE|MID LAYER 6_V5=TRUE|MID LAYER 7_V5=TRUE|MID LAYER 8_V5=TRUE|MID LAYER 9_V5=TRUE|MID LAYER 10_V5=TRUE|MID LAYER 11_V5=TRUE|MID LAYER 12_V5=TRUE|MID LAYER 13_V5=TRUE|MID LAYER 14_V5=TRUE|MID LAYER 15_V5=TRUE|MID LAYER 16_V5=TRUE|MID LAYER 17_V5=TRUE|MID LAYER 18_V5=TRUE|MID LAYER 19_V5=TRUE|MID LAYER 20_V5=TRUE|MID LAYER 21_V5=TRUE|MID LAYER 22_V5=TRUE|MID LAYER 23_V5=TRUE|MID LAYER 24_V5=TRUE|MID LAYER 25_V5=TRUE|MID LAYER 26_V5=TRUE|MID LAYER 27_V5=TRUE|MID LAYER 28_V5=TRUE|MID LAYER 29_V5=TRUE|MID LAYER 30_V5=TRUE|BOTTOM LAYER_V5=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingCorners|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingCorners|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=VFCSLNBG|DEFINEDBYLOGICALDOCUMENT=FALSE|CORNERSTYLE=45-Degree|MINSETBACK=100mil|MAXSETBACK=100mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingVias|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingVias|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KHNJIBJL|DEFINEDBYLOGICALDOCUMENT=FALSE|HOLEWIDTH=11.811mil|WIDTH=25.5906mil|VIASTYLE=Through Hole|MINHOLEWIDTH=7.874mil|MINWIDTH=17.7165mil|MAXHOLEWIDTH=19.685mil|MAXWIDTH=39.37mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsBGA|SCOPE2EXPRESSION=All|NAME=Fanout_BGA|ENABLED=TRUE|PRIORITY=1|COMMENT=Fanout_BGA (Default Rule)|UNIQUEID=YFOKDBUL|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsLCC|SCOPE2EXPRESSION=All|NAME=Fanout_LCC|ENABLED=TRUE|PRIORITY=2|COMMENT=Fanout_LCC (Default Rule)|UNIQUEID=ETJACWOL|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsSOIC|SCOPE2EXPRESSION=All|NAME=Fanout_SOIC|ENABLED=TRUE|PRIORITY=3|COMMENT=Fanout_SOIC (Default Rule)|UNIQUEID=KRWTMPUA|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(CompPinCount < 5)|SCOPE2EXPRESSION=All|NAME=Fanout_Small|ENABLED=TRUE|PRIORITY=4|COMMENT=Fanout_Small (Default Rule)|UNIQUEID=UIDLDVQI|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=OutThenIn|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Fanout_Default|ENABLED=TRUE|PRIORITY=5|COMMENT=Fanout_Default (Default Rule)|UNIQUEID=OHJXWVNB|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=DiffPairsRouting|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=DiffPairsRouting|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=NXYBQHEL|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=7.874mil|MINLIMIT=3.937mil|MOSTFREQGAP=3.937mil|TOPLAYER_MINGAP=7.874mil|TOPLAYER_PREFGAP=7.874mil|TOPLAYER_MINWIDTH=3.937mil|TOPLAYER_MAXWIDTH=3.937mil|TOPLAYER_PREFWIDTH=3.937mil|MIDLAYER1_MAXGAP=3.937mil|MIDLAYER1_MINWIDTH=3.1496mil|MIDLAYER1_MAXWIDTH=3.1496mil|MIDLAYER1_PREFWIDTH=3.1496mil|MIDLAYER2_MAXGAP=3.937mil|MIDLAYER2_MINWIDTH=3.1496mil|MIDLAYER2_MAXWIDTH=3.1496mil|MIDLAYER2_PREFWIDTH=3.1496mil|MIDLAYER3_MAXGAP=3.937mil|MIDLAYER3_MINWIDTH=3.1496mil|MIDLAYER3_MAXWIDTH=3.1496mil|MIDLAYER3_PREFWIDTH=3.1496mil|MIDLAYER4_MAXGAP=3.937mil|MIDLAYER4_MINWIDTH=3.1496mil|MIDLAYER4_MAXWIDTH=3.1496mil|MIDLAYER4_PREFWIDTH=3.1496mil|MIDLAYER5_MINGAP=4.7244mil|MIDLAYER5_MAXGAP=10mil|MIDLAYER5_PREFGAP=4.7244mil|MIDLAYER5_MINWIDTH=3.1496mil|MIDLAYER5_MAXWIDTH=15mil|MIDLAYER5_PREFWIDTH=3.1496mil|MIDLAYER6_MINGAP=4.7244mil|MIDLAYER6_MAXGAP=10mil|MIDLAYER6_PREFGAP=4.7244mil|MIDLAYER6_MINWIDTH=3.1496mil|MIDLAYER6_MAXWIDTH=15mil|MIDLAYER6_PREFWIDTH=3.1496mil|MIDLAYER7_MINGAP=4.7244mil|MIDLAYER7_MAXGAP=10mil|MIDLAYER7_PREFGAP=4.7244mil|MIDLAYER7_MINWIDTH=3.1496mil|MIDLAYER7_MAXWIDTH=15mil|MIDLAYER7_PREFWIDTH=3.1496mil|MIDLAYER8_MINGAP=4.7244mil|MIDLAYER8_MAXGAP=10mil|MIDLAYER8_PREFGAP=4.7244mil|MIDLAYER8_MINWIDTH=3.1496mil|MIDLAYER8_MAXWIDTH=15mil|MIDLAYER8_PREFWIDTH=3.1496mil|MIDLAYER9_MINGAP=4.7244mil|MIDLAYER9_MAXGAP=10mil|MIDLAYER9_PREFGAP=4.7244mil|MIDLAYER9_MINWIDTH=3.1496mil|MIDLAYER9_MAXWIDTH=15mil|MIDLAYER9_PREFWIDTH=3.1496mil|MIDLAYER10_MINGAP=4.7244mil|MIDLAYER10_MAXGAP=10mil|MIDLAYER10_PREFGAP=4.7244mil|MIDLAYER10_MINWIDTH=3.1496mil|MIDLAYER10_MAXWIDTH=15mil|MIDLAYER10_PREFWIDTH=3.1496mil|MIDLAYER11_MINGAP=4.7244mil|MIDLAYER11_MAXGAP=10mil|MIDLAYER11_PREFGAP=4.7244mil|MIDLAYER11_MINWIDTH=3.1496mil|MIDLAYER11_MAXWIDTH=15mil|MIDLAYER11_PREFWIDTH=3.1496mil|MIDLAYER12_MINGAP=4.7244mil|MIDLAYER12_MAXGAP=10mil|MIDLAYER12_PREFGAP=4.7244mil|MIDLAYER12_MINWIDTH=3.1496mil|MIDLAYER12_MAXWIDTH=15mil|MIDLAYER12_PREFWIDTH=3.1496mil|MIDLAYER13_MINGAP=4.7244mil|MIDLAYER13_MAXGAP=10mil|MIDLAYER13_PREFGAP=4.7244mil|MIDLAYER13_MINWIDTH=3.1496mil|MIDLAYER13_MAXWIDTH=15mil|MIDLAYER13_PREFWIDTH=3.1496mil|MIDLAYER14_MINGAP=4.7244mil|MIDLAYER14_MAXGAP=10mil|MIDLAYER14_PREFGAP=4.7244mil|MIDLAYER14_MINWIDTH=3.1496mil|MIDLAYER14_MAXWIDTH=15mil|MIDLAYER14_PREFWIDTH=3.1496mil|MIDLAYER15_MINGAP=4.7244mil|MIDLAYER15_MAXGAP=10mil|MIDLAYER15_PREFGAP=4.7244mil|MIDLAYER15_MINWIDTH=3.1496mil|MIDLAYER15_MAXWIDTH=15mil|MIDLAYER15_PREFWIDTH=3.1496mil|MIDLAYER16_MINGAP=4.7244mil|MIDLAYER16_MAXGAP=10mil|MIDLAYER16_PREFGAP=4.7244mil|MIDLAYER16_MINWIDTH=3.1496mil|MIDLAYER16_MAXWIDTH=15mil|MIDLAYER16_PREFWIDTH=3.1496mil|MIDLAYER17_MINGAP=4.7244mil|MIDLAYER17_MAXGAP=10mil|MIDLAYER17_PREFGAP=4.7244mil|MIDLAYER17_MINWIDTH=3.1496mil|MIDLAYER17_MAXWIDTH=15mil|MIDLAYER17_PREFWIDTH=3.1496mil|MIDLAYER18_MINGAP=4.7244mil|MIDLAYER18_MAXGAP=10mil|MIDLAYER18_PREFGAP=4.7244mil|MIDLAYER18_MINWIDTH=3.1496mil|MIDLAYER18_MAXWIDTH=15mil|MIDLAYER18_PREFWIDTH=3.1496mil|MIDLAYER19_MINGAP=4.7244mil|MIDLAYER19_MAXGAP=10mil|MIDLAYER19_PREFGAP=4.7244mil|MIDLAYER19_MINWIDTH=3.1496mil|MIDLAYER19_MAXWIDTH=15mil|MIDLAYER19_PREFWIDTH=3.1496mil|MIDLAYER20_MINGAP=4.7244mil|MIDLAYER20_MAXGAP=10mil|MIDLAYER20_PREFGAP=4.7244mil|MIDLAYER20_MINWIDTH=3.1496mil|MIDLAYER20_MAXWIDTH=15mil|MIDLAYER20_PREFWIDTH=3.1496mil|MIDLAYER21_MINGAP=4.7244mil|MIDLAYER21_MAXGAP=10mil|MIDLAYER21_PREFGAP=4.7244mil|MIDLAYER21_MINWIDTH=3.1496mil|MIDLAYER21_MAXWIDTH=15mil|MIDLAYER21_PREFWIDTH=3.1496mil|MIDLAYER22_MINGAP=4.7244mil|MIDLAYER22_MAXGAP=10mil|MIDLAYER22_PREFGAP=4.7244mil|MIDLAYER22_MINWIDTH=3.1496mil|MIDLAYER22_MAXWIDTH=15mil|MIDLAYER22_PREFWIDTH=3.1496mil|MIDLAYER23_MINGAP=4.7244mil|MIDLAYER23_MAXGAP=10mil|MIDLAYER23_PREFGAP=4.7244mil|MIDLAYER23_MINWIDTH=3.1496mil|MIDLAYER23_MAXWIDTH=15mil|MIDLAYER23_PREFWIDTH=3.1496mil|MIDLAYER24_MINGAP=4.7244mil|MIDLAYER24_MAXGAP=10mil|MIDLAYER24_PREFGAP=4.7244mil|MIDLAYER24_MINWIDTH=3.1496mil|MIDLAYER24_MAXWIDTH=15mil|MIDLAYER24_PREFWIDTH=3.1496mil|MIDLAYER25_MINGAP=4.7244mil|MIDLAYER25_MAXGAP=10mil|MIDLAYER25_PREFGAP=4.7244mil|MIDLAYER25_MINWIDTH=3.1496mil|MIDLAYER25_MAXWIDTH=15mil|MIDLAYER25_PREFWIDTH=3.1496mil|MIDLAYER26_MINGAP=4.7244mil|MIDLAYER26_MAXGAP=10mil|MIDLAYER26_PREFGAP=4.7244mil|MIDLAYER26_MINWIDTH=3.1496mil|MIDLAYER26_MAXWIDTH=15mil|MIDLAYER26_PREFWIDTH=3.1496mil|MIDLAYER27_MINGAP=4.7244mil|MIDLAYER27_MAXGAP=10mil|MIDLAYER27_PREFGAP=4.7244mil|MIDLAYER27_MINWIDTH=3.1496mil|MIDLAYER27_MAXWIDTH=15mil|MIDLAYER27_PREFWIDTH=3.1496mil|MIDLAYER28_MINGAP=4.7244mil|MIDLAYER28_MAXGAP=10mil|MIDLAYER28_PREFGAP=4.7244mil|MIDLAYER28_MINWIDTH=3.1496mil|MIDLAYER28_MAXWIDTH=15mil|MIDLAYER28_PREFWIDTH=3.1496mil|MIDLAYER29_MINGAP=4.7244mil|MIDLAYER29_MAXGAP=10mil|MIDLAYER29_PREFGAP=4.7244mil|MIDLAYER29_MINWIDTH=3.1496mil|MIDLAYER29_MAXWIDTH=15mil|MIDLAYER29_PREFWIDTH=3.1496mil|MIDLAYER30_MINGAP=4.7244mil|MIDLAYER30_MAXGAP=10mil|MIDLAYER30_PREFGAP=4.7244mil|MIDLAYER30_MINWIDTH=3.1496mil|MIDLAYER30_MAXWIDTH=15mil|MIDLAYER30_PREFWIDTH=3.1496mil|BOTTOMLAYER_MINGAP=7.874mil|BOTTOMLAYER_PREFGAP=7.874mil|BOTTOMLAYER_MINWIDTH=3.937mil|BOTTOMLAYER_MAXWIDTH=3.937mil|BOTTOMLAYER_PREFWIDTH=3.937mil|MAXUNCOUPLEDLENGTH=1200mil¶
diff --git a/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Testpoint.RUL b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Testpoint.RUL
new file mode 100644
index 0000000000000000000000000000000000000000..6d21a68bc40724cc8e50e8348f833bd157ce2a10
--- /dev/null
+++ b/DIOT-bPOL12V/Rules/EDA-DIOT-bPOL12-Testpoint.RUL
@@ -0,0 +1,4 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FabricationTestpoint|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Testpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=JBKURYLU|DEFINEDBYLOGICALDOCUMENT=FALSE|SIDE=3|TESTPOINTUNDERCOMPONENT=TRUE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32.0079mil|TESTPOINTGRID=0.9843mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE|USEGRID=TRUE|GRIDTOLERANCE=0.01mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FabricationTestPointUsage|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=TestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=GWYYRLHO|DEFINEDBYLOGICALDOCUMENT=FALSE|VALID=0|ALLOWMULTIPLE=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestpoint|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FQRXBMHC|DEFINEDBYLOGICALDOCUMENT=FALSE|TESTPOINTUNDERCOMPONENT=TRUE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32mil|TESTPOINTGRID=1mil|USEGRID=TRUE|GRIDTOLERANCE=0.01mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestPointUsage|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=PLBJDVGJ|DEFINEDBYLOGICALDOCUMENT=FALSE¶
diff --git a/DIOT-bPOL12V/Schematics/DIOT_bPOL12V.SCHLIB b/DIOT-bPOL12V/Schematics/DIOT_bPOL12V.SCHLIB
new file mode 100644
index 0000000000000000000000000000000000000000..bce5bc0985cc3ddd7e15588aa2f5d957889d06f3
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diff --git a/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_1V2.SchDoc b/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_1V2.SchDoc
new file mode 100644
index 0000000000000000000000000000000000000000..b16eb1c221f8d1ed04e14a1a059c564029a3c90c
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diff --git a/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_2V5.SchDoc b/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_2V5.SchDoc
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index 0000000000000000000000000000000000000000..410d6bb4b390bb12749b82e94cc8967e0f0919f8
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diff --git a/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_3V3.SchDoc b/DIOT-bPOL12V/Schematics/DIOT_bPOL12V_3V3.SchDoc
new file mode 100644
index 0000000000000000000000000000000000000000..cc836e88aa6cd3c567e4031599508185ff5ba5e2
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