Tags

## [2.2.1](https://be-cem-edl.web.cern.ch/diot-boot-image/v2.2.1) - (2025-06-27)

### Embedded software
- Fix GPIO patch to not powercycle itself during FSBL

## [2.2.0](https://be-cem-edl.web.cern.ch/diot-boot-image/v2.2.0) - (2025-06-25)

### Build system
- Add failed build when patch does not apply
- Fix script for tampering

### Documentation
- Add information about serial ports

### Gateware
- Add reference gateware for version 4
- Update some IPs to version 2024.2
- Add C2C reset using I2C lines in the backplane
- Fix pinout for FMC diff lines in v3 and v4

### Embedded software
- Fix reliable booting
- Fix FSBL patch for EMIOs
- Fix problem I2C IRPS in FSBL

### Device tree
- Update driver for PSU

### U-Boot
- Add XIIC driver
- Fix reliable booting

## [2.1.0-rc](https://be-cem-edl.web.cern.ch/diot-boot-image/v2.1.0-rc/) - (2025-05-28)

### Build system
- Some fixes to improve the make it more user friendly
- Xilinx toolchain upgrade to **2024.2**
- Support for golden firmware in **system board V4**

### Gateware
- Remove CDMA

### Embedded software
- Add reliable booting

### U-Boot
- Add reliable booting

# [2.0.0-rc](https://be-cem-edl.web.cern.ch/diot-boot-image/v2.0.0-rc/) - (2024-10-29)

## Build system
- The current repository must be used as entry point for every DIOT user project
- Xilinx toolchain version is **2022.2**
- Integration with the **CI4FPGA** project
- Complete redesign of the build system:
    - It provides entrypoints for gateware, block design, constraints and device tree to facilitate user customization
    - It warns if the user modifies files that are considered critical for the system
    - It warns if the TCL project sources are out of date

## Documentation
- Support sphinx documentation

## Gateware
- The block design was refactored to better reflect the performance domains
- The gateware build warns about critical warnings and fails if the timing requirements are not met
- HDL top level is now autogenerated from block design

## Embedded software
- No changes

## Device tree
- Device tree is automatically generated from the XSA file

## Arm trusted firmware
- No changes

## U-Boot
- Remove devicetree from the u-boot project

## License
- Compliant with [evergreen project](https://be-cem-edl.web.cern.ch/procedures/licences/)

Version 1.0.0 - (23/11/2023)
============================
Common
------
- Xilinx Toolchain migrated from v2019.2 to v2022.2

Gateware
--------

- FPGA ID Ip core to read git version, build date, commit hash..
- CDMA Engine
- Chip 2 Chip + Aurora 64/66b for communication with peripheral boards
- Chip 2 Chip hotplug mechanism
- Change Aurora 64/66b speed to 8 Gbps
- Change Aurora for bank 225 changed to MGT_CLKREF.CLK_P3 (125 MHz)
- Change Aurora for bank 227 changed to MGT_CLKREF.CLK_P2 (125 MHz)
- Added extra PL Reset for hard reset of CDMA, C2C and Aurora 64/66b
- Added clock to enable PTP synchronization
- Creating IP Repository

Embedded software
-----------------

- Reduced amount of FSBL patches from 5 to 1

Arm trusted firmware
--------------------

- No changes

Device-tree
-----------

- Added SMBIOS information
- Added node that deletes 3rd and 4th CPU
- Added subnode mdio in the gem description
- Added SPI DAC to control VCXO in device-tree
- Change QSPI maximun frequency to 50MHz
- Deleted backup local-mac-address

U-Boot
------

- Added efi boot option for grub
- Added option to override U-Boot environment with uEnv.txt file in BOOTFS partition of SD Card
- Removed patches and implemented their functionality with native U-Boot variables and commands
- Removed PetaLinux platform-top/auto.h, added diot.h
- Removed functionality to mount root filesystem in QSPI flash

- END OF SUPPORT OF 2019.2 and AURORA 8/10b