From 7dc84f4cd0b7761577a4bc82a6c2d226fcf9e984 Mon Sep 17 00:00:00 2001
From: Konstantinos Blantos <konstantinos.blantos@cern.ch>
Date: Tue, 30 Jan 2024 15:36:29 +0100
Subject: [PATCH 1/3] All the dependencies are treated now as git submodules
---
.gitmodules | 40 +++++++++++++++++++++++++++++++++++
dependencies/ddr3-sp6-core | 1 +
dependencies/general-cores | 1 +
dependencies/gn4124-core | 1 +
dependencies/nanofip-gateware | 1 +
dependencies/spec | 1 +
dependencies/svec | 1 +
dependencies/urv-core | 1 +
dependencies/vme64x-core | 1 +
dependencies/wr-cores | 1 +
10 files changed, 49 insertions(+)
create mode 160000 dependencies/ddr3-sp6-core
create mode 160000 dependencies/general-cores
create mode 160000 dependencies/gn4124-core
create mode 160000 dependencies/nanofip-gateware
create mode 160000 dependencies/spec
create mode 160000 dependencies/svec
create mode 160000 dependencies/urv-core
create mode 160000 dependencies/vme64x-core
create mode 160000 dependencies/wr-cores
diff --git a/.gitmodules b/.gitmodules
index 8e3e68d0..7cd161d0 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,4 +7,44 @@
[submodule "software/ertec/ecos"]
path = software/ertec/ecos
url = https://gitlab.cern.ch/be-cem-edl/diot/masterfip/ecos.git
+[submodule "general-cores"]
+ path = dependencies/general-cores
+ url = https://ohwr.org/project/general-cores.git
+[submodule "ddr3-sp6-core"]
+ path = dependencies/ddr3-sp6-core
+ url = https://ohwr.org/project/ddr3-sp6-core.git
+[submodule "gn4124-core"]
+ path = dependencies/gn4124-core
+ url = https://ohwr.org/project/gn4124-core.git
+[submodule "nanofip-gateware"]
+ path = dependencies/nanofip-gateware
+ url = https://ohwr.org/project/nanofip-gateware.git
+[submodule "spec"]
+ path = dependencies/spec
+ url = https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/spec.git
+[submodule "svec"]
+ path = dependencies/svec
+ url = https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec.git
+[submodule "urv-core"]
+ path = dependencies/urv-core
+ url = https://ohwr.org/project/urv-core.git
+[submodule "vme64x-core"]
+ path = dependencies/vme64x-core
+ url = https://gitlab.cern.ch/be-cem-edl/common/vme64x-core.git
+[submodule "wr-core"]
+ path = dependencies/wr-core
+ url = https://ohwr.org/project/wr-cores.git
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/dependencies/ddr3-sp6-core b/dependencies/ddr3-sp6-core
new file mode 160000
index 00000000..01a07e1d
--- /dev/null
+++ b/dependencies/ddr3-sp6-core
@@ -0,0 +1 @@
+Subproject commit 01a07e1d6d118c0a9afc4a4a3c009bfc2027abca
diff --git a/dependencies/general-cores b/dependencies/general-cores
new file mode 160000
index 00000000..3ca2f67c
--- /dev/null
+++ b/dependencies/general-cores
@@ -0,0 +1 @@
+Subproject commit 3ca2f67c6a89e7d82470fcce9cbf71a27db3fb88
diff --git a/dependencies/gn4124-core b/dependencies/gn4124-core
new file mode 160000
index 00000000..ea7e8213
--- /dev/null
+++ b/dependencies/gn4124-core
@@ -0,0 +1 @@
+Subproject commit ea7e82131f0c228b9bdea4f9fb828dc14561c93e
diff --git a/dependencies/nanofip-gateware b/dependencies/nanofip-gateware
new file mode 160000
index 00000000..e51c789c
--- /dev/null
+++ b/dependencies/nanofip-gateware
@@ -0,0 +1 @@
+Subproject commit e51c789c8d2351b0ff07716e4ae064426337a748
diff --git a/dependencies/spec b/dependencies/spec
new file mode 160000
index 00000000..483c3fc7
--- /dev/null
+++ b/dependencies/spec
@@ -0,0 +1 @@
+Subproject commit 483c3fc7306cec24a5e770dd548820c8cc3147f7
diff --git a/dependencies/svec b/dependencies/svec
new file mode 160000
index 00000000..c91efa5e
--- /dev/null
+++ b/dependencies/svec
@@ -0,0 +1 @@
+Subproject commit c91efa5e378b0b65a0f4fff9729079007d99ba57
diff --git a/dependencies/urv-core b/dependencies/urv-core
new file mode 160000
index 00000000..65e80de2
--- /dev/null
+++ b/dependencies/urv-core
@@ -0,0 +1 @@
+Subproject commit 65e80de29a85668bdf2f60539a413fe2889b5141
diff --git a/dependencies/vme64x-core b/dependencies/vme64x-core
new file mode 160000
index 00000000..b86ede3d
--- /dev/null
+++ b/dependencies/vme64x-core
@@ -0,0 +1 @@
+Subproject commit b86ede3d620dd6a5bd04f78b7ca26bd9d1407a47
diff --git a/dependencies/wr-cores b/dependencies/wr-cores
new file mode 160000
index 00000000..f4748f9e
--- /dev/null
+++ b/dependencies/wr-cores
@@ -0,0 +1 @@
+Subproject commit f4748f9ee2c4153601e2e0ede69567288e11ada6
--
GitLab
From fa286b96d67d24b9c51ec9b4b19b5992411c25e1 Mon Sep 17 00:00:00 2001
From: Konstantinos Blantos <konstantinos.blantos@cern.ch>
Date: Tue, 30 Jan 2024 16:38:06 +0100
Subject: [PATCH 2/3] Fix to wr-cores submodule and changes in Manifest.py
files to adopt the new git submodule
---
.gitmodules | 4 ++--
hdl/syn/svec/Manifest.py | 1 -
hdl/top/svec/Manifest.py | 28 ++++++++++++++--------------
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/.gitmodules b/.gitmodules
index 7cd161d0..bde718ab 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -31,8 +31,8 @@
[submodule "vme64x-core"]
path = dependencies/vme64x-core
url = https://gitlab.cern.ch/be-cem-edl/common/vme64x-core.git
-[submodule "wr-core"]
- path = dependencies/wr-core
+[submodule "wr-cores"]
+ path = dependencies/wr-cores
url = https://ohwr.org/project/wr-cores.git
diff --git a/hdl/syn/svec/Manifest.py b/hdl/syn/svec/Manifest.py
index 8107f7dc..089a25fc 100644
--- a/hdl/syn/svec/Manifest.py
+++ b/hdl/syn/svec/Manifest.py
@@ -1,7 +1,6 @@
action = "synthesis"
target = "xilinx"
board = "svec"
-fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
diff --git a/hdl/top/svec/Manifest.py b/hdl/top/svec/Manifest.py
index 9263131f..8decb10c 100644
--- a/hdl/top/svec/Manifest.py
+++ b/hdl/top/svec/Manifest.py
@@ -10,14 +10,14 @@
files = [
"svec_masterfip_mt_urv.ucf",
"svec_masterfip_mt_urv.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_crc.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_decr_counter.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_incr_counter.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_rx_deglitcher.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_rx_deserializer.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_rx_osc.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_tx_osc.vhd",
- "../../ip_cores/nanofip-gateware/src/wf_tx_serializer.vhd"
+ "../../../dependencies/nanofip-gateware/src/wf_crc.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_decr_counter.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_incr_counter.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_rx_deglitcher.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_rx_deserializer.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_rx_osc.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_tx_osc.vhd",
+ "../../../dependencies/nanofip-gateware/src/wf_tx_serializer.vhd"
]
fetchto = "../../ip_cores"
@@ -25,13 +25,13 @@ fetchto = "../../ip_cores"
modules = {
"local" : [
"../../rtl",
- "../../ip_cores/svec",
- "../../ip_cores/vme64x-core",
- "../../ip_cores/general-cores",
- "../../ip_cores/urv-core",
+ "../../../dependencies/svec",
+ "../../../dependencies/vme64x-core",
+ "../../../dependencies/general-cores",
+ "../../../dependencies/urv-core",
"../../../dependencies/mockturtle",
- "../../ip_cores/wr-cores",
- "../../ip_cores/ddr3-sp6-core"
+ "../../../dependencies/wr-cores",
+ "../../../dependencies/ddr3-sp6-core"
],
}
--
GitLab
From 5e4772e37080686f966fd2ba5135f507a5545577 Mon Sep 17 00:00:00 2001
From: Konstantinos Blantos <konstantinos.blantos@cern.ch>
Date: Tue, 30 Jan 2024 16:46:47 +0100
Subject: [PATCH 3/3] Delete unused Makefiles
---
.gitlab-ci.yml | 4 +-
Makefile | 49 -
hdl/syn/Makefile.rules | 56 -
hdl/syn/spec/Makefile.spec | 81 --
hdl/syn/svec/Makefile.svec | 112 --
hdl/syn/svec_masterfip_mt_urv.twr | 2234 -----------------------------
6 files changed, 2 insertions(+), 2534 deletions(-)
delete mode 100644 Makefile
delete mode 100644 hdl/syn/Makefile.rules
delete mode 100644 hdl/syn/spec/Makefile.spec
delete mode 100644 hdl/syn/svec/Makefile.svec
delete mode 100644 hdl/syn/svec_masterfip_mt_urv.twr
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 967f4ea4..b62e0090 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -70,8 +70,8 @@ build_ertec_fw:
gateware_svec:
extends: .synthesis-ise-14-7
interruptible: true
- before_script:
- - make svec.setup_lib
+ # before_script:
+ # - make svec.setup_lib
variables:
EDL_CI_SYN_SRC_PATH: hdl/syn/svec
diff --git a/Makefile b/Makefile
deleted file mode 100644
index 1b15503a..00000000
--- a/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#!/usr/bin/Make
-# ##############################################################################
-# Define project list
-TARGET_FOLDER:=hdl/syn
-TARGET_LIST:=$(patsubst ${TARGET_FOLDER}/%,%,$(patsubst %/,%,$(dir $(wildcard ${TARGET_FOLDER}/*/Manifest.py))))
-
-# ##############################################################################
-# Define different targets:
-# Setup libraries
-TARGET_SETUP_LIB:=$(addsuffix .setup_lib, ${TARGET_LIST})
-# Prepare HDLMake
-TARGET_HDLMAKE:=$(addsuffix .hdlmake, ${TARGET_LIST})
-# Build binary file
-TARGET_BUILD:=$(addsuffix .build, ${TARGET_LIST})
-# Build binary file
-TARGET_CHECK:=$(addsuffix .check, ${TARGET_LIST})
-# Clean the whole project
-TARGET_CLEAN:=$(addsuffix .clean, ${TARGET_LIST})
-
-# ##############################################################################
-# Define action for each target:
-# Clone libraries
-${TARGET_SETUP_LIB}:
- @echo "Setup libraries for $(basename $@)"
- make -f Makefile.$(basename $@) -C $(TARGET_FOLDER)/$(basename $@)/ setup_lib
-
-# HDLMAKE
-${TARGET_HDLMAKE}:
- @echo "Setup Makefile for $(basename $@)"
- make -f Makefile.$(basename $@) -C $(TARGET_FOLDER)/$(basename $@)/ hdlmake
-
-# Build
-${TARGET_BUILD}:
- @echo "Build project for $(basename $@)"
- make -f Makefile.$(basename $@) -C $(TARGET_FOLDER)/$(basename $@)/ build
-
-# Build
-${TARGET_CHECK}:
- @echo "Build project for $(basename $@)"
- make -f Makefile.$(basename $@) -C $(TARGET_FOLDER)/$(basename $@)/ check
-
-# Clean project
-${TARGET_CLEAN}:
- @echo "Clean project $(basename $@)"
- make -f Makefile.$(basename $@) -C $(TARGET_FOLDER)/$(basename $@)/ clean
-
-# ##############################################################################
-# Clean all projects
-clean: ${TARGET_CLEAN}
diff --git a/hdl/syn/Makefile.rules b/hdl/syn/Makefile.rules
deleted file mode 100644
index cd6b1c96..00000000
--- a/hdl/syn/Makefile.rules
+++ /dev/null
@@ -1,56 +0,0 @@
-#!/usr/bin/Make
-# ##############################################################################
-# Settings Docker
-DOCKER_NAME?=gitlab-registry.cern.ch/be-cem-edl/diot/docker-util/ise:latest
-APP=/bin/bash -c
-
-CALL_DOCKER?=docker run -w${CURDIR} \
- -v${CURDIR}:${CURDIR} \
- -v ${HOME}:${HOME} \
- -v /etc/group:/etc/group:ro \
- -v /etc/localtime:/etc/localtime:ro \
- -v /etc/passwd:/etc/passwd:ro \
- -v /etc/shadow:/etc/shadow:ro \
- -v /etc/timezone:/etc/timezone:ro \
- -v /tmp:/tmp \
- -v /tmp/.X11-unix:/tmp/.X11-unix \
- -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
- -v /var/run/dbus:/var/run/dbus \
- -e DISPLAY=${DISPLAY} \
- -u $$(id -u):$$(id -g) \
- --privileged \
- --net=host \
- -t ${DOCKER_NAME} ${APP}
-
-# ##############################################################################
-# CI commands
-ifdef GITLAB_CI
- CMD_DOCKER=eval
-else
- CMD_DOCKER=${CALL_DOCKER}
-endif
-
-# ##############################################################################
-# Setup libraries
-setup_lib:
- @echo "Nothing to do here"
-
-# Call HDLMake
-hdlmake: setup_lib
- @echo "Setting up hdlmake"
- ${CMD_DOCKER} 'hdlmake makefile'
-
-# Build
-build: hdlmake
- @echo "Building bitstream"
- ${CMD_DOCKER} 'make -f Makefile'
-
-# Check
-check:
- @echo "Check possible bitstream issues"
- ${CMD_DOCKER} 'sh check_build.sh'
-
-# ##############################################################################
-# Clean rule
-clean:
- rm -rf ${LIB_DIR}
diff --git a/hdl/syn/spec/Makefile.spec b/hdl/syn/spec/Makefile.spec
deleted file mode 100644
index f992b2b1..00000000
--- a/hdl/syn/spec/Makefile.spec
+++ /dev/null
@@ -1,81 +0,0 @@
-#!/usr/bin/make
-# ##############################################################################
-#
-# The purpose off this makefile is define settings
-#
-# ##############################################################################
-include ../Makefile.rules
-
-# ##############################################################################
-# Defining Configuration for the libraries
-LIB_DIR?=../../ip_cores
-SETUP_CMD=/bin/bash -c
-
-# Specify Directories
-ETHERNET_CORE_DIR=${LIB_DIR}/etherbone-core
-GENERAL_CORES_DIR=${LIB_DIR}/general-cores
-GN4124_CORE_DIR=${LIB_DIR}/gn4124-core
-MOCKTURTLE_DIR=${LIB_DIR}/mockturtle
-NANOFIP_DIR=${LIB_DIR}/nanofip
-SPEC_DIR=${LIB_DIR}/spec
-WR_CORE_DIR=${LIB_DIR}/wr-cores
-
-# Specify TAGs
-ETHERNET_CORE_TAG=master
-GENERAL_CORES_TAG=master
-GN4124_CORE_TAG=proposed_master
-MOCKTURTLE_TAG=v3.1.0
-NANOFIP_TAG=master
-SPEC_TAG=v2.1.6
-WR_CORE_TAG=tom-wr-node
-
-# Specify Commit if is needed
-GN4124_CORE_COMMIT=e3a0bf97e125020c83bff6e40199a717e7fda738
-
-# ##############################################################################
-# CI commands
-ifdef GITLAB_CI
- ETHERNET_CORE_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/hdl-core-lib/etherbone-core.git
- GENERAL_CORES_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/hdl-core-lib/general-cores.git
- GN4124_CORE_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/hdl-core-lib/gn4124-core.git
- MOCKTURTLE_URL=https://gitlab-reader:${CI_JOB_TOKEN}@gitlab.cern.ch/coht/mockturtle.git
- NANOFIP_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/cern-fip/nanofip/nanofip-gateware.git
- SPEC_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/project/spec.git
- WR_CORE_URL=https://gitlab-reader:${CI_JOB_TOKEN}@ohwr.org/project/wr-cores.git
-
- ETHERNET_CORE_CMD='git clone --depth=1 -b ${ETHERNET_CORE_TAG} ${ETHERNET_CORE_URL} ${ETHERNET_CORE_DIR}'
- GENERAL_CORES_CMD='git clone --depth=1 -b ${GENERAL_CORES_TAG} ${GENERAL_CORES_URL} ${GENERAL_CORES_DIR}'
- GN4124_CORE_CMD='git clone -b ${GN4124_CORE_TAG} ${GN4124_CORE_URL} ${GN4124_CORE_DIR}'
- MOCKTURTLE_CMD='git clone --depth=1 -b ${MOCKTURTLE_TAG} ${MOCKTURTLE_URL} ${MOCKTURTLE_DIR}'
- NANOFIP_CMD='git clone --depth=1 -b ${NANOFIP_TAG} ${NANOFIP_URL} ${NANOFIP_DIR}'
- SPEC_CMD='git clone --depth=1 -b ${SPEC_TAG} ${SPEC_URL} ${SPEC_DIR}'
- WR_CORE_CMD='git clone --depth=1 -b ${WR_CORE_TAG} ${WR_CORE_URL} ${WR_CORE_DIR}'
-else
- ETHERNET_CORE_URL=https://ohwr.org/hdl-core-lib/etherbone-core.git
- GENERAL_CORES_URL=https://ohwr.org/hdl-core-lib/general-cores.git
- GN4124_CORE_URL=https://ohwr.org/hdl-core-lib/gn4124-core.git
- MOCKTURTLE_URL=https://gitlab.cern.ch/coht/mockturtle.git
- NANOFIP_URL=https://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
- SPEC_URL=https://ohwr.org/project/spec.git
- WR_CORE_URL=https://ohwr.org/project/wr-cores.git
-
- ETHERNET_CORE_CMD='git clone -b ${ETHERNET_CORE_TAG} ${ETHERNET_CORE_URL} ${ETHERNET_CORE_DIR}'
- GENERAL_CORES_CMD='git clone -b ${GENERAL_CORES_TAG} ${GENERAL_CORES_URL} ${GENERAL_CORES_DIR}'
- GN4124_CORE_CMD='git clone -b ${GN4124_CORE_TAG} ${GN4124_CORE_URL} ${GN4124_CORE_DIR}'
- MOCKTURTLE_CMD='git clone -b ${MOCKTURTLE_TAG} ${MOCKTURTLE_URL} ${MOCKTURTLE_DIR}'
- NANOFIP_CMD='git clone -b ${NANOFIP_TAG} ${NANOFIP_URL} ${NANOFIP_DIR}'
- SPEC_CMD='git clone -b ${SPEC_TAG} ${SPEC_URL} ${SPEC_DIR}'
- WR_CORE_CMD='git clone -b ${WR_CORE_TAG} ${WR_CORE_URL} ${WR_CORE_DIR}'
-endif
-
-setup_lib:
- @echo "Cloninig submodules in ${LIB_DIR}"
- ${SETUP_CMD} ${ETHERNET_CORE_CMD}
- ${SETUP_CMD} ${GENERAL_CORES_CMD}
- ${SETUP_CMD} ${GN4124_CORE_CMD}
- ${SETUP_CMD} ${MOCKTURTLE_CMD}
- ${SETUP_CMD} ${NANOFIP_CMD}
- ${SETUP_CMD} ${SPEC_CMD}
- ${SETUP_CMD} ${WR_CORE_CMD}
- @echo "Checkout commit ${GN4124_CORE_COMMIT} in ${GN4124_CORE_DIR}"
- ${SETUP_CMD} 'cd ${GN4124_CORE_DIR} && git checkout ${GN4124_CORE_COMMIT}'
diff --git a/hdl/syn/svec/Makefile.svec b/hdl/syn/svec/Makefile.svec
deleted file mode 100644
index 8d07fc18..00000000
--- a/hdl/syn/svec/Makefile.svec
+++ /dev/null
@@ -1,112 +0,0 @@
-#!/usr/bin/make
-# ##############################################################################
-#
-# The purpose off this makefile is define settings
-#
-# ##############################################################################
-include ../Makefile.rules
-
-# ##############################################################################
-# Defining Configuration for the libraries
-LIB_DIR?=../../ip_cores
-SETUP_CMD=/bin/bash -c
-
-# Specify Directories
-DDR3_SP6_DIR=${LIB_DIR}/ddr3-sp6-core
-GENERAL_CORES_DIR=${LIB_DIR}/general-cores
-GN4124_CORE_DIR=${LIB_DIR}/gn4124-core
-#MOCKTURTLE_DIR=${LIB_DIR}/mockturtle
-NANOFIP_DIR=${LIB_DIR}/nanofip-gateware
-SPEC_DIR=${LIB_DIR}/spec
-SVEC_DIR=${LIB_DIR}/svec
-URV_DIR=${LIB_DIR}/urv-core
-VME_DIR=${LIB_DIR}/vme64x-core
-WR_CORE_DIR=${LIB_DIR}/wr-cores
-
-# Specify TAGs
-DDR3_SP6_TAG=master
-GENERAL_CORES_TAG=master
-GN4124_CORE_TAG=master
-NANOFIP_TAG=master
-#MOCKTURTLE_TAG=master
-SPEC_TAG=v2.1.6
-SVEC_TAG=v3.0.0
-URV_TAG=proposed_master
-VME_TAG=v2.1
-WR_CORE_TAG=proposed_master
-
-# Specify Commit if is needed
-DDR3_SP6_COMMIT=70f9de318f155764fdd4b7e1ae7f9c5b77131930
-#GENERAL_CORES_COMMIT=c1277ee6df0653aec12be8ed50c44bf47f1d3422
-GN4124_CORE_COMMIT=461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
-#MOCKTURTLE_COMMIT=7ec23c8ff119cb48d5ac3ca08f9a3cece1f3b3aa # 5e8ad5b47e02b8d809521db45837eeddd4e61504
-URV_COMMIT=10f8dc294c52661c80337e33093a8e4624d4bee2
-WR_CORE_COMMIT=f4748f9ee2c4153601e2e0ede69567288e11ada6
-
-# ##############################################################################
-# CI commands
-ifdef GITLAB_CI
- DDR3_SP6_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/ddr3-sp6-core.git
- GENERAL_CORES_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/general-cores.git
- GN4124_CORE_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/gn4124-core.git
-# MOCKTURTLE_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@gitlab.cern.ch/coht/mockturtle.git
- NANOFIP_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/cern-fip/nanofip/nanofip-gateware.git
- SVEC_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec.git
- URV_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/urv-core.git
- VME_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/vme64x-core.git
- WR_CORE_URL=https://gitlab-ci-token:${CI_JOB_TOKEN}@ohwr.org/project/wr-cores.git
-
- DDR3_SP6_CMD='git clone -b ${DDR3_SP6_TAG} ${DDR3_SP6_URL} ${DDR3_SP6_DIR}'
- GENERAL_CORES_CMD='git clone -b ${GENERAL_CORES_TAG} ${GENERAL_CORES_URL} ${GENERAL_CORES_DIR}'
- GN4124_CORE_CMD='git clone -b ${GN4124_CORE_TAG} ${GN4124_CORE_URL} ${GN4124_CORE_DIR}'
-# MOCKTURTLE_CMD='git clone -b ${MOCKTURTLE_TAG} ${MOCKTURTLE_URL} ${MOCKTURTLE_DIR}'
- NANOFIP_CMD='git clone --depth=1 -b ${NANOFIP_TAG} ${NANOFIP_URL} ${NANOFIP_DIR}'
- SVEC_CMD='git clone --depth=1 -b ${SVEC_TAG} ${SVEC_URL} ${SVEC_DIR}'
- URV_CMD='git clone -b ${URV_TAG} ${URV_URL} ${URV_DIR}'
- VME_CMD='git clone --depth=1 -b ${VME_TAG} ${VME_URL} ${VME_DIR}'
- WR_CORE_CMD='git clone -b ${WR_CORE_TAG} ${WR_CORE_URL} ${WR_CORE_DIR}'
-else
- DDR3_SP6_URL=https://ohwr.org/project/ddr3-sp6-core.git
- GENERAL_CORES_URL=https://ohwr.org/project/general-cores.git
- GN4124_CORE_URL=https://ohwr.org/project/gn4124-core.git
-# MOCKTURTLE_URL=https://gitlab.cern.ch/coht/mockturtle.git
- NANOFIP_URL=https://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
- SVEC_URL=https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec.git
- URV_URL=https://ohwr.org/project/urv-core.git
- VME_URL=https://ohwr.org/project/vme64x-core.git
- WR_CORE_URL=https://ohwr.org/project/wr-cores.git
-
- DDR3_SP6_CMD='git clone -b ${DDR3_SP6_TAG} ${DDR3_SP6_URL} ${DDR3_SP6_DIR}'
- GENERAL_CORES_CMD='git clone -b ${GENERAL_CORES_TAG} ${GENERAL_CORES_URL} ${GENERAL_CORES_DIR}'
- GN4124_CORE_CMD='git clone -b ${GN4124_CORE_TAG} ${GN4124_CORE_URL} ${GN4124_CORE_DIR}'
-# MOCKTURTLE_CMD='git clone -b ${MOCKTURTLE_TAG} ${MOCKTURTLE_URL} ${MOCKTURTLE_DIR}'
- NANOFIP_CMD='git clone -b ${NANOFIP_TAG} ${NANOFIP_URL} ${NANOFIP_DIR}'
- SVEC_CMD='git clone -b ${SVEC_TAG} ${SVEC_URL} ${SVEC_DIR}'
- URV_CMD='git clone -b ${URV_TAG} ${URV_URL} ${URV_DIR}'
- VME_CMD='git clone -b ${VME_TAG} ${VME_URL} ${VME_DIR}'
- WR_CORE_CMD='git clone -b ${WR_CORE_TAG} ${WR_CORE_URL} ${WR_CORE_DIR}'
-endif
-
-setup_lib:
- @echo "Cloninig submodules in ${LIB_DIR}"
- ${SETUP_CMD} ${DDR3_SP6_CMD}
- ${SETUP_CMD} ${GENERAL_CORES_CMD}
- ${SETUP_CMD} ${GN4124_CORE_CMD}
-# ${SETUP_CMD} ${MOCKTURTLE_CMD}
- ${SETUP_CMD} ${NANOFIP_CMD}
- ${SETUP_CMD} ${SVEC_CMD}
- ${SETUP_CMD} ${URV_CMD}
- ${SETUP_CMD} ${VME_CMD}
- ${SETUP_CMD} ${WR_CORE_CMD}
- @echo "Adjusting commits in the libraries"
- ${SETUP_CMD} 'cd ${DDR3_SP6_DIR} && git checkout ${DDR3_SP6_COMMIT}'
-# ${SETUP_CMD} 'cd ${GENERAL_CORES_DIR} && git checkout ${GENERAL_CORES_COMMIT}'
- ${SETUP_CMD} 'cd ${GN4124_CORE_DIR} && git checkout ${GN4124_CORE_COMMIT}'
-# ${SETUP_CMD} 'cd ${MOCKTURTLE_DIR} && git checkout ${MOCKTURTLE_COMMIT}'
- ${SETUP_CMD} 'cd ${URV_DIR} && git checkout ${URV_COMMIT}'
- ${SETUP_CMD} 'cd ${WR_CORE_DIR} && git checkout ${WR_CORE_COMMIT}'
-
-clean:
- rm -rf ${LIB_DIR}
- rm -rf Makefile project synthesize translate par map bistream
- rm -rf buildinfo_pkg.vhd *.par *.syr *.twr *.xise *_map.mrp
diff --git a/hdl/syn/svec_masterfip_mt_urv.twr b/hdl/syn/svec_masterfip_mt_urv.twr
deleted file mode 100644
index 06589218..00000000
--- a/hdl/syn/svec_masterfip_mt_urv.twr
+++ /dev/null
@@ -1,2234 +0,0 @@
---------------------------------------------------------------------------------
-Release 14.7 Trace (lin64)
-Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-
-/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 3 -n
-3 -fastpaths -xml svec_masterfip_mt_urv.twx svec_masterfip_mt_urv.ncd -o
-svec_masterfip_mt_urv.twr svec_masterfip_mt_urv.pcf
-
-Design file: svec_masterfip_mt_urv.ncd
-Physical constraint file: svec_masterfip_mt_urv.pcf
-Device,package,speed: xc6slx150t,fgg900,C,-3 (PRODUCTION 1.23 2013-10-13)
-Report level: verbose report
-
-Environment Variable Effect
--------------------- ------
-NONE No environment variables were set
---------------------------------------------------------------------------------
-
-WARNING:Timing:3223 - Timing constraint PATH "TS_ref_sync_ffs_path" TIG;
- ignored during timing analysis.
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
- information, see the TSI report. Please consult the Xilinx Command Line
- Tools User Guide for information on generating a TSI report.
-INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
-
-================================================================================
-Timing constraint: TS_clk_125m_pllref = PERIOD TIMEGRP "clk_125m_ref" 8 ns HIGH
-50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.334ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_125m_pllref = PERIOD TIMEGRP "clk_125m_ref" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.666ns (period - (min low pulse limit / (low pulse / period)))
- Period: 8.000ns
- Low pulse: 4.000ns
- Low pulse limit: 1.667ns (Tdcmpw_CLKIN_100_150)
- Physical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Logical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV_ML_NEW_DIVCLK
---------------------------------------------------------------------------------
-Slack: 4.666ns (period - (min high pulse limit / (high pulse / period)))
- Period: 8.000ns
- High pulse: 4.000ns
- High pulse limit: 1.667ns (Tdcmpw_CLKIN_100_150)
- Physical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Logical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV_ML_NEW_DIVCLK
---------------------------------------------------------------------------------
-Slack: 6.148ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 1.852ns (539.957MHz) (Tpllper_CLKIN(Finmax))
- Physical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Logical resource: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: inst_svec_base/gen_no_wr.cmp_sys_clk_pll/PLL_ADV_ML_NEW_DIVCLK
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_ref_sync_ffs_path" TIG;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_sys_sync_ffs_path" TIG;
-
- 111 paths analyzed, 37 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/s_rd_state_FSM_FFd1 (SLICE_X104Y130.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path): 8.828ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd1 (FF)
- Data Path Delay: 7.974ns (Levels of Logic = 1)
- Clock Path Skew: -0.633ns (1.428 - 2.061)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A5 net (fanout=12) 1.291 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X104Y130.SR net (fanout=68) 5.743 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X104Y130.CLK Trck 0.234 cmp_mt_profip_translator/PWR_23_o_PWR_23_o_OR_80_o
- cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- ------------------------------------------------- ---------------------------
- Total 7.974ns (0.940ns logic, 7.034ns route)
- (11.8% logic, 88.2% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 8.348ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd1 (FF)
- Data Path Delay: 7.499ns (Levels of Logic = 1)
- Clock Path Skew: -0.628ns (1.428 - 2.056)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 to cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y84.DQ Tcko 0.391 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0
- SLICE_X57Y80.A4 net (fanout=160) 0.872 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X104Y130.SR net (fanout=68) 5.743 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X104Y130.CLK Trck 0.234 cmp_mt_profip_translator/PWR_23_o_PWR_23_o_OR_80_o
- cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- ------------------------------------------------- ---------------------------
- Total 7.499ns (0.884ns logic, 6.615ns route)
- (11.8% logic, 88.2% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 8.111ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd1 (FF)
- Data Path Delay: 7.258ns (Levels of Logic = 1)
- Clock Path Skew: -0.632ns (1.428 - 2.060)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg to cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y82.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A3 net (fanout=75) 0.631 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X104Y130.SR net (fanout=68) 5.743 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X104Y130.CLK Trck 0.234 cmp_mt_profip_translator/PWR_23_o_PWR_23_o_OR_80_o
- cmp_mt_profip_translator/s_rd_state_FSM_FFd1
- ------------------------------------------------- ---------------------------
- Total 7.258ns (0.884ns logic, 6.374ns route)
- (12.2% logic, 87.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/rd_en (SLICE_X103Y117.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path): 7.895ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/rd_en (FF)
- Data Path Delay: 7.114ns (Levels of Logic = 1)
- Clock Path Skew: -0.560ns (1.501 - 2.061)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/rd_en
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A5 net (fanout=12) 1.291 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X103Y117.SR net (fanout=68) 4.828 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X103Y117.CLK Trck 0.289 cmp_mt_profip_translator/rd_en
- cmp_mt_profip_translator/rd_en
- ------------------------------------------------- ---------------------------
- Total 7.114ns (0.995ns logic, 6.119ns route)
- (14.0% logic, 86.0% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 7.415ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 (FF)
- Destination: cmp_mt_profip_translator/rd_en (FF)
- Data Path Delay: 6.639ns (Levels of Logic = 1)
- Clock Path Skew: -0.555ns (1.501 - 2.056)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 to cmp_mt_profip_translator/rd_en
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y84.DQ Tcko 0.391 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0
- SLICE_X57Y80.A4 net (fanout=160) 0.872 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X103Y117.SR net (fanout=68) 4.828 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X103Y117.CLK Trck 0.289 cmp_mt_profip_translator/rd_en
- cmp_mt_profip_translator/rd_en
- ------------------------------------------------- ---------------------------
- Total 6.639ns (0.939ns logic, 5.700ns route)
- (14.1% logic, 85.9% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 7.178ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg (FF)
- Destination: cmp_mt_profip_translator/rd_en (FF)
- Data Path Delay: 6.398ns (Levels of Logic = 1)
- Clock Path Skew: -0.559ns (1.501 - 2.060)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg to cmp_mt_profip_translator/rd_en
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y82.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A3 net (fanout=75) 0.631 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A Tilo 0.259 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X103Y117.SR net (fanout=68) 4.828 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X103Y117.CLK Trck 0.289 cmp_mt_profip_translator/rd_en
- cmp_mt_profip_translator/rd_en
- ------------------------------------------------- ---------------------------
- Total 6.398ns (0.939ns logic, 5.459ns route)
- (14.7% logic, 85.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 (SLICE_X71Y48.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path): 7.594ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 (FF)
- Data Path Delay: 6.743ns (Levels of Logic = 2)
- Clock Path Skew: -0.630ns (1.431 - 2.061)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B6 net (fanout=12) 1.149 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X78Y65.A4 net (fanout=286) 2.783 local_reset_n
- SLICE_X78Y65.A Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv1_INV_0
- SLICE_X71Y48.SR net (fanout=1) 1.667 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- SLICE_X71Y48.CLK Trck 0.289 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- ------------------------------------------------- ---------------------------
- Total 6.743ns (1.144ns logic, 5.599ns route)
- (17.0% logic, 83.0% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 6.877ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 (FF)
- Data Path Delay: 6.217ns (Levels of Logic = 2)
- Clock Path Skew: -0.439ns (1.431 - 1.870)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 to cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y103.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B4 net (fanout=1) 0.679 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X78Y65.A4 net (fanout=286) 2.783 local_reset_n
- SLICE_X78Y65.A Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv1_INV_0
- SLICE_X71Y48.SR net (fanout=1) 1.667 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- SLICE_X71Y48.CLK Trck 0.289 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- ------------------------------------------------- ---------------------------
- Total 6.217ns (1.088ns logic, 5.129ns route)
- (17.5% logic, 82.5% route)
-
---------------------------------------------------------------------------------
-Delay (setup path): 6.616ns (data path - clock path skew + uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 (FF)
- Data Path Delay: 5.954ns (Levels of Logic = 2)
- Clock Path Skew: -0.441ns (1.431 - 1.872)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 to cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y102.AMUX Tshcko 0.461 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<4>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B5 net (fanout=1) 0.346 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X78Y65.A4 net (fanout=286) 2.783 local_reset_n
- SLICE_X78Y65.A Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv1_INV_0
- SLICE_X71Y48.SR net (fanout=1) 1.667 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/rst_n_a_i_inv
- SLICE_X71Y48.CLK Trck 0.289 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- ------------------------------------------------- ---------------------------
- Total 5.954ns (1.158ns logic, 4.796ns route)
- (19.4% logic, 80.6% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: PATH "TS_sys_sync_ffs_path" TIG;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/miso_data_reg_6 (SLICE_X102Y92.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (hold path): 2.585ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_6 (FF)
- Data Path Delay: 2.786ns (Levels of Logic = 1)
- Clock Path Skew: -0.020ns (0.850 - 0.870)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg to cmp_mt_profip_translator/miso_data_reg_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y82.AQ Tcko 0.198 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A3 net (fanout=75) 0.366 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.106 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_6
- ------------------------------------------------- ---------------------------
- Total 2.786ns (0.460ns logic, 2.326ns route)
- (16.5% logic, 83.5% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 2.718ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_6 (FF)
- Data Path Delay: 2.923ns (Levels of Logic = 1)
- Clock Path Skew: -0.016ns (0.850 - 0.866)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 to cmp_mt_profip_translator/miso_data_reg_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y84.DQ Tcko 0.198 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0
- SLICE_X57Y80.A4 net (fanout=160) 0.503 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.106 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_6
- ------------------------------------------------- ---------------------------
- Total 2.923ns (0.460ns logic, 2.463ns route)
- (15.7% logic, 84.3% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 2.988ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_6 (FF)
- Data Path Delay: 3.188ns (Levels of Logic = 1)
- Clock Path Skew: -0.021ns (0.850 - 0.871)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/miso_data_reg_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.234 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A5 net (fanout=12) 0.732 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.106 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_6
- ------------------------------------------------- ---------------------------
- Total 3.188ns (0.496ns logic, 2.692ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/miso_data_reg_22 (SLICE_X102Y92.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (hold path): 2.596ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_22 (FF)
- Data Path Delay: 2.797ns (Levels of Logic = 1)
- Clock Path Skew: -0.020ns (0.850 - 0.870)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg to cmp_mt_profip_translator/miso_data_reg_22
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y82.AQ Tcko 0.198 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A3 net (fanout=75) 0.366 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.117 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_22
- ------------------------------------------------- ---------------------------
- Total 2.797ns (0.471ns logic, 2.326ns route)
- (16.8% logic, 83.2% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 2.729ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_22 (FF)
- Data Path Delay: 2.934ns (Levels of Logic = 1)
- Clock Path Skew: -0.016ns (0.850 - 0.866)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 to cmp_mt_profip_translator/miso_data_reg_22
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y84.DQ Tcko 0.198 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0
- SLICE_X57Y80.A4 net (fanout=160) 0.503 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.117 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_22
- ------------------------------------------------- ---------------------------
- Total 2.934ns (0.471ns logic, 2.463ns route)
- (16.1% logic, 83.9% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 2.999ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/miso_data_reg_22 (FF)
- Data Path Delay: 3.199ns (Levels of Logic = 1)
- Clock Path Skew: -0.021ns (0.850 - 0.871)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/miso_data_reg_22
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.234 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A5 net (fanout=12) 0.732 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y92.SR net (fanout=68) 1.960 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y92.CLK Tremck (-Th) -0.117 cmp_mt_profip_translator/miso_data_reg<22>
- cmp_mt_profip_translator/miso_data_reg_22
- ------------------------------------------------- ---------------------------
- Total 3.199ns (0.507ns logic, 2.692ns route)
- (15.8% logic, 84.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/s_rd_state_FSM_FFd2 (SLICE_X102Y96.SR), 3 paths
---------------------------------------------------------------------------------
-Delay (hold path): 2.785ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd2 (FF)
- Data Path Delay: 2.991ns (Levels of Logic = 1)
- Clock Path Skew: -0.015ns (0.855 - 0.870)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg to cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y82.AQ Tcko 0.198 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A3 net (fanout=75) 0.366 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y96.SR net (fanout=68) 2.133 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y96.CLK Tremck (-Th) -0.138 cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- ------------------------------------------------- ---------------------------
- Total 2.991ns (0.492ns logic, 2.499ns route)
- (16.4% logic, 83.6% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 2.918ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd2 (FF)
- Data Path Delay: 3.128ns (Levels of Logic = 1)
- Clock Path Skew: -0.011ns (0.855 - 0.866)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0 to cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y84.DQ Tcko 0.198 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0
- SLICE_X57Y80.A4 net (fanout=160) 0.503 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<0>
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y96.SR net (fanout=68) 2.133 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y96.CLK Tremck (-Th) -0.138 cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- ------------------------------------------------- ---------------------------
- Total 3.128ns (0.492ns logic, 2.636ns route)
- (15.7% logic, 84.3% route)
-
---------------------------------------------------------------------------------
-Delay (hold path): 3.188ns (datapath - clock path skew - uncertainty)
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/s_rd_state_FSM_FFd2 (FF)
- Data Path Delay: 3.393ns (Levels of Logic = 1)
- Clock Path Skew: -0.016ns (0.855 - 0.871)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.221ns
-
- Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.120ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.234 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A5 net (fanout=12) 0.732 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X57Y80.A Tilo 0.156 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv1
- SLICE_X102Y96.SR net (fanout=68) 2.133 cmp_mt_profip_translator/cmp_spi_dv_o_detect/rst_n_i_inv
- SLICE_X102Y96.CLK Tremck (-Th) -0.138 cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- cmp_mt_profip_translator/s_rd_state_FSM_FFd2
- ------------------------------------------------- ---------------------------
- Total 3.393ns (0.528ns logic, 2.865ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_ref_sync_reg = MAXDELAY FROM TIMEGRP "ref_clk" TO TIMEGRP
-"ref_sync_reg" 8 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 22 paths analyzed, 22 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 1.817ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_8 (SLICE_X108Y154.A3), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.183ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_8 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_8 (FF)
- Requirement: 8.000ns
- Data Path Delay: 1.817ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_8 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X103Y147.AQ Tcko 0.391 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin<10>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_8
- SLICE_X108Y154.A3 net (fanout=2) 1.272 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<8>
- SLICE_X108Y154.CLK Tas 0.154 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0<3>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<8>_rt
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_8
- ------------------------------------------------- ---------------------------
- Total 1.817ns (0.545ns logic, 1.272ns route)
- (30.0% logic, 70.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_5 (SLICE_X109Y155.BX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.289ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_5 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_5 (FF)
- Requirement: 8.000ns
- Data Path Delay: 1.711ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_5 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X103Y150.AQ Tcko 0.391 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<5>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_5
- SLICE_X109Y155.BX net (fanout=2) 1.257 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<5>
- SLICE_X109Y155.CLK Tdick 0.063 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0<7>
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_5
- ------------------------------------------------- ---------------------------
- Total 1.711ns (0.454ns logic, 1.257ns route)
- (26.5% logic, 73.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_9 (SLICE_X108Y154.B2), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.319ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_9 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_9 (FF)
- Requirement: 8.000ns
- Data Path Delay: 1.681ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_9 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X105Y149.CMUX Tshcko 0.461 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<6>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray_9
- SLICE_X108Y154.B2 net (fanout=2) 1.066 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<9>
- SLICE_X108Y154.CLK Tas 0.154 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0<3>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_gray<9>_rt
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync1/sync0_9
- ------------------------------------------------- ---------------------------
- Total 1.681ns (0.615ns logic, 1.066ns route)
- (36.6% logic, 63.4% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_ref_sync_reg = MAXDELAY FROM TIMEGRP "ref_clk" TO TIMEGRP "ref_sync_reg" 8 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_2 (SLICE_X110Y29.CX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.565ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_2 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.565ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_2 to cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X109Y27.AQ Tcko 0.198 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<4>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_2
- SLICE_X110Y29.CX net (fanout=1) 0.319 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<2>
- SLICE_X110Y29.CLK Tckdi (-Th) -0.048 cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_2
- ------------------------------------------------- ---------------------------
- Total 0.565ns (0.246ns logic, 0.319ns route)
- (43.5% logic, 56.5% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_9 (SLICE_X110Y29.B3), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.575ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_9 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.575ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 to cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X111Y28.DQ Tcko 0.198 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- SLICE_X110Y29.B3 net (fanout=1) 0.256 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>
- SLICE_X110Y29.CLK Tah (-Th) -0.121 cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>_rt
- cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_9
- ------------------------------------------------- ---------------------------
- Total 0.575ns (0.319ns logic, 0.256ns route)
- (55.5% logic, 44.5% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_0 (SLICE_X110Y29.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.578ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_0 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.578ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_0 to cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X109Y27.BQ Tcko 0.198 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<4>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_0
- SLICE_X110Y29.AX net (fanout=1) 0.332 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<0>
- SLICE_X110Y29.CLK Tckdi (-Th) -0.048 cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/U_Sync2/sync0_0
- ------------------------------------------------- ---------------------------
- Total 0.578ns (0.246ns logic, 0.332ns route)
- (42.6% logic, 57.4% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_sys_sync_reg = MAXDELAY FROM TIMEGRP "sys_clk" TO TIMEGRP
-"sys_sync_reg" 16 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 103 paths analyzed, 49 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 9.312ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int (SLICE_X106Y28.SR), 3 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 6.688ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int (FF)
- Requirement: 16.000ns
- Data Path Delay: 9.312ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B6 net (fanout=12) 1.149 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X106Y28.SR net (fanout=16) 0.912 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X106Y28.CLK Trck 0.195 cmp_mt_profip_translator/mosi_fifo_wr_full
- cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- ------------------------------------------------- ---------------------------
- Total 9.312ns (1.104ns logic, 8.208ns route)
- (11.9% logic, 88.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.214ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.786ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y103.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B4 net (fanout=1) 0.679 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X106Y28.SR net (fanout=16) 0.912 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X106Y28.CLK Trck 0.195 cmp_mt_profip_translator/mosi_fifo_wr_full
- cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- ------------------------------------------------- ---------------------------
- Total 8.786ns (1.048ns logic, 7.738ns route)
- (11.9% logic, 88.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.477ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.523ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y102.AMUX Tshcko 0.461 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<4>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B5 net (fanout=1) 0.346 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X106Y28.SR net (fanout=16) 0.912 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X106Y28.CLK Trck 0.195 cmp_mt_profip_translator/mosi_fifo_wr_full
- cmp_mt_profip_translator/cmp_mosi_async_fifo/full_int
- ------------------------------------------------- ---------------------------
- Total 8.523ns (1.118ns logic, 7.405ns route)
- (13.1% logic, 86.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 (SLICE_X111Y28.SR), 3 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 6.933ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 (FF)
- Requirement: 16.000ns
- Data Path Delay: 9.067ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B6 net (fanout=12) 1.149 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X111Y28.SR net (fanout=16) 0.549 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X111Y28.CLK Trck 0.313 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- ------------------------------------------------- ---------------------------
- Total 9.067ns (1.222ns logic, 7.845ns route)
- (13.5% logic, 86.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.459ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.541ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y103.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B4 net (fanout=1) 0.679 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X111Y28.SR net (fanout=16) 0.549 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X111Y28.CLK Trck 0.313 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- ------------------------------------------------- ---------------------------
- Total 8.541ns (1.166ns logic, 7.375ns route)
- (13.7% logic, 86.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.722ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9 (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.278ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y102.AMUX Tshcko 0.461 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<4>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B5 net (fanout=1) 0.346 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X111Y28.SR net (fanout=16) 0.549 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X111Y28.CLK Trck 0.313 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray<9>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_gray_9
- ------------------------------------------------- ---------------------------
- Total 8.278ns (1.236ns logic, 7.042ns route)
- (14.9% logic, 85.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10 (SLICE_X112Y27.SR), 3 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 6.985ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10 (FF)
- Requirement: 16.000ns
- Data Path Delay: 9.015ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X64Y94.AQ Tcko 0.447 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B6 net (fanout=12) 1.149 inst_svec_base/inst_svec_base_regs/csr_resets_appl_reg
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X112Y27.SR net (fanout=16) 0.593 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X112Y27.CLK Trck 0.217 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin<10>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- ------------------------------------------------- ---------------------------
- Total 9.015ns (1.126ns logic, 7.889ns route)
- (12.5% logic, 87.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.511ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10 (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.489ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y103.AQ Tcko 0.391 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B4 net (fanout=1) 0.679 inst_svec_base/inst_svec_base_regs/csr_resets_global_reg_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X112Y27.SR net (fanout=16) 0.593 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X112Y27.CLK Trck 0.217 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin<10>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- ------------------------------------------------- ---------------------------
- Total 8.489ns (1.070ns logic, 7.419ns route)
- (12.6% logic, 87.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.774ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 (FF)
- Destination: cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10 (FF)
- Requirement: 16.000ns
- Data Path Delay: 8.226ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1 to cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y102.AMUX Tshcko 0.461 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0<4>
- inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B5 net (fanout=1) 0.346 inst_svec_base/gen_no_wr.cmp_rstlogic_reset/rst_chains_0_0_1
- SLICE_X72Y103.B Tilo 0.203 local_reset_n
- inst_svec_base/rst_sys_62m5_n_o1
- SLICE_X109Y26.C6 net (fanout=286) 6.147 local_reset_n
- SLICE_X109Y26.C Tilo 0.259 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv1_INV_0
- SLICE_X112Y27.SR net (fanout=16) 0.593 cmp_mt_profip_translator/cmp_mosi_async_fifo/rst_n_i_inv
- SLICE_X112Y27.CLK Trck 0.217 cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin<10>
- cmp_mt_profip_translator/cmp_mosi_async_fifo/wcb_bin_10
- ------------------------------------------------- ---------------------------
- Total 8.226ns (1.140ns logic, 7.086ns route)
- (13.9% logic, 86.1% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_sys_sync_reg = MAXDELAY FROM TIMEGRP "sys_clk" TO TIMEGRP "sys_sync_reg" 16 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_4 (SLICE_X102Y148.A4), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.656ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_4 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_4 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.656ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_4 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X103Y154.CQ Tcko 0.198 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<6>
- cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_4
- SLICE_X102Y148.A4 net (fanout=1) 0.337 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<4>
- SLICE_X102Y148.CLK Tah (-Th) -0.121 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<4>_rt
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_4
- ------------------------------------------------- ---------------------------
- Total 0.656ns (0.319ns logic, 0.337ns route)
- (48.6% logic, 51.4% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_5 (SLICE_X102Y148.B5), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.670ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_5 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_5 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.670ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_5 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X103Y154.DMUX Tshcko 0.244 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<6>
- cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_5
- SLICE_X102Y148.B5 net (fanout=1) 0.305 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<5>
- SLICE_X102Y148.CLK Tah (-Th) -0.121 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<5>_rt
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_5
- ------------------------------------------------- ---------------------------
- Total 0.670ns (0.365ns logic, 0.305ns route)
- (54.5% logic, 45.5% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_0 (SLICE_X102Y148.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.671ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_0 (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.671ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_0 to cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X103Y154.AQ Tcko 0.198 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<6>
- cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray_0
- SLICE_X102Y148.AX net (fanout=1) 0.425 cmp_mt_profip_translator/cmp_miso_async_fifo/wcb_gray<0>
- SLICE_X102Y148.CLK Tckdi (-Th) -0.048 cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0<3>
- cmp_mt_profip_translator/cmp_miso_async_fifo/U_Sync2/sync0_0
- ------------------------------------------------- ---------------------------
- Total 0.671ns (0.246ns logic, 0.425ns route)
- (36.7% logic, 63.3% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_inst_svec_base_gen_no_wr_pllout_clk_125m = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_125m" TS_clk_125m_pllref HIGH
- 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 3467 paths analyzed, 988 endpoints analyzed, 145 failing endpoints
- 145 timing errors detected. (145 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 13.191ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (OLOGIC_X35Y99.OCE), 9 paths
---------------------------------------------------------------------------------
-Slack (setup path): -5.191ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 12.790ns (Levels of Logic = 1)
- Clock Path Skew: -0.311ns (1.239 - 1.550)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- ILOGIC_X11Y1.Q4 Tickq 0.992 fp_gpio2_b_OBUF
- cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X73Y49.D4 net (fanout=58) 5.065 cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X35Y99.OCE net (fanout=16) 5.726 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X35Y99.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 12.790ns (1.999ns logic, 10.791ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -3.387ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 11.811ns (Levels of Logic = 2)
- Clock Path Skew: 0.514ns (1.239 - 0.725)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X100Y41.AMUX Tshcko 0.488 cmp_mt_profip_translator/cmp_spi_slave/GND_25_o_GND_25_o_sub_9_OUT<3>_FRB
- cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0
- SLICE_X101Y66.C2 net (fanout=3) 1.966 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<0>
- SLICE_X101Y66.C Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D5 net (fanout=1) 2.365 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X35Y99.OCE net (fanout=16) 5.726 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X35Y99.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 11.811ns (1.754ns logic, 10.057ns route)
- (14.9% logic, 85.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -2.843ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 11.186ns (Levels of Logic = 2)
- Clock Path Skew: 0.433ns (1.239 - 0.806)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X101Y76.AQ Tcko 0.391 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<3>
- cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3
- SLICE_X101Y66.C1 net (fanout=3) 1.438 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<3>
- SLICE_X101Y66.C Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D5 net (fanout=1) 2.365 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X35Y99.OCE net (fanout=16) 5.726 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X35Y99.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 11.186ns (1.657ns logic, 9.529ns route)
- (14.8% logic, 85.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (OLOGIC_X35Y99.D1), 4 paths
---------------------------------------------------------------------------------
-Slack (setup path): -4.673ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 12.272ns (Levels of Logic = 1)
- Clock Path Skew: -0.311ns (1.239 - 1.550)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- ILOGIC_X11Y1.Q4 Tickq 0.992 fp_gpio2_b_OBUF
- cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X62Y34.D5 net (fanout=58) 3.775 cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X62Y34.D Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- cmp_mt_profip_translator/cmp_spi_slave/Mmux_data_reg_i[31]_data_reg_i[30]_mux_2_OUT251
- OLOGIC_X35Y99.D1 net (fanout=2) 6.497 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- OLOGIC_X35Y99.CLK0 Todck 0.803 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 12.272ns (2.000ns logic, 10.272ns route)
- (16.3% logic, 83.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -0.868ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 9.285ns (Levels of Logic = 1)
- Clock Path Skew: 0.507ns (1.239 - 0.732)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y48.DQ Tcko 0.391 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1
- SLICE_X62Y34.D6 net (fanout=50) 1.389 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- SLICE_X62Y34.D Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- cmp_mt_profip_translator/cmp_spi_slave/Mmux_data_reg_i[31]_data_reg_i[30]_mux_2_OUT251
- OLOGIC_X35Y99.D1 net (fanout=2) 6.497 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- OLOGIC_X35Y99.CLK0 Todck 0.803 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 9.285ns (1.399ns logic, 7.886ns route)
- (15.1% logic, 84.9% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -0.763ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_30 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1 (FF)
- Requirement: 8.000ns
- Data Path Delay: 9.178ns (Levels of Logic = 1)
- Clock Path Skew: 0.505ns (1.239 - 0.734)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_30 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y44.AQ Tcko 0.391 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i<30>
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_30
- SLICE_X62Y34.D3 net (fanout=1) 1.282 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i<30>
- SLICE_X62Y34.D Tilo 0.205 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- cmp_mt_profip_translator/cmp_spi_slave/Mmux_data_reg_i[31]_data_reg_i[30]_mux_2_OUT251
- OLOGIC_X35Y99.D1 net (fanout=2) 6.497 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i[31]_data_reg_i[30]_mux_2_OUT<31>
- OLOGIC_X35Y99.CLK0 Todck 0.803 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31_1
- ------------------------------------------------- ---------------------------
- Total 9.178ns (1.399ns logic, 7.779ns route)
- (15.2% logic, 84.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31 (OLOGIC_X11Y0.OCE), 9 paths
---------------------------------------------------------------------------------
-Slack (setup path): -4.223ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31 (FF)
- Requirement: 8.000ns
- Data Path Delay: 12.051ns (Levels of Logic = 1)
- Clock Path Skew: -0.082ns (0.565 - 0.647)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- ILOGIC_X11Y1.Q4 Tickq 0.992 fp_gpio2_b_OBUF
- cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X73Y49.D4 net (fanout=58) 5.065 cmp_mt_profip_translator/cmp_spi_slave/spi_clk_dl
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X11Y0.OCE net (fanout=16) 4.987 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X11Y0.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i<31>
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- ------------------------------------------------- ---------------------------
- Total 12.051ns (1.999ns logic, 10.052ns route)
- (16.6% logic, 83.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -2.435ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31 (FF)
- Requirement: 8.000ns
- Data Path Delay: 11.072ns (Levels of Logic = 2)
- Clock Path Skew: 0.727ns (1.358 - 0.631)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X100Y41.AMUX Tshcko 0.488 cmp_mt_profip_translator/cmp_spi_slave/GND_25_o_GND_25_o_sub_9_OUT<3>_FRB
- cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_0
- SLICE_X101Y66.C2 net (fanout=3) 1.966 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<0>
- SLICE_X101Y66.C Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D5 net (fanout=1) 2.365 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X11Y0.OCE net (fanout=16) 4.987 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X11Y0.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i<31>
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- ------------------------------------------------- ---------------------------
- Total 11.072ns (1.754ns logic, 9.318ns route)
- (15.8% logic, 84.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): -1.891ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31 (FF)
- Requirement: 8.000ns
- Data Path Delay: 10.447ns (Levels of Logic = 2)
- Clock Path Skew: 0.646ns (1.358 - 0.712)
- Source Clock: inst_svec_base/clk_ref_125m rising at 0.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.090ns
-
- Clock Uncertainty: 0.090ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.164ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X101Y76.AQ Tcko 0.391 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<3>
- cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt_3
- SLICE_X101Y66.C1 net (fanout=3) 1.438 cmp_mt_profip_translator/cmp_spi_slave/mosi_cnt<3>
- SLICE_X101Y66.C Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D5 net (fanout=1) 2.365 cmp_mt_profip_translator/cmp_spi_slave/s_ready<32>1_REPLICA_0
- SLICE_X73Y49.D Tilo 0.259 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv1
- OLOGIC_X11Y0.OCE net (fanout=16) 4.987 cmp_mt_profip_translator/cmp_spi_slave/_n0058_inv
- OLOGIC_X11Y0.CLK0 Tooceck 0.748 cmp_mt_profip_translator/cmp_spi_slave/data_reg_i<31>
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_i_31
- ------------------------------------------------- ---------------------------
- Total 10.447ns (1.657ns logic, 8.790ns route)
- (15.9% logic, 84.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_inst_svec_base_gen_no_wr_pllout_clk_125m = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_125m" TS_clk_125m_pllref HIGH
- 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1 (SLICE_X71Y48.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.393ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.393ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0 to cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y48.CQ Tcko 0.198 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- SLICE_X71Y48.DX net (fanout=1) 0.136 cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync0
- SLICE_X71Y48.CLK Tckdi (-Th) -0.059 cmp_mt_profip_translator/cmp_spi_slave/spi_cs_n_sync
- cmp_mt_profip_translator/cmp_spi_slave/cmp_spi_cs_sync/sync1
- ------------------------------------------------- ---------------------------
- Total 0.393ns (0.257ns logic, 0.136ns route)
- (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin_10 (SLICE_X103Y147.CX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.401ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_miso_async_fifo/Result<10>1_FRB (FF)
- Destination: cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin_10 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.403ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.041 - 0.039)
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_miso_async_fifo/Result<10>1_FRB to cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin_10
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X102Y147.CQ Tcko 0.200 cmp_mt_profip_translator/cmp_miso_async_fifo/Result<10>1_FRB
- cmp_mt_profip_translator/cmp_miso_async_fifo/Result<10>1_FRB
- SLICE_X103Y147.CX net (fanout=2) 0.144 cmp_mt_profip_translator/cmp_miso_async_fifo/Result<10>1_FRB
- SLICE_X103Y147.CLK Tckdi (-Th) -0.059 cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin<10>
- cmp_mt_profip_translator/cmp_miso_async_fifo/rcb_bin_10
- ------------------------------------------------- ---------------------------
- Total 0.403ns (0.259ns logic, 0.144ns route)
- (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_4 (SLICE_X77Y40.B5), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.428ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_3 (FF)
- Destination: cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_4 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.428ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Destination Clock: inst_svec_base/clk_ref_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_3 to cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X77Y40.BQ Tcko 0.198 cmp_mt_profip_translator/cmp_spi_slave/data_reg_o<8>
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_3
- SLICE_X77Y40.B5 net (fanout=2) 0.075 cmp_mt_profip_translator/cmp_spi_slave/data_reg_o<3>
- SLICE_X77Y40.CLK Tah (-Th) -0.155 cmp_mt_profip_translator/cmp_spi_slave/data_reg_o<8>
- cmp_mt_profip_translator/cmp_spi_slave/Mmux_data_reg_o[31]_data_reg_o[30]_mux_5_OUT271
- cmp_mt_profip_translator/cmp_spi_slave/data_reg_o_4
- ------------------------------------------------- ---------------------------
- Total 0.428ns (0.353ns logic, 0.075ns route)
- (82.5% logic, 17.5% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_inst_svec_base_gen_no_wr_pllout_clk_125m = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_125m" TS_clk_125m_pllref HIGH
- 50%;
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem1/CLKA
- Logical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem1/CLKA
- Location pin: RAMB16_X4Y12.CLKA
- Clock network: inst_svec_base/clk_ref_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem2/CLKA
- Logical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem2/CLKA
- Location pin: RAMB16_X5Y12.CLKA
- Clock network: inst_svec_base/clk_ref_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_miso_async_fifo/Mram_mem1/CLKB
- Logical resource: cmp_mt_profip_translator/cmp_miso_async_fifo/Mram_mem1/CLKB
- Location pin: RAMB16_X4Y76.CLKB
- Clock network: inst_svec_base/clk_ref_125m
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_inst_svec_base_gen_no_wr_pllout_clk_62m5 = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_62m5" TS_clk_125m_pllref / 0.5
- HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 25428434 paths analyzed, 108352 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 15.773ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05 (RAMB16_X0Y90.ADDRA6), 10 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.227ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_split/master_o[0]_adr_8 (FF)
- Destination: cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.675ns (Levels of Logic = 2)
- Clock Path Skew: 0.003ns (1.035 - 1.032)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_split/master_o[0]_adr_8 to cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y88.DQ Tcko 0.391 inst_svec_base/inst_split/master_o[0]_adr<8>
- inst_svec_base/inst_split/master_o[0]_adr_8
- SLICE_X66Y80.B2 net (fanout=38) 1.694 inst_svec_base/inst_split/master_o[0]_adr<8>
- SLICE_X66Y80.BMUX Tilo 0.251 cnx_master_out[1]_adr<5>
- cmp_mt_intercon/crossbar/master_oe[1]_adr<8>1
- SLICE_X61Y94.B5 net (fanout=29) 1.957 cnx_master_out[1]_adr<8>
- SLICE_X61Y94.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/csr_regs/mbx_data<24>
- cmp_mock_turtle_urv/U_Shared_Interconnect/master_oe[0]_adr<8>
- RAMB16_X0Y90.ADDRA6 net (fanout=32) 10.773 cmp_mock_turtle_urv/si_master_out[0]_adr<8>
- RAMB16_X0Y90.CLKA Trcck_ADDRA 0.350 cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- ------------------------------------------------- ---------------------------
- Total 15.675ns (1.251ns logic, 14.424ns route)
- (8.0% logic, 92.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.858ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_8 (FF)
- Destination: cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.278ns (Levels of Logic = 2)
- Clock Path Skew: 0.237ns (0.946 - 0.709)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_8 to cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X73Y118.DMUX Tshcko 0.461 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mmux_ab_i[16]_PWR_74_o_mux_47_OUT141_8
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_8
- SLICE_X61Y94.A2 net (fanout=7) 2.836 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr<8>
- SLICE_X61Y94.AMUX Tilo 0.313 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/csr_regs/mbx_data<24>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Local_Interconnect/master_oe[4]_adr<8>1
- SLICE_X61Y94.B6 net (fanout=1) 0.286 cmp_mock_turtle_urv/si_slave_in[1]_adr<8>
- SLICE_X61Y94.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/csr_regs/mbx_data<24>
- cmp_mock_turtle_urv/U_Shared_Interconnect/master_oe[0]_adr<8>
- RAMB16_X0Y90.ADDRA6 net (fanout=32) 10.773 cmp_mock_turtle_urv/si_master_out[0]_adr<8>
- RAMB16_X0Y90.CLKA Trcck_ADDRA 0.350 cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- ------------------------------------------------- ---------------------------
- Total 15.278ns (1.383ns logic, 13.895ns route)
- (9.1% logic, 90.9% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.964ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_intercon/crossbar/matrix_old_0_1_2 (FF)
- Destination: cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 14.931ns (Levels of Logic = 2)
- Clock Path Skew: -0.004ns (1.035 - 1.039)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_intercon/crossbar/matrix_old_0_1_2 to cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X60Y84.BQ Tcko 0.447 cmp_mt_intercon/crossbar/matrix_old_0_1_2
- cmp_mt_intercon/crossbar/matrix_old_0_1_2
- SLICE_X66Y80.B4 net (fanout=2) 0.894 cmp_mt_intercon/crossbar/matrix_old_0_1_2
- SLICE_X66Y80.BMUX Tilo 0.251 cnx_master_out[1]_adr<5>
- cmp_mt_intercon/crossbar/master_oe[1]_adr<8>1
- SLICE_X61Y94.B5 net (fanout=29) 1.957 cnx_master_out[1]_adr<8>
- SLICE_X61Y94.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/csr_regs/mbx_data<24>
- cmp_mock_turtle_urv/U_Shared_Interconnect/master_oe[0]_adr<8>
- RAMB16_X0Y90.ADDRA6 net (fanout=32) 10.773 cmp_mock_turtle_urv/si_master_out[0]_adr<8>
- RAMB16_X0Y90.CLKA Trcck_ADDRA 0.350 cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- cmp_mock_turtle_urv/U_Shared_Mem/Mram_mem05
- ------------------------------------------------- ---------------------------
- Total 14.931ns (1.307ns logic, 13.624ns route)
- (8.8% logic, 91.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148 (RAMB16_X5Y44.WEB3), 7780 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.252ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.664ns (Levels of Logic = 7)
- Clock Path Skew: 0.017ns (0.828 - 0.811)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y124.AQ Tcko 0.391 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0
- SLICE_X71Y124.B4 net (fanout=2) 1.784 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<0>
- SLICE_X71Y124.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0_1
- SLICE_X71Y124.C4 net (fanout=3) 0.309 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0
- SLICE_X71Y124.C Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_1
- SLICE_X70Y119.B4 net (fanout=1) 0.699 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x2
- SLICE_X70Y119.BMUX Topbb 0.368 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/w_dm_addr_o<1>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_lut<1>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<3>
- SLICE_X75Y119.B2 net (fanout=31) 0.714 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_addr<1>
- SLICE_X75Y119.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/exception_unit/csr_mcause_interrupt_BRB2
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/unaligned_addr_d_opcode_i[4]_AND_3689_o1
- SLICE_X75Y124.A5 net (fanout=9) 0.608 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/unaligned_addr_d_opcode_i[4]_AND_3689_o
- SLICE_X75Y124.A Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/w_valid_o
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Mmux_x_exception11
- SLICE_X62Y115.B2 net (fanout=14) 1.690 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/x_exception
- SLICE_X62Y115.B Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write1
- SLICE_X62Y115.A5 net (fanout=13) 0.201 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- SLICE_X62Y115.A Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.WEB3 net (fanout=32) 7.154 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.CLKB Trcck_WEB 0.300 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- ------------------------------------------------- ---------------------------
- Total 15.664ns (2.505ns logic, 13.159ns route)
- (16.0% logic, 84.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.259ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.657ns (Levels of Logic = 10)
- Clock Path Skew: 0.017ns (0.828 - 0.811)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y124.AQ Tcko 0.391 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0
- SLICE_X71Y124.B4 net (fanout=2) 1.784 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<0>
- SLICE_X71Y124.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0_1
- SLICE_X71Y122.A5 net (fanout=3) 0.388 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0
- SLICE_X71Y122.A Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/w_rd_o_3_1
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_2
- SLICE_X70Y122.A1 net (fanout=19) 1.062 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x3
- SLICE_X70Y122.COUT Topcya 0.395 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_lut<12>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- SLICE_X70Y123.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- SLICE_X70Y123.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_19_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<19>
- SLICE_X70Y124.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<19>
- SLICE_X70Y124.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_23_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<23>
- SLICE_X70Y125.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<23>
- SLICE_X70Y125.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_27_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<27>
- SLICE_X70Y126.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<27>
- SLICE_X70Y126.AMUX Tcina 0.177 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_31_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_xor<31>
- SLICE_X71Y128.B3 net (fanout=3) 0.697 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_addr<28>
- SLICE_X71Y128.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/exception_unit/csr_mcause_interrupt_BRB4
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_is_wishbone_INV_500_o<31>3_SW0
- SLICE_X62Y115.B3 net (fanout=2) 1.681 cmp_mock_turtle_urv/N1267
- SLICE_X62Y115.B Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write1
- SLICE_X62Y115.A5 net (fanout=13) 0.201 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- SLICE_X62Y115.A Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.WEB3 net (fanout=32) 7.154 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.CLKB Trcck_WEB 0.300 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- ------------------------------------------------- ---------------------------
- Total 15.657ns (2.678ns logic, 12.979ns route)
- (17.1% logic, 82.9% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.320ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148 (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.596ns (Levels of Logic = 10)
- Clock Path Skew: 0.017ns (0.828 - 0.811)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y124.AQ Tcko 0.391 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1_0
- SLICE_X71Y124.B4 net (fanout=2) 1.784 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<0>
- SLICE_X71Y124.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/decode/x_rs1<3>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0_1
- SLICE_X71Y122.A5 net (fanout=3) 0.388 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_SW0
- SLICE_X71Y122.A Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/w_rd_o_3_1
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x_2
- SLICE_X70Y122.A1 net (fanout=19) 1.062 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/regfile/rs1_bypass_x3
- SLICE_X70Y122.COUT Topcya 0.395 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_lut<12>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- SLICE_X70Y123.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<15>
- SLICE_X70Y123.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_19_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<19>
- SLICE_X70Y124.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<19>
- SLICE_X70Y124.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_23_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<23>
- SLICE_X70Y125.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<23>
- SLICE_X70Y125.COUT Tbyp 0.076 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_27_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<27>
- SLICE_X70Y126.CIN net (fanout=1) 0.003 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_cy<27>
- SLICE_X70Y126.BMUX Tcinb 0.260 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dwb_out_adr_31_BRB3
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/Madd_dm_addr_xor<31>
- SLICE_X71Y128.B4 net (fanout=3) 0.553 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_addr<29>
- SLICE_X71Y128.B Tilo 0.259 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_cpu_core/execute/exception_unit/csr_mcause_interrupt_BRB4
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_is_wishbone_INV_500_o<31>3_SW0
- SLICE_X62Y115.B3 net (fanout=2) 1.681 cmp_mock_turtle_urv/N1267
- SLICE_X62Y115.B Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write1
- SLICE_X62Y115.A5 net (fanout=13) 0.201 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- SLICE_X62Y115.A Tilo 0.205 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/dm_data_write
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.WEB3 net (fanout=32) 7.154 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/write_ctrl23
- RAMB16_X5Y44.CLKB Trcck_WEB 0.300 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram148
- ------------------------------------------------- ---------------------------
- Total 15.596ns (2.761ns logic, 12.835ns route)
- (17.7% logic, 82.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH (SLICE_X120Y56.DX), 3 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.270ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mock_turtle_urv/U_Host_Access_CB/matrix_old_0_0 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.346ns (Levels of Logic = 1)
- Clock Path Skew: -0.283ns (0.603 - 0.886)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mock_turtle_urv/U_Host_Access_CB/matrix_old_0_0 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X61Y72.DQ Tcko 0.391 cmp_mock_turtle_urv/U_Host_Access_CB/matrix_old_0<0>
- cmp_mock_turtle_urv/U_Host_Access_CB/matrix_old_0_0
- SLICE_X27Y102.B4 net (fanout=441) 4.037 cmp_mock_turtle_urv/U_Host_Access_CB/matrix_old_0<0>
- SLICE_X27Y102.BMUX Tilo 0.313 cmp_mock_turtle_urv/gen_cpus[1].U_CPU_Block/U_Host_MQ/gen_slots[0].U_In_SlotX/mem_rdata_in<6>
- cmp_mock_turtle_urv/U_Host_Access_CB/master_oe[0]_dat<5>1
- SLICE_X120Y56.DX net (fanout=42) 10.020 cmp_mock_turtle_urv/hac_master_out[0]_dat<5>
- SLICE_X120Y56.CLK Tds 0.585 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/N52
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- ------------------------------------------------- ---------------------------
- Total 15.346ns (1.289ns logic, 14.057ns route)
- (8.4% logic, 91.6% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.337ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_mt_intercon/crossbar/matrix_old_0_1 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH (RAM)
- Requirement: 16.000ns
- Data Path Delay: 15.222ns (Levels of Logic = 2)
- Clock Path Skew: -0.340ns (0.603 - 0.943)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_mt_intercon/crossbar/matrix_old_0_1 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y85.AQ Tcko 0.391 cmp_mt_intercon/crossbar/matrix_old_0<1>
- cmp_mt_intercon/crossbar/matrix_old_0_1
- SLICE_X50Y93.C1 net (fanout=36) 1.382 cmp_mt_intercon/crossbar/matrix_old_0<1>
- SLICE_X50Y93.CMUX Tilo 0.251 inst_svec_base/inst_split/master_o[0]_dat<7>
- cmp_mt_intercon/crossbar/master_oe[1]_dat<5>1
- SLICE_X27Y102.B1 net (fanout=18) 2.280 cnx_master_out[1]_dat<5>
- SLICE_X27Y102.BMUX Tilo 0.313 cmp_mock_turtle_urv/gen_cpus[1].U_CPU_Block/U_Host_MQ/gen_slots[0].U_In_SlotX/mem_rdata_in<6>
- cmp_mock_turtle_urv/U_Host_Access_CB/master_oe[0]_dat<5>1
- SLICE_X120Y56.DX net (fanout=42) 10.020 cmp_mock_turtle_urv/hac_master_out[0]_dat<5>
- SLICE_X120Y56.CLK Tds 0.585 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/N52
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- ------------------------------------------------- ---------------------------
- Total 15.222ns (1.540ns logic, 13.682ns route)
- (10.1% logic, 89.9% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.014ns (requirement - (data path - clock path skew + uncertainty))
- Source: inst_svec_base/inst_split/master_o[0]_dat_5 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH (RAM)
- Requirement: 16.000ns
- Data Path Delay: 14.539ns (Levels of Logic = 2)
- Clock Path Skew: -0.346ns (0.603 - 0.949)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 0.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.101ns
-
- Clock Uncertainty: 0.101ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.188ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: inst_svec_base/inst_split/master_o[0]_dat_5 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X50Y93.BQ Tcko 0.408 inst_svec_base/inst_split/master_o[0]_dat<7>
- inst_svec_base/inst_split/master_o[0]_dat_5
- SLICE_X50Y93.C4 net (fanout=3) 0.682 inst_svec_base/inst_split/master_o[0]_dat<5>
- SLICE_X50Y93.CMUX Tilo 0.251 inst_svec_base/inst_split/master_o[0]_dat<7>
- cmp_mt_intercon/crossbar/master_oe[1]_dat<5>1
- SLICE_X27Y102.B1 net (fanout=18) 2.280 cnx_master_out[1]_dat<5>
- SLICE_X27Y102.BMUX Tilo 0.313 cmp_mock_turtle_urv/gen_cpus[1].U_CPU_Block/U_Host_MQ/gen_slots[0].U_In_SlotX/mem_rdata_in<6>
- cmp_mock_turtle_urv/U_Host_Access_CB/master_oe[0]_dat<5>1
- SLICE_X120Y56.DX net (fanout=42) 10.020 cmp_mock_turtle_urv/hac_master_out[0]_dat<5>
- SLICE_X120Y56.CLK Tds 0.585 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/N52
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_Host_MQ/gen_slots[4].U_In_SlotX/Mram_mem024/DP.HIGH
- ------------------------------------------------- ---------------------------
- Total 14.539ns (1.557ns logic, 12.982ns route)
- (10.7% logic, 89.3% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_inst_svec_base_gen_no_wr_pllout_clk_62m5 = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_62m5" TS_clk_125m_pllref / 0.5
- HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table25/DP (SLICE_X18Y77.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.303ns (requirement - (clock path skew + uncertainty - data path))
- Source: inst_svec_base/inst_svec_base_regs/wr_dat_d0_24 (FF)
- Destination: inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table25/DP (RAM)
- Requirement: 0.000ns
- Data Path Delay: 0.306ns (Levels of Logic = 0)
- Clock Path Skew: 0.003ns (0.081 - 0.078)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/wr_dat_d0_24 to inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table25/DP
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X20Y77.AQ Tcko 0.200 inst_svec_base/inst_svec_base_regs/wr_dat_d0<27>
- inst_svec_base/inst_svec_base_regs/wr_dat_d0_24
- SLICE_X18Y77.AX net (fanout=2) 0.226 inst_svec_base/inst_svec_base_regs/wr_dat_d0<24>
- SLICE_X18Y77.CLK Tdh (-Th) 0.120 inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/vic_ivt_ram_data_towb<26>
- inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table25/DP
- ------------------------------------------------- ---------------------------
- Total 0.306ns (0.080ns logic, 0.226ns route)
- (26.1% logic, 73.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram21 (RAMB16_X3Y52.DIA0), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.346ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/ha_im_wdata_16 (FF)
- Destination: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram21 (RAM)
- Requirement: 0.000ns
- Data Path Delay: 0.352ns (Levels of Logic = 0)
- Clock Path Skew: 0.006ns (0.069 - 0.063)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/ha_im_wdata_16 to cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram21
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X84Y104.AQ Tcko 0.234 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/ha_im_wdata<19>
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/ha_im_wdata_16
- RAMB16_X3Y52.DIA0 net (fanout=6) 0.171 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/ha_im_wdata<16>
- RAMB16_X3Y52.CLKA Trckd_DIA (-Th) 0.053 cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram21
- cmp_mock_turtle_urv/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/U_iram/gen_splitram.U_RAM_SPLIT/Mram_ram21
- ------------------------------------------------- ---------------------------
- Total 0.352ns (0.181ns logic, 0.171ns route)
- (51.4% logic, 48.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table26/SP (SLICE_X18Y77.CI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.349ns (requirement - (clock path skew + uncertainty - data path))
- Source: inst_svec_base/inst_svec_base_regs/wr_dat_d0_25 (FF)
- Destination: inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table26/SP (RAM)
- Requirement: 0.000ns
- Data Path Delay: 0.352ns (Levels of Logic = 0)
- Clock Path Skew: 0.003ns (0.081 - 0.078)
- Source Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Destination Clock: inst_svec_base/clk_sys_62m5 rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: inst_svec_base/inst_svec_base_regs/wr_dat_d0_25 to inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table26/SP
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X20Y77.BQ Tcko 0.200 inst_svec_base/inst_svec_base_regs/wr_dat_d0<27>
- inst_svec_base/inst_svec_base_regs/wr_dat_d0_25
- SLICE_X18Y77.CI net (fanout=2) 0.128 inst_svec_base/inst_svec_base_regs/wr_dat_d0<25>
- SLICE_X18Y77.CLK Tdh (-Th) -0.024 inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/vic_ivt_ram_data_towb<26>
- inst_svec_base/gen_vic.i_vic/U_Wrapped_VIC/Mram_vector_table26/SP
- ------------------------------------------------- ---------------------------
- Total 0.352ns (0.224ns logic, 0.128ns route)
- (63.6% logic, 36.4% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_inst_svec_base_gen_no_wr_pllout_clk_62m5 = PERIOD TIMEGRP
- "inst_svec_base_gen_no_wr_pllout_clk_62m5" TS_clk_125m_pllref / 0.5
- HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem1/CLKB
- Logical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem1/CLKB
- Location pin: RAMB16_X4Y12.CLKB
- Clock network: inst_svec_base/clk_sys_62m5
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem2/CLKB
- Logical resource: cmp_mt_profip_translator/cmp_mosi_async_fifo/Mram_mem2/CLKB
- Location pin: RAMB16_X5Y12.CLKB
- Clock network: inst_svec_base/clk_sys_62m5
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_mt_profip_translator/cmp_miso_async_fifo/Mram_mem1/CLKA
- Logical resource: cmp_mt_profip_translator/cmp_miso_async_fifo/Mram_mem1/CLKA
- Location pin: RAMB16_X4Y76.CLKA
- Clock network: inst_svec_base/clk_sys_62m5
---------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Derived Constraints for TS_clk_125m_pllref
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_clk_125m_pllref | 8.000ns| 3.334ns| 13.191ns| 0| 145| 0| 25431901|
-| TS_inst_svec_base_gen_no_wr_pl| 8.000ns| 13.191ns| N/A| 145| 0| 3467| 0|
-| lout_clk_125m | | | | | | | |
-| TS_inst_svec_base_gen_no_wr_pl| 16.000ns| 15.773ns| N/A| 0| 0| 25428434| 0|
-| lout_clk_62m5 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-1 constraint not met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Clock to Setup on destination clock clk_125m_pllref_n_i
--------------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
-clk_125m_pllref_n_i| 15.773| | | |
-clk_125m_pllref_p_i| 15.773| | | |
--------------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock clk_125m_pllref_p_i
--------------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
-clk_125m_pllref_n_i| 15.773| | | |
-clk_125m_pllref_p_i| 15.773| | | |
--------------------+---------+---------+---------+---------+
-
-
-Timing summary:
----------------
-
-Timing errors: 145 Score: 154094 (Setup/Max: 154094, Hold: 0)
-
-Constraints cover 25432137 paths, 0 nets, and 126707 connections
-
-Design statistics:
- Minimum period: 15.773ns{1} (Maximum frequency: 63.399MHz)
- Maximum path delay from/to any node: 9.312ns
-
-
-------------------------------------Footnotes-----------------------------------
-1) The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Wed Feb 8 09:31:14 2023
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings
-
-Peak Memory Usage: 1072 MB
-
-
-
--
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