PS_POR_B asserted before the end of power sequence

According to Xilinx DS925 v1.23, page 16: "The PS_POR_B input must be asserted to GND during the power-on sequence", and for a minimum of 10us.

The PS_POR_B is driven by the PGOOD signal of two LDOs used to generate the DDR voltages. These LDOs are powered by 3V3 rail.

In SPEXI7U v1 this was ok because the 3V3 was a generated voltage, controlled by us.

In SPEXI7U v2 this is wrong because the 3V3 is coming from the backplane and the PS_POR_B will be asserted too early.