From f56fd45ca22f9464a2028a34350c1c258d5f28ec Mon Sep 17 00:00:00 2001
From: Karol Krizka <karol.krizka@cern.ch>
Date: Tue, 15 Oct 2019 20:02:51 +0000
Subject: [PATCH] Update endeavour_master to reset dataout only on send and
require a 0 before reading data. Add noise smoothing to endeavour.
---
.gitlab-ci.yml | 49 +
.../endeavour_axi_controller_1.0/bd/bd.tcl | 86 +
.../component.xml | 990 +
.../data/endeavour_axi_controller.mdd | 10 +
.../data/endeavour_axi_controller.tcl | 5 +
.../src/Makefile | 26 +
.../src/endeavour_axi_controller.c | 6 +
.../src/endeavour_axi_controller.h | 83 +
.../src/endeavour_axi_controller_selftest.c | 60 +
.../example_designs/bfm_design/design.tcl | 88 +
.../endeavour_axi_controller_v1_0_tb.sv | 197 +
.../debug_hw_design/design.tcl | 118 +
.../endeavour_axi_controller_v1_0_hw_test.tcl | 45 +
.../hdl/TopLevel_clk_wiz_0_0.v | 191 +
.../hdl/endeavour_axi_controller_v1_0.vhd | 321 +
.../endeavour_axi_controller_v1_0_S00_AXI.vhd | 565 +
.../hdl/endeavour_master.vhd | 289 +
.../hdl/smooth.vhd | 63 +
.../xgui/endeavour_axi_controller_v1_0.tcl | 62 +
.../.gitignore | 12 +
.../.petalinux/metadata | 2 +
.../config.project | 11 +
.../project-spec/attributes | 7 +
.../project-spec/configs/config | 257 +
.../project-spec/configs/rootfs_config | 3952 +
.../hw-description/TopLevel_wrapper.bit | Bin 0 -> 4045676 bytes
.../data/endeavour_axi_controller.mdd | 10 +
.../data/endeavour_axi_controller.tcl | 5 +
.../src/Makefile | 26 +
.../src/endeavour_axi_controller.c | 6 +
.../src/endeavour_axi_controller.h | 83 +
.../src/endeavour_axi_controller_selftest.c | 60 +
.../project-spec/hw-description/metadata | 1 +
.../project-spec/hw-description/ps7_init.c | 12086 ++
.../project-spec/hw-description/ps7_init.h | 139 +
.../project-spec/hw-description/ps7_init.html | 137152 +++++++++++++++
.../project-spec/hw-description/ps7_init.tcl | 814 +
.../hw-description/ps7_init_gpl.c | 12080 ++
.../hw-description/ps7_init_gpl.h | 131 +
.../project-spec/hw-description/system.hdf | Bin 0 -> 494210 bytes
.../project-spec/meta-user/COPYING.MIT | 17 +
.../project-spec/meta-user/README | 64 +
.../project-spec/meta-user/conf/layer.conf | 11 +
.../meta-user/conf/petalinuxbsp.conf | 19 +
.../recipes-apps/gpio-demo/files/Makefile | 14 +
.../recipes-apps/gpio-demo/files/gpio-demo.c | 355 +
.../recipes-apps/gpio-demo/gpio-demo.bb | 23 +
.../recipes-apps/peekpoke/files/Makefile | 19 +
.../recipes-apps/peekpoke/files/peek.c | 77 +
.../recipes-apps/peekpoke/files/poke.c | 77 +
.../recipes-apps/peekpoke/peekpoke.bb | 25 +
.../device-tree/device-tree.bbappend | 3 +
.../device-tree/files/system-user.dtsi | 7 +
.../recipes-bsp/u-boot/files/platform-top.h | 36 +
.../recipes-bsp/u-boot/u-boot-xlnx_%.bbappend | 3 +
.../images/petalinux-image-full.bbappend | 4 +
.../linux-xlnx/user_2019-09-21-06-14-00.cfg | 1 +
.../linux-xlnx/user_2019-09-21-16-08-00.cfg | 22 +
.../linux/linux-xlnx_%.bbappend | 6 +
... Z7020 MicroZed with MBCC-FMC-PCB-B_v2.xdc | 500 +-
.../constrs_1/new/pins.xdc | 6 +
.../sources_1/bd/ActiveBoard/ActiveBoard.bd | 11 -
.../sources_1/bd/ActiveBoard/ActiveBoard.bxml | 11 -
.../sources_1/bd/TopLevel/TopLevel.bd | 300 +-
.../sources_1/bd/TopLevel/TopLevel.bxml | 67 +-
.../sources_1/bd/TopLevel/TopLevel_ooc.xdc | 11 +
.../bd/TopLevel/hdl/TopLevel_wrapper.vhd | 16 +-
.../bd/TopLevel/hw_handoff/TopLevel.hwh | 3736 +
.../bd/TopLevel/hw_handoff/TopLevel_bd.tcl | 676 +
.../TopLevel_auto_pc_0/TopLevel_auto_pc_0.dcp | Bin 0 -> 270005 bytes
.../TopLevel_auto_pc_0.xci} | 20 +-
.../TopLevel_auto_pc_0.xml} | 731 +-
.../TopLevel_auto_pc_0_ooc.xdc | 57 +
.../TopLevel_auto_pc_0_sim_netlist.v | 12751 ++
.../TopLevel_auto_pc_0_sim_netlist.vhdl | 14945 ++
.../TopLevel_auto_pc_0_stub.v | 87 +
.../TopLevel_auto_pc_0_stub.vhdl | 88 +
.../sim/TopLevel_auto_pc_0.v | 354 +
.../synth/TopLevel_auto_pc_0.v | 356 +
.../TopLevel_axi_iic_0_0.dcp | Bin 0 -> 194207 bytes
.../TopLevel_axi_iic_0_0.xci | 18 +-
.../TopLevel_axi_iic_0_0.xml | 464 +-
.../TopLevel_axi_iic_0_0_board.xdc | 2 +
.../TopLevel_axi_iic_0_0_ooc.xdc | 50 +
.../TopLevel_axi_iic_0_0_sim_netlist.v | 10687 ++
.../TopLevel_axi_iic_0_0_sim_netlist.vhdl | 12192 ++
.../TopLevel_axi_iic_0_0_stub.v | 50 +
.../TopLevel_axi_iic_0_0_stub.vhdl | 56 +
.../sim/TopLevel_axi_iic_0_0.vhd | 218 +
.../synth/TopLevel_axi_iic_0_0.vhd | 224 +
.../TopLevel_endeavour_axi_contro_5_0.dcp | Bin 0 -> 130273 bytes
.../TopLevel_endeavour_axi_contro_5_0.xci | 111 +
.../TopLevel_endeavour_axi_contro_5_0.xml | 1361 +
...vel_endeavour_axi_contro_5_0_sim_netlist.v | 7860 +
..._endeavour_axi_contro_5_0_sim_netlist.vhdl | 10165 ++
.../TopLevel_endeavour_axi_contro_5_0_stub.v | 54 +
...opLevel_endeavour_axi_contro_5_0_stub.vhdl | 59 +
.../sim/TopLevel_endeavour_axi_contro_5_0.vhd | 197 +
.../TopLevel_endeavour_axi_contro_5_0.vhd | 201 +
.../TopLevel_processing_system7_0_0.dcp | Bin 0 -> 215703 bytes
.../TopLevel_processing_system7_0_0.xci} | 17 +-
.../TopLevel_processing_system7_0_0.xdc | 654 +
.../TopLevel_processing_system7_0_0.xml} | 2457 +-
...Level_processing_system7_0_0_sim_netlist.v | 5209 +
...el_processing_system7_0_0_sim_netlist.vhdl | 4611 +
.../TopLevel_processing_system7_0_0_stub.v | 100 +
.../TopLevel_processing_system7_0_0_stub.vhdl | 98 +
.../TopLevel_processing_system7_0_0.hwdef | Bin 0 -> 337998 bytes
...ocessing_system7_v5_5_processing_system7.v | 3935 +
.../ps7_init.c | 12086 ++
.../ps7_init.h | 139 +
.../ps7_init.html | 137152 +++++++++++++++
.../ps7_init.tcl | 814 +
.../ps7_init_gpl.c | 12080 ++
.../ps7_init_gpl.h | 131 +
.../ps7_parameters.xml | 6 +-
.../sim/TopLevel_processing_system7_0_0.sv | 1145 +
.../sim/TopLevel_processing_system7_0_0.v | 592 +
.../sim/libps7.dll | Bin 0 -> 471040 bytes
.../sim/libps7.so | Bin 0 -> 336328 bytes
.../sim/libremoteport.dll | Bin 0 -> 369152 bytes
.../sim/libremoteport.so | Bin 0 -> 63704 bytes
.../synth/TopLevel_processing_system7_0_0.v | 1007 +
.../TopLevel_ps7_0_axi_periph_0.xci} | 6 +-
.../TopLevel_ps7_0_axi_periph_0.xml} | 6 +-
.../TopLevel_rst_ps7_0_100M_0.dcp | Bin 0 -> 21187 bytes
.../TopLevel_rst_ps7_0_100M_0.xci | 3 +-
.../TopLevel_rst_ps7_0_100M_0.xdc | 49 +
.../TopLevel_rst_ps7_0_100M_0.xml | 301 +-
.../TopLevel_rst_ps7_0_100M_0_board.xdc | 2 +
.../TopLevel_rst_ps7_0_100M_0_ooc.xdc | 57 +
.../TopLevel_rst_ps7_0_100M_0_sim_netlist.v | 946 +
...TopLevel_rst_ps7_0_100M_0_sim_netlist.vhdl | 1105 +
.../TopLevel_rst_ps7_0_100M_0_stub.v | 31 +
.../TopLevel_rst_ps7_0_100M_0_stub.vhdl | 39 +
.../sim/TopLevel_rst_ps7_0_100M_0.vhd | 147 +
.../synth/TopLevel_rst_ps7_0_100M_0.vhd | 153 +
.../ip/TopLevel_xbar_0/TopLevel_xbar_0.dcp | Bin 0 -> 97988 bytes
.../ip/TopLevel_xbar_0/TopLevel_xbar_0.xci | 2878 +
.../ip/TopLevel_xbar_0/TopLevel_xbar_0.xml | 44232 +++++
.../TopLevel_xbar_0/TopLevel_xbar_0_ooc.xdc | 57 +
.../TopLevel_xbar_0_sim_netlist.v | 3541 +
.../TopLevel_xbar_0_sim_netlist.vhdl | 3963 +
.../ip/TopLevel_xbar_0/TopLevel_xbar_0_stub.v | 65 +
.../TopLevel_xbar_0/TopLevel_xbar_0_stub.vhdl | 69 +
.../ip/TopLevel_xbar_0/sim/TopLevel_xbar_0.v | 309 +
.../TopLevel_xbar_0/synth/TopLevel_xbar_0.v | 312 +
.../bd/TopLevel/sim/TopLevel.protoinst | 518 +
.../sources_1/bd/TopLevel/sim/TopLevel.vhd | 1693 +
.../bd/TopLevel/synth/TopLevel.hwdef | Bin 0 -> 34930 bytes
.../sources_1/bd/TopLevel/synth/TopLevel.vhd | 1693 +
.../sources_1/bd/TopLevel/ui/bd_4421cacf.ui | 48 +-
pbv3_mass_test_adapter_firmware.xpr | 98 +-
153 files changed, 492850 insertions(+), 1267 deletions(-)
create mode 100644 .gitlab-ci.yml
create mode 100644 ip_repo/endeavour_axi_controller_1.0/bd/bd.tcl
create mode 100644 ip_repo/endeavour_axi_controller_1.0/component.xml
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/Makefile
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
create mode 100644 ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
create mode 100644 ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/design.tcl
create mode 100644 ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/endeavour_axi_controller_v1_0_tb.sv
create mode 100644 ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/design.tcl
create mode 100644 ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/endeavour_axi_controller_v1_0_hw_test.tcl
create mode 100644 ip_repo/endeavour_axi_controller_1.0/hdl/TopLevel_clk_wiz_0_0.v
create mode 100644 ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0.vhd
create mode 100644 ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0_S00_AXI.vhd
create mode 100644 ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_master.vhd
create mode 100644 ip_repo/endeavour_axi_controller_1.0/hdl/smooth.vhd
create mode 100644 ip_repo/endeavour_axi_controller_1.0/xgui/endeavour_axi_controller_v1_0.tcl
create mode 100644 pbv3_mass_test_adapter_firmware.linux/.gitignore
create mode 100644 pbv3_mass_test_adapter_firmware.linux/.petalinux/metadata
create mode 100644 pbv3_mass_test_adapter_firmware.linux/config.project
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/attributes
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/configs/config
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/configs/rootfs_config
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/TopLevel_wrapper.bit
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/Makefile
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/metadata
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.h
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.html
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.tcl
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.h
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/system.hdf
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/COPYING.MIT
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/README
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/layer.conf
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/petalinuxbsp.conf
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-06-14-00.cfg
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-16-08-00.cfg
create mode 100644 pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
delete mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bd
delete mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bxml
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel_ooc.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel.hwh
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel_bd.tcl
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.dcp
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_auto_pc_2/TopLevel_auto_pc_2.xci => TopLevel_auto_pc_0/TopLevel_auto_pc_0.xci} (97%)
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_auto_pc_2/TopLevel_auto_pc_2.xml => TopLevel_auto_pc_0/TopLevel_auto_pc_0.xml} (82%)
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_ooc.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/sim/TopLevel_auto_pc_0.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/synth/TopLevel_auto_pc_0.v
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.dcp
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_board.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_ooc.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/sim/TopLevel_axi_iic_0_0.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/synth/TopLevel_axi_iic_0_0.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.dcp
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xci
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xml
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/sim/TopLevel_endeavour_axi_contro_5_0.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/synth/TopLevel_endeavour_axi_contro_5_0.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.dcp
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xci => TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xci} (99%)
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xdc
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xml => TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xml} (93%)
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/hdl/verilog/TopLevel_processing_system7_0_0.hwdef
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init.c
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init.h
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init.html
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init.tcl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init_gpl.c
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/ps7_init_gpl.h
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_processing_system7_0_1 => TopLevel_processing_system7_0_0}/ps7_parameters.xml (99%)
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/TopLevel_processing_system7_0_0.sv
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/TopLevel_processing_system7_0_0.v
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/libps7.dll
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/libps7.so
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/libremoteport.dll
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/sim/libremoteport.so
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/synth/TopLevel_processing_system7_0_0.v
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_ps7_0_axi_periph_1/TopLevel_ps7_0_axi_periph_1.xci => TopLevel_ps7_0_axi_periph_0/TopLevel_ps7_0_axi_periph_0.xci} (99%)
rename pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/{TopLevel_ps7_0_axi_periph_1/TopLevel_ps7_0_axi_periph_1.xml => TopLevel_ps7_0_axi_periph_0/TopLevel_ps7_0_axi_periph_0.xml} (99%)
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0.dcp
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_board.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_ooc.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/TopLevel_rst_ps7_0_100M_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/sim/TopLevel_rst_ps7_0_100M_0.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_rst_ps7_0_100M_0/synth/TopLevel_rst_ps7_0_100M_0.vhd
create mode 100755 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0.dcp
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0.xci
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0.xml
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0_ooc.xdc
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0_sim_netlist.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0_sim_netlist.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0_stub.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/TopLevel_xbar_0_stub.vhdl
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/sim/TopLevel_xbar_0.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_xbar_0/synth/TopLevel_xbar_0.v
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/sim/TopLevel.protoinst
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/sim/TopLevel.vhd
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/synth/TopLevel.hwdef
create mode 100644 pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 0000000..5337503
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,49 @@
+variables:
+ GIT_STRATEGY: clone
+
+stages:
+ - firmware
+ - petalinux
+
+build:firmware:
+ stage: firmware
+ tags:
+ - lbl
+ - vivado
+ script:
+ - pwd
+ - source /opt/Xilinx/Vivado/2019.1/settings64.sh
+ - echo generate_target all [get_files TopLevel.bd] >> compile.tcl
+ - echo launch_runs impl_1 -to_step write_bitstream >> compile.tcl
+ - echo wait_on_run impl_1 >> compile.tcl
+ - vivado -mode batch -source compile.tcl pbv3_mass_test_adapter_firmware.xpr
+ - mkdir pbv3_mass_test_adapter_firmware.sdk
+ - cp pbv3_mass_test_adapter_firmware.runs/impl_1/TopLevel_wrapper.sysdef pbv3_mass_test_adapter_firmware.sdk/TopLevel_wrapper.hdf
+
+ - find .
+ artifacts:
+ paths:
+ - pbv3_mass_test_adapter_firmware.runs/impl_1/TopLevel_wrapper.bit
+ - pbv3_mass_test_adapter_firmware.sdk/TopLevel_wrapper.hdf
+
+build:petalinux:
+ stage: petalinux
+ tags:
+ - lbl
+ - petalinux
+ script:
+ - pwd
+ - source ${HOME}/petalinux/2019.1/settings.sh
+ - cd pbv3_mass_test_adapter_firmware.linux
+ - petalinux-config --get-hw-description ../pbv3_mass_test_adapter_firmware.sdk --silentconfig
+ - petalinux-build
+ - find .
+ - petalinux-package --boot --fpga ../pbv3_mass_test_adapter_firmware.runs/impl_1/TopLevel_wrapper.bit --fsbl images/linux/zynq_fsbl.elf --u-boot -o images/linux/BOOT.bin --force
+ dependencies:
+ - build:firmware
+ artifacts:
+ paths:
+ - pbv3_mass_test_adapter_firmware.linux/images/linux/BOOT.bin
+ - pbv3_mass_test_adapter_firmware.linux/images/linux/image.ub
+ - pbv3_mass_test_adapter_firmware.linux/images/linux/rootfs.tar.bz2
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/bd/bd.tcl b/ip_repo/endeavour_axi_controller_1.0/bd/bd.tcl
new file mode 100644
index 0000000..4804aeb
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/component.xml b/ip_repo/endeavour_axi_controller_1.0/component.xml
new file mode 100644
index 0000000..60373f2
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/component.xml
@@ -0,0 +1,990 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>lbl.gov</spirit:vendor>
+ <spirit:library>endeavour</spirit:library>
+ <spirit:name>endeavour_axi_controller</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIZ_NUM_REG</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_RST</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_CLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
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+ <spirit:name>hdl/endeavour_axi_controller_v1_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_07363f16</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/endeavour_axi_controller_v1_0_S00_AXI.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/endeavour_master.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/smooth.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/endeavour_axi_controller_v1_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd</spirit:name>
+ <spirit:userFileType>mdd</spirit:userFileType>
+ <spirit:userFileType>driver_mdd</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>driver_tcl</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/src/Makefile</spirit:name>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/endeavour_axi_controller_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_dda4df14</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>Endeavour controller IP for the AMACv2</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI data bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI address bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">6</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
+ <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
+ <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">endeavour_axi_controller_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>endeavour_axi_controller_v1.0</xilinx:displayName>
+ <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>xilinx.com:user:endeavour_axi_controller:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2019-10-14T18:14:07Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="xilinx.com:user:endeavour_axi_controller:1.0_ARCHIVE_LOCATION">/home/kkrizka/Firmware/amacv2_tester/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="lbl.gov:user:endeavour_axi_controller:1.0_ARCHIVE_LOCATION">/home/kkrizka/Firmware/amacv2_tester/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="lbl.gov:endeavour:endeavour_axi_controller:1.0_ARCHIVE_LOCATION">/home/kkrizka/ITkStrips/AMACv2/amacv2_tester/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@fe8cac1_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ee3351_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c05d181_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11175760_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58ee0488_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7c81676d_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@676ae7e0_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@652e38ee_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7b0930a0_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7bb0de0e_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7d69e595_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23ab5969_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bbd6f03_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2d3908a7_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5da7258c_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d678bf6_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3bfd77ad_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7f5dab08_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@135a994d_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d0809cf_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b664b0b_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@cb6c9f3_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c005e0b_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="206b0a70"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7274744c"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f96fcf9"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e7b50784"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="4b93d213"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
new file mode 100644
index 0000000..4428971
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER endeavour_axi_controller
+ OPTION supported_peripherals = (endeavour_axi_controller);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = endeavour_axi_controller;
+END DRIVER
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
new file mode 100644
index 0000000..ca357f9
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "endeavour_axi_controller" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/Makefile b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/Makefile
new file mode 100644
index 0000000..e3be7d8
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling endeavour_axi_controller..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
new file mode 100644
index 0000000..788d112
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "endeavour_axi_controller.h"
+
+/************************** Function Definitions ***************************/
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
new file mode 100644
index 0000000..a4b6216
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
@@ -0,0 +1,83 @@
+
+#ifndef ENDEAVOUR_FMC_CONTROLLER_H
+#define ENDEAVOUR_FMC_CONTROLLER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG0_OFFSET 0
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG1_OFFSET 4
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG2_OFFSET 8
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG3_OFFSET 12
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG4_OFFSET 16
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG5_OFFSET 20
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG6_OFFSET 24
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG7_OFFSET 28
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a ENDEAVOUR_FMC_CONTROLLER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the ENDEAVOUR_FMC_CONTROLLERdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void ENDEAVOUR_FMC_CONTROLLER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define ENDEAVOUR_FMC_CONTROLLER_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a ENDEAVOUR_FMC_CONTROLLER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the ENDEAVOUR_FMC_CONTROLLER device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 ENDEAVOUR_FMC_CONTROLLER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define ENDEAVOUR_FMC_CONTROLLER_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the ENDEAVOUR_FMC_CONTROLLER instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus ENDEAVOUR_FMC_CONTROLLER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // ENDEAVOUR_FMC_CONTROLLER_H
diff --git a/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
new file mode 100644
index 0000000..fbb3cbb
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "endeavour_axi_controller.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the ENDEAVOUR_FMC_CONTROLLERinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus ENDEAVOUR_FMC_CONTROLLER_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ ENDEAVOUR_FMC_CONTROLLER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( ENDEAVOUR_FMC_CONTROLLER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
diff --git a/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/design.tcl b/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/design.tcl
new file mode 100644
index 0000000..4b59cd5
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/design.tcl
@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create Clock and Reset Ports
+ set ACLK [ create_bd_port -dir I -type clk ACLK ]
+ set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+ set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+ set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
+ set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+ # Create instance: endeavour_axi_controller_0, and set properties
+ set endeavour_axi_controller_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:endeavour_axi_controller:1.0 endeavour_axi_controller_0]
+
+ # Create instance: master_0, and set properties
+ set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
+ set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+ # Create interface connections
+ connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins endeavour_axi_controller_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins endeavour_axi_controller_0/S00_AXI_ACLK]
+ connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins endeavour_axi_controller_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+ # Auto assign address
+ assign_bd_address
+
+ # Copy all address to interface_address.vh file
+ set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/endeavour_axi_controller_v1_0_tb_include.svh"
+ set fp [open $offset_file "w"]
+ puts $fp "`ifndef endeavour_axi_controller_v1_0_tb_include_vh_"
+ puts $fp "`define endeavour_axi_controller_v1_0_tb_include_vh_\n"
+ puts $fp "//Configuration current bd names"
+ puts $fp "`define BD_NAME ${design_name}"
+ puts $fp "`define BD_INST_NAME ${design_name}_i"
+ puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+ puts $fp "//Configuration address parameters"
+
+ puts $fp "`endif"
+ close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:endeavour_axi_controller:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/endeavour_axi_controller_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "endeavour_axi_controller_v1_0_bfm_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 endeavour_axi_controller_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top endeavour_axi_controller_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral
diff --git a/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/endeavour_axi_controller_v1_0_tb.sv b/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/endeavour_axi_controller_v1_0_tb.sv
new file mode 100644
index 0000000..c08e339
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/example_designs/bfm_design/endeavour_axi_controller_v1_0_tb.sv
@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "endeavour_axi_controller_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import endeavour_axi_controller_v1_0_bfm_1_master_0_0_pkg::*;
+
+module endeavour_axi_controller_v1_0_tb();
+
+
+xil_axi_uint error_cnt = 0;
+xil_axi_uint comparison_cnt = 0;
+axi_transaction wr_transaction;
+axi_transaction rd_transaction;
+axi_monitor_transaction mst_monitor_transaction;
+axi_monitor_transaction master_moniter_transaction_queue[$];
+xil_axi_uint master_moniter_transaction_queue_size =0;
+axi_monitor_transaction mst_scb_transaction;
+axi_monitor_transaction passthrough_monitor_transaction;
+axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
+xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
+axi_monitor_transaction passthrough_mst_scb_transaction;
+axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
+xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
+axi_monitor_transaction passthrough_slv_scb_transaction;
+axi_monitor_transaction slv_monitor_transaction;
+axi_monitor_transaction slave_moniter_transaction_queue[$];
+xil_axi_uint slave_moniter_transaction_queue_size =0;
+axi_monitor_transaction slv_scb_transaction;
+xil_axi_uint mst_agent_verbosity = 0;
+xil_axi_uint slv_agent_verbosity = 0;
+xil_axi_uint passthrough_agent_verbosity = 0;
+bit clock;
+bit reset;
+integer result_slave;
+bit [31:0] S00_AXI_test_data[3:0];
+ localparam LC_AXI_BURST_LENGTH = 8;
+ localparam LC_AXI_DATA_WIDTH = 32;
+task automatic COMPARE_DATA;
+ input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
+ input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
+ begin
+ if (expected === 'hx || actual === 'hx) begin
+ $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
+ result_slave = 0; $stop;
+ end
+ if (actual != expected) begin
+ $display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
+ result_slave = 0;
+ $stop;
+ end
+ else
+ begin
+ $display("TESTBENCH Passed! Data expected is equal to actual.",
+ " expected = 0x%h",expected, " actual = 0x%h",actual);
+ end
+ end
+endtask
+integer i;
+integer j;
+xil_axi_uint trans_cnt_before_switch = 48;
+xil_axi_uint passthrough_cmd_switch_cnt = 0;
+event passthrough_mastermode_start_event;
+event passthrough_mastermode_end_event;
+event passthrough_slavemode_end_event;
+xil_axi_uint mtestID;
+xil_axi_ulong mtestADDR;
+xil_axi_len_t mtestBurstLength;
+xil_axi_size_t mtestDataSize;
+xil_axi_burst_t mtestBurstType;
+xil_axi_lock_t mtestLOCK;
+xil_axi_cache_t mtestCacheType = 0;
+xil_axi_prot_t mtestProtectionType = 3'b000;
+xil_axi_region_t mtestRegion = 4'b000;
+xil_axi_qos_t mtestQOS = 4'b000;
+xil_axi_data_beat dbeat;
+xil_axi_data_beat [255:0] mtestWUSER;
+xil_axi_data_beat mtestAWUSER = 'h0;
+xil_axi_data_beat mtestARUSER = 0;
+xil_axi_data_beat [255:0] mtestRUSER;
+xil_axi_uint mtestBUSER = 0;
+xil_axi_resp_t mtestBresp;
+xil_axi_resp_t[255:0] mtestRresp;
+bit [63:0] mtestWDataL;
+bit [63:0] mtestRDataL;
+axi_transaction pss_wr_transaction;
+axi_transaction pss_rd_transaction;
+axi_transaction reactive_transaction;
+axi_transaction rd_payload_transaction;
+axi_transaction wr_rand;
+axi_transaction rd_rand;
+axi_transaction wr_reactive;
+axi_transaction rd_reactive;
+axi_transaction wr_reactive2;
+axi_transaction rd_reactive2;
+axi_ready_gen bready_gen;
+axi_ready_gen rready_gen;
+axi_ready_gen awready_gen;
+axi_ready_gen wready_gen;
+axi_ready_gen arready_gen;
+axi_ready_gen bready_gen2;
+axi_ready_gen rready_gen2;
+axi_ready_gen awready_gen2;
+axi_ready_gen wready_gen2;
+axi_ready_gen arready_gen2;
+xil_axi_payload_byte data_mem[xil_axi_ulong];
+endeavour_axi_controller_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
+
+ `BD_WRAPPER DUT(
+ .ARESETN(reset),
+ .ACLK(clock)
+ );
+
+initial begin
+ mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
+ mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
+ mst_agent_0.set_agent_tag("Master VIP");
+ mst_agent_0.set_verbosity(mst_agent_verbosity);
+ mst_agent_0.start_master();
+ $timeformat (-12, 1, " ps", 1);
+ end
+ initial begin
+ reset <= 1'b0;
+ #100ns;
+ reset <= 1'b1;
+ repeat (5) @(negedge clock);
+ end
+ always #5 clock <= ~clock;
+ initial begin
+ S_AXI_TEST ( );
+
+ #1ns;
+ $finish;
+ end
+task automatic S_AXI_TEST;
+begin
+#1;
+ $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
+ mtestID = 0;
+ mtestADDR = 64'h00000000;
+ mtestBurstLength = 0;
+ mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
+ mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
+ mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
+ mtestCacheType = 0;
+ mtestProtectionType = 0;
+ mtestRegion = 0;
+ mtestQOS = 0;
+ result_slave = 1;
+ mtestWDataL[31:0] = 32'h00000001;
+ for(int i = 0; i < 4;i++) begin
+ S00_AXI_test_data[i] <= mtestWDataL[31:0];
+ mst_agent_0.AXI4LITE_WRITE_BURST(
+ mtestADDR,
+ mtestProtectionType,
+ mtestWDataL,
+ mtestBresp
+ );
+ mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
+ mtestADDR = mtestADDR + 64'h4;
+ end
+ $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
+ $display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
+ mtestID = 0;
+ mtestADDR = 64'h00000000;
+ mtestBurstLength = 0;
+ mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
+ mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
+ mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
+ mtestCacheType = 0;
+ mtestProtectionType = 0;
+ mtestRegion = 0;
+ mtestQOS = 0;
+ for(int i = 0; i < 4;i++) begin
+ mst_agent_0.AXI4LITE_READ_BURST(
+ mtestADDR,
+ mtestProtectionType,
+ mtestRDataL,
+ mtestRresp
+ );
+ mtestADDR = mtestADDR + 64'h4;
+ COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
+ end
+ $display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
+ $display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
+ $display("---------------------------------------------------------");
+ $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
+ if ( result_slave ) begin
+ $display("PTGEN_TEST: PASSED!");
+ end else begin
+ $display("PTGEN_TEST: FAILED!");
+ end
+ $display("---------------------------------------------------------");
+ end
+endtask
+
+endmodule
diff --git a/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/design.tcl b/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/design.tcl
new file mode 100644
index 0000000..464d9c6
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/design.tcl
@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create and configure Clock/Reset
+ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+ #Constraints will be provided manually while pin planning.
+ create_bd_port -dir I -type rst reset_rtl
+ set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+ set external_reset_port reset_rtl
+ create_bd_port -dir I -type clk clock_rtl
+ connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+ set external_clock_port clock_rtl
+
+ #Avoid IPI DRC, make clock port synchronous to reset
+ if { $external_clock_port ne "" && $external_reset_port ne "" } {
+ set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+ }
+
+ # Connect other sys_reset pins
+ connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+ # Create instance: endeavour_axi_controller_0, and set properties
+ set endeavour_axi_controller_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:endeavour_axi_controller:1.0 endeavour_axi_controller_0 ]
+
+ # Create instance: jtag_axi_0, and set properties
+ set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+ set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+ connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Create instance: axi_peri_interconnect, and set properties
+ set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+ set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+ set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Connect all clock & reset of endeavour_axi_controller_0 slave interfaces..
+ connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins endeavour_axi_controller_0/S00_AXI]
+ connect_bd_net [get_bd_pins endeavour_axi_controller_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins endeavour_axi_controller_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+ # Auto assign address
+ assign_bd_address
+
+ # Copy all address to endeavour_axi_controller_v1_0_include.tcl file
+ set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/endeavour_axi_controller_v1_0_include.tcl"
+ set fp [open $offset_file "w"]
+ puts $fp "# Configuration address parameters"
+
+ set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_endeavour_axi_controller_0_S00_AXI_* ]]
+ puts $fp "set s00_axi_addr ${offset}"
+
+ close $fp
+}
+
+# Set IP Repository and Update IP Catalogue
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:endeavour_axi_controller:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/endeavour_axi_controller_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "endeavour_axi_controller_v1_0_hw_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts " please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts " : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/endeavour_axi_controller_v1_0_hw_test.tcl b/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/endeavour_axi_controller_v1_0_hw_test.tcl
new file mode 100644
index 0000000..13bb961
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/example_designs/debug_hw_design/endeavour_axi_controller_v1_0_hw_test.tcl
@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - endeavour_axi_controller_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/endeavour_axi_controller_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+ delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+ puts "Data comparison test pass for - S00_AXI"
+} else {
+ puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+ inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+ puts "PTGEN_TEST: PASSED!"
+} else {
+ puts "PTGEN_TEST: FAILED!"
+}
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/hdl/TopLevel_clk_wiz_0_0.v b/ip_repo/endeavour_axi_controller_1.0/hdl/TopLevel_clk_wiz_0_0.v
new file mode 100644
index 0000000..3496e53
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/hdl/TopLevel_clk_wiz_0_0.v
@@ -0,0 +1,191 @@
+
+// file: TopLevel_clk_wiz_0_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____80.000______0.000______50.0______137.143_____98.575
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module TopLevel_clk_wiz_0_0_clk_wiz
+
+ (// Clock in ports
+ // Clock out ports
+ output clk_out1,
+ input clk_in1
+ );
+ // Input buffering
+ //------------------------------------
+
+
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+
+ wire clk_out1_TopLevel_clk_wiz_0_0;
+ wire clk_out2_TopLevel_clk_wiz_0_0;
+ wire clk_out3_TopLevel_clk_wiz_0_0;
+ wire clk_out4_TopLevel_clk_wiz_0_0;
+ wire clk_out5_TopLevel_clk_wiz_0_0;
+ wire clk_out6_TopLevel_clk_wiz_0_0;
+ wire clk_out7_TopLevel_clk_wiz_0_0;
+
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_TopLevel_clk_wiz_0_0;
+ wire clkfbout_buf_TopLevel_clk_wiz_0_0;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1_unused;
+ wire clkout1b_unused;
+ wire clkout2_unused;
+ wire clkout2b_unused;
+ wire clkout3_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (10.000),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (12.500),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.000))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_TopLevel_clk_wiz_0_0),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clkout1_unused),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clkout2_unused),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clkout3_unused),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_TopLevel_clk_wiz_0_0),
+ .CLKIN1 (clk_in1),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (1'b0));
+
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_TopLevel_clk_wiz_0_0),
+ .I (clkfbout_TopLevel_clk_wiz_0_0));
+
+
+
+
+
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0.vhd b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0.vhd
new file mode 100644
index 0000000..b0fda11
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0.vhd
@@ -0,0 +1,321 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity endeavour_axi_controller_v1_0 is
+ generic (
+ -- Users to add parameters here
+ -- User parameters ends
+ -- Do not modify the parameters beyond this line
+
+ -- Parameters of Axi Slave Bus Interface S00_AXI
+ C_S00_AXI_DATA_WIDTH : integer := 32;
+ C_S00_AXI_ADDR_WIDTH : integer := 6
+ );
+ port (
+ -- Users to add ports here
+ busy : out std_logic;
+ datavalid : out std_logic;
+ error : out std_logic;
+ CMD_IN_P : out std_logic;
+ CMD_IN_N : out std_logic;
+
+ CMD_OUT_P : in std_logic;
+ CMD_OUT_N : in std_logic;
+
+ cmd_in : out std_logic;
+ cmd_out : out std_logic;
+ -- User ports ends
+ -- Do not modify the ports beyond this line
+
+
+ -- Ports of Axi Slave Bus Interface S00_AXI
+ s00_axi_aclk : in std_logic;
+ s00_axi_aresetn : in std_logic;
+ s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_awprot : in std_logic_vector(2 downto 0);
+ s00_axi_awvalid : in std_logic;
+ s00_axi_awready : out std_logic;
+ s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+ s00_axi_wvalid : in std_logic;
+ s00_axi_wready : out std_logic;
+ s00_axi_bresp : out std_logic_vector(1 downto 0);
+ s00_axi_bvalid : out std_logic;
+ s00_axi_bready : in std_logic;
+ s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_arprot : in std_logic_vector(2 downto 0);
+ s00_axi_arvalid : in std_logic;
+ s00_axi_arready : out std_logic;
+ s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_rresp : out std_logic_vector(1 downto 0);
+ s00_axi_rvalid : out std_logic;
+ s00_axi_rready : in std_logic
+ );
+end endeavour_axi_controller_v1_0;
+
+architecture arch_imp of endeavour_axi_controller_v1_0 is
+
+ -- component declaration
+ component endeavour_axi_controller_v1_0_S00_AXI is
+ generic (
+ C_S_AXI_DATA_WIDTH : integer := 32;
+ C_S_AXI_ADDR_WIDTH : integer := 6
+ );
+ port (
+ axi_control : out std_logic_vector(31 downto 0);
+ axi_status : in std_logic_vector(31 downto 0);
+ axi_nbitsin : out std_logic_vector(31 downto 0);
+ axi_datain : out std_logic_vector(63 downto 0);
+ axi_nbitsout : in std_logic_vector(31 downto 0);
+ axi_dataout : in std_logic_vector(63 downto 0);
+ axi_config : out std_logic_vector(31 downto 0);
+
+ TICKS_DIT_MIN : out integer range 0 to 4095;
+ TICKS_DIT_MID : out integer range 0 to 4095;
+ TICKS_DIT_MAX : out integer range 0 to 4095;
+
+ TICKS_DAH_MIN : out integer range 0 to 4095;
+ TICKS_DAH_MID : out integer range 0 to 4095;
+ TICKS_DAH_MAX : out integer range 0 to 4095;
+
+ TICKS_BITGAP_MIN : out integer range 0 to 4095;
+ TICKS_BITGAP_MID : out integer range 0 to 4095;
+ TICKS_BITGAP_MAX : out integer range 0 to 4095;
+
+ S_AXI_ACLK : in std_logic;
+ S_AXI_ARESETN : in std_logic;
+ S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ S_AXI_AWPROT : in std_logic_vector(2 downto 0);
+ S_AXI_AWVALID : in std_logic;
+ S_AXI_AWREADY : out std_logic;
+ S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+ S_AXI_WVALID : in std_logic;
+ S_AXI_WREADY : out std_logic;
+ S_AXI_BRESP : out std_logic_vector(1 downto 0);
+ S_AXI_BVALID : out std_logic;
+ S_AXI_BREADY : in std_logic;
+ S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ S_AXI_ARPROT : in std_logic_vector(2 downto 0);
+ S_AXI_ARVALID : in std_logic;
+ S_AXI_ARREADY : out std_logic;
+ S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ S_AXI_RRESP : out std_logic_vector(1 downto 0);
+ S_AXI_RVALID : out std_logic;
+ S_AXI_RREADY : in std_logic
+ );
+ end component endeavour_axi_controller_v1_0_S00_AXI;
+
+ component endeavour_master is
+ generic (
+ TICKS_QUIESCENT : integer := 75
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ TICKS_DIT_MIN : in integer range 0 to 4095 := 6;
+ TICKS_DIT_MID : in integer range 0 to 4095 := 14;
+ TICKS_DIT_MAX : in integer range 0 to 4095 := 22;
+ TICKS_DAH_MIN : in integer range 0 to 4095 := 29;
+ TICKS_DAH_MID : in integer range 0 to 4095 := 76;
+ TICKS_DAH_MAX : in integer range 0 to 4095 := 124;
+ TICKS_BITGAP_MIN : in integer range 0 to 4095 := 11;
+ TICKS_BITGAP_MID : in integer range 0 to 4095 := 43;
+ TICKS_BITGAP_MAX : in integer range 0 to 4095 := 75;
+ nbitsin : in integer range 0 to 63;
+ datain : in std_logic_vector(63 downto 0);
+ send : in std_logic;
+ busy : out std_logic;
+ nbitsout : out integer range 0 to 63;
+ dataout : out std_logic_vector(63 downto 0);
+ datavalid : out std_logic;
+ error : out std_logic;
+ serialin : in std_logic;
+ serialout : out std_logic
+ );
+ end component endeavour_master;
+
+ component smooth is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ input : in std_logic;
+ output : out std_logic
+ );
+ end component smooth;
+
+ component TopLevel_clk_wiz_0_0_clk_wiz is
+ port (
+ clk_out1 : out std_logic;
+ clk_in1 : in std_logic
+ );
+ end component TopLevel_clk_wiz_0_0_clk_wiz;
+
+ --
+ -- signal declarations
+ signal clock100MHz : std_logic;
+ signal clock80MHz : std_logic;
+ signal reset : std_logic;
+ signal invert_cmdin : std_logic;
+ signal invert_cmdout : std_logic;
+ signal seriali : std_logic;
+ signal seriali_buf : std_logic;
+ signal seriali_noise : std_logic;
+ signal serialo : std_logic;
+ signal serialo_buf : std_logic;
+ signal axi_control : std_logic_vector(31 downto 0);
+ signal axi_status : std_logic_vector(31 downto 0);
+ signal axi_nbitsin : std_logic_vector(31 downto 0);
+ signal axi_datain : std_logic_vector(63 downto 0);
+ signal axi_nbitsout : std_logic_vector(31 downto 0);
+ signal axi_dataout : std_logic_vector(63 downto 0);
+ signal axi_config : std_logic_vector(31 downto 0);
+
+ signal axi_nbitsout_integer : integer range 0 to 63;
+
+ -- configuration signals
+ signal TICKS_DIT_MIN : integer range 0 to 4095;
+ signal TICKS_DIT_MID : integer range 0 to 4095;
+ signal TICKS_DIT_MAX : integer range 0 to 4095;
+ signal TICKS_DAH_MIN : integer range 0 to 4095;
+ signal TICKS_DAH_MID : integer range 0 to 4095;
+ signal TICKS_DAH_MAX : integer range 0 to 4095;
+ signal TICKS_BITGAP_MIN : integer range 0 to 4095;
+ signal TICKS_BITGAP_MID : integer range 0 to 4095;
+ signal TICKS_BITGAP_MAX : integer range 0 to 4095;
+begin
+
+-- Instantiation of Axi Bus Interface S00_AXI
+ endeavour_axi_controller_v1_0_S00_AXI_inst : endeavour_axi_controller_v1_0_S00_AXI
+ generic map (
+ C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
+ C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
+ )
+ port map (
+ axi_control => axi_control,
+ axi_status => axi_status,
+ axi_nbitsin => axi_nbitsin,
+ axi_datain => axi_datain,
+ axi_nbitsout => axi_nbitsout,
+ axi_dataout => axi_dataout,
+ axi_config => axi_config,
+ TICKS_DIT_MIN => TICKS_DIT_MIN ,
+ TICKS_DIT_MID => TICKS_DIT_MID ,
+ TICKS_DIT_MAX => TICKS_DIT_MAX ,
+ TICKS_DAH_MIN => TICKS_DAH_MIN ,
+ TICKS_DAH_MID => TICKS_DAH_MID ,
+ TICKS_DAH_MAX => TICKS_DAH_MAX ,
+ TICKS_BITGAP_MIN => TICKS_BITGAP_MIN,
+ TICKS_BITGAP_MID => TICKS_BITGAP_MID,
+ TICKS_BITGAP_MAX => TICKS_BITGAP_MAX,
+ S_AXI_ACLK => s00_axi_aclk,
+ S_AXI_ARESETN => s00_axi_aresetn,
+ S_AXI_AWADDR => s00_axi_awaddr,
+ S_AXI_AWPROT => s00_axi_awprot,
+ S_AXI_AWVALID => s00_axi_awvalid,
+ S_AXI_AWREADY => s00_axi_awready,
+ S_AXI_WDATA => s00_axi_wdata,
+ S_AXI_WSTRB => s00_axi_wstrb,
+ S_AXI_WVALID => s00_axi_wvalid,
+ S_AXI_WREADY => s00_axi_wready,
+ S_AXI_BRESP => s00_axi_bresp,
+ S_AXI_BVALID => s00_axi_bvalid,
+ S_AXI_BREADY => s00_axi_bready,
+ S_AXI_ARADDR => s00_axi_araddr,
+ S_AXI_ARPROT => s00_axi_arprot,
+ S_AXI_ARVALID => s00_axi_arvalid,
+ S_AXI_ARREADY => s00_axi_arready,
+ S_AXI_RDATA => s00_axi_rdata,
+ S_AXI_RRESP => s00_axi_rresp,
+ S_AXI_RVALID => s00_axi_rvalid,
+ S_AXI_RREADY => s00_axi_rready
+ );
+
+-- Add user logic here
+ reset <= axi_control(0);
+
+ invert_cmdin <= axi_config(0);
+ invert_cmdout <= axi_config(1);
+ -- Differential buffers for AMAC communication
+ CMD_IN_buf_inst : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS_25"
+ )
+ port map(
+ I => serialo_buf,
+ O => CMD_IN_P,
+ OB => CMD_IN_N
+ );
+
+ CMD_OUT_buf_inst : IBUFDS
+ generic map(
+ IOSTANDARD => "LVDS_25"
+ )
+ port map(
+ I => CMD_OUT_P,
+ IB => CMD_OUT_N,
+ O => seriali_buf
+ );
+
+ cmd_in <= serialo;
+ cmd_out <= seriali;
+
+ serialo_buf <= serialo when invert_cmdin ='0' else not serialo;
+ seriali <= seriali_buf when invert_cmdout='0' else not seriali_buf;
+
+ --inst_smoothinput : smooth
+ -- port map (
+ -- clock => clock100MHz,
+ -- reset => reset,
+ -- input => seriali_noise,
+ -- output => seriali
+ -- );
+
+
+ busy <= axi_status(0);
+ datavalid <= axi_status(1);
+ error <= axi_status(2);
+ --
+ clock100MHz <= s00_axi_aclk;
+ -- inst_TopLevel_clk_wiz_0_0_clk_wiz : TopLevel_clk_wiz_0_0_clk_wiz
+ -- port map(
+ -- clk_out1 => clock80MHz,
+ -- clk_in1 => clock100MHz
+ -- );
+
+ inst_endeavour_master : endeavour_master
+ generic map (
+ TICKS_QUIESCENT => 150
+ )
+ port map (
+ clock => clock100MHz,
+ reset => reset,
+ TICKS_DIT_MIN => TICKS_DIT_MIN ,
+ TICKS_DIT_MID => TICKS_DIT_MID ,
+ TICKS_DIT_MAX => TICKS_DIT_MAX ,
+ TICKS_DAH_MIN => TICKS_DAH_MIN ,
+ TICKS_DAH_MID => TICKS_DAH_MID ,
+ TICKS_DAH_MAX => TICKS_DAH_MAX ,
+ TICKS_BITGAP_MIN => TICKS_BITGAP_MIN,
+ TICKS_BITGAP_MID => TICKS_BITGAP_MID,
+ TICKS_BITGAP_MAX => TICKS_BITGAP_MAX,
+ nbitsin => to_integer(unsigned(axi_nbitsin)),
+ datain => axi_datain,
+ send => axi_control(1),
+ busy => axi_status(0),
+ nbitsout => axi_nbitsout_integer,
+ dataout => axi_dataout,
+ datavalid => axi_status(1),
+ error => axi_status(2),
+ serialin => seriali,
+ serialout => serialo
+ );
+ axi_nbitsout <= std_logic_vector(to_unsigned(axi_nbitsout_integer,axi_nbitsout'length));
+
+ -- User logic ends
+
+end arch_imp;
diff --git a/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0_S00_AXI.vhd b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0_S00_AXI.vhd
new file mode 100644
index 0000000..abd9916
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_axi_controller_v1_0_S00_AXI.vhd
@@ -0,0 +1,565 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--
+-- AXI Register map
+-- reg0(W) - control, pulsed
+-- reg0(R) - status
+-- reg1(RW) - nbits in
+-- reg2(RW) - data in (LSB)
+-- reg3(RW) - data in (MSB)
+-- reg4(R) - nbits out
+-- reg5(R) - data out (LSB)
+-- reg6(R) - data out (MSB)
+-- reg7(RW) - DIT lengths
+-- reg8(RW) - DAH lengths
+-- reg9(RW) - BITGAP lengths
+-- reg10(RW) - configuration
+--
+-- For length definitions, the format is as follows:
+-- 0xAAABBBCC
+-- AAA - maximum (used for Rx interpretation)
+-- BBB - median (used for Tx generation)
+-- CC - minmum (used for Rx interpretation)
+--
+
+entity endeavour_axi_controller_v1_0_S00_AXI is
+ generic (
+ -- Users to add parameters here
+
+ -- User parameters ends
+ -- Do not modify the parameters beyond this line
+
+ -- Width of S_AXI data bus
+ C_S_AXI_DATA_WIDTH : integer := 32;
+ -- Width of S_AXI address bus
+ C_S_AXI_ADDR_WIDTH : integer := 6
+ );
+ port (
+ -- Users to add ports here
+ axi_control : out std_logic_vector(31 downto 0);
+ axi_status : in std_logic_vector(31 downto 0);
+ axi_nbitsin : out std_logic_vector(31 downto 0);
+ axi_datain : out std_logic_vector(63 downto 0);
+ axi_nbitsout : in std_logic_vector(31 downto 0);
+ axi_dataout : in std_logic_vector(63 downto 0);
+ axi_config : out std_logic_vector(31 downto 0);
+
+ TICKS_DIT_MIN : out integer range 0 to 4095;
+ TICKS_DIT_MID : out integer range 0 to 4095;
+ TICKS_DIT_MAX : out integer range 0 to 4095;
+
+ TICKS_DAH_MIN : out integer range 0 to 4095;
+ TICKS_DAH_MID : out integer range 0 to 4095;
+ TICKS_DAH_MAX : out integer range 0 to 4095;
+
+ TICKS_BITGAP_MIN : out integer range 0 to 4095;
+ TICKS_BITGAP_MID : out integer range 0 to 4095;
+ TICKS_BITGAP_MAX : out integer range 0 to 4095;
+
+ -- User ports ends
+ -- Do not modify the ports beyond this line
+
+ -- Global Clock Signal
+ S_AXI_ACLK : in std_logic;
+ -- Global Reset Signal. This Signal is Active LOW
+ S_AXI_ARESETN : in std_logic;
+ -- Write address (issued by master, acceped by Slave)
+ S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ -- Write channel Protection type. This signal indicates the
+ -- privilege and security level of the transaction, and whether
+ -- the transaction is a data access or an instruction access.
+ S_AXI_AWPROT : in std_logic_vector(2 downto 0);
+ -- Write address valid. This signal indicates that the master signaling
+ -- valid write address and control information.
+ S_AXI_AWVALID : in std_logic;
+ -- Write address ready. This signal indicates that the slave is ready
+ -- to accept an address and associated control signals.
+ S_AXI_AWREADY : out std_logic;
+ -- Write data (issued by master, acceped by Slave)
+ S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ -- Write strobes. This signal indicates which byte lanes hold
+ -- valid data. There is one write strobe bit for each eight
+ -- bits of the write data bus.
+ S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+ -- Write valid. This signal indicates that valid write
+ -- data and strobes are available.
+ S_AXI_WVALID : in std_logic;
+ -- Write ready. This signal indicates that the slave
+ -- can accept the write data.
+ S_AXI_WREADY : out std_logic;
+ -- Write response. This signal indicates the status
+ -- of the write transaction.
+ S_AXI_BRESP : out std_logic_vector(1 downto 0);
+ -- Write response valid. This signal indicates that the channel
+ -- is signaling a valid write response.
+ S_AXI_BVALID : out std_logic;
+ -- Response ready. This signal indicates that the master
+ -- can accept a write response.
+ S_AXI_BREADY : in std_logic;
+ -- Read address (issued by master, acceped by Slave)
+ S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ -- Protection type. This signal indicates the privilege
+ -- and security level of the transaction, and whether the
+ -- transaction is a data access or an instruction access.
+ S_AXI_ARPROT : in std_logic_vector(2 downto 0);
+ -- Read address valid. This signal indicates that the channel
+ -- is signaling valid read address and control information.
+ S_AXI_ARVALID : in std_logic;
+ -- Read address ready. This signal indicates that the slave is
+ -- ready to accept an address and associated control signals.
+ S_AXI_ARREADY : out std_logic;
+ -- Read data (issued by slave)
+ S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ -- Read response. This signal indicates the status of the
+ -- read transfer.
+ S_AXI_RRESP : out std_logic_vector(1 downto 0);
+ -- Read valid. This signal indicates that the channel is
+ -- signaling the required read data.
+ S_AXI_RVALID : out std_logic;
+ -- Read ready. This signal indicates that the master can
+ -- accept the read data and response information.
+ S_AXI_RREADY : in std_logic
+ );
+end endeavour_axi_controller_v1_0_S00_AXI;
+
+architecture arch_imp of endeavour_axi_controller_v1_0_S00_AXI is
+
+ -- AXI4LITE signals
+ signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ signal axi_awready : std_logic;
+ signal axi_wready : std_logic;
+ signal axi_bresp : std_logic_vector(1 downto 0);
+ signal axi_bvalid : std_logic;
+ signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ signal axi_arready : std_logic;
+ signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal axi_rresp : std_logic_vector(1 downto 0);
+ signal axi_rvalid : std_logic;
+
+ -- Example-specific design signals
+ -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ -- ADDR_LSB is used for addressing 32/64 bit registers/memories
+ -- ADDR_LSB = 2 for 32 bits (n downto 2)
+ -- ADDR_LSB = 3 for 64 bits (n downto 3)
+ constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+ constant OPT_MEM_ADDR_BITS : integer := 3;
+ ------------------------------------------------
+ ---- Signals for user logic register space example
+ --------------------------------------------------
+ ---- Number of Slave Registers 8
+ signal slv_reg0_read :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg0_pulse :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg_rden : std_logic;
+ signal slv_reg_wren : std_logic;
+ signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal byte_index : integer;
+ signal aw_en : std_logic;
+
+begin
+ -- I/O Connections assignments
+
+ S_AXI_AWREADY <= axi_awready;
+ S_AXI_WREADY <= axi_wready;
+ S_AXI_BRESP <= axi_bresp;
+ S_AXI_BVALID <= axi_bvalid;
+ S_AXI_ARREADY <= axi_arready;
+ S_AXI_RDATA <= axi_rdata;
+ S_AXI_RRESP <= axi_rresp;
+ S_AXI_RVALID <= axi_rvalid;
+ -- Implement axi_awready generation
+ -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ -- de-asserted when reset is low.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_awready <= '0';
+ aw_en <= '1';
+ else
+ if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+ -- slave is ready to accept write address when
+ -- there is a valid write address and write data
+ -- on the write address and data bus. This design
+ -- expects no outstanding transactions.
+ axi_awready <= '1';
+ elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
+ aw_en <= '1';
+ axi_awready <= '0';
+ else
+ axi_awready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_awaddr latching
+ -- This process is used to latch the address when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_awaddr <= (others => '0');
+ else
+ if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+ -- Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_wready generation
+ -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ -- de-asserted when reset is low.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_wready <= '0';
+ else
+ if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
+ -- slave is ready to accept write data when
+ -- there is a valid write address and write data
+ -- on the write address and data bus. This design
+ -- expects no outstanding transactions.
+ axi_wready <= '1';
+ else
+ axi_wready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement memory mapped register select and write logic generation
+ -- The write data is accepted and written to memory mapped registers when
+ -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ -- select byte enables of slave registers while writing.
+ -- These registers are cleared when reset (active low) is applied.
+ -- Slave register write enable is asserted when valid address and data are available
+ -- and the slave is ready to accept the write address and write data.
+ slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+ process (S_AXI_ACLK)
+ variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ slv_reg0_pulse <= (others => '0');
+ slv_reg1 <= (others => '0');
+ slv_reg2 <= (others => '0');
+ slv_reg3 <= (others => '0');
+ --slv_reg4 <= (others => '0');
+ --slv_reg5 <= (others => '0');
+ --slv_reg6 <= (others => '0');
+ slv_reg7 <= x"0370230F";
+ slv_reg8 <= x"1360BE48";
+ slv_reg9 <= x"0BB06B1B";
+ slv_reg10 <= (others => '0');
+ else
+ loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+ if (slv_reg_wren = '1') then
+ case loc_addr is
+ when b"0000" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 0
+ slv_reg0_pulse(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0001" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 1
+ slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0010" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 2
+ slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0011" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 3
+ slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ --when b"0100" =>
+ -- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ -- if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- -- Respective byte enables are asserted as per write strobes
+ -- -- slave registor 4
+ -- slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ -- end if;
+ -- end loop;
+ --when b"0101" =>
+ -- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ -- if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- -- Respective byte enables are asserted as per write strobes
+ -- -- slave registor 5
+ -- slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ -- end if;
+ -- end loop;
+ --when b"0110" =>
+ -- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ -- if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- -- Respective byte enables are asserted as per write strobes
+ -- -- slave registor 6
+ -- slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ -- end if;
+ -- end loop;
+ when b"0111" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 7
+ slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1000" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 7
+ slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1001" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 7
+ slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1010" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 7
+ slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when others =>
+ slv_reg0_pulse <= slv_reg0_pulse;
+ slv_reg1 <= slv_reg1;
+ slv_reg2 <= slv_reg2;
+ slv_reg3 <= slv_reg3;
+ --slv_reg4 <= slv_reg4;
+ --slv_reg5 <= slv_reg5;
+ --slv_reg6 <= slv_reg6;
+ slv_reg7 <= slv_reg7;
+ slv_reg8 <= slv_reg8;
+ slv_reg9 <= slv_reg9;
+ slv_reg10<= slv_reg10;
+ end case;
+ else
+ slv_reg0_pulse <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement write response logic generation
+ -- The write response and response valid signals are asserted by the slave
+ -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ -- This marks the acceptance of address and indicates the status of
+ -- write transaction.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_bvalid <= '0';
+ axi_bresp <= "00"; --need to work more on the responses
+ else
+ if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
+ axi_bvalid <= '1';
+ axi_bresp <= "00";
+ elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
+ axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_arready generation
+ -- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ -- S_AXI_ARVALID is asserted. axi_awready is
+ -- de-asserted when reset (active low) is asserted.
+ -- The read address is also latched when S_AXI_ARVALID is
+ -- asserted. axi_araddr is reset to zero on reset assertion.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_arready <= '0';
+ axi_araddr <= (others => '1');
+ else
+ if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+ -- indicates that the slave has acceped the valid read address
+ axi_arready <= '1';
+ -- Read Address latching
+ axi_araddr <= S_AXI_ARADDR;
+ else
+ axi_arready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_arvalid generation
+ -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ -- data are available on the axi_rdata bus at this instance. The
+ -- assertion of axi_rvalid marks the validity of read data on the
+ -- bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ -- is deasserted on reset (active low). axi_rresp and axi_rdata are
+ -- cleared to zero on reset (active low).
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_rvalid <= '0';
+ axi_rresp <= "00";
+ else
+ if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+ -- Valid read data is available at the read data bus
+ axi_rvalid <= '1';
+ axi_rresp <= "00"; -- 'OKAY' response
+ elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+ -- Read data is accepted by the master
+ axi_rvalid <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement memory mapped register select and read logic generation
+ -- Slave register read enable is asserted when valid address is available
+ -- and the slave is ready to accept the read address.
+ slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+ process (slv_reg0_read, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+ variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+ begin
+ -- Address decoding for reading registers
+ loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+ case loc_addr is
+ when b"0000" =>
+ reg_data_out <= slv_reg0_read;
+ when b"0001" =>
+ reg_data_out <= slv_reg1;
+ when b"0010" =>
+ reg_data_out <= slv_reg2;
+ when b"0011" =>
+ reg_data_out <= slv_reg3;
+ when b"0100" =>
+ reg_data_out <= slv_reg4;
+ when b"0101" =>
+ reg_data_out <= slv_reg5;
+ when b"0110" =>
+ reg_data_out <= slv_reg6;
+ when b"0111" =>
+ reg_data_out <= slv_reg7;
+ when b"1000" =>
+ reg_data_out <= slv_reg8;
+ when b"1001" =>
+ reg_data_out <= slv_reg9;
+ when b"1010" =>
+ reg_data_out <= slv_reg10;
+ when others =>
+ reg_data_out <= (others => '0');
+ end case;
+ end process;
+
+ -- Output register or memory read data
+ process( S_AXI_ACLK ) is
+ begin
+ if (rising_edge (S_AXI_ACLK)) then
+ if ( S_AXI_ARESETN = '0' ) then
+ axi_rdata <= (others => '0');
+ else
+ if (slv_reg_rden = '1') then
+ -- When there is a valid read address (S_AXI_ARVALID) with
+ -- acceptance of read address by the slave (axi_arready),
+ -- output the read dada
+ -- Read address mux
+ axi_rdata <= reg_data_out; -- register read data
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Add user logic here
+ --
+
+ -- Remap outputs
+ TICKS_DIT_MAX <= to_integer(unsigned(slv_reg7(31 downto 20)));
+ TICKS_DIT_MID <= to_integer(unsigned(slv_reg7(19 downto 8)));
+ TICKS_DIT_MIN <= to_integer(unsigned(slv_reg7( 7 downto 0)));
+
+ TICKS_DAH_MAX <= to_integer(unsigned(slv_reg8(31 downto 20)));
+ TICKS_DAH_MID <= to_integer(unsigned(slv_reg8(19 downto 8)));
+ TICKS_DAH_MIN <= to_integer(unsigned(slv_reg8( 7 downto 0)));
+
+ TICKS_BITGAP_MAX <= to_integer(unsigned(slv_reg9(31 downto 20)));
+ TICKS_BITGAP_MID <= to_integer(unsigned(slv_reg9(19 downto 8)));
+ TICKS_BITGAP_MIN <= to_integer(unsigned(slv_reg9( 7 downto 0)));
+
+ axi_control <= slv_reg0_pulse;
+
+ axi_nbitsin(31 downto 0) <= slv_reg1;
+ axi_datain (31 downto 0) <= slv_reg2;
+ axi_datain (63 downto 32) <= slv_reg3;
+ axi_config (31 downto 0) <= slv_reg10;
+
+ -- Read-Only Register inputs
+ process ( S_AXI_ACLK )
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ slv_reg0_read <= (others => '0');
+ slv_reg4 <= (others => '0');
+ slv_reg5 <= (others => '0');
+ slv_reg6 <= (others => '0');
+ else
+ slv_reg0_read <= axi_status;
+
+ slv_reg4 <= axi_nbitsout(31 downto 0);
+ slv_reg5 <= axi_dataout (31 downto 0);
+ slv_reg6 <= axi_dataout (63 downto 32);
+ end if;
+ end if;
+ end process;
+
+ --
+ -- User logic ends
+
+end arch_imp;
diff --git a/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_master.vhd b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_master.vhd
new file mode 100644
index 0000000..f941fe3
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/hdl/endeavour_master.vhd
@@ -0,0 +1,289 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+----
+-- Entity: endeavour_master
+-- Author: Karol Krizka <kkrizka@gmail.com>
+--
+-- Entity responsible for acting as a master in the Endeavour protocol. The entity is very dumb, with the
+-- software responsible for most of the work. It acts only as a (de)serializer for the morse code. The Tx
+-- and Rx parts are kept almost competely separate. The only interaction is
+-- that the send command also clears the datavalid flag.
+--
+--Generic ports
+-- clock - Clock used for internal logic and to time the serial line (nominal 80 MHz)
+-- reset - Active high reset signal to reset internal state machines
+-- serialin - The data sent from the the Endeavour slave
+-- serialout - The data sent to the the Endeavour slave
+--
+--Transfer ports
+-- nbitsin - Number of bits to transfer from the datain
+-- datain - The data to transfer. The least significant nbitsin will be send, starting with bit at nbitsin-1.
+-- send - Pulse to send data stored in datain.
+-- busy - Indicates that the Tx FSM is sending data. Any calls to send will be ignored.
+--
+--Receive ports
+-- nbitsout - Number of valid bits received from the slave.
+-- dataout - The data recieved from the slave, stored in the nbitsout least significant bits. The bit at nbitsout-1 was recieved first.
+-- datavalid - High signal indicates that dataout contains valid and complete data. Goes low after reset,when a new word is being serialized and when data was sent.
+-- error - Inidicates an error condition during serialization of serialin. Currently only the length of a pulse must be in the specified number of clock cycles.
+----
+entity endeavour_master is
+ generic (
+ -- required pause between words
+ TICKS_QUIESCENT : integer := 75
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+
+ -- minimum, middle and maximum widths of "ZERO"
+ -- middle is used for Tx
+ -- min and max is used for Rx
+ TICKS_DIT_MIN : in integer range 0 to 4095 := 6;
+ TICKS_DIT_MID : in integer range 0 to 4095 := 14;
+ TICKS_DIT_MAX : in integer range 0 to 4095 := 22;
+
+ -- minimum, middle and maximum widths of "ONE"
+ -- middle is used for Tx
+ -- min and max is used for Rx
+ TICKS_DAH_MIN : in integer range 0 to 4095 := 29;
+ TICKS_DAH_MID : in integer range 0 to 4095 := 76;
+ TICKS_DAH_MAX : in integer range 0 to 4095 := 124;
+
+ -- minimum, middle and maximum widths of gap between bits
+ -- middle is used for Tx
+ -- min and max is used for Rx
+ TICKS_BITGAP_MIN : in integer range 0 to 4095 := 11;
+ TICKS_BITGAP_MID : in integer range 0 to 4095 := 43;
+ TICKS_BITGAP_MAX : in integer range 0 to 4095 := 75;
+
+ -- control signals
+ nbitsin : in integer range 0 to 63;
+ datain : in std_logic_vector(63 downto 0);
+ send : in std_logic;
+ busy : out std_logic;
+
+ nbitsout : out integer range 0 to 63;
+ dataout : out std_logic_vector(63 downto 0);
+ datavalid : out std_logic;
+ error : out std_logic;
+
+ -- serial signals
+ serialin : in std_logic;
+ serialout : out std_logic
+
+ );
+end entity endeavour_master;
+
+architecture behavioural of endeavour_master is
+
+ signal reg_serialin1 : std_logic;
+ signal reg_serialin : std_logic;
+
+ type fsm_wr_t is (idle, senddata, sendbit, sendgap, sendendgap);
+ signal fsm_wr : fsm_wr_t := idle;
+
+ type fsm_rd_t is (idle, waitdata, waitbit, readbit, waitgap);
+ signal fsm_rd : fsm_rd_t := idle;
+
+ signal reg_nbitsin : integer range 0 to 63 := 0;
+ signal reg_datain : std_logic_vector(63 downto 0) := (others => '0');
+ signal reg_busy : std_logic;
+
+ signal reg_nbitsout : integer range 0 to 63 := 0;
+ signal reg_dataout : std_logic_vector(63 downto 0) := (others => '0');
+ signal reg_datavalid : std_logic;
+ signal reg_error : std_logic;
+
+begin
+ busy <= reg_busy;
+ datavalid <= reg_datavalid;
+ error <= reg_error;
+
+ nbitsout <= reg_nbitsout;
+ dataout <= reg_dataout;
+
+ --
+ -- Register serialin on clock
+ --
+ process (clock)
+ begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ reg_serialin1 <= '0';
+ reg_serialin <= '0';
+ else
+ reg_serialin1 <= serialin;
+ reg_serialin <= reg_serialin1;
+ end if;
+ end if;
+ end process;
+
+ --
+ -- The FSM for writing data to AMAC
+ --
+ process (clock)
+ variable writebit : std_logic;
+ variable counter : integer range 0 to 4095 := 0;
+ begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ fsm_wr <= idle;
+ reg_nbitsin <= 0;
+ reg_datain <= (others => '0');
+ reg_busy <= '0';
+ counter := 0;
+ serialout <= '0';
+ else
+ case fsm_wr is
+ when idle =>
+ serialout <= '0';
+
+ if send = '1' then
+ -- latch data to send
+ reg_datain <= datain;
+ reg_nbitsin <= nbitsin;
+ reg_busy <= '1';
+ fsm_wr <= senddata;
+ else
+ reg_busy <= '0';
+ fsm_wr <= idle;
+ end if;
+
+ when senddata =>
+ reg_busy <= '1';
+ if reg_nbitsin = 0 then
+ serialout <= '0';
+ counter := TICKS_QUIESCENT;
+ fsm_wr <= sendendgap;
+ else
+ writebit := reg_datain(reg_nbitsin-1);
+ reg_nbitsin <= reg_nbitsin - 1;
+ if writebit = '0' then
+ counter := TICKS_DIT_MID;
+ else
+ counter := TICKS_DAH_MID;
+ end if;
+ fsm_wr <= sendbit;
+ end if;
+
+ when sendbit =>
+ reg_busy <= '1';
+ if counter = 0 then
+ fsm_wr <= sendgap;
+ serialout <= '0';
+ counter := TICKS_BITGAP_MID;
+ else
+ fsm_wr <= sendbit;
+ serialout <= '1';
+ counter := counter-1;
+ end if;
+
+ when sendgap =>
+ reg_busy <= '1';
+ serialout <= '0';
+ if counter = 0 then
+ fsm_wr <= senddata;
+ else
+ fsm_wr <= sendgap;
+ counter := counter-1;
+ end if;
+
+ when sendendgap =>
+ reg_busy <= '1';
+ serialout <= '0';
+ if counter = 0 then
+ fsm_wr <= idle;
+ else
+ fsm_wr <= sendendgap;
+ counter := counter-1;
+ end if;
+
+ when others =>
+ fsm_wr <= idle;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ --
+ -- The FSM for receiving data from AMAC
+ --
+ process (clock)
+ variable counter : integer range 0 to 4095 := 0;
+ begin
+ if rising_edge(clock) then
+ if reset = '1' or send='1' then
+ fsm_rd <= idle;
+ reg_nbitsout <= 0;
+ reg_dataout <= (others => '0');
+ reg_datavalid <= '0';
+ reg_error <= '0';
+ counter := 0;
+ else
+ case fsm_rd is
+ when idle =>
+ if reg_serialin = '0' then
+ counter := counter+1;
+ else -- reg_serialin = '1'
+ counter := 0;
+ end if;
+
+ if counter = 16 then
+ fsm_rd <= waitdata;
+ end if;
+
+ when waitdata =>
+ if reg_serialin = '1' then
+ counter := 1;
+ fsm_rd <= readbit;
+ end if;
+
+ when waitbit =>
+ if reg_serialin = '1' then
+ counter := counter+1;
+ if (counter = 256) then -- idle 1 hack for PBv3 mass tester
+ reg_datavalid <= '1';
+ fsm_rd <= idle;
+ end if;
+ else
+ fsm_rd <= readbit;
+ end if;
+
+ when readbit =>
+ if (TICKS_DIT_MIN < counter) and (counter < TICKS_DIT_MAX) then
+ reg_dataout <= reg_dataout(62 downto 0) & '0';
+ reg_nbitsout <= reg_nbitsout + 1;
+ reg_error <= '0';
+ elsif (TICKS_DAH_MIN < counter) and (counter < TICKS_DAH_MAX) then
+ reg_dataout <= reg_dataout(62 downto 0) & '1';
+ reg_nbitsout <= reg_nbitsout + 1;
+ reg_error <= '0';
+ else
+ reg_error <= '1';
+ end if;
+ counter := 0;
+ fsm_rd <= waitgap;
+
+ when waitgap =>
+ if reg_serialin = '1' then
+ counter := 1;
+ fsm_rd <= waitbit;
+ else
+ counter := counter + 1;
+ if counter > TICKS_QUIESCENT then
+ reg_datavalid <= '1';
+ fsm_rd <= idle;
+ end if;
+ end if;
+
+ when others =>
+ fsm_rd <= idle;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end behavioural;
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/hdl/smooth.vhd b/ip_repo/endeavour_axi_controller_1.0/hdl/smooth.vhd
new file mode 100644
index 0000000..3105beb
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/hdl/smooth.vhd
@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+----
+-- Entity: smooth
+-- Author: Karol Krizka <kkrizka@gmail.com>
+--
+-- Simple smoothing for over-sampled input.
+--
+-- The algorithm decides on the value of bit X by doing majority vote on the
+-- input bits X-1,X,X+1.
+--
+-- The following decribes the behaviour for all cases:
+--
+-- 110 -> 1
+-- 011 -> 1
+-- 111 -> 1
+-- 101 -> 1
+-- 001 -> 0
+-- 100 -> 0
+-- 000 -> 0
+-- 010 -> 0
+--
+----
+entity smooth is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+
+ input : in std_logic;
+ output : out std_logic
+ );
+end entity smooth;
+
+architecture behavioural of smooth is
+
+ signal vote01 : std_logic;
+ signal vote12 : std_logic;
+ signal vote02 : std_logic;
+
+ signal reg_data : std_logic_vector(2 downto 0) := (others => '0');
+
+begin
+ process (clock)
+ begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ reg_data <= (others => '0');
+ else
+ reg_data <= reg_data(1 downto 0) & input;
+ end if;
+ end if;
+ end process;
+
+
+ vote01 <= not (reg_data(0) and reg_data(1));
+ vote12 <= not (reg_data(1) and reg_data(2));
+ vote02 <= not (reg_data(0) and reg_data(2));
+
+ output <= not (vote01 and vote12 and vote02);
+
+end behavioural;
+
diff --git a/ip_repo/endeavour_axi_controller_1.0/xgui/endeavour_axi_controller_v1_0.tcl b/ip_repo/endeavour_axi_controller_1.0/xgui/endeavour_axi_controller_v1_0.tcl
new file mode 100644
index 0000000..d8bf174
--- /dev/null
+++ b/ip_repo/endeavour_axi_controller_1.0/xgui/endeavour_axi_controller_v1_0.tcl
@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+ set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+ set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+ set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+ ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to validate C_S00_AXI_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to validate C_S00_AXI_HIGHADDR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/.gitignore b/pbv3_mass_test_adapter_firmware.linux/.gitignore
new file mode 100644
index 0000000..4547901
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/.gitignore
@@ -0,0 +1,12 @@
+*/*/config.old
+*/*/rootfs_config.old
+build/
+images/linux/
+pre-built/linux/
+.petalinux/*
+!.petalinux/metadata
+*.o
+*.jou
+*.log
+project-spec/meta-plnx-generated/
+/components/plnx_workspace
diff --git a/pbv3_mass_test_adapter_firmware.linux/.petalinux/metadata b/pbv3_mass_test_adapter_firmware.linux/.petalinux/metadata
new file mode 100644
index 0000000..d1f37bf
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/.petalinux/metadata
@@ -0,0 +1,2 @@
+PETALINUX_VER=2019.1
+project_id=d845ad6c6cc7af4e99c38124adbe7614
diff --git a/pbv3_mass_test_adapter_firmware.linux/config.project b/pbv3_mass_test_adapter_firmware.linux/config.project
new file mode 100644
index 0000000..3d5b675
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/config.project
@@ -0,0 +1,11 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# PetaLinux SDK Project Configuration
+#
+CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH=""
+
+#
+# Subsystems of the project
+#
+CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y
+CONFIG_PROJECT_SUBSYSTEMS=y
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/attributes b/pbv3_mass_test_adapter_firmware.linux/project-spec/attributes
new file mode 100644
index 0000000..7e67f9d
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/attributes
@@ -0,0 +1,7 @@
+#Virtual Providers
+
+
+
+#defconfigs
+
+UBOOT_DEFAULT_DEFCONFIG="zynq_zc702_config"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/config b/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/config
new file mode 100644
index 0000000..769acd1
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/config
@@ -0,0 +1,257 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# misc/config System Configuration
+#
+CONFIG_SUBSYSTEM_TYPE_LINUX=y
+CONFIG_SYSTEM_ZYNQ=y
+
+#
+# Linux Components Selection
+#
+CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQ_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
+CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
+CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
+
+#
+# Auto Config Settings
+#
+CONFIG_SUBSYSTEM_AUTOCONFIG_FSBL=y
+CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
+# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
+CONFIG_SUBSYSTEM_DEVICE_TREE_INCLUDE_DIR="${STAGING_KERNEL_DIR}/include"
+CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL=y
+CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT=y
+CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
+CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="ps7_cortexa9_0"
+CONFIG_SUBSYSTEM_PROCESSOR_PS7_CORTEXA9_0_SELECT=y
+CONFIG_SUBSYSTEM_ARCH_ARM=y
+
+#
+# Memory Settings
+#
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_MEMORY_SIMPLE_SELECT is not set
+# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x40000000
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x400000
+CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PS7_DDR_0"
+
+#
+# Serial Settings
+#
+CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_SELECT=y
+# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_9600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_28800 is not set
+CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_115200=y
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_230400 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_460800 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_BAUDRATE_921600 is not set
+CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_1"
+
+#
+# Ethernet Settings
+#
+CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_SELECT=y
+# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC_AUTO is not set
+CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC="00:0a:35:00:1e:53"
+CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_USE_DHCP=y
+
+#
+# Flash Settings
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
+
+#
+# partition 0
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_NAME="boot"
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x500000
+
+#
+# partition 1
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_NAME="bootenv"
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_SIZE=0x20000
+
+#
+# partition 2
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_NAME="kernel"
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0xA80000
+
+#
+# partition 3
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="spare"
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x0
+
+#
+# partition 4
+#
+CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART4_NAME=""
+CONFIG_SUBSYSTEM_FLASH_IP_NAME="ps7_qspi_0"
+
+#
+# SD/SDIO Settings
+#
+CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_0_SELECT=y
+# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_SD_PS7_SD_0_SELECT=y
+
+#
+# RTC Settings
+#
+CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT=y
+CONFIG_SUBSYSTEM_USB_PS7_USB_0_SELECT=y
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
+
+#
+# boot image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
+
+#
+# u-boot env partition settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
+
+#
+# kernel image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub"
+
+#
+# jffs2 rootfs image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2"
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
+
+#
+# dtb image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
+CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
+
+#
+# DTG Settings
+#
+CONFIG_SUBSYSTEM_MACHINE_NAME="template"
+
+#
+# Kernel Bootargs
+#
+# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
+CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlyprintk root=/dev/nfs nfsroot=128.3.2.121:/opt/petalinux/pbv3_mass_tester,v4,tcp ip=dhcp rw uio_pdrv_genirq.of_id=generic-uio"
+CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
+# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
+# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
+
+#
+# FPGA Manager
+#
+# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
+
+#
+# u-boot Configuration
+#
+CONFIG_SUBSYSTEM_UBOOT_CONFIG_PETALINUX=y
+# CONFIG_SUBSYSTEM_UBOOT_CONFIG_OTHER is not set
+CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="zynq_zc702_config"
+CONFIG_SUBSYSTEM_NETBOOT_OFFSET=0x10000000
+CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO"
+
+#
+# Image Packaging Configuration
+#
+# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
+# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
+# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
+CONFIG_SUBSYSTEM_ROOTFS_NFS=y
+# CONFIG_SUBSYSTEM_ROOTFS_SD is not set
+# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
+CONFIG_SUBSYSTEM_NFSROOT_DIR="/opt/petalinux/pbv3_mass_tester,v4"
+CONFIG_SUBSYSTEM_NFSSERVER_IP="128.3.2.121"
+CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
+CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
+# CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT is not set
+
+#
+# Firmware Version Configuration
+#
+CONFIG_SUBSYSTEM_HOSTNAME="pbv3_mass_test_adapter_firmware.linux"
+CONFIG_SUBSYSTEM_PRODUCT="pbv3_mass_test_adapter_firmware.linux"
+CONFIG_SUBSYSTEM_FW_VERSION="1.00"
+
+#
+# Yocto Settings
+#
+CONFIG_YOCTO_MACHINE_NAME="plnx-zynq7"
+
+#
+# TMPDIR Location
+#
+CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
+
+#
+# Parallel thread execution
+#
+CONFIG_YOCTO_BB_NUMBER_THREADS=""
+CONFIG_YOCTO_PARALLEL_MAKE=""
+
+#
+# Add pre-mirror url
+#
+CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads"
+
+#
+# Local sstate feeds settings
+#
+
+#
+# Default sstate feeds ${PETALINUX}/components/yocto always added
+#
+CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
+# CONFIG_YOCTO_ENABLE_DEBUG_TWEAKS is not set
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
+
+#
+# Network sstate feeds URL
+#
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/arm/sstate-cache"
+# CONFIG_YOCTO_BB_NO_NETWORK is not set
+
+#
+# User Layers
+#
+CONFIG_USER_LAYER_0=""
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/rootfs_config b/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/rootfs_config
new file mode 100644
index 0000000..ae93385
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/configs/rootfs_config
@@ -0,0 +1,3952 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Configuration
+#
+CONFIG_system-zynq=y
+
+#
+# Filesystem Packages
+#
+
+#
+# admin
+#
+
+#
+# sudo
+#
+# CONFIG_sudo is not set
+# CONFIG_sudo-dbg is not set
+# CONFIG_sudo-dev is not set
+
+#
+# base
+#
+
+#
+# base-files
+#
+# CONFIG_base-files is not set
+# CONFIG_base-files-dbg is not set
+# CONFIG_base-files-dev is not set
+
+#
+# base-passwd
+#
+# CONFIG_base-passwd is not set
+# CONFIG_base-passwd-dev is not set
+# CONFIG_base-passwd-dbg is not set
+# CONFIG_base-passwd-update is not set
+
+#
+# bc
+#
+# CONFIG_bc is not set
+# CONFIG_bc-dev is not set
+# CONFIG_bc-dbg is not set
+
+#
+# busybox
+#
+CONFIG_busybox=y
+# CONFIG_busybox-udhcpd is not set
+# CONFIG_busybox-httpd is not set
+# CONFIG_busybox-dbg is not set
+# CONFIG_busybox-inetd is not set
+# CONFIG_busybox-dev is not set
+# CONFIG_busybox-hwclock is not set
+# CONFIG_busybox-udhcpc is not set
+# CONFIG_busybox-syslog is not set
+
+#
+# cpio
+#
+# CONFIG_cpio is not set
+# CONFIG_cpio-dbg is not set
+# CONFIG_cpio-dev is not set
+# CONFIG_cpio-rmt is not set
+
+#
+# dbus
+#
+# CONFIG_dbus is not set
+# CONFIG_dbus-lib is not set
+# CONFIG_dbus-dev is not set
+# CONFIG_dbus-dbg is not set
+
+#
+# dbus-glib
+#
+# CONFIG_dbus-glib is not set
+# CONFIG_dbus-glib-bash-completion is not set
+# CONFIG_dbus-glib-tests is not set
+# CONFIG_dbus-glib-dbg is not set
+# CONFIG_dbus-glib-dev is not set
+
+#
+# dbus-wait
+#
+# CONFIG_dbus-wait is not set
+# CONFIG_dbus-wait-dbg is not set
+# CONFIG_dbus-wait-dev is not set
+
+#
+# diffutils
+#
+# CONFIG_diffutils is not set
+# CONFIG_diffutils-dbg is not set
+# CONFIG_diffutils-dev is not set
+
+#
+# dnf
+#
+# CONFIG_dnf is not set
+
+#
+# e2fsprogs
+#
+# CONFIG_e2fsprogs is not set
+# CONFIG_e2fsprogs-resize2fs is not set
+# CONFIG_e2fsprogs-badblocks is not set
+# CONFIG_e2fsprogs-e2fsck is not set
+# CONFIG_libss is not set
+# CONFIG_libcomerr is not set
+# CONFIG_libext2fs is not set
+# CONFIG_e2fsprogs-dev is not set
+# CONFIG_e2fsprogs-tune2fs is not set
+# CONFIG_libe2p is not set
+# CONFIG_e2fsprogs-mke2fs is not set
+# CONFIG_e2fsprogs-dbg is not set
+
+#
+# ed
+#
+# CONFIG_ed is not set
+# CONFIG_ed-dev is not set
+# CONFIG_ed-dbg is not set
+
+#
+# elfutils
+#
+# CONFIG_elfutils is not set
+# CONFIG_libdw is not set
+# CONFIG_elfutils-dev is not set
+# CONFIG_elfutils-binutils is not set
+# CONFIG_libelf is not set
+# CONFIG_libasm is not set
+# CONFIG_elfutils-dbg is not set
+
+#
+# formfactor
+#
+# CONFIG_formfactor is not set
+# CONFIG_formfactor-dbg is not set
+# CONFIG_formfactor-dev is not set
+
+#
+# i2c-tools
+#
+CONFIG_i2c-tools=y
+# CONFIG_i2c-tools-dev is not set
+# CONFIG_i2c-tools-dbg is not set
+CONFIG_i2c-tools-misc=y
+
+#
+# init-ifupdown
+#
+# CONFIG_init-ifupdown is not set
+# CONFIG_init-ifupdown-dev is not set
+# CONFIG_init-ifupdown-dbg is not set
+
+#
+# initscripts
+#
+# CONFIG_initscripts is not set
+# CONFIG_initscripts-dev is not set
+# CONFIG_initscripts-dbg is not set
+# CONFIG_initscripts-functions is not set
+
+#
+# iproute2
+#
+# CONFIG_iproute2 is not set
+# CONFIG_iproute2-tc is not set
+# CONFIG_iproute2-nstat is not set
+# CONFIG_iproute2-dev is not set
+# CONFIG_iproute2-lnstat is not set
+# CONFIG_iproute2-rtacct is not set
+# CONFIG_iproute2-ss is not set
+# CONFIG_iproute2-ifstat is not set
+# CONFIG_iproute2-genl is not set
+# CONFIG_iproute2-bash-completion is not set
+# CONFIG_iproute2-dbg is not set
+
+#
+# kmod
+#
+# CONFIG_kmod is not set
+# CONFIG_kmod-dbg is not set
+# CONFIG_libkmod is not set
+# CONFIG_kmod-dev is not set
+# CONFIG_kmod-bash-completion is not set
+
+#
+# lsbinitscripts
+#
+# CONFIG_lsbinitscripts is not set
+# CONFIG_lsbinitscripts-dev is not set
+# CONFIG_lsbinitscripts-dbg is not set
+
+#
+# modutils-initscripts
+#
+# CONFIG_modutils-initscripts is not set
+# CONFIG_modutils-initscripts-dev is not set
+# CONFIG_modutils-initscripts-dbg is not set
+
+#
+# mtd-utils
+#
+CONFIG_mtd-utils=y
+# CONFIG_mtd-utils-ubifs is not set
+# CONFIG_mtd-utils-dev is not set
+# CONFIG_mtd-utils-jffs2 is not set
+# CONFIG_mtd-utils-dbg is not set
+# CONFIG_mtd-utils-misc is not set
+
+#
+# netbase
+#
+# CONFIG_netbase is not set
+# CONFIG_netbase-dbg is not set
+# CONFIG_netbase-dev is not set
+
+#
+# opkg
+#
+# CONFIG_opkg is not set
+# CONFIG_opkg-dev is not set
+# CONFIG_libopkg is not set
+# CONFIG_opkg-dbg is not set
+
+#
+# opkg-utils
+#
+# CONFIG_opkg-utils is not set
+# CONFIG_update-alternatives-opkg is not set
+# CONFIG_opkg-utils-dbg is not set
+
+#
+# procps
+#
+# CONFIG_procps is not set
+# CONFIG_procps-dbg is not set
+# CONFIG_procps-dev is not set
+
+#
+# pseudo
+#
+# CONFIG_pseudo is not set
+# CONFIG_pseudo-dbg is not set
+# CONFIG_pseudo-dev is not set
+
+#
+# psplash
+#
+# CONFIG_psplash is not set
+# CONFIG_psplash-dbg is not set
+# CONFIG_psplash-default is not set
+# CONFIG_psplash-dev is not set
+
+#
+# quota
+#
+# CONFIG_quota is not set
+# CONFIG_quota-dev is not set
+# CONFIG_quota-dbg is not set
+
+#
+# shared-mime-info
+#
+# CONFIG_shared-mime-info is not set
+# CONFIG_shared-mime-info-dev is not set
+# CONFIG_shared-mime-info-dbg is not set
+# CONFIG_shared-mime-info-data is not set
+
+#
+# shell
+#
+
+#
+# bash
+#
+# CONFIG_bash is not set
+# CONFIG_bash-dev is not set
+# CONFIG_bash-dbg is not set
+
+#
+# sysvinit
+#
+# CONFIG_sysvinit is not set
+# CONFIG_sysvinit-pidof is not set
+# CONFIG_sysvinit-dbg is not set
+# CONFIG_sysvinit-dev is not set
+# CONFIG_sysvinit-sulogin is not set
+
+#
+# tar
+#
+# CONFIG_tar is not set
+# CONFIG_tar-dev is not set
+# CONFIG_tar-rmt is not set
+# CONFIG_tar-dbg is not set
+
+#
+# tzdata
+#
+# CONFIG_tzdata is not set
+# CONFIG_tzdata-asia is not set
+# CONFIG_tzdata-arctic is not set
+# CONFIG_tzdata-posix is not set
+# CONFIG_tzdata-africa is not set
+# CONFIG_tzdata-europe is not set
+# CONFIG_tzdata-americas is not set
+# CONFIG_tzdata-antarctica is not set
+# CONFIG_tzdata-atlantic is not set
+# CONFIG_tzdata-misc is not set
+# CONFIG_tzdata-right is not set
+# CONFIG_tzdata-pacific is not set
+# CONFIG_tzdata-australia is not set
+
+#
+# update-rc.d
+#
+# CONFIG_update-rc.d is not set
+# CONFIG_update-rc.d-dev is not set
+# CONFIG_update-rc.d-dbg is not set
+
+#
+# usbutils
+#
+# CONFIG_usbutils is not set
+# CONFIG_usbutils-dbg is not set
+# CONFIG_usbutils-dev is not set
+
+#
+# util-linux
+#
+# CONFIG_util-linux is not set
+# CONFIG_util-linux-dev is not set
+# CONFIG_util-linux-fsck.cramfs is not set
+# CONFIG_util-linux-swaponoff is not set
+# CONFIG_util-linux-sfdisk is not set
+# CONFIG_util-linux-uuidd is not set
+# CONFIG_util-linux-getopt is not set
+# CONFIG_util-linux-findfs is not set
+# CONFIG_util-linux-mountpoint is not set
+# CONFIG_util-linux-hwclock is not set
+# CONFIG_util-linux-mcookie is not set
+# CONFIG_util-linux-dbg is not set
+# CONFIG_util-linux-mkfs.cramfs is not set
+# CONFIG_util-linux-blkid is not set
+# CONFIG_util-linux-sulogin is not set
+# CONFIG_util-linux-losetup is not set
+# CONFIG_util-linux-fstrim is not set
+# CONFIG_util-linux-cfdisk is not set
+# CONFIG_util-linux-agetty is not set
+# CONFIG_util-linux-bash-completion is not set
+# CONFIG_util-linux-lscpu is not set
+# CONFIG_util-linux-prlimit is not set
+# CONFIG_util-linux-umount is not set
+# CONFIG_util-linux-partx is not set
+# CONFIG_util-linux-mkfs is not set
+# CONFIG_util-linux-readprofile is not set
+# CONFIG_util-linux-uuidgen is not set
+# CONFIG_util-linux-mount is not set
+# CONFIG_util-linux-fdisk is not set
+# CONFIG_util-linux-fsck is not set
+
+#
+# utils
+#
+
+#
+# shadow
+#
+# CONFIG_shadow is not set
+# CONFIG_shadow-base is not set
+# CONFIG_shadow-dev is not set
+# CONFIG_shadow-dbg is not set
+
+#
+# xz
+#
+# CONFIG_xz is not set
+# CONFIG_xz-dev is not set
+# CONFIG_xz-dbg is not set
+# CONFIG_liblzma is not set
+
+#
+# baseutils
+#
+
+#
+# shadow-securetty
+#
+# CONFIG_shadow-securetty is not set
+# CONFIG_shadow-securetty-dev is not set
+# CONFIG_shadow-securetty-dbg is not set
+
+#
+# console
+#
+
+#
+# network
+#
+
+#
+# canutils
+#
+CONFIG_canutils=y
+# CONFIG_canutils-dbg is not set
+# CONFIG_canutils-dev is not set
+
+#
+# curl
+#
+# CONFIG_curl is not set
+# CONFIG_curl-dev is not set
+# CONFIG_libcurl is not set
+# CONFIG_curl-dbg is not set
+
+#
+# dropbear
+#
+# CONFIG_dropbear is not set
+# CONFIG_dropbear-dev is not set
+# CONFIG_dropbear-dbg is not set
+
+#
+# ethtool
+#
+# CONFIG_ethtool is not set
+# CONFIG_ethtool-dbg is not set
+# CONFIG_ethtool-dev is not set
+
+#
+# lrzsz
+#
+# CONFIG_lrzsz is not set
+# CONFIG_lrzsz-dbg is not set
+# CONFIG_lrzsz-dev is not set
+
+#
+# mailx
+#
+# CONFIG_mailx is not set
+# CONFIG_mailx-dbg is not set
+# CONFIG_mailx-dev is not set
+
+#
+# minicom
+#
+# CONFIG_minicom is not set
+# CONFIG_minicom-dbg is not set
+# CONFIG_minicom-dev is not set
+
+#
+# nfs-utils
+#
+# CONFIG_nfs-utils is not set
+# CONFIG_nfs-utils-dev is not set
+CONFIG_nfs-utils-client=y
+# CONFIG_nfs-utils-stats is not set
+# CONFIG_nfs-utils-dbg is not set
+
+#
+# openssh
+#
+# CONFIG_openssh is not set
+# CONFIG_openssh-misc is not set
+# CONFIG_openssh-dbg is not set
+# CONFIG_openssh-sshd is not set
+# CONFIG_openssh-keygen is not set
+# CONFIG_openssh-ssh is not set
+# CONFIG_openssh-dev is not set
+# CONFIG_openssh-sftp is not set
+CONFIG_openssh-sftp-server=y
+# CONFIG_openssh-scp is not set
+
+#
+# ppp
+#
+# CONFIG_ppp is not set
+# CONFIG_ppp-minconn is not set
+# CONFIG_ppp-l2tp is not set
+# CONFIG_ppp-dev is not set
+# CONFIG_ppp-password is not set
+# CONFIG_ppp-radius is not set
+# CONFIG_ppp-tools is not set
+# CONFIG_ppp-dbg is not set
+# CONFIG_ppp-oe is not set
+# CONFIG_ppp-oa is not set
+# CONFIG_ppp-winbind is not set
+
+#
+# rpcbind
+#
+# CONFIG_rpcbind is not set
+# CONFIG_rpcbind-dbg is not set
+# CONFIG_rpcbind-dev is not set
+
+#
+# rsync
+#
+CONFIG_rsync=y
+# CONFIG_rsync-dev is not set
+# CONFIG_rsync-dbg is not set
+
+#
+# socat
+#
+# CONFIG_socat is not set
+# CONFIG_socat-dbg is not set
+# CONFIG_socat-dev is not set
+
+#
+# subversion
+#
+# CONFIG_subversion is not set
+# CONFIG_subversion-dev is not set
+# CONFIG_subversion-dbg is not set
+
+#
+# tcp-wrappers
+#
+# CONFIG_tcp-wrappers is not set
+# CONFIG_tcp-wrappers-dbg is not set
+# CONFIG_libwrap-dev is not set
+# CONFIG_libwrap is not set
+
+#
+# wget
+#
+# CONFIG_wget is not set
+# CONFIG_wget-dev is not set
+# CONFIG_wget-dbg is not set
+
+#
+# tools
+#
+
+#
+# parted
+#
+# CONFIG_parted is not set
+# CONFIG_parted-dbg is not set
+# CONFIG_parted-dev is not set
+
+#
+# utils
+#
+
+#
+# alsa-utils
+#
+# CONFIG_alsa-utils is not set
+# CONFIG_alsa-utils-aconnect is not set
+# CONFIG_alsa-utils-alsaloop is not set
+# CONFIG_alsa-utils-aseqdump is not set
+# CONFIG_alsa-utils-aplay is not set
+# CONFIG_alsa-utils-iecset is not set
+# CONFIG_alsa-utils-alsaucm is not set
+# CONFIG_alsa-utils-dev is not set
+# CONFIG_alsa-utils-alsamixer is not set
+# CONFIG_alsa-utils-amixer is not set
+# CONFIG_alsa-utils-speakertest is not set
+# CONFIG_alsa-utils-alsactl is not set
+# CONFIG_alsa-utils-dbg is not set
+# CONFIG_alsa-utils-midi is not set
+# CONFIG_alsa-utils-aseqnet is not set
+# CONFIG_alsa-utils-alsatplg is not set
+
+#
+# bash-completion
+#
+# CONFIG_bash-completion is not set
+# CONFIG_bash-completion-dev is not set
+# CONFIG_bash-completion-extra is not set
+# CONFIG_bash-completion-dbg is not set
+
+#
+# bzip2
+#
+# CONFIG_bzip2 is not set
+# CONFIG_libbz2 is not set
+# CONFIG_bzip2-dbg is not set
+# CONFIG_bzip2-dev is not set
+
+#
+# file
+#
+# CONFIG_file is not set
+# CONFIG_file-dbg is not set
+# CONFIG_file-dev is not set
+
+#
+# findutils
+#
+# CONFIG_findutils is not set
+# CONFIG_findutils-dbg is not set
+# CONFIG_findutils-dev is not set
+
+#
+# gawk
+#
+# CONFIG_gawk is not set
+# CONFIG_gawk-dbg is not set
+# CONFIG_gawk-dev is not set
+
+#
+# git
+#
+# CONFIG_git is not set
+# CONFIG_git-bash-completion is not set
+# CONFIG_gitweb is not set
+# CONFIG_git-perltools is not set
+# CONFIG_git-dev is not set
+# CONFIG_git-dbg is not set
+
+#
+# grep
+#
+# CONFIG_grep is not set
+# CONFIG_grep-dbg is not set
+# CONFIG_grep-dev is not set
+
+#
+# groff
+#
+# CONFIG_groff is not set
+# CONFIG_groff-dev is not set
+# CONFIG_groff-dbg is not set
+
+#
+# gzip
+#
+# CONFIG_gzip is not set
+# CONFIG_gzip-dbg is not set
+# CONFIG_gzip-dev is not set
+
+#
+# hdparm
+#
+# CONFIG_hdparm is not set
+# CONFIG_wiper is not set
+# CONFIG_hdparm-dbg is not set
+# CONFIG_hdparm-dev is not set
+
+#
+# less
+#
+# CONFIG_less is not set
+# CONFIG_less-dev is not set
+# CONFIG_less-dbg is not set
+
+#
+# lsb
+#
+# CONFIG_lsb is not set
+# CONFIG_lsb-dbg is not set
+# CONFIG_lsb-dev is not set
+
+#
+# ltp
+#
+# CONFIG_ltp is not set
+# CONFIG_ltp-dev is not set
+# CONFIG_ltp-dbg is not set
+
+#
+# man
+#
+# CONFIG_man is not set
+
+#
+# man-pages
+#
+# CONFIG_man-pages is not set
+# CONFIG_man-pages-dbg is not set
+# CONFIG_man-pages-dev is not set
+
+#
+# mc
+#
+# CONFIG_mc is not set
+# CONFIG_mc-dev is not set
+# CONFIG_mc-helpers-perl is not set
+# CONFIG_mc-helpers is not set
+# CONFIG_mc-fish is not set
+# CONFIG_mc-dbg is not set
+
+#
+# pciutils
+#
+CONFIG_pciutils=y
+# CONFIG_pciutils-ids is not set
+# CONFIG_pciutils-dev is not set
+# CONFIG_libpci is not set
+# CONFIG_pciutils-dbg is not set
+
+#
+# pkgconfig
+#
+# CONFIG_pkgconfig is not set
+# CONFIG_pkgconfig-dbg is not set
+# CONFIG_pkgconfig-dev is not set
+
+#
+# screen
+#
+# CONFIG_screen is not set
+# CONFIG_screen-dbg is not set
+# CONFIG_screen-dev is not set
+
+#
+# sed
+#
+# CONFIG_sed is not set
+# CONFIG_sed-dbg is not set
+# CONFIG_sed-dev is not set
+
+#
+# setserial
+#
+# CONFIG_setserial is not set
+# CONFIG_setserial-dev is not set
+# CONFIG_setserial-dbg is not set
+
+#
+# smartmontools
+#
+# CONFIG_smartmontools is not set
+# CONFIG_smartmontools-dbg is not set
+# CONFIG_smartmontools-dev is not set
+
+#
+# strace
+#
+# CONFIG_strace is not set
+# CONFIG_strace-dev is not set
+# CONFIG_strace-dbg is not set
+
+#
+# sysstat
+#
+# CONFIG_sysstat is not set
+# CONFIG_sysstat-dev is not set
+# CONFIG_sysstat-dbg is not set
+
+#
+# texinfo
+#
+# CONFIG_texinfo is not set
+# CONFIG_texinfo-dev is not set
+# CONFIG_info is not set
+# CONFIG_texinfo-dbg is not set
+
+#
+# unzip
+#
+# CONFIG_unzip is not set
+# CONFIG_unzip-dbg is not set
+# CONFIG_unzip-dev is not set
+
+#
+# vim
+#
+CONFIG_vim=y
+CONFIG_vim-syntax=y
+# CONFIG_vim-dev is not set
+# CONFIG_vim-help is not set
+CONFIG_vim-common=y
+CONFIG_vim-vimrc=y
+# CONFIG_vim-tutor is not set
+# CONFIG_vim-tools is not set
+# CONFIG_vim-dbg is not set
+
+#
+# zip
+#
+# CONFIG_zip is not set
+# CONFIG_zip-dev is not set
+# CONFIG_zip-dbg is not set
+
+#
+# devel
+#
+
+#
+# autoconf
+#
+# CONFIG_autoconf is not set
+# CONFIG_autoconf-dev is not set
+# CONFIG_autoconf-dbg is not set
+
+#
+# automake
+#
+# CONFIG_automake is not set
+# CONFIG_automake-dev is not set
+# CONFIG_automake-dbg is not set
+
+#
+# binutils
+#
+# CONFIG_binutils is not set
+# CONFIG_binutils-dev is not set
+# CONFIG_binutils-dbg is not set
+
+#
+# bison
+#
+# CONFIG_bison is not set
+# CONFIG_bison-dbg is not set
+# CONFIG_bison-dev is not set
+
+#
+# ccache
+#
+# CONFIG_ccache is not set
+# CONFIG_ccache-dbg is not set
+# CONFIG_ccache-dev is not set
+
+#
+# diffstat
+#
+# CONFIG_diffstat is not set
+# CONFIG_diffstat-dbg is not set
+# CONFIG_diffstat-dev is not set
+
+#
+# distcc
+#
+# CONFIG_distcc is not set
+# CONFIG_distcc-dbg is not set
+# CONFIG_distcc-distmon-gnome is not set
+# CONFIG_distcc-dev is not set
+
+#
+# expect
+#
+# CONFIG_expect is not set
+# CONFIG_expect-dbg is not set
+# CONFIG_expect-dev is not set
+
+#
+# flex
+#
+# CONFIG_flex is not set
+# CONFIG_flex-dev is not set
+# CONFIG_flex-dbg is not set
+
+#
+# gmp
+#
+# CONFIG_gmp is not set
+# CONFIG_gmp-dbg is not set
+# CONFIG_gmp-dev is not set
+# CONFIG_libgmpxx is not set
+
+#
+# gnu-config
+#
+# CONFIG_gnu-config is not set
+
+#
+# intltool
+#
+# CONFIG_intltool is not set
+# CONFIG_intltool-dev is not set
+# CONFIG_intltool-dbg is not set
+
+#
+# libarchive
+#
+# CONFIG_libarchive is not set
+# CONFIG_libarchive-dev is not set
+# CONFIG_bsdcpio is not set
+# CONFIG_bsdtar is not set
+# CONFIG_libarchive-dbg is not set
+
+#
+# libcheck
+#
+# CONFIG_libcheck is not set
+# CONFIG_libcheck-dev is not set
+# CONFIG_libcheck-dbg is not set
+
+#
+# libpcre
+#
+# CONFIG_libpcre is not set
+# CONFIG_libpcre-dev is not set
+# CONFIG_libpcreposix is not set
+# CONFIG_libpcre-dbg is not set
+# CONFIG_libpcrecpp is not set
+# CONFIG_pcretest is not set
+# CONFIG_pcregrep is not set
+
+#
+# lsof
+#
+# CONFIG_lsof is not set
+# CONFIG_lsof-dev is not set
+# CONFIG_lsof-dbg is not set
+
+#
+# make
+#
+# CONFIG_make is not set
+# CONFIG_make-dbg is not set
+# CONFIG_make-dev is not set
+
+#
+# mpfr
+#
+# CONFIG_mpfr is not set
+# CONFIG_mpfr-dev is not set
+# CONFIG_mpfr-dbg is not set
+
+#
+# perl
+#
+# CONFIG_perl is not set
+# CONFIG_perl-module-unicore is not set
+# CONFIG_perl-dev is not set
+# CONFIG_perl-misc is not set
+# CONFIG_perl-dbg is not set
+# CONFIG_perl-module-cpan is not set
+# CONFIG_perl-lib is not set
+# CONFIG_perl-modules is not set
+# CONFIG_perl-pod is not set
+
+#
+# python
+#
+
+#
+# python
+#
+# CONFIG_python is not set
+# CONFIG_python-dbg is not set
+# CONFIG_python-mailbox is not set
+# CONFIG_python-resource is not set
+# CONFIG_python-compile is not set
+# CONFIG_python-math is not set
+# CONFIG_python-difflib is not set
+# CONFIG_python-gdbm is not set
+# CONFIG_python-image is not set
+# CONFIG_python-fcntl is not set
+# CONFIG_python-2to3 is not set
+# CONFIG_python-distutils is not set
+# CONFIG_python-terminal is not set
+# CONFIG_python-profile is not set
+# CONFIG_python-mmap is not set
+# CONFIG_python-robotparser is not set
+# CONFIG_python-threading is not set
+# CONFIG_python-zlib is not set
+# CONFIG_python-pickle is not set
+# CONFIG_python-xml is not set
+# CONFIG_python-lang is not set
+# CONFIG_python-email is not set
+# CONFIG_python-contextlib is not set
+# CONFIG_python-netclient is not set
+# CONFIG_python-dev is not set
+# CONFIG_python-idle is not set
+# CONFIG_python-modules is not set
+# CONFIG_python-logging is not set
+# CONFIG_python-xmlrpc is not set
+# CONFIG_python-codecs is not set
+# CONFIG_python-stringold is not set
+# CONFIG_python-argparse is not set
+# CONFIG_python-numbers is not set
+# CONFIG_python-debugger is not set
+# CONFIG_python-html is not set
+# CONFIG_python-shell is not set
+# CONFIG_python-tkinter is not set
+# CONFIG_python-textutils is not set
+# CONFIG_python-compression is not set
+# CONFIG_python-hotshot is not set
+# CONFIG_python-core is not set
+# CONFIG_python-json is not set
+# CONFIG_python-sqlite3 is not set
+# CONFIG_python-plistlib is not set
+# CONFIG_python-curses is not set
+# CONFIG_python-misc is not set
+# CONFIG_python-tests is not set
+# CONFIG_python-netserver is not set
+# CONFIG_python-multiprocessing is not set
+# CONFIG_python-syslog is not set
+# CONFIG_python-pprint is not set
+# CONFIG_python-pkgutil is not set
+# CONFIG_python-mime is not set
+# CONFIG_libpython2 is not set
+# CONFIG_python-smtpd is not set
+# CONFIG_python-pydoc is not set
+# CONFIG_python-bsddb is not set
+# CONFIG_python-re is not set
+# CONFIG_python-ctypes is not set
+# CONFIG_python-compiler is not set
+# CONFIG_python-unittest is not set
+# CONFIG_python-db is not set
+# CONFIG_python-io is not set
+# CONFIG_python-unixadmin is not set
+# CONFIG_python-datetime is not set
+# CONFIG_python-subprocess is not set
+# CONFIG_python-audio is not set
+# CONFIG_python-crypt is not set
+
+#
+# python-nose
+#
+# CONFIG_python-nose is not set
+# CONFIG_python-nose-dbg is not set
+# CONFIG_python-nose-dev is not set
+
+#
+# python-numpy
+#
+# CONFIG_python-numpy is not set
+# CONFIG_python-numpy-dev is not set
+# CONFIG_python-numpy-dbg is not set
+
+#
+# python-scons
+#
+# CONFIG_python-scons is not set
+# CONFIG_python-scons-dev is not set
+# CONFIG_python-scons-dbg is not set
+
+#
+# python3-dbus
+#
+# CONFIG_python3-dbus is not set
+# CONFIG_python3-dbus-dbg is not set
+# CONFIG_python3-dbus-dev is not set
+
+#
+# python3-pygobject
+#
+# CONFIG_python3-pygobject is not set
+# CONFIG_python3-pygobject-dbg is not set
+# CONFIG_python3-pygobject-dev is not set
+
+#
+# quilt
+#
+# CONFIG_quilt is not set
+# CONFIG_quilt-dbg is not set
+# CONFIG_quilt-dev is not set
+# CONFIG_guards is not set
+
+#
+# ruby
+#
+
+#
+# ruby
+#
+# CONFIG_ruby is not set
+# CONFIG_ruby-dev is not set
+# CONFIG_ruby-rdoc is not set
+# CONFIG_ruby-dbg is not set
+
+#
+# run-postinsts
+#
+CONFIG_run-postinsts=y
+# CONFIG_run-postinsts-dbg is not set
+# CONFIG_run-postinsts-dev is not set
+
+#
+# swig
+#
+# CONFIG_swig is not set
+# CONFIG_swig-dev is not set
+# CONFIG_swig-dbg is not set
+
+#
+# tcltk
+#
+
+#
+# tcl
+#
+# CONFIG_tcl is not set
+# CONFIG_tcl-dev is not set
+# CONFIG_tcl-lib is not set
+# CONFIG_tcl-dbg is not set
+
+#
+# vala
+#
+# CONFIG_vala is not set
+# CONFIG_vala-dev is not set
+# CONFIG_vala-dbg is not set
+
+#
+# fonts
+#
+
+#
+# cantarell-fonts
+#
+# CONFIG_cantarell-fonts is not set
+# CONFIG_cantarell-fonts-dbg is not set
+# CONFIG_cantarell-fonts-dev is not set
+
+#
+# kernel
+#
+
+#
+# userland
+#
+
+#
+# kexec-tools
+#
+# CONFIG_kexec-tools is not set
+# CONFIG_kexec-tools-dbg is not set
+# CONFIG_kdump is not set
+# CONFIG_kexec-tools-dev is not set
+# CONFIG_kexec is not set
+# CONFIG_vmcore-dmesg is not set
+
+#
+# libs
+#
+
+#
+# acl
+#
+# CONFIG_acl is not set
+# CONFIG_acl-dev is not set
+# CONFIG_libacl is not set
+# CONFIG_acl-dbg is not set
+
+#
+# apr
+#
+# CONFIG_apr is not set
+# CONFIG_apr-dbg is not set
+# CONFIG_apr-dev is not set
+
+#
+# apr-util
+#
+# CONFIG_apr-util is not set
+# CONFIG_apr-util-dev is not set
+# CONFIG_apr-util-dbg is not set
+
+#
+# attr
+#
+# CONFIG_attr is not set
+# CONFIG_attr-dbg is not set
+# CONFIG_attr-dev is not set
+# CONFIG_libattr is not set
+
+#
+# bluez5
+#
+# CONFIG_bluez5 is not set
+# CONFIG_bluez5-testtools is not set
+# CONFIG_bluez5-dbg is not set
+# CONFIG_bluez5-obex is not set
+# CONFIG_bluez5-dev is not set
+# CONFIG_bluez5-noinst-tools is not set
+
+#
+# boost
+#
+# CONFIG_boost is not set
+# CONFIG_boost-random is not set
+# CONFIG_boost-regex is not set
+# CONFIG_boost-atomic is not set
+# CONFIG_boost-thread is not set
+# CONFIG_boost-serialization is not set
+# CONFIG_boost-filesystem is not set
+# CONFIG_boost-test is not set
+# CONFIG_boost-system is not set
+# CONFIG_boost-graph is not set
+# CONFIG_boost-container is not set
+# CONFIG_boost-date-time is not set
+# CONFIG_boost-math is not set
+# CONFIG_boost-signals is not set
+# CONFIG_boost-wave is not set
+# CONFIG_boost-chrono is not set
+# CONFIG_boost-timer is not set
+# CONFIG_boost-dev is not set
+# CONFIG_boost-program-options is not set
+# CONFIG_boost-iostreams is not set
+# CONFIG_boost-dbg is not set
+# CONFIG_boost-log is not set
+
+#
+# cairo
+#
+# CONFIG_cairo is not set
+# CONFIG_cairo-gobject is not set
+# CONFIG_cairo-script-interpreter is not set
+# CONFIG_cairo-perf-utils is not set
+# CONFIG_cairo-dbg is not set
+# CONFIG_cairo-dev is not set
+
+#
+# db
+#
+# CONFIG_db is not set
+# CONFIG_db-dbg is not set
+# CONFIG_db-cxx is not set
+# CONFIG_db-dev is not set
+# CONFIG_db-bin is not set
+
+#
+# devel
+#
+
+#
+# libyaml
+#
+# CONFIG_libyaml is not set
+# CONFIG_libyaml-dev is not set
+# CONFIG_libyaml-dbg is not set
+
+#
+# expat
+#
+# CONFIG_expat is not set
+# CONFIG_expat-bin is not set
+# CONFIG_expat-dbg is not set
+# CONFIG_expat-dev is not set
+
+#
+# faad2
+#
+# CONFIG_faad2 is not set
+# CONFIG_libfaad-dev is not set
+# CONFIG_faad2-dev is not set
+# CONFIG_faad2-dbg is not set
+# CONFIG_libmp4ff-dev is not set
+# CONFIG_libfaad is not set
+
+#
+# ffmpeg
+#
+# CONFIG_ffmpeg is not set
+# CONFIG_ffmpeg-dbg is not set
+# CONFIG_ffmpeg-dev is not set
+
+#
+# flac
+#
+# CONFIG_flac is not set
+# CONFIG_flac-dbg is not set
+# CONFIG_libflacPLUSPLUS is not set
+# CONFIG_libflac is not set
+# CONFIG_flac-dev is not set
+
+#
+# fontconfig
+#
+# CONFIG_fontconfig is not set
+# CONFIG_fontconfig-utils is not set
+# CONFIG_fontconfig-dbg is not set
+# CONFIG_fontconfig-dev is not set
+
+#
+# freetype
+#
+# CONFIG_freetype is not set
+# CONFIG_freetype-dbg is not set
+# CONFIG_freetype-dev is not set
+
+#
+# gdbm
+#
+# CONFIG_gdbm is not set
+# CONFIG_gdbm-bin is not set
+# CONFIG_gdbm-compat is not set
+# CONFIG_gdbm-dbg is not set
+# CONFIG_gdbm-dev is not set
+
+#
+# gdk-pixbuf
+#
+# CONFIG_gdk-pixbuf is not set
+# CONFIG_gdk-pixbuf-xlib is not set
+# CONFIG_gdk-pixbuf-dbg is not set
+# CONFIG_gdk-pixbuf-dev is not set
+
+#
+# gettext
+#
+# CONFIG_gettext is not set
+# CONFIG_libgettextlib is not set
+# CONFIG_gettext-dev is not set
+# CONFIG_gettext-runtime is not set
+# CONFIG_libgettextsrc is not set
+# CONFIG_gettext-dbg is not set
+
+#
+# glib-networking
+#
+# CONFIG_glib-networking is not set
+# CONFIG_glib-networking-dbg is not set
+# CONFIG_glib-networking-dev is not set
+
+#
+# gobject-introspection
+#
+# CONFIG_gobject-introspection is not set
+# CONFIG_gobject-introspection-dev is not set
+# CONFIG_gobject-introspection-dbg is not set
+
+#
+# gtk+
+#
+# CONFIG_gtkPLUS is not set
+# CONFIG_gtkPLUS-dev is not set
+# CONFIG_gtkPLUS-dbg is not set
+# CONFIG_libgail is not set
+# CONFIG_gtk-demo is not set
+
+#
+# gtk+3
+#
+# CONFIG_gtkPLUS3 is not set
+# CONFIG_gtkPLUS3-demo is not set
+# CONFIG_gtkPLUS3-dev is not set
+# CONFIG_gtkPLUS3-dbg is not set
+
+#
+# harfbuzz
+#
+# CONFIG_harfbuzz is not set
+# CONFIG_harfbuzz-icu is not set
+# CONFIG_harfbuzz-icu-dev is not set
+# CONFIG_harfbuzz-bin is not set
+# CONFIG_harfbuzz-dev is not set
+# CONFIG_harfbuzz-dbg is not set
+
+#
+# libaio
+#
+# CONFIG_libaio is not set
+# CONFIG_libaio-dev is not set
+# CONFIG_libaio-dbg is not set
+
+#
+# libcap
+#
+# CONFIG_libcap is not set
+# CONFIG_libcap-dbg is not set
+# CONFIG_libcap-dev is not set
+# CONFIG_libcap-bin is not set
+
+#
+# libdaemon
+#
+# CONFIG_libdaemon is not set
+# CONFIG_libdaemon-dbg is not set
+# CONFIG_libdaemon-dev is not set
+
+#
+# libdmx
+#
+# CONFIG_libdmx is not set
+# CONFIG_libdmx-dbg is not set
+# CONFIG_libdmx-dev is not set
+
+#
+# libeigen
+#
+# CONFIG_libeigen-dev is not set
+# CONFIG_libeigen-dbg is not set
+
+#
+# libepoxy
+#
+# CONFIG_libepoxy is not set
+# CONFIG_libepoxy-dev is not set
+# CONFIG_libepoxy-dbg is not set
+
+#
+# libevdev
+#
+# CONFIG_libevdev is not set
+# CONFIG_libevdev-dbg is not set
+# CONFIG_libevdev-dev is not set
+
+#
+# libevent
+#
+# CONFIG_libevent is not set
+# CONFIG_libevent-dev is not set
+# CONFIG_libevent-dbg is not set
+
+#
+# libexif
+#
+# CONFIG_libexif is not set
+# CONFIG_libexif-dbg is not set
+# CONFIG_libexif-dev is not set
+
+#
+# libffi
+#
+# CONFIG_libffi is not set
+# CONFIG_libffi-dev is not set
+# CONFIG_libffi-dbg is not set
+
+#
+# libfontenc
+#
+# CONFIG_libfontenc is not set
+# CONFIG_libfontenc-dev is not set
+# CONFIG_libfontenc-dbg is not set
+
+#
+# libgcrypt
+#
+# CONFIG_libgcrypt is not set
+# CONFIG_libgcrypt-dbg is not set
+# CONFIG_libgcrypt-dev is not set
+# CONFIG_dumpsexp-dev is not set
+
+#
+# libgpg-error
+#
+# CONFIG_libgpg-error is not set
+# CONFIG_libgpg-error-dbg is not set
+# CONFIG_libgpg-error-dev is not set
+
+#
+# libgphoto2
+#
+# CONFIG_libgphoto2 is not set
+# CONFIG_libgphoto2-dbg is not set
+# CONFIG_libgphotoport is not set
+# CONFIG_libgphoto2-bin is not set
+# CONFIG_libgphoto2-camlibs is not set
+# CONFIG_libgphoto2-dev is not set
+
+#
+# libgpiod
+#
+# CONFIG_libgpiod is not set
+# CONFIG_libgpiod-dev is not set
+# CONFIG_libgpiod-dbg is not set
+
+#
+# libgudev
+#
+# CONFIG_libgudev is not set
+# CONFIG_libgudev-dev is not set
+# CONFIG_libgudev-dbg is not set
+
+#
+# libhugetlbfs
+#
+# CONFIG_libhugetlbfs is not set
+# CONFIG_libhugetlbfs-tests is not set
+# CONFIG_libhugetlbfs-dbg is not set
+# CONFIG_libhugetlbfs-dev is not set
+
+#
+# libical
+#
+# CONFIG_libical is not set
+# CONFIG_libical-dev is not set
+# CONFIG_libical-dbg is not set
+
+#
+# libice
+#
+# CONFIG_libice is not set
+# CONFIG_libice-dbg is not set
+# CONFIG_libice-dev is not set
+
+#
+# libid3tag
+#
+# CONFIG_libid3tag is not set
+# CONFIG_libid3tag-dbg is not set
+# CONFIG_libid3tag-dev is not set
+
+#
+# libidn
+#
+# CONFIG_libidn is not set
+# CONFIG_idn is not set
+# CONFIG_libidn-dbg is not set
+# CONFIG_libidn-dev is not set
+
+#
+# libinput
+#
+# CONFIG_libinput is not set
+# CONFIG_libinput-dbg is not set
+# CONFIG_libinput-dev is not set
+
+#
+# libjpeg-turbo
+#
+# CONFIG_libjpeg-turbo is not set
+# CONFIG_libturbojpeg is not set
+# CONFIG_jpeg-tools is not set
+# CONFIG_libjpeg-turbo-dbg is not set
+# CONFIG_libjpeg-turbo-dev is not set
+
+#
+# libmetal
+#
+# CONFIG_libmetal is not set
+# CONFIG_libmetal-dbg is not set
+# CONFIG_libmetal-dev is not set
+
+#
+# libmpc
+#
+# CONFIG_libmpc is not set
+# CONFIG_libmpc-dev is not set
+# CONFIG_libmpc-dbg is not set
+
+#
+# libnet
+#
+# CONFIG_libnet is not set
+# CONFIG_libnet-dev is not set
+# CONFIG_libnet-dbg is not set
+
+#
+# libnewt
+#
+# CONFIG_libnewt is not set
+# CONFIG_libnewt-dev is not set
+# CONFIG_libnewt-dbg is not set
+# CONFIG_whiptail is not set
+
+#
+# libnotify
+#
+# CONFIG_libnotify is not set
+# CONFIG_libnotify-dbg is not set
+# CONFIG_libnotify-dev is not set
+
+#
+# libnss-mdns
+#
+# CONFIG_libnss-mdns is not set
+# CONFIG_libnss-mdns-dbg is not set
+# CONFIG_libnss-mdns-dev is not set
+
+#
+# libogg
+#
+# CONFIG_libogg is not set
+# CONFIG_libogg-dev is not set
+# CONFIG_libogg-dbg is not set
+
+#
+# libpciaccess
+#
+# CONFIG_libpciaccess is not set
+# CONFIG_libpciaccess-dbg is not set
+# CONFIG_libpciaccess-dev is not set
+
+#
+# libpng
+#
+# CONFIG_libpng is not set
+# CONFIG_libpng-dev is not set
+# CONFIG_libpng-dbg is not set
+# CONFIG_libpng-tools is not set
+
+#
+# libproxy
+#
+# CONFIG_libproxy is not set
+# CONFIG_libproxy-dev is not set
+# CONFIG_libproxy-dbg is not set
+
+#
+# libsamplerate0
+#
+# CONFIG_libsamplerate0 is not set
+# CONFIG_libsamplerate0-dbg is not set
+# CONFIG_libsamplerate0-dev is not set
+
+#
+# libsecret
+#
+# CONFIG_libsecret is not set
+# CONFIG_libsecret-dbg is not set
+# CONFIG_libsecret-dev is not set
+
+#
+# libsm
+#
+# CONFIG_libsm is not set
+# CONFIG_libsm-dev is not set
+# CONFIG_libsm-dbg is not set
+
+#
+# libtasn1
+#
+# CONFIG_libtasn1 is not set
+# CONFIG_libtasn1-bin is not set
+# CONFIG_libtasn1-dev is not set
+# CONFIG_libtasn1-dbg is not set
+
+#
+# libtheora
+#
+# CONFIG_libtheora is not set
+# CONFIG_libtheora-dbg is not set
+# CONFIG_libtheora-dev is not set
+
+#
+# libtool
+#
+# CONFIG_libtool is not set
+# CONFIG_libtool-dbg is not set
+# CONFIG_libltdl is not set
+# CONFIG_libtool-dev is not set
+
+#
+# liburcu
+#
+# CONFIG_liburcu is not set
+# CONFIG_liburcu-dev is not set
+# CONFIG_liburcu-dbg is not set
+
+#
+# libusb-compat
+#
+# CONFIG_libusb-compat is not set
+# CONFIG_libusb-compat-dev is not set
+# CONFIG_libusb-compat-dbg is not set
+
+#
+# libusb1
+#
+# CONFIG_libusb1 is not set
+# CONFIG_libusb1-dbg is not set
+# CONFIG_libusb1-dev is not set
+
+#
+# libvorbis
+#
+# CONFIG_libvorbis is not set
+# CONFIG_libvorbis-dbg is not set
+# CONFIG_libvorbis-dev is not set
+
+#
+# libwebp
+#
+# CONFIG_libwebp is not set
+# CONFIG_libwebp-bin is not set
+# CONFIG_libwebp-dev is not set
+# CONFIG_libwebp-dbg is not set
+
+#
+# libx11
+#
+# CONFIG_libx11 is not set
+# CONFIG_libx11-dbg is not set
+# CONFIG_libx11-xcb is not set
+# CONFIG_libx11-dev is not set
+
+#
+# libxau
+#
+# CONFIG_libxau is not set
+# CONFIG_libxau-dbg is not set
+# CONFIG_libxau-dev is not set
+
+#
+# libxcomposite
+#
+# CONFIG_libxcomposite is not set
+# CONFIG_libxcomposite-dbg is not set
+# CONFIG_libxcomposite-dev is not set
+
+#
+# libxcursor
+#
+# CONFIG_libxcursor is not set
+# CONFIG_libxcursor-dev is not set
+# CONFIG_libxcursor-dbg is not set
+
+#
+# libxdamage
+#
+# CONFIG_libxdamage is not set
+# CONFIG_libxdamage-dev is not set
+# CONFIG_libxdamage-dbg is not set
+
+#
+# libxdmcp
+#
+# CONFIG_libxdmcp is not set
+# CONFIG_libxdmcp-dev is not set
+# CONFIG_libxdmcp-dbg is not set
+
+#
+# libxext
+#
+# CONFIG_libxext is not set
+# CONFIG_libxext-dbg is not set
+# CONFIG_libxext-dev is not set
+
+#
+# libxfixes
+#
+# CONFIG_libxfixes is not set
+# CONFIG_libxfixes-dev is not set
+# CONFIG_libxfixes-dbg is not set
+
+#
+# libxfont
+#
+# CONFIG_libxfont is not set
+# CONFIG_libxfont-dev is not set
+# CONFIG_libxfont-dbg is not set
+
+#
+# libxft
+#
+# CONFIG_libxft is not set
+# CONFIG_libxft-dev is not set
+# CONFIG_libxft-dbg is not set
+
+#
+# libxi
+#
+# CONFIG_libxi is not set
+# CONFIG_libxi-dbg is not set
+# CONFIG_libxi-dev is not set
+
+#
+# libxinerama
+#
+# CONFIG_libxinerama is not set
+# CONFIG_libxinerama-dbg is not set
+# CONFIG_libxinerama-dev is not set
+
+#
+# libxkbcommon
+#
+# CONFIG_libxkbcommon is not set
+# CONFIG_libxkbcommon-dbg is not set
+# CONFIG_libxkbcommon-dev is not set
+
+#
+# libxkbfile
+#
+# CONFIG_libxkbfile is not set
+# CONFIG_libxkbfile-dbg is not set
+# CONFIG_libxkbfile-dev is not set
+
+#
+# libxml-parser-perl
+#
+# CONFIG_libxml-parser-perl is not set
+# CONFIG_libxml-parser-perl-dbg is not set
+# CONFIG_libxml-parser-perl-dev is not set
+
+#
+# libxml2
+#
+# CONFIG_libxml2 is not set
+# CONFIG_libxml2-dbg is not set
+# CONFIG_libxml2-dev is not set
+# CONFIG_libxml2-python is not set
+
+#
+# libxmu
+#
+# CONFIG_libxmu is not set
+# CONFIG_libxmu-dev is not set
+# CONFIG_libxmu-dbg is not set
+# CONFIG_libxmuu is not set
+
+#
+# libxrandr
+#
+# CONFIG_libxrandr is not set
+# CONFIG_libxrandr-dev is not set
+# CONFIG_libxrandr-dbg is not set
+
+#
+# libxrender
+#
+# CONFIG_libxrender is not set
+# CONFIG_libxrender-dev is not set
+# CONFIG_libxrender-dbg is not set
+
+#
+# libxres
+#
+# CONFIG_libxres is not set
+# CONFIG_libxres-dev is not set
+# CONFIG_libxres-dbg is not set
+
+#
+# libxslt
+#
+# CONFIG_libxslt is not set
+# CONFIG_libxslt-dev is not set
+# CONFIG_libxslt-bin is not set
+# CONFIG_libxslt-dbg is not set
+
+#
+# libxt
+#
+# CONFIG_libxt is not set
+# CONFIG_libxt-dbg is not set
+# CONFIG_libxt-dev is not set
+
+#
+# libxtst
+#
+# CONFIG_libxtst is not set
+# CONFIG_libxtst-dev is not set
+# CONFIG_libxtst-dbg is not set
+
+#
+# libxv
+#
+# CONFIG_libxv is not set
+# CONFIG_libxv-dbg is not set
+# CONFIG_libxv-dev is not set
+
+#
+# libxxf86dga
+#
+# CONFIG_libxxf86dga is not set
+# CONFIG_libxxf86dga-dbg is not set
+# CONFIG_libxxf86dga-dev is not set
+
+#
+# libxxf86misc
+#
+# CONFIG_libxxf86misc is not set
+# CONFIG_libxxf86misc-dev is not set
+# CONFIG_libxxf86misc-dbg is not set
+
+#
+# libxxf86vm
+#
+# CONFIG_libxxf86vm is not set
+# CONFIG_libxxf86vm-dbg is not set
+# CONFIG_libxxf86vm-dev is not set
+
+#
+# lzo
+#
+# CONFIG_lzo is not set
+# CONFIG_lzo-dbg is not set
+# CONFIG_lzo-dev is not set
+
+#
+# mtdev
+#
+# CONFIG_mtdev is not set
+# CONFIG_mtdev-dbg is not set
+# CONFIG_mtdev-dev is not set
+
+#
+# multimedia
+#
+
+#
+# alsa-lib
+#
+# CONFIG_alsa-lib is not set
+# CONFIG_alsa-lib-dbg is not set
+# CONFIG_alsa-lib-dev is not set
+# CONFIG_alsa-server is not set
+# CONFIG_libasound is not set
+# CONFIG_alsa-conf-base is not set
+# CONFIG_alsa-conf is not set
+# CONFIG_alsa-oss is not set
+
+#
+# libsndfile1
+#
+# CONFIG_libsndfile1 is not set
+# CONFIG_libsndfile1-dbg is not set
+# CONFIG_libsndfile1-dev is not set
+# CONFIG_libsndfile1-bin is not set
+
+#
+# pulseaudio
+#
+# CONFIG_pulseaudio is not set
+# CONFIG_pulseaudio-misc is not set
+# CONFIG_libpulse-mainloop-glib is not set
+# CONFIG_pulseaudio-dbg is not set
+# CONFIG_libpulsecommon is not set
+# CONFIG_pulseaudio-module-console-kit is not set
+# CONFIG_pulseaudio-bash-completion is not set
+# CONFIG_libpulse-simple is not set
+# CONFIG_libpulsecore is not set
+# CONFIG_libpulse is not set
+# CONFIG_pulseaudio-dev is not set
+# CONFIG_pulseaudio-server is not set
+
+#
+# taglib
+#
+# CONFIG_taglib is not set
+# CONFIG_taglib-dev is not set
+# CONFIG_taglib-c is not set
+# CONFIG_taglib-dbg is not set
+
+#
+# ncurses
+#
+# CONFIG_ncurses is not set
+# CONFIG_ncurses-terminfo-base is not set
+# CONFIG_ncurses-dev is not set
+# CONFIG_ncurses-tools is not set
+# CONFIG_ncurses-terminfo is not set
+# CONFIG_ncurses-dbg is not set
+
+#
+# neon
+#
+# CONFIG_neon is not set
+# CONFIG_neon-dev is not set
+# CONFIG_neon-dbg is not set
+
+#
+# nettle
+#
+# CONFIG_nettle is not set
+# CONFIG_nettle-dev is not set
+# CONFIG_nettle-dbg is not set
+
+#
+# network
+#
+
+#
+# libnl
+#
+# CONFIG_libnl is not set
+# CONFIG_libnl-xfrm is not set
+# CONFIG_libnl-nf is not set
+# CONFIG_libnl-dev is not set
+# CONFIG_libnl-cli is not set
+# CONFIG_libnl-dbg is not set
+# CONFIG_libnl-route is not set
+# CONFIG_libnl-idiag is not set
+# CONFIG_libnl-genl is not set
+
+#
+# libpcap
+#
+# CONFIG_libpcap is not set
+# CONFIG_libpcap-dev is not set
+# CONFIG_libpcap-dbg is not set
+
+#
+# libsocketcan
+#
+# CONFIG_libsocketcan is not set
+# CONFIG_libsocketcan-dbg is not set
+# CONFIG_libsocketcan-dev is not set
+
+#
+# libtirpc
+#
+# CONFIG_libtirpc is not set
+# CONFIG_libtirpc-dev is not set
+# CONFIG_libtirpc-dbg is not set
+
+#
+# openssl
+#
+# CONFIG_openssl is not set
+# CONFIG_openssl-conf is not set
+# CONFIG_openssl-dbg is not set
+# CONFIG_openssl-engines is not set
+# CONFIG_libcrypto is not set
+# CONFIG_openssl-dev is not set
+# CONFIG_openssl-misc is not set
+# CONFIG_libssl is not set
+
+#
+# open-amp
+#
+# CONFIG_open-amp is not set
+# CONFIG_open-amp-dbg is not set
+# CONFIG_open-amp-dev is not set
+
+#
+# opencv
+#
+# CONFIG_opencv is not set
+# CONFIG_opencv-dev is not set
+# CONFIG_opencv-apps is not set
+# CONFIG_opencv-samples is not set
+# CONFIG_opencv-dbg is not set
+
+#
+# pango
+#
+# CONFIG_pango is not set
+# CONFIG_pango-dbg is not set
+# CONFIG_pango-dev is not set
+
+#
+# popt
+#
+# CONFIG_popt is not set
+# CONFIG_popt-dbg is not set
+# CONFIG_popt-dev is not set
+
+#
+# readline
+#
+# CONFIG_readline is not set
+# CONFIG_readline-dev is not set
+# CONFIG_readline-dbg is not set
+
+#
+# sbc
+#
+# CONFIG_sbc is not set
+# CONFIG_sbc-dev is not set
+# CONFIG_sbc-dbg is not set
+
+#
+# slang
+#
+# CONFIG_slang is not set
+# CONFIG_slang-dev is not set
+# CONFIG_slang-dbg is not set
+
+#
+# speex
+#
+# CONFIG_speex is not set
+# CONFIG_speex-dev is not set
+# CONFIG_speex-dbg is not set
+
+#
+# speexdsp
+#
+# CONFIG_speexdsp is not set
+# CONFIG_speexdsp-dev is not set
+# CONFIG_speexdsp-dbg is not set
+
+#
+# sqlite3
+#
+# CONFIG_sqlite3 is not set
+# CONFIG_libsqlite3 is not set
+# CONFIG_sqlite3-dbg is not set
+# CONFIG_libsqlite3-dev is not set
+
+#
+# startup-notification
+#
+# CONFIG_startup-notification is not set
+# CONFIG_startup-notification-dev is not set
+# CONFIG_startup-notification-dbg is not set
+
+#
+# tremor
+#
+# CONFIG_tremor is not set
+# CONFIG_tremor-dev is not set
+# CONFIG_tremor-dbg is not set
+
+#
+# which
+#
+# CONFIG_which is not set
+# CONFIG_which-dev is not set
+# CONFIG_which-dbg is not set
+
+#
+# zlib
+#
+# CONFIG_zlib is not set
+# CONFIG_zlib-dbg is not set
+# CONFIG_zlib-dev is not set
+
+#
+# misc
+#
+
+#
+# alsa-state
+#
+# CONFIG_alsa-state is not set
+# CONFIG_alsa-state-dev is not set
+# CONFIG_alsa-state-dbg is not set
+# CONFIG_alsa-states is not set
+
+#
+# apache2
+#
+# CONFIG_apache2 is not set
+# CONFIG_apache2-dbg is not set
+# CONFIG_apache2-dev is not set
+
+#
+# at-spi2-atk
+#
+# CONFIG_at-spi2-atk is not set
+# CONFIG_at-spi2-atk-dbg is not set
+# CONFIG_at-spi2-atk-gnome is not set
+# CONFIG_at-spi2-atk-dev is not set
+# CONFIG_at-spi2-atk-gtk2 is not set
+
+#
+# at-spi2-core
+#
+# CONFIG_at-spi2-core is not set
+# CONFIG_at-spi2-core-dev is not set
+# CONFIG_at-spi2-core-dbg is not set
+
+#
+# babeltrace
+#
+# CONFIG_babeltrace is not set
+# CONFIG_babeltrace-dev is not set
+# CONFIG_babeltrace-dbg is not set
+
+#
+# blktool
+#
+# CONFIG_blktool is not set
+# CONFIG_blktool-dev is not set
+# CONFIG_blktool-dbg is not set
+
+#
+# blktrace
+#
+# CONFIG_blktrace is not set
+# CONFIG_blktrace-dbg is not set
+# CONFIG_blktrace-dev is not set
+
+#
+# ca-certificates
+#
+# CONFIG_ca-certificates is not set
+# CONFIG_ca-certificates-dev is not set
+# CONFIG_ca-certificates-dbg is not set
+
+#
+# chkconfig
+#
+# CONFIG_chkconfig is not set
+# CONFIG_chkconfig-dbg is not set
+# CONFIG_chkconfig-dev is not set
+# CONFIG_chkconfig-alternatives is not set
+
+#
+# chrpath
+#
+# CONFIG_chrpath is not set
+# CONFIG_chrpath-dev is not set
+# CONFIG_chrpath-dbg is not set
+
+#
+# connman
+#
+# CONFIG_connman is not set
+# CONFIG_connman-tests is not set
+# CONFIG_connman-dev is not set
+# CONFIG_connman-dbg is not set
+# CONFIG_connman-tools is not set
+# CONFIG_connman-wait-online is not set
+# CONFIG_connman-client is not set
+
+#
+# connman-conf
+#
+# CONFIG_connman-conf-dbg is not set
+
+#
+# consolekit
+#
+# CONFIG_consolekit is not set
+# CONFIG_consolekit-dbg is not set
+# CONFIG_consolekit-dev is not set
+
+#
+# coreutils
+#
+# CONFIG_coreutils is not set
+# CONFIG_coreutils-dev is not set
+# CONFIG_coreutils-dbg is not set
+
+#
+# cpufrequtils
+#
+# CONFIG_cpufrequtils is not set
+# CONFIG_cpufrequtils-dev is not set
+# CONFIG_cpufrequtils-dbg is not set
+
+#
+# cryptodev-linux
+#
+# CONFIG_cryptodev-linux is not set
+# CONFIG_cryptodev-linux-dev is not set
+# CONFIG_cryptodev-linux-dbg is not set
+
+#
+# encodings
+#
+# CONFIG_encodings is not set
+# CONFIG_encodings-dev is not set
+# CONFIG_encodings-dbg is not set
+
+#
+# epiphany
+#
+# CONFIG_epiphany is not set
+# CONFIG_epiphany-dbg is not set
+# CONFIG_epiphany-dev is not set
+
+#
+# eudev
+#
+# CONFIG_eudev is not set
+# CONFIG_libudev is not set
+# CONFIG_eudev-dev is not set
+# CONFIG_eudev-dbg is not set
+# CONFIG_eudev-hwdb is not set
+CONFIG_udev-extraconf=y
+
+#
+# fbset
+#
+# CONFIG_fbset is not set
+# CONFIG_fbset-dbg is not set
+# CONFIG_fbset-dev is not set
+
+#
+# fbset-modes
+#
+# CONFIG_fbset-modes is not set
+# CONFIG_fbset-modes-dev is not set
+# CONFIG_fbset-modes-dbg is not set
+
+#
+# font-util
+#
+# CONFIG_font-util is not set
+# CONFIG_font-util-dev is not set
+# CONFIG_font-util-dbg is not set
+
+#
+# gcc-runtime
+#
+# CONFIG_libstdcPLUSPLUS is not set
+# CONFIG_libstdcPLUSPLUS-dev is not set
+
+#
+# gcc-sanitizers
+#
+# CONFIG_gcc-sanitizers is not set
+# CONFIG_libubsan-dev is not set
+# CONFIG_libubsan is not set
+# CONFIG_gcc-sanitizers-dbg is not set
+# CONFIG_libasan is not set
+# CONFIG_libasan-dev is not set
+
+#
+# gcr
+#
+# CONFIG_gcr is not set
+# CONFIG_gcr-dev is not set
+# CONFIG_gcr-dbg is not set
+
+#
+# gdb
+#
+# CONFIG_gdb is not set
+# CONFIG_gdb-dbg is not set
+# CONFIG_gdb-dev is not set
+# CONFIG_gdbserver is not set
+
+#
+# glib-2.0
+#
+# CONFIG_glib-2.0 is not set
+# CONFIG_glib-2.0-codegen is not set
+# CONFIG_glib-2.0-utils is not set
+# CONFIG_glib-2.0-dbg is not set
+# CONFIG_glib-2.0-bash-completion is not set
+# CONFIG_glib-2.0-dev is not set
+
+#
+# glibc
+#
+# CONFIG_glibc is not set
+# CONFIG_glibc-dev is not set
+# CONFIG_glibc-dbg is not set
+# CONFIG_ldd is not set
+
+#
+# gnome-desktop-testing
+#
+# CONFIG_gnome-desktop-testing is not set
+# CONFIG_gnome-desktop-testing-dbg is not set
+# CONFIG_gnome-desktop-testing-dev is not set
+
+#
+# gnutls
+#
+# CONFIG_gnutls is not set
+# CONFIG_gnutls-dev is not set
+# CONFIG_gnutls-dbg is not set
+# CONFIG_gnutls-bin is not set
+# CONFIG_gnutls-xx is not set
+# CONFIG_gnutls-openssl is not set
+
+#
+# gsettings-desktop-schemas
+#
+# CONFIG_gsettings-desktop-schemas is not set
+# CONFIG_gsettings-desktop-schemas-dev is not set
+# CONFIG_gsettings-desktop-schemas-dbg is not set
+
+#
+# gst-player
+#
+# CONFIG_gst-player is not set
+
+#
+# gst-plugins-base
+#
+# CONFIG_gst-plugins-base is not set
+# CONFIG_gst-plugins-base-apps is not set
+# CONFIG_gst-plugins-base-meta is not set
+# CONFIG_gst-plugins-base-dbg is not set
+# CONFIG_gst-plugins-base-dev is not set
+
+#
+# gst-plugins-good
+#
+# CONFIG_gst-plugins-good is not set
+# CONFIG_gst-plugins-good-dev is not set
+# CONFIG_gst-plugins-good-meta is not set
+# CONFIG_gst-plugins-good-dbg is not set
+
+#
+# gstreamer1.0-plugins-bad
+#
+# CONFIG_gstreamer1.0-plugins-bad is not set
+# CONFIG_gstreamer1.0-plugins-bad-meta is not set
+# CONFIG_gstreamer1.0-plugins-bad-dev is not set
+# CONFIG_gstreamer1.0-plugins-bad-dbg is not set
+
+#
+# gstreamer1.0-plugins-base
+#
+# CONFIG_gstreamer1.0-plugins-base is not set
+# CONFIG_gstreamer1.0-plugins-base-dev is not set
+# CONFIG_gstreamer1.0-plugins-base-apps is not set
+# CONFIG_gstreamer1.0-plugins-base-meta is not set
+# CONFIG_gstreamer1.0-plugins-base-dbg is not set
+
+#
+# gstreamer1.0-plugins-good
+#
+# CONFIG_gstreamer1.0-plugins-good is not set
+# CONFIG_gstreamer1.0-plugins-good-meta is not set
+# CONFIG_gstreamer1.0-plugins-good-dev is not set
+# CONFIG_gstreamer1.0-plugins-good-dbg is not set
+
+#
+# hicolor-icon-theme
+#
+# CONFIG_hicolor-icon-theme is not set
+# CONFIG_hicolor-icon-theme-dbg is not set
+# CONFIG_hicolor-icon-theme-dev is not set
+
+#
+# icu
+#
+# CONFIG_icu is not set
+# CONFIG_libicudata is not set
+# CONFIG_libicuio is not set
+# CONFIG_libicui18n is not set
+# CONFIG_icu-dbg is not set
+# CONFIG_libicuuc is not set
+# CONFIG_libicutu is not set
+# CONFIG_icu-dev is not set
+
+#
+# iptables
+#
+# CONFIG_iptables is not set
+# CONFIG_iptables-dbg is not set
+# CONFIG_iptables-dev is not set
+
+#
+# iso-codes
+#
+# CONFIG_iso-codes is not set
+# CONFIG_iso-codes-dbg is not set
+# CONFIG_iso-codes-dev is not set
+
+#
+# json-c
+#
+# CONFIG_json-c is not set
+# CONFIG_json-c-dbg is not set
+# CONFIG_json-c-dev is not set
+
+#
+# l3afpad
+#
+# CONFIG_l3afpad is not set
+# CONFIG_l3afpad-dev is not set
+# CONFIG_l3afpad-dbg is not set
+
+#
+# lttng-ust
+#
+# CONFIG_lttng-ust is not set
+# CONFIG_lttng-ust-dbg is not set
+# CONFIG_lttng-ust-bin is not set
+# CONFIG_lttng-ust-dev is not set
+
+#
+# m4
+#
+# CONFIG_m4 is not set
+# CONFIG_m4-dbg is not set
+# CONFIG_m4-dev is not set
+
+#
+# matchbox-config-gtk
+#
+# CONFIG_matchbox-config-gtk is not set
+# CONFIG_matchbox-config-gtk-dev is not set
+# CONFIG_matchbox-config-gtk-dbg is not set
+
+#
+# matchbox-panel-2
+#
+# CONFIG_matchbox-panel-2 is not set
+# CONFIG_matchbox-panel-2-dbg is not set
+# CONFIG_matchbox-panel-2-dev is not set
+
+#
+# mdadm
+#
+# CONFIG_mdadm is not set
+# CONFIG_mdadm-dbg is not set
+# CONFIG_mdadm-dev is not set
+
+#
+# mkfontdir
+#
+# CONFIG_mkfontdir is not set
+# CONFIG_mkfontdir-dev is not set
+# CONFIG_mkfontdir-dbg is not set
+
+#
+# mkfontscale
+#
+# CONFIG_mkfontscale is not set
+# CONFIG_mkfontscale-dbg is not set
+# CONFIG_mkfontscale-dev is not set
+
+#
+# net-tools
+#
+# CONFIG_net-tools is not set
+# CONFIG_net-tools-dbg is not set
+# CONFIG_net-tools-dev is not set
+
+#
+# ofono
+#
+# CONFIG_ofono is not set
+# CONFIG_ofono-tests is not set
+# CONFIG_ofono-dev is not set
+# CONFIG_ofono-dbg is not set
+
+#
+# openamp-fw-echo-testd
+#
+# CONFIG_openamp-fw-echo-testd is not set
+# CONFIG_openamp-fw-echo-testd-dev is not set
+# CONFIG_openamp-fw-echo-testd-dbg is not set
+
+#
+# openamp-fw-mat-muld
+#
+# CONFIG_openamp-fw-mat-muld is not set
+# CONFIG_openamp-fw-mat-muld-dev is not set
+# CONFIG_openamp-fw-mat-muld-dbg is not set
+
+#
+# openamp-fw-rpc-demo
+#
+# CONFIG_openamp-fw-rpc-demo is not set
+# CONFIG_openamp-fw-rpc-demo-dev is not set
+# CONFIG_openamp-fw-rpc-demo-dbg is not set
+
+#
+# opkg-arch-config
+#
+# CONFIG_opkg-arch-config is not set
+# CONFIG_opkg-arch-config-dbg is not set
+# CONFIG_opkg-arch-config-dev is not set
+
+#
+# orc
+#
+# CONFIG_orc is not set
+# CONFIG_orc-dbg is not set
+# CONFIG_orc-dev is not set
+
+#
+# p11-kit
+#
+# CONFIG_p11-kit is not set
+# CONFIG_p11-kit-dev is not set
+# CONFIG_p11-kit-dbg is not set
+
+#
+# packagegroup-core-boot
+#
+CONFIG_packagegroup-core-boot=y
+# CONFIG_packagegroup-core-boot-dev is not set
+# CONFIG_packagegroup-core-boot-dbg is not set
+
+#
+# packagegroup-core-buildessential
+#
+CONFIG_packagegroup-core-buildessential=y
+# CONFIG_packagegroup-core-buildessential-dev is not set
+# CONFIG_packagegroup-core-buildessential-dbg is not set
+
+#
+# packagegroup-core-sdk
+#
+# CONFIG_packagegroup-core-sdk is not set
+# CONFIG_packagegroup-core-sdk-dbg is not set
+# CONFIG_packagegroup-core-sdk-dev is not set
+
+#
+# packagegroup-core-ssh-dropbear
+#
+CONFIG_packagegroup-core-ssh-dropbear=y
+# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
+# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
+
+#
+# packagegroup-core-standalone-sdk-target
+#
+# CONFIG_packagegroup-core-standalone-sdk-target is not set
+# CONFIG_packagegroup-core-standalone-sdk-target-dev is not set
+# CONFIG_packagegroup-core-standalone-sdk-target-dbg is not set
+
+#
+# packagegroup-core-tools-debug
+#
+# CONFIG_packagegroup-core-tools-debug is not set
+# CONFIG_packagegroup-core-tools-debug-dev is not set
+# CONFIG_packagegroup-core-tools-debug-dbg is not set
+
+#
+# packagegroup-core-tools-profile
+#
+# CONFIG_packagegroup-core-tools-profile is not set
+# CONFIG_packagegroup-core-tools-profile-dbg is not set
+# CONFIG_packagegroup-core-tools-profile-dev is not set
+
+#
+# packagegroup-core-tools-testapps
+#
+# CONFIG_packagegroup-core-tools-testapps is not set
+# CONFIG_packagegroup-core-tools-testapps-dbg is not set
+# CONFIG_packagegroup-core-tools-testapps-dev is not set
+
+#
+# packagegroup-core-x11
+#
+# CONFIG_packagegroup-core-x11 is not set
+# CONFIG_packagegroup-core-x11-dbg is not set
+# CONFIG_packagegroup-core-x11-utils-dbg is not set
+# CONFIG_packagegroup-core-x11-dev is not set
+# CONFIG_packagegroup-core-x11-utils is not set
+# CONFIG_packagegroup-core-x11-utils-dev is not set
+
+#
+# packagegroup-core-x11-base
+#
+# CONFIG_packagegroup-core-x11-base is not set
+# CONFIG_packagegroup-core-x11-base-dev is not set
+# CONFIG_packagegroup-core-x11-base-dbg is not set
+
+#
+# packagegroup-core-x11-xserver
+#
+# CONFIG_packagegroup-core-x11-xserver is not set
+# CONFIG_packagegroup-core-x11-xserver-dev is not set
+# CONFIG_packagegroup-core-x11-xserver-dbg is not set
+
+#
+# packagegroup-self-hosted
+#
+# CONFIG_packagegroup-self-hosted is not set
+# CONFIG_packagegroup-self-hosted-extended-dev is not set
+# CONFIG_packagegroup-self-hosted-debug-dev is not set
+# CONFIG_packagegroup-self-hosted-dev is not set
+# CONFIG_packagegroup-self-hosted-extended-dbg is not set
+# CONFIG_packagegroup-self-hosted-sdk-dev is not set
+# CONFIG_packagegroup-self-hosted-dbg is not set
+# CONFIG_packagegroup-self-hosted-graphics-dev is not set
+# CONFIG_packagegroup-self-hosted-sdk is not set
+# CONFIG_packagegroup-self-hosted-debug is not set
+# CONFIG_packagegroup-self-hosted-host-tools is not set
+# CONFIG_packagegroup-self-hosted-debug-dbg is not set
+# CONFIG_packagegroup-self-hosted-extended is not set
+# CONFIG_packagegroup-self-hosted-host-tools-dev is not set
+# CONFIG_packagegroup-self-hosted-graphics-dbg is not set
+# CONFIG_packagegroup-self-hosted-sdk-dbg is not set
+# CONFIG_packagegroup-self-hosted-host-tools-dbg is not set
+# CONFIG_packagegroup-self-hosted-graphics is not set
+
+#
+# perf
+#
+# CONFIG_perf is not set
+# CONFIG_perf-tests is not set
+# CONFIG_perf-python is not set
+# CONFIG_perf-dbg is not set
+# CONFIG_perf-dev is not set
+
+#
+# pixman
+#
+# CONFIG_pixman is not set
+# CONFIG_pixman-dbg is not set
+# CONFIG_pixman-dev is not set
+
+#
+# powertop
+#
+# CONFIG_powertop is not set
+# CONFIG_powertop-dev is not set
+# CONFIG_powertop-dbg is not set
+
+#
+# ptest-runner
+#
+# CONFIG_ptest-runner is not set
+# CONFIG_ptest-runner-dev is not set
+# CONFIG_ptest-runner-dbg is not set
+
+#
+# python3
+#
+# CONFIG_python3 is not set
+# CONFIG_python3-smtpd is not set
+# CONFIG_python3-syslog is not set
+# CONFIG_python3-pickle is not set
+# CONFIG_python3-dbg is not set
+# CONFIG_python3-db is not set
+# CONFIG_python3-fcntl is not set
+# CONFIG_python3-html is not set
+# CONFIG_python3-core is not set
+# CONFIG_python3-distutils is not set
+# CONFIG_python3-terminal is not set
+# CONFIG_python3-pprint is not set
+# CONFIG_python3-tkinter is not set
+# CONFIG_python3-unixadmin is not set
+# CONFIG_python3-mime is not set
+# CONFIG_python3-logging is not set
+# CONFIG_python3-resource is not set
+# CONFIG_python3-email is not set
+# CONFIG_python3-math is not set
+# CONFIG_python3-json is not set
+# CONFIG_python3-image is not set
+# CONFIG_python3-stringold is not set
+# CONFIG_python3-pydoc is not set
+# CONFIG_python3-codecs is not set
+# CONFIG_python3-debugger is not set
+# CONFIG_python3-xmlrpc is not set
+# CONFIG_python3-io is not set
+# CONFIG_python3-pkgutil is not set
+# CONFIG_python3-idle is not set
+# CONFIG_python3-difflib is not set
+# CONFIG_python3-unittest is not set
+# CONFIG_python3-netserver is not set
+# CONFIG_python3-netclient is not set
+# CONFIG_python3-gdbm is not set
+# CONFIG_python3-profile is not set
+# CONFIG_python3-sqlite3 is not set
+# CONFIG_python3-2to3 is not set
+# CONFIG_libpython3 is not set
+# CONFIG_python3-xml is not set
+# CONFIG_python3-threading is not set
+# CONFIG_python3-modules is not set
+# CONFIG_python3-dev is not set
+# CONFIG_python3-curses is not set
+# CONFIG_python3-multiprocessing is not set
+# CONFIG_python3-crypt is not set
+# CONFIG_python3-compression is not set
+# CONFIG_python3-shell is not set
+# CONFIG_python3-tests is not set
+# CONFIG_python3-numbers is not set
+# CONFIG_python3-audio is not set
+# CONFIG_python3-pyvenv is not set
+# CONFIG_python3-asyncio is not set
+# CONFIG_python3-misc is not set
+# CONFIG_python3-datetime is not set
+# CONFIG_python3-compile is not set
+# CONFIG_python3-mmap is not set
+# CONFIG_python3-mailbox is not set
+# CONFIG_python3-ctypes is not set
+
+#
+# python3-async
+#
+# CONFIG_python3-async is not set
+# CONFIG_python3-async-dev is not set
+# CONFIG_python3-async-dbg is not set
+
+#
+# python3-git
+#
+# CONFIG_python3-git is not set
+# CONFIG_python3-git-dbg is not set
+# CONFIG_python3-git-dev is not set
+
+#
+# python3-gitdb
+#
+# CONFIG_python3-gitdb is not set
+# CONFIG_python3-gitdb-dev is not set
+# CONFIG_python3-gitdb-dbg is not set
+
+#
+# python3-setuptools
+#
+# CONFIG_python3-setuptools is not set
+# CONFIG_python3-setuptools-dev is not set
+# CONFIG_python3-setuptools-dbg is not set
+
+#
+# python3-smmap
+#
+# CONFIG_python3-smmap is not set
+# CONFIG_python3-smmap-dbg is not set
+# CONFIG_python3-smmap-dev is not set
+
+#
+# qtbase
+#
+# CONFIG_qtbase is not set
+# CONFIG_qtbase-tools is not set
+# CONFIG_qtbase-plugins is not set
+# CONFIG_qtbase-examples is not set
+# CONFIG_qtbase-dbg is not set
+# CONFIG_qtbase-dev is not set
+# CONFIG_qtbase-mkspecs is not set
+
+#
+# qtcharts
+#
+# CONFIG_qtcharts is not set
+# CONFIG_qtcharts-mkspecs is not set
+# CONFIG_qtcharts-dev is not set
+# CONFIG_qtcharts-dbg is not set
+# CONFIG_qtcharts-examples is not set
+# CONFIG_qtcharts-qmlplugins is not set
+# CONFIG_qtcharts-qmldesigner is not set
+
+#
+# qtconnectivity
+#
+# CONFIG_qtconnectivity is not set
+# CONFIG_qtconnectivity-tools is not set
+# CONFIG_qtconnectivity-mkspecs is not set
+# CONFIG_qtconnectivity-dev is not set
+# CONFIG_qtconnectivity-examples is not set
+# CONFIG_qtconnectivity-dbg is not set
+# CONFIG_qtconnectivity-qmlplugins is not set
+
+#
+# qtdeclarative
+#
+# CONFIG_qtdeclarative is not set
+# CONFIG_qtdeclarative-examples is not set
+# CONFIG_qtdeclarative-dev is not set
+# CONFIG_qtdeclarative-dbg is not set
+# CONFIG_qtdeclarative-qmlplugins is not set
+# CONFIG_qtdeclarative-tools is not set
+# CONFIG_qtdeclarative-mkspecs is not set
+
+#
+# qtenginio
+#
+# CONFIG_qtenginio is not set
+# CONFIG_qtenginio-qmlplugins is not set
+# CONFIG_qtenginio-mkspecs is not set
+# CONFIG_qtenginio-dbg is not set
+# CONFIG_qtenginio-dev is not set
+# CONFIG_qtenginio-examples is not set
+
+#
+# qtimageformats
+#
+# CONFIG_qtimageformats is not set
+# CONFIG_qtimageformats-plugins is not set
+# CONFIG_qtimageformats-dbg is not set
+# CONFIG_qtimageformats-dev is not set
+
+#
+# qtlocation
+#
+# CONFIG_qtlocation is not set
+# CONFIG_qtlocation-plugins is not set
+# CONFIG_qtlocation-qmlplugins is not set
+# CONFIG_qtlocation-dbg is not set
+# CONFIG_qtlocation-examples is not set
+# CONFIG_qtlocation-dev is not set
+# CONFIG_qtlocation-mkspecs is not set
+
+#
+# qtmultimedia
+#
+# CONFIG_qtmultimedia is not set
+# CONFIG_qtmultimedia-plugins is not set
+# CONFIG_qtmultimedia-mkspecs is not set
+# CONFIG_qtmultimedia-examples is not set
+# CONFIG_qtmultimedia-qmlplugins is not set
+# CONFIG_qtmultimedia-dev is not set
+# CONFIG_qtmultimedia-dbg is not set
+
+#
+# qtquickcontrols
+#
+# CONFIG_qtquickcontrols is not set
+# CONFIG_qtquickcontrols-dbg is not set
+# CONFIG_qtquickcontrols-examples is not set
+# CONFIG_qtquickcontrols-dev is not set
+# CONFIG_qtquickcontrols-qmlplugins is not set
+# CONFIG_qtquickcontrols-qmldesigner is not set
+
+#
+# qtscript
+#
+# CONFIG_qtscript is not set
+# CONFIG_qtscript-examples is not set
+# CONFIG_qtscript-mkspecs is not set
+# CONFIG_qtscript-dbg is not set
+# CONFIG_qtscript-dev is not set
+
+#
+# qtsensors
+#
+# CONFIG_qtsensors is not set
+# CONFIG_qtsensors-dbg is not set
+# CONFIG_qtsensors-examples-dev is not set
+# CONFIG_qtsensors-mkspecs is not set
+# CONFIG_qtsensors-examples is not set
+# CONFIG_qtsensors-dev is not set
+# CONFIG_qtsensors-plugins is not set
+# CONFIG_qtsensors-qmlplugins is not set
+
+#
+# qtserialport
+#
+# CONFIG_qtserialport is not set
+# CONFIG_qtserialport-mkspecs is not set
+# CONFIG_qtserialport-dev is not set
+# CONFIG_qtserialport-examples is not set
+# CONFIG_qtserialport-dbg is not set
+
+#
+# qtsvg
+#
+# CONFIG_qtsvg is not set
+# CONFIG_qtsvg-plugins is not set
+# CONFIG_qtsvg-mkspecs is not set
+# CONFIG_qtsvg-dbg is not set
+# CONFIG_qtsvg-dev is not set
+# CONFIG_qtsvg-examples is not set
+
+#
+# qtsystems
+#
+# CONFIG_qtsystems is not set
+# CONFIG_qtsystems-dbg is not set
+# CONFIG_qtsystems-tools is not set
+# CONFIG_qtsystems-dev is not set
+# CONFIG_qtsystems-qmlplugins is not set
+# CONFIG_qtsystems-examples is not set
+# CONFIG_qtsystems-mkspecs is not set
+
+#
+# qttools
+#
+# CONFIG_qttools is not set
+# CONFIG_qttools-examples is not set
+# CONFIG_qttools-mkspecs is not set
+# CONFIG_qttools-dbg is not set
+# CONFIG_qttools-tools is not set
+# CONFIG_qttools-plugins is not set
+# CONFIG_qttools-dev is not set
+
+#
+# qttranslations
+#
+# CONFIG_qttranslations is not set
+# CONFIG_qttranslations-qthelp is not set
+# CONFIG_qttranslations-assistant is not set
+# CONFIG_qttranslations-qtwebsockets is not set
+# CONFIG_qttranslations-qtquickcontrols2 is not set
+# CONFIG_qttranslations-qtquick1 is not set
+# CONFIG_qttranslations-qtdeclarative is not set
+# CONFIG_qttranslations-qtxmlpatterns is not set
+# CONFIG_qttranslations-qtmultimedia is not set
+# CONFIG_qttranslations-qtconnectivity is not set
+# CONFIG_qttranslations-qt is not set
+# CONFIG_qttranslations-qtbase is not set
+# CONFIG_qttranslations-qtserialport is not set
+# CONFIG_qttranslations-linguist is not set
+# CONFIG_qttranslations-dbg is not set
+# CONFIG_qttranslations-qmlviewer is not set
+# CONFIG_qttranslations-qtlocation is not set
+# CONFIG_qttranslations-qtscript is not set
+# CONFIG_qttranslations-qtwebengine is not set
+# CONFIG_qttranslations-designer is not set
+# CONFIG_qttranslations-qtquickcontrols is not set
+# CONFIG_qttranslations-dev is not set
+
+#
+# qtwebchannel
+#
+# CONFIG_qtwebchannel is not set
+# CONFIG_qtwebchannel-dev is not set
+# CONFIG_qtwebchannel-examples is not set
+# CONFIG_qtwebchannel-dbg is not set
+# CONFIG_qtwebchannel-qmlplugins is not set
+# CONFIG_qtwebchannel-mkspecs is not set
+
+#
+# qtwebkit
+#
+# CONFIG_qtwebkit is not set
+# CONFIG_qtwebkit-qmlplugins is not set
+# CONFIG_qtwebkit-dev is not set
+# CONFIG_qtwebkit-dbg is not set
+# CONFIG_qtwebkit-mkspecs is not set
+
+#
+# qtwebsockets
+#
+# CONFIG_qtwebsockets is not set
+# CONFIG_qtwebsockets-dev is not set
+# CONFIG_qtwebsockets-qmlplugins is not set
+# CONFIG_qtwebsockets-examples is not set
+# CONFIG_qtwebsockets-mkspecs is not set
+# CONFIG_qtwebsockets-dbg is not set
+
+#
+# qtxmlpatterns
+#
+# CONFIG_qtxmlpatterns is not set
+# CONFIG_qtxmlpatterns-mkspecs is not set
+# CONFIG_qtxmlpatterns-dbg is not set
+# CONFIG_qtxmlpatterns-dev is not set
+# CONFIG_qtxmlpatterns-examples is not set
+# CONFIG_qtxmlpatterns-tools is not set
+
+#
+# rgb
+#
+# CONFIG_rgb is not set
+# CONFIG_rgb-dbg is not set
+# CONFIG_rgb-dev is not set
+
+#
+# rpm
+#
+# CONFIG_rpm is not set
+# CONFIG_rpm-build is not set
+# CONFIG_rpm-dev is not set
+# CONFIG_rpm-dbg is not set
+
+#
+# rpmsg-echo-test
+#
+# CONFIG_rpmsg-echo-test is not set
+# CONFIG_rpmsg-echo-test-dbg is not set
+# CONFIG_rpmsg-echo-test-dev is not set
+
+#
+# rpmsg-mat-mul
+#
+# CONFIG_rpmsg-mat-mul is not set
+# CONFIG_rpmsg-mat-mul-dev is not set
+# CONFIG_rpmsg-mat-mul-dbg is not set
+
+#
+# rpmsg-proxy-app
+#
+# CONFIG_rpmsg-proxy-app is not set
+# CONFIG_rpmsg-proxy-app-dev is not set
+# CONFIG_rpmsg-proxy-app-dbg is not set
+
+#
+# serf
+#
+# CONFIG_serf is not set
+# CONFIG_serf-dev is not set
+# CONFIG_serf-dbg is not set
+
+#
+# sysfsutils
+#
+# CONFIG_sysfsutils is not set
+# CONFIG_libsysfs is not set
+# CONFIG_sysfsutils-dev is not set
+# CONFIG_sysfsutils-dbg is not set
+
+#
+# sysprof
+#
+# CONFIG_sysprof is not set
+# CONFIG_sysprof-dev is not set
+# CONFIG_sysprof-dbg is not set
+
+#
+# systemtap
+#
+# CONFIG_systemtap is not set
+# CONFIG_systemtap-dev is not set
+# CONFIG_systemtap-dbg is not set
+
+#
+# sysvinit-inittab
+#
+# CONFIG_sysvinit-inittab is not set
+# CONFIG_sysvinit-inittab-dbg is not set
+# CONFIG_sysvinit-inittab-dev is not set
+
+#
+# tbb
+#
+# CONFIG_tbb is not set
+# CONFIG_tbb-dev is not set
+# CONFIG_tbb-dbg is not set
+
+#
+# tcf-agent
+#
+CONFIG_tcf-agent=y
+# CONFIG_tcf-agent-dbg is not set
+# CONFIG_tcf-agent-dev is not set
+
+#
+# texi2html
+#
+# CONFIG_texi2html is not set
+# CONFIG_texi2html-dbg is not set
+# CONFIG_texi2html-dev is not set
+
+#
+# tiff
+#
+# CONFIG_tiff is not set
+# CONFIG_tiff-dev is not set
+# CONFIG_tiffxx is not set
+# CONFIG_tiff-dbg is not set
+# CONFIG_tiff-utils is not set
+
+#
+# util-macros
+#
+# CONFIG_util-macros is not set
+# CONFIG_util-macros-dbg is not set
+# CONFIG_util-macros-dev is not set
+
+#
+# v4l-utils
+#
+# CONFIG_v4l-utils is not set
+# CONFIG_libv4l is not set
+# CONFIG_ir-keytable is not set
+# CONFIG_v4l-utils-dev is not set
+# CONFIG_media-ctl is not set
+# CONFIG_rc-keymaps is not set
+# CONFIG_v4l-utils-dbg is not set
+# CONFIG_libv4l-dev is not set
+
+#
+# valgrind
+#
+# CONFIG_valgrind is not set
+# CONFIG_valgrind-dbg is not set
+# CONFIG_valgrind-dev is not set
+
+#
+# vte
+#
+# CONFIG_vte is not set
+# CONFIG_libvte is not set
+# CONFIG_vte-dbg is not set
+# CONFIG_vte-dev is not set
+
+#
+# watchdog
+#
+# CONFIG_watchdog is not set
+# CONFIG_watchdog-dbg is not set
+# CONFIG_watchdog-keepalive is not set
+# CONFIG_watchdog-dev is not set
+
+#
+# watchdog-config
+#
+# CONFIG_watchdog-config is not set
+# CONFIG_watchdog-config-dbg is not set
+# CONFIG_watchdog-config-dev is not set
+
+#
+# webkitgtk
+#
+# CONFIG_webkitgtk is not set
+# CONFIG_webkitgtk-dbg is not set
+# CONFIG_webkitgtk-dev is not set
+
+#
+# x11perf
+#
+# CONFIG_x11perf is not set
+# CONFIG_x11perf-dbg is not set
+# CONFIG_x11perf-dev is not set
+
+#
+# x264
+#
+# CONFIG_x264 is not set
+# CONFIG_x264-dbg is not set
+# CONFIG_x264-dev is not set
+# CONFIG_x264-bin is not set
+
+#
+# xauth
+#
+# CONFIG_xauth is not set
+# CONFIG_xauth-dbg is not set
+# CONFIG_xauth-dev is not set
+
+#
+# xcb-util-image
+#
+# CONFIG_xcb-util-image is not set
+# CONFIG_xcb-util-image-dev is not set
+# CONFIG_xcb-util-image-dbg is not set
+
+#
+# xcb-util-keysyms
+#
+# CONFIG_xcb-util-keysyms is not set
+# CONFIG_xcb-util-keysyms-dev is not set
+# CONFIG_xcb-util-keysyms-dbg is not set
+
+#
+# xcb-util-renderutil
+#
+# CONFIG_xcb-util-renderutil is not set
+# CONFIG_xcb-util-renderutil-dbg is not set
+# CONFIG_xcb-util-renderutil-dev is not set
+
+#
+# xcb-util-wm
+#
+# CONFIG_xcb-util-wm is not set
+# CONFIG_xcb-util-wm-dbg is not set
+# CONFIG_xcb-util-wm-dev is not set
+
+#
+# xdg-utils
+#
+# CONFIG_xdg-utils is not set
+# CONFIG_xdg-utils-dbg is not set
+# CONFIG_xdg-utils-dev is not set
+
+#
+# xdpyinfo
+#
+# CONFIG_xdpyinfo is not set
+# CONFIG_xdpyinfo-dev is not set
+# CONFIG_xdpyinfo-dbg is not set
+
+#
+# xf86-input-evdev
+#
+# CONFIG_xf86-input-evdev is not set
+# CONFIG_xf86-input-evdev-dbg is not set
+# CONFIG_xf86-input-evdev-dev is not set
+
+#
+# xf86-input-keyboard
+#
+# CONFIG_xf86-input-keyboard is not set
+# CONFIG_xf86-input-keyboard-dev is not set
+# CONFIG_xf86-input-keyboard-dbg is not set
+
+#
+# xf86-input-mouse
+#
+# CONFIG_xf86-input-mouse is not set
+# CONFIG_xf86-input-mouse-dbg is not set
+# CONFIG_xf86-input-mouse-dev is not set
+
+#
+# xf86-video-fbdev
+#
+# CONFIG_xf86-video-fbdev is not set
+# CONFIG_xf86-video-fbdev-dbg is not set
+# CONFIG_xf86-video-fbdev-dev is not set
+
+#
+# xhost
+#
+# CONFIG_xhost is not set
+# CONFIG_xhost-dbg is not set
+# CONFIG_xhost-dev is not set
+
+#
+# xinetd
+#
+# CONFIG_xinetd is not set
+# CONFIG_xinetd-dbg is not set
+# CONFIG_xinetd-dev is not set
+
+#
+# xinit
+#
+# CONFIG_xinit is not set
+# CONFIG_xinit-dev is not set
+# CONFIG_xinit-dbg is not set
+
+#
+# xinput
+#
+# CONFIG_xinput is not set
+# CONFIG_xinput-dev is not set
+# CONFIG_xinput-dbg is not set
+
+#
+# xinput-calibrator
+#
+# CONFIG_xinput-calibrator is not set
+# CONFIG_xinput-calibrator-dbg is not set
+# CONFIG_xinput-calibrator-dev is not set
+
+#
+# xkbcomp
+#
+# CONFIG_xkbcomp is not set
+# CONFIG_xkbcomp-dev is not set
+# CONFIG_xkbcomp-dbg is not set
+
+#
+# xmodmap
+#
+# CONFIG_xmodmap is not set
+# CONFIG_xmodmap-dbg is not set
+# CONFIG_xmodmap-dev is not set
+
+#
+# xprop
+#
+# CONFIG_xprop is not set
+# CONFIG_xprop-dbg is not set
+# CONFIG_xprop-dev is not set
+
+#
+# xrandr
+#
+# CONFIG_xrandr is not set
+# CONFIG_xrandr-dbg is not set
+# CONFIG_xrandr-dev is not set
+
+#
+# xserver-common
+#
+# CONFIG_xserver-common is not set
+# CONFIG_xserver-common-dev is not set
+# CONFIG_xserver-common-dbg is not set
+
+#
+# xset
+#
+# CONFIG_xset is not set
+# CONFIG_xset-dbg is not set
+# CONFIG_xset-dev is not set
+
+#
+# xtrans
+#
+# CONFIG_xtrans-dev is not set
+# CONFIG_xtrans-dbg is not set
+
+#
+# xvideo-tests
+#
+# CONFIG_xvideo-tests is not set
+# CONFIG_xvideo-tests-dev is not set
+# CONFIG_xvideo-tests-dbg is not set
+
+#
+# xwininfo
+#
+# CONFIG_xwininfo is not set
+# CONFIG_xwininfo-dev is not set
+# CONFIG_xwininfo-dbg is not set
+
+#
+# yavta
+#
+# CONFIG_yavta is not set
+# CONFIG_yavta-dbg is not set
+# CONFIG_yavta-dev is not set
+
+#
+# multimedia
+#
+
+#
+# alsa-plugins
+#
+# CONFIG_alsa-plugins is not set
+# CONFIG_alsa-plugins-dev is not set
+# CONFIG_alsa-plugins-dbg is not set
+# CONFIG_alsa-plugins-pulseaudio-conf is not set
+
+#
+# gstreamer
+#
+# CONFIG_gstreamer is not set
+# CONFIG_gstreamer-dbg is not set
+# CONFIG_gstreamer-dev is not set
+
+#
+# gstreamer1.0
+#
+# CONFIG_gstreamer1.0 is not set
+# CONFIG_gstreamer1.0-dev is not set
+# CONFIG_gstreamer1.0-bash-completion is not set
+# CONFIG_gstreamer1.0-dbg is not set
+
+#
+# net
+#
+
+#
+# bridge-utils
+#
+CONFIG_bridge-utils=y
+# CONFIG_bridge-utils-dbg is not set
+# CONFIG_bridge-utils-dev is not set
+
+#
+# netcat
+#
+# CONFIG_netcat is not set
+# CONFIG_netcat-dbg is not set
+# CONFIG_netcat-dev is not set
+
+#
+# tcpdump
+#
+# CONFIG_tcpdump is not set
+# CONFIG_tcpdump-dbg is not set
+# CONFIG_tcpdump-dev is not set
+
+#
+# network
+#
+
+#
+# avahi
+#
+# CONFIG_avahi-dbg is not set
+# CONFIG_libavahi-glib is not set
+# CONFIG_libavahi-client is not set
+# CONFIG_libavahi-core is not set
+# CONFIG_avahi-dev is not set
+# CONFIG_avahi-dnsconfd is not set
+# CONFIG_avahi-autoipd is not set
+# CONFIG_avahi-utils is not set
+# CONFIG_libavahi-common is not set
+# CONFIG_avahi-daemon is not set
+# CONFIG_libavahi-gobject is not set
+
+#
+# mobile-broadband-provider-info
+#
+# CONFIG_mobile-broadband-provider-info is not set
+# CONFIG_mobile-broadband-provider-info-dbg is not set
+# CONFIG_mobile-broadband-provider-info-dev is not set
+
+#
+# wpa-supplicant
+#
+# CONFIG_wpa-supplicant is not set
+# CONFIG_wpa-supplicant-passphrase is not set
+# CONFIG_wpa-supplicant-cli is not set
+# CONFIG_wpa-supplicant-dev is not set
+# CONFIG_wpa-supplicant-dbg is not set
+
+#
+# optional
+#
+
+#
+# libatomic-ops
+#
+# CONFIG_libatomic-ops is not set
+# CONFIG_libatomic-ops-dbg is not set
+# CONFIG_libatomic-ops-dev is not set
+
+#
+# mtools
+#
+# CONFIG_mtools is not set
+# CONFIG_mtools-dev is not set
+# CONFIG_mtools-dbg is not set
+
+#
+# utils
+#
+
+#
+# patch
+#
+# CONFIG_patch is not set
+# CONFIG_patch-dev is not set
+# CONFIG_patch-dbg is not set
+
+#
+# x11
+#
+
+#
+# base
+#
+
+#
+# libdrm
+#
+# CONFIG_libdrm is not set
+# CONFIG_libdrm-omap is not set
+# CONFIG_libdrm-amdgpu is not set
+# CONFIG_libdrm-dev is not set
+# CONFIG_libdrm-dbg is not set
+# CONFIG_libdrm-drivers is not set
+# CONFIG_libdrm-nouveau is not set
+# CONFIG_libdrm-tests is not set
+# CONFIG_libdrm-freedreno is not set
+# CONFIG_libdrm-radeon is not set
+# CONFIG_libdrm-kms is not set
+
+#
+# xcursor-transparent-theme
+#
+# CONFIG_xcursor-transparent-theme is not set
+# CONFIG_xcursor-transparent-theme-dev is not set
+# CONFIG_xcursor-transparent-theme-dbg is not set
+
+#
+# xserver-xf86-config
+#
+# CONFIG_xserver-xf86-config is not set
+# CONFIG_xserver-xf86-config-dbg is not set
+# CONFIG_xserver-xf86-config-dev is not set
+
+#
+# xserver-xorg
+#
+# CONFIG_xserver-xorg is not set
+# CONFIG_xserver-xorg-extension-record is not set
+# CONFIG_xserver-xorg-dev is not set
+# CONFIG_xserver-xorg-extension-glx is not set
+# CONFIG_xserver-xorg-extension-dbe is not set
+# CONFIG_xserver-xorg-utils is not set
+# CONFIG_xserver-xorg-module-libint10 is not set
+# CONFIG_xserver-xorg-extension-dri2 is not set
+# CONFIG_xserver-xorg-dbg is not set
+# CONFIG_xf86-video-modesetting is not set
+# CONFIG_xserver-xorg-module-exa is not set
+# CONFIG_xserver-xorg-extension-extmod is not set
+# CONFIG_xserver-xorg-extension-dri is not set
+# CONFIG_xserver-xorg-xvfb is not set
+# CONFIG_xserver-xorg-module-libwfb is not set
+
+#
+# builder
+#
+# CONFIG_builder is not set
+# CONFIG_builder-dev is not set
+# CONFIG_builder-dbg is not set
+
+#
+# fonts
+#
+
+#
+# liberation-fonts
+#
+# CONFIG_liberation-fonts is not set
+
+#
+# glew
+#
+# CONFIG_glew is not set
+# CONFIG_glew-dbg is not set
+# CONFIG_glew-bin is not set
+# CONFIG_glew-dev is not set
+
+#
+# gnome
+#
+
+#
+# adwaita-icon-theme
+#
+# CONFIG_adwaita-icon-theme is not set
+# CONFIG_adwaita-icon-theme-symbolic is not set
+# CONFIG_adwaita-icon-theme-hires is not set
+# CONFIG_adwaita-icon-theme-symbolic-hires is not set
+# CONFIG_adwaita-icon-theme-cursors is not set
+
+#
+# gconf
+#
+# CONFIG_gconf is not set
+# CONFIG_gconf-dev is not set
+# CONFIG_gconf-dbg is not set
+
+#
+# gnome-common
+#
+# CONFIG_gnome-common is not set
+# CONFIG_gnome-common-dbg is not set
+# CONFIG_gnome-common-dev is not set
+
+#
+# gnome-desktop3
+#
+# CONFIG_gnome-desktop3 is not set
+# CONFIG_gnome-desktop3-dbg is not set
+# CONFIG_gnome-desktop3-dev is not set
+# CONFIG_libgnome-desktop3 is not set
+
+#
+# gnome-themes-standard
+#
+# CONFIG_gnome-themes-standard-dev is not set
+# CONFIG_gnome-themes-standard-dbg is not set
+# CONFIG_gnome-theme-adwaita is not set
+
+#
+# libsoup-2.4
+#
+# CONFIG_libsoup-2.4 is not set
+# CONFIG_libsoup-2.4-dev is not set
+# CONFIG_libsoup-2.4-dbg is not set
+
+#
+# libglu
+#
+# CONFIG_libglu is not set
+# CONFIG_libglu-dbg is not set
+# CONFIG_libglu-dev is not set
+
+#
+# libs
+#
+
+#
+# atk
+#
+# CONFIG_atk is not set
+# CONFIG_atk-dbg is not set
+# CONFIG_atk-dev is not set
+
+#
+# libfm
+#
+# CONFIG_libfm is not set
+# CONFIG_libfm-mime is not set
+# CONFIG_libfm-dev is not set
+# CONFIG_libfm-dbg is not set
+
+#
+# libfm-extra
+#
+# CONFIG_libfm-extra is not set
+# CONFIG_libfm-extra-dev is not set
+# CONFIG_libfm-extra-dbg is not set
+
+#
+# libmatchbox
+#
+# CONFIG_libmatchbox is not set
+# CONFIG_libmatchbox-dev is not set
+# CONFIG_libmatchbox-dbg is not set
+
+#
+# libpthread-stubs
+#
+# CONFIG_libpthread-stubs is not set
+# CONFIG_libpthread-stubs-dev is not set
+# CONFIG_libpthread-stubs-dbg is not set
+
+#
+# libwnck3
+#
+# CONFIG_libwnck3 is not set
+# CONFIG_libwnck3-dbg is not set
+# CONFIG_libwnck3-dev is not set
+
+#
+# libxcb
+#
+# CONFIG_libxcb is not set
+# CONFIG_libxcb-dev is not set
+# CONFIG_libxcb-dbg is not set
+
+#
+# menu-cache
+#
+# CONFIG_menu-cache is not set
+# CONFIG_menu-cache-dev is not set
+# CONFIG_menu-cache-dbg is not set
+
+#
+# xcb-proto
+#
+# CONFIG_xcb-proto-dev is not set
+# CONFIG_python-xcbgen is not set
+# CONFIG_xcb-proto-dbg is not set
+
+#
+# xcb-util
+#
+# CONFIG_xcb-util is not set
+# CONFIG_xcb-util-dev is not set
+# CONFIG_xcb-util-dbg is not set
+
+#
+# xkeyboard-config
+#
+# CONFIG_xkeyboard-config is not set
+# CONFIG_xkeyboard-config-dbg is not set
+# CONFIG_xkeyboard-config-dev is not set
+
+#
+# matchbox-keyboard
+#
+# CONFIG_matchbox-keyboard is not set
+# CONFIG_matchbox-keyboard-dbg is not set
+# CONFIG_matchbox-keyboard-applet is not set
+# CONFIG_matchbox-keyboard-dev is not set
+# CONFIG_matchbox-keyboard-im is not set
+
+#
+# matchbox-session
+#
+# CONFIG_matchbox-session is not set
+# CONFIG_matchbox-session-dev is not set
+# CONFIG_matchbox-session-dbg is not set
+
+#
+# matchbox-session-sato
+#
+# CONFIG_matchbox-session-sato is not set
+# CONFIG_matchbox-session-sato-dev is not set
+# CONFIG_matchbox-session-sato-dbg is not set
+
+#
+# mesa
+#
+# CONFIG_mesa is not set
+# CONFIG_libgles2-mesa is not set
+# CONFIG_libgbm is not set
+# CONFIG_libegl-mesa is not set
+# CONFIG_mesa-dbg is not set
+# CONFIG_libgles1-mesa is not set
+# CONFIG_libgl-mesa-dev is not set
+# CONFIG_libegl-mesa-dev is not set
+# CONFIG_mesa-megadriver is not set
+# CONFIG_libgles2-mesa-dev is not set
+# CONFIG_libgles1-mesa-dev is not set
+# CONFIG_libglapi-dev is not set
+# CONFIG_mesa-dev is not set
+# CONFIG_libglapi is not set
+# CONFIG_libgbm-dev is not set
+# CONFIG_libgl-mesa is not set
+# CONFIG_libgles3-mesa-dev is not set
+
+#
+# mesa-demos
+#
+# CONFIG_mesa-demos is not set
+# CONFIG_mesa-demos-dev is not set
+# CONFIG_mesa-demos-dbg is not set
+
+#
+# mini-x-session
+#
+# CONFIG_mini-x-session is not set
+# CONFIG_mini-x-session-dbg is not set
+# CONFIG_mini-x-session-dev is not set
+
+#
+# pcmanfm
+#
+# CONFIG_pcmanfm is not set
+# CONFIG_pcmanfm-dbg is not set
+# CONFIG_pcmanfm-dev is not set
+
+#
+# settings-daemon
+#
+# CONFIG_settings-daemon is not set
+# CONFIG_settings-daemon-dev is not set
+# CONFIG_settings-daemon-dbg is not set
+
+#
+# utils
+#
+
+#
+# libcroco
+#
+# CONFIG_libcroco is not set
+# CONFIG_libcroco-dbg is not set
+# CONFIG_libcroco-dev is not set
+
+#
+# librsvg
+#
+# CONFIG_librsvg is not set
+# CONFIG_librsvg-gtk is not set
+# CONFIG_librsvg-dbg is not set
+# CONFIG_librsvg-dev is not set
+# CONFIG_rsvg is not set
+
+#
+# matchbox-terminal
+#
+# CONFIG_matchbox-terminal is not set
+# CONFIG_matchbox-terminal-dbg is not set
+# CONFIG_matchbox-terminal-dev is not set
+
+#
+# xrestop
+#
+# CONFIG_xrestop is not set
+# CONFIG_xrestop-dev is not set
+# CONFIG_xrestop-dbg is not set
+
+#
+# wm
+#
+
+#
+# libfakekey
+#
+# CONFIG_libfakekey is not set
+# CONFIG_libfakekey-dev is not set
+# CONFIG_libfakekey-dbg is not set
+
+#
+# matchbox-desktop
+#
+# CONFIG_matchbox-desktop is not set
+# CONFIG_matchbox-desktop-dev is not set
+# CONFIG_matchbox-desktop-dbg is not set
+
+#
+# matchbox-theme-sato
+#
+# CONFIG_matchbox-theme-sato is not set
+# CONFIG_matchbox-theme-sato-dev is not set
+# CONFIG_matchbox-theme-sato-dbg is not set
+
+#
+# matchbox-wm
+#
+# CONFIG_matchbox-wm is not set
+# CONFIG_matchbox-wm-dbg is not set
+# CONFIG_matchbox-wm-dev is not set
+
+#
+# xserver-nodm-init
+#
+# CONFIG_xserver-nodm-init is not set
+# CONFIG_xserver-nodm-init-dbg is not set
+# CONFIG_xserver-nodm-init-dev is not set
+
+#
+# Petalinux Package Groups
+#
+
+#
+# packagegroup-petalinux
+#
+CONFIG_packagegroup-petalinux=y
+# CONFIG_packagegroup-petalinux-dev is not set
+# CONFIG_packagegroup-petalinux-dbg is not set
+
+#
+# packagegroup-petalinux-display-debug
+#
+# CONFIG_packagegroup-petalinux-display-debug is not set
+# CONFIG_packagegroup-petalinux-display-debug-dbg is not set
+# CONFIG_packagegroup-petalinux-display-debug-dev is not set
+
+#
+# packagegroup-petalinux-lmsensors
+#
+# CONFIG_packagegroup-petalinux-lmsensors is not set
+# CONFIG_packagegroup-petalinux-lmsensors-dbg is not set
+# CONFIG_packagegroup-petalinux-lmsensors-dev is not set
+
+#
+# packagegroup-petalinux-matchbox
+#
+# CONFIG_packagegroup-petalinux-matchbox is not set
+# CONFIG_packagegroup-petalinux-matchbox-dbg is not set
+# CONFIG_packagegroup-petalinux-matchbox-dev is not set
+
+#
+# packagegroup-petalinux-networking-debug
+#
+# CONFIG_packagegroup-petalinux-networking-debug is not set
+# CONFIG_packagegroup-petalinux-networking-debug-dbg is not set
+# CONFIG_packagegroup-petalinux-networking-debug-dev is not set
+
+#
+# packagegroup-petalinux-networking-stack
+#
+# CONFIG_packagegroup-petalinux-networking-stack is not set
+# CONFIG_packagegroup-petalinux-networking-stack-dbg is not set
+# CONFIG_packagegroup-petalinux-networking-stack-dev is not set
+
+#
+# packagegroup-petalinux-openamp
+#
+# CONFIG_packagegroup-petalinux-openamp is not set
+# CONFIG_packagegroup-petalinux-openamp-dbg is not set
+# CONFIG_packagegroup-petalinux-openamp-dev is not set
+
+#
+# packagegroup-petalinux-opencv
+#
+# CONFIG_packagegroup-petalinux-opencv is not set
+# CONFIG_packagegroup-petalinux-opencv-dbg is not set
+# CONFIG_packagegroup-petalinux-opencv-dev is not set
+
+#
+# packagegroup-petalinux-python-modules
+#
+CONFIG_packagegroup-petalinux-python-modules=y
+# CONFIG_packagegroup-petalinux-python-modules-dbg is not set
+# CONFIG_packagegroup-petalinux-python-modules-dev is not set
+
+#
+# packagegroup-petalinux-qt
+#
+# CONFIG_packagegroup-petalinux-qt is not set
+# CONFIG_packagegroup-petalinux-qt-dbg is not set
+# CONFIG_packagegroup-petalinux-qt-dev is not set
+# CONFIG_inherit-populate-sdk-qt5 is not set
+
+#
+# packagegroup-petalinux-qt-extended
+#
+# CONFIG_packagegroup-petalinux-qt-extended is not set
+# CONFIG_packagegroup-petalinux-qt-extended-dbg is not set
+# CONFIG_packagegroup-petalinux-qt-extended-dev is not set
+
+#
+# packagegroup-petalinux-self-hosted
+#
+# CONFIG_packagegroup-petalinux-self-hosted is not set
+# CONFIG_packagegroup-petalinux-self-hosted-dbg is not set
+# CONFIG_packagegroup-petalinux-self-hosted-dev is not set
+
+#
+# packagegroup-petalinux-utils
+#
+CONFIG_packagegroup-petalinux-utils=y
+# CONFIG_packagegroup-petalinux-utils-dbg is not set
+# CONFIG_packagegroup-petalinux-utils-dev is not set
+
+#
+# packagegroup-petalinux-v4lutils
+#
+# CONFIG_packagegroup-petalinux-v4lutils is not set
+# CONFIG_packagegroup-petalinux-v4lutils-dbg is not set
+# CONFIG_packagegroup-petalinux-v4lutils-dev is not set
+
+#
+# packagegroup-petalinux-x11
+#
+# CONFIG_packagegroup-petalinux-x11 is not set
+# CONFIG_packagegroup-petalinux-x11-dbg is not set
+# CONFIG_packagegroup-petalinux-x11-dev is not set
+
+#
+# Image Features
+#
+CONFIG_imagefeature-ssh-server-dropbear=y
+# CONFIG_imagefeature-ssh-server-openssh is not set
+CONFIG_imagefeature-hwcodecs=y
+CONFIG_imagefeature-package-management=y
+# CONFIG_imagefeature-debug-tweaks is not set
+
+#
+# apps
+#
+# CONFIG_gpio-demo is not set
+CONFIG_peekpoke=y
+
+#
+# user packages
+#
+
+#
+# PetaLinux RootFS Settings
+#
+CONFIG_ROOTFS_ROOT_PASSWD="cmssucks"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/TopLevel_wrapper.bit b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/TopLevel_wrapper.bit
new file mode 100644
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diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
new file mode 100644
index 0000000..4428971
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER endeavour_axi_controller
+ OPTION supported_peripherals = (endeavour_axi_controller);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = endeavour_axi_controller;
+END DRIVER
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
new file mode 100644
index 0000000..ca357f9
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/data/endeavour_axi_controller.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "endeavour_axi_controller" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/Makefile b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/Makefile
new file mode 100644
index 0000000..e3be7d8
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling endeavour_axi_controller..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
new file mode 100644
index 0000000..788d112
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "endeavour_axi_controller.h"
+
+/************************** Function Definitions ***************************/
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
new file mode 100644
index 0000000..a4b6216
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller.h
@@ -0,0 +1,83 @@
+
+#ifndef ENDEAVOUR_FMC_CONTROLLER_H
+#define ENDEAVOUR_FMC_CONTROLLER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG0_OFFSET 0
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG1_OFFSET 4
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG2_OFFSET 8
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG3_OFFSET 12
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG4_OFFSET 16
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG5_OFFSET 20
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG6_OFFSET 24
+#define ENDEAVOUR_FMC_CONTROLLER_S00_AXI_SLV_REG7_OFFSET 28
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a ENDEAVOUR_FMC_CONTROLLER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the ENDEAVOUR_FMC_CONTROLLERdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void ENDEAVOUR_FMC_CONTROLLER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define ENDEAVOUR_FMC_CONTROLLER_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a ENDEAVOUR_FMC_CONTROLLER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the ENDEAVOUR_FMC_CONTROLLER device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 ENDEAVOUR_FMC_CONTROLLER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define ENDEAVOUR_FMC_CONTROLLER_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the ENDEAVOUR_FMC_CONTROLLER instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus ENDEAVOUR_FMC_CONTROLLER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // ENDEAVOUR_FMC_CONTROLLER_H
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
new file mode 100644
index 0000000..fbb3cbb
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/drivers/endeavour_axi_controller_v1_0/src/endeavour_axi_controller_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "endeavour_axi_controller.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the ENDEAVOUR_FMC_CONTROLLERinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus ENDEAVOUR_FMC_CONTROLLER_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ ENDEAVOUR_FMC_CONTROLLER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( ENDEAVOUR_FMC_CONTROLLER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/metadata b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/metadata
new file mode 100644
index 0000000..7d9fa0b
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/metadata
@@ -0,0 +1 @@
+HARDWARE_SOURCE=
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.c
new file mode 100644
index 0000000..f4d8fc6
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.c
@@ -0,0 +1,12086 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
+* otherwise to promote the sale, use or other dealings in this Software without prior written
+* authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. .. START: AFI2 SECURE REGISTER
+ // .. .. FINISH: AFI2 SECURE REGISTER
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ {
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.h b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.h
new file mode 100644
index 0000000..8d25378
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.h
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158730
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 25000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 10000000
+#define FPGA2_FREQ 10000000
+#define FPGA3_FREQ 10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.html b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.html
new file mode 100644
index 0000000..12a00a7
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.html
@@ -0,0 +1,137152 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="content-type" content="text/html;charset=UTF-8">
+<title>Zynq PS configuration detail</title>
+<style type="text/css">.sitename { background-color: #EEE;border:2px ridge #FFCF01;color: #B20838; font-size:22px; font-style:oblique; font-weight:bold;margin:0px 0px 10px 0px;padding:5px 0px; text-align:center; z-index: 3; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.navpath {color: #FFCF01; font-size:8px;padding: 7px 2px 2px 11px; text-transform: capitalize; z-index:2;}.navbar { background-color: #B20838; background-color: #EE3424;color: #fff;border: 1px solid #000; border-left: 0px solid #000; border-right: 0px solid #000; font-family: arial, sans-serif; font-weight: bold;height:50px; letter-spacing: 2px; text-transform: uppercase;position:fixed;top:0px;left:0px;right:0px; z-index: 0; /* -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px; */}.navlink_container { text-align:center;position: absolute;bottom:-1px;}.navbar a {color: #FFF;}.navbar a:hover {color: #EC891D;}.navbar ul { margin-left: 0px;height: 70px;overflow: hidden;}.navbar li { background-color: #B20838;padding: 4px 400px 4px 400px;float: left; font-size:24px;width: 800px;}.navbar li:hover { background-color: #000;color: #eee;}.navbar li#last { padding-right: 10px; border-right: 1px solid #050505; background-image: none;}.nav_splash {width: 80%;float:right; z-index: 0;}.search_form {position:fixed;top:25px;right:5px; z-index:2;}.action_tray {padding:5px;position: fixed;top: 57px;width: 210px;}.action_tray_header { text-align: center; background-color: #DDD;border: 2px groove #FFCF01; margin-bottom: 10px; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.action_tray_header:hover { background-color: #eee;}.action_container {padding:10px 5px; text-align: center;}.action { background-color: #FFF;border: 1px outset #B20838;padding: 5px 0px; font-weight:bolder; margin-bottom: 2px; -moz-border-radius: 7px; -webkit-border-radius: 7px; -khtml-border-radius: 7px; border-radius: 7px; text-transform:uppercase;color: #B20838; }.action:hover {border: 1px inset #000; background-color: #FFCF01;color: #000;}.content_container { background-color:#fff;border: 0px solid #000; border-left: 1px solid #000;color: #000;overflow:auto;padding: 10px;position:fixed;left: 224px;top: 52px;right: 0px;bottom:0px; text-align: left; padding-right:25px; z-index:1;}.SelectButtons { background-color:white; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 10px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.viewButtons { background-color:#F3F781; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 0px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.db_selector {margin:10px 0px 10px 0px;}.db_selector_title { background-color: #00FFFF;border: 1px solid #000; margin-bottom:5px; font-weight:bold;padding:5px 3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select { background-color: #FFEFC0; font-weight:bolder;padding:3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select:hover { background-color: #AFEFF0; }</style>
+<script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_3_0"; window.location = '#ps7_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_2_0"; window.location = '#ps7_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_1_0"; window.location = '#ps7_mio_init_data_1_0'; }}</script>
+<body>
+<DIV class="navbar">
+<DIV class="navlink_container">
+<A id="Summary" href="#">
+<li>
+<DIV class="navlink">Zynq PS Register Summary Viewer
+</DIV>
+</li>
+</A>
+</DIV>
+</DIV>
+<DIV class="action_tray">
+<A id="Report" href="#">
+<DIV class="sitename">Zynq PS7 Summary Report
+</DIV>
+</A>
+<DIV class="viewButtons">User Configurations
+</DIV>
+<DIV class="viewButtons">
+<A id="MIO_Configurations" href="#ZynqPerTab">
+<DIV class="viewButtonHalf">MIO Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="CLK_Configurations" href="#ClockInfoTab">
+<DIV class="viewButtonHalf">CLK Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="DDR_Configurations" href="#DDRInfoTab">
+<DIV class="viewButtonHalf">DDR Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="SMC_Configurations" href="#SMCInfoTab">
+<DIV class="viewButtonHalf">SMC Configurations
+</DIV>
+</A>
+</DIV>
+<DIV class="db_selector">
+<DIV class="db_selector_title">Select Version:
+<select id="db_selection" class="db_selection" onChange="ChangeSilRegLink(this.id)" width="210" style="width: 210px">
+<option value="Silicon3.0">Silicon 3.0</option>
+<option value="Silicon2.0">Silicon 2.0</option>
+<option value="Silicon1.0">Silicon 1.0</option>
+</select>
+</DIV>
+</DIV>
+<DIV class="viewButtons">Zynq Register View
+</DIV>
+<DIV class="action_container">
+<A id="MIO_Registers" href="#ps7_mio_init_data_3_0">
+<DIV class="action">MIO Registers
+</DIV>
+</A>
+<A id="PLL_Registers" href="#ps7_pll_init_data_3_0">
+<DIV class="action">PLL Registers
+</DIV>
+</A>
+<A id="Clock_Registers" href="#ps7_clock_init_data_3_0">
+<DIV class="action">Clock Registers
+</DIV>
+</A>
+<A id="DDR_Registers" href="#ps7_ddr_init_data_3_0">
+<DIV class="action">DDR Registers
+</DIV>
+</A>
+<A id="Peri_Registers" href="#ps7_peripherals_init_data_3_0">
+<DIV class="action">Peripherals Registers
+</DIV>
+</A>
+</DIV>
+<DIV class="content_container">This design is targeted for xc7z020 board (part number: xc7z020clg400-1)
+
+<br>
+<H1>Zynq Design Summary</H1>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Device</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+xc7z020
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>SpeedGrade</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+-1
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Part</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+xc7z020clg400-1
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Description</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+Zynq PS Configuration Report with register details
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Vendor</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+Xilinx
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ZynqPerTab">MIO Table View</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>MIO Pin</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Peripheral</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Signal</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>IO Type</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Speed</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Pullup</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_ss_b
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[3]/HOLD_B
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_sclk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[7]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi_fbclk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[9]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[10]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[11]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[12]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[13]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[14]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[15]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tx_clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tx_ctl
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rx_clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rx_ctl
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[4]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+dir
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+stp
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+nxt
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 33</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 34</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 35</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 36</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 37</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[5]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[6]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 39</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[7]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 41</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+cmd
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 42</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 43</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 45</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 46</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+cd
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 47</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[47]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+UART 1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tx
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 49</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+UART 1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rx
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+wp
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 51</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[51]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 52</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+mdc
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 53</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+mdio
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+</TABLE>
+<H2><a name="DDRInfoTab">DDR Memory information</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Parameter name</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Value</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Enable DDR</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enable DDR Controller of Zynq PS
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Memory Part</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+MT41K256M16 RE-125
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM bus width</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+32 Bit
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ECC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+ECC is supported only for data width of 16-bit
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>BURST Length (lppdr only)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+8
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Internal Vref</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Operating Frequency (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+533.333333
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>HIGH temperature</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Normal (0-85)
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the operating temparature
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM IC bus width</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+16 Bits
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the width of the DRAM chip
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM Device Capacity</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+4096 MBits
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Speed Bin</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+DDR3_1066F
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Speed Bin
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>BANK Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+3
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ROW Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+15
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row address for ACTIVE commands
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>COLUMN Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row address for READ/WRITE commands
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CAS Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CAS Write Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+6
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the CAS Write Latency
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RAS to CAS Delay</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RECHARGE Time</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tRC (ns )</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+48.75
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row cycle time tRC (ns)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tRASmin ( ns )</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+35.0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tFAW</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+40.0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+It restricts the number of activates that can be done within a certain window of time
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ADDITIVE Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Write levelling</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Read gate</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Read gate</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [0] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.073
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [1] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.072
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [2] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.024
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [3] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.023
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [0] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.294
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [1] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.298
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [2] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.338
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [3] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.334
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ClockInfoTab">PS Clocks information</a></H2>
+<H2><a name="ClockInfoTab">PS Reference Clock : 33.333333</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Peripheral</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>PLL source</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Frequency (MHz)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CPU 6x Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+ARM PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+666.666687
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>QSPI Flash Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+200.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ENET0 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+125.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>SDIO Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+25.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>UART Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+50.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>TTC0 CLK0 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+CPU_1X
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+111.111115
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>TTC0 CLK1 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+CPU_1X
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+111.111115
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>TTC0 CLK2 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+CPU_1X
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+111.111115
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA0 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+100.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA1 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA2 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA3 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the CPU clock source.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_1x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_3x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_3x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_2x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Rx Clock and Rx Signals Select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control - 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Rx Clock and Rx Signals Select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Second divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for Quad SPI Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for UART Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1402</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1ec044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg5">
+ctrl_reg5
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg6">
+ctrl_reg6
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_dfi_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fdffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>270872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c008</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable Write Combine: 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksrx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckesr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg5@0XF8006078</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>466111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckcsx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg6@0XF800607C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>32222</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum d'128)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2ec00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2ec03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>6ffffefe</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff5</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c61c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_REFIO_TEST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Mode. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7feffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables Pullup on IO Buffer pin 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2e0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0032</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_INP_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PL to PS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_OUT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PS to PL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_INP_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PL to PS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_OUT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PS to PL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>AFI2 SECURE REGISTER</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
+<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the CPU clock source.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_1x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_3x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_3x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_2x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Rx Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control - 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Rx Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Second divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for Quad SPI Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for UART Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1402</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the CPU clock ration: 0: 4:2:1 1: 6:2:1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1ec044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg5">
+ctrl_reg5
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg6">
+ctrl_reg6
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_REFRESH_TIMER01">
+CHE_REFRESH_TIMER01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config0">
+PHY_Config0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config1">
+PHY_Config1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config2">
+PHY_Config2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config3">
+PHY_Config3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio0">
+phy_init_ratio0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio1">
+phy_init_ratio1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio2">
+phy_init_ratio2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio3">
+phy_init_ratio3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg0">
+phy_rd_dqs_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg1">
+phy_rd_dqs_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg2">
+phy_rd_dqs_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg3">
+phy_rd_dqs_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg0">
+phy_wr_dqs_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg1">
+phy_wr_dqs_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg2">
+phy_wr_dqs_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg3">
+phy_wr_dqs_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg0">
+phy_we_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg1">
+phy_we_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg2">
+phy_we_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg3">
+phy_we_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv0">
+wr_data_slv0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv1">
+wr_data_slv1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv2">
+wr_data_slv2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv3">
+wr_data_slv3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port0">
+axi_priority_wr_port0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port1">
+axi_priority_wr_port1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port2">
+axi_priority_wr_port2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port3">
+axi_priority_wr_port3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port0">
+axi_priority_rd_port0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port1">
+axi_priority_rd_port1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port2">
+axi_priority_rd_port2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port3">
+axi_priority_rd_port3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_block</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_open_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_4bank_ram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_sdram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: sdram device 0: non-sdram device</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_clock_stop_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>272872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_rank_rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_debug_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq0_wait_t</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c248</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>101</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable Write Combine: 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksrx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckesr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg5@0XF8006078</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>466111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckcsx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg6@0XF800607C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>32222</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer0_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer1_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_2t_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pre_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config0">Register (<A href=#mod___slcr> slcr </A>)PHY_Config0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config0@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config1">Register (<A href=#mod___slcr> slcr </A>)PHY_Config1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config1@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config2">Register (<A href=#mod___slcr> slcr </A>)PHY_Config2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config2@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config3">Register (<A href=#mod___slcr> slcr </A>)PHY_Config3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config3@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio0">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio0@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio1">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio1@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio2">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio2@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio3">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2ec00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio3@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2ec03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg0@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg1@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg2@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg3@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg0@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg1@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg2@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg3@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg0@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg1@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg2@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg3@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv0">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv0@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv1">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv1@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv2">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv2@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv3">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv3@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Loopback testing. 1: enable, 0: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_all_dq_mpr_rd_resp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rank0_delays</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_int_lpbk</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10040080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port0@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port1@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port2@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port3@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port0@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port1@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port2@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port3@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_per_bank_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Address 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Address 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Address</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Data</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Diff</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Address 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Address 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c61c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Address</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Data</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Diff</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Clock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_TEST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 if any iob's use a terminate type, or if dci test block used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>test Internal to IO bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate DCI clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRN)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRP)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate Reset</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Need explanation here</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up on IO Buffer pin 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2e0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0032</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: start break transmission, 1: stop break transmission.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter, 0: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
+<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CORTEX A9 Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CORTEX A9 Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor value for the ddr_3xclk</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Linear Quad-SPI Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP 2X Clock Contol</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA 0 Output Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>6:2:1 ratio clock, if set</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Linear Quad-SPI Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1402</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active 0 - Clock is disabled 1 - Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP 2X Clock Contol</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA 0 Output Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>6:2:1 ratio clock, if set</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1ec044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two rank configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM initialization parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM burst 8 read/write register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM bank address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_REFRESH_TIMER01">
+CHE_REFRESH_TIMER01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register (2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register (3)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_block</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_open_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_4bank_ram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two rank configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_sdram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = sdram device 0 = non-sdram device</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_clock_stop_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = disable the pad power down feature 0 = Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>272872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = DDRC will use 2T timing 0 = DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_rank_rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 1 = read 0 = write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM initialization parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM burst 8 read/write register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_debug_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq0_wait_t</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM bank address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c248</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>101</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable Write Combine</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer0_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer1_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_2t_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pre_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2c400</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2ec00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2ec03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>83</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>105</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>106</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>110</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Loopback testing. 1: enable, 0: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_all_dq_mpr_rd_resp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rank0_delays</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_int_lpbk</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10040080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register (2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register (3)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_per_bank_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Address 0 Configuartion Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Address 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential Clock Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Address Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Data Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Differential Strobe Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Clcok Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DDR Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 10</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 11</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 12</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 13</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 14</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 15</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 17</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 18</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 19</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 20</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 21</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 22</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 23</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 24</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 25</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 26</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 27</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 28</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 29</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 30</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 31</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 32</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 34</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 35</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 36</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 37</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 38</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 39</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 40</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 41</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 42</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 43</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 44</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 45</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 46</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 47</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 48</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 49</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 50</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 51</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 52</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 53</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Address 0 Configuartion Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Address 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential Clock Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c61c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Address Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Data Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Differential Strobe Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f9861c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Clcok Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>73ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DDR Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 if any iob's use a terminate type, or if dci test block used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>test Internal to IO bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate DCI clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRN)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRP)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate Reset</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Need explanation here</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 7</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 8</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 9</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 10</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 11</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 12</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 13</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 14</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 15</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 17</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 18</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 19</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 20</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>202</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 21</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 22</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 23</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 24</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 25</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 26</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>203</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 27</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 28</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 29</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 30</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 31</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 32</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 33</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 34</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 35</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>205</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 36</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 37</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 38</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>204</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 39</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 40</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 41</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 42</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 43</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 44</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 45</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 46</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 47</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 48</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 49</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 50</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 51</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 52</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 53</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2e0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2e0032</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break. 1 = stop transmission of the break.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter 1 = receiver timeout counter is restarted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable. 1, the transmitter is disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable. 1= receiver is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.tcl b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.tcl
new file mode 100644
index 0000000..7c5f7b7
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init.tcl
@@ -0,0 +1,814 @@
+proc ps7_pll_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00002801
+ mask_write 0XF8000154 0x00003F33 0x00001402
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x0007FFFF 0x00001082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+ mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00000003 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x0003F03F 0x0003C008
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x00010000 0x00000000
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF8006078 0x03FFFFFF 0x00466111
+ mask_write 0XF800607C 0x000FFFFF 0x00032222
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x00000200 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x0002C000
+ mask_write 0XF8006130 0x000FFFFF 0x0002C400
+ mask_write 0XF8006134 0x000FFFFF 0x0002F003
+ mask_write 0XF8006138 0x000FFFFF 0x0002EC03
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x00000077
+ mask_write 0XF8006158 0x000FFFFF 0x00000077
+ mask_write 0XF800615C 0x000FFFFF 0x00000083
+ mask_write 0XF8006160 0x000FFFFF 0x00000083
+ mask_write 0XF8006168 0x001FFFFF 0x00000105
+ mask_write 0XF800616C 0x001FFFFF 0x00000106
+ mask_write 0XF8006170 0x001FFFFF 0x00000111
+ mask_write 0XF8006174 0x001FFFFF 0x00000110
+ mask_write 0XF800617C 0x000FFFFF 0x000000B7
+ mask_write 0XF8006180 0x000FFFFF 0x000000B7
+ mask_write 0XF8006184 0x000FFFFF 0x000000C3
+ mask_write 0XF8006188 0x000FFFFF 0x000000C3
+ mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000703FF 0x000003FF
+ mask_write 0XF800620C 0x000703FF 0x000003FF
+ mask_write 0XF8006210 0x000703FF 0x000003FF
+ mask_write 0XF8006214 0x000703FF 0x000003FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF5 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B6C 0x00007FFF 0x00000260
+ mask_write 0XF8000B70 0x00000001 0x00000001
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00000600
+ mask_write 0XF8000704 0x00003FFF 0x00000602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00000600
+ mask_write 0XF8000728 0x00003FFF 0x00000600
+ mask_write 0XF800072C 0x00003FFF 0x00000600
+ mask_write 0XF8000730 0x00003FFF 0x00000600
+ mask_write 0XF8000734 0x00003FFF 0x00000600
+ mask_write 0XF8000738 0x00003FFF 0x00000600
+ mask_write 0XF800073C 0x00003FFF 0x00000600
+ mask_write 0XF8000740 0x00003FFF 0x00000202
+ mask_write 0XF8000744 0x00003FFF 0x00000202
+ mask_write 0XF8000748 0x00003FFF 0x00000202
+ mask_write 0XF800074C 0x00003FFF 0x00000202
+ mask_write 0XF8000750 0x00003FFF 0x00000202
+ mask_write 0XF8000754 0x00003FFF 0x00000202
+ mask_write 0XF8000758 0x00003FFF 0x00000203
+ mask_write 0XF800075C 0x00003FFF 0x00000203
+ mask_write 0XF8000760 0x00003FFF 0x00000203
+ mask_write 0XF8000764 0x00003FFF 0x00000203
+ mask_write 0XF8000768 0x00003FFF 0x00000203
+ mask_write 0XF800076C 0x00003FFF 0x00000203
+ mask_write 0XF8000770 0x00003FFF 0x00000204
+ mask_write 0XF8000774 0x00003FFF 0x00000205
+ mask_write 0XF8000778 0x00003FFF 0x00000204
+ mask_write 0XF800077C 0x00003FFF 0x00000205
+ mask_write 0XF8000780 0x00003FFF 0x00000204
+ mask_write 0XF8000784 0x00003FFF 0x00000204
+ mask_write 0XF8000788 0x00003FFF 0x00000204
+ mask_write 0XF800078C 0x00003FFF 0x00000204
+ mask_write 0XF8000790 0x00003FFF 0x00000205
+ mask_write 0XF8000794 0x00003FFF 0x00000204
+ mask_write 0XF8000798 0x00003FFF 0x00000204
+ mask_write 0XF800079C 0x00003FFF 0x00000204
+ mask_write 0XF80007A0 0x00003FFF 0x00000280
+ mask_write 0XF80007A4 0x00003FFF 0x00000280
+ mask_write 0XF80007A8 0x00003FFF 0x00000280
+ mask_write 0XF80007AC 0x00003FFF 0x00000280
+ mask_write 0XF80007B0 0x00003FFF 0x00000280
+ mask_write 0XF80007B4 0x00003FFF 0x00000280
+ mask_write 0XF80007B8 0x00003F01 0x00000201
+ mask_write 0XF80007BC 0x00003FFF 0x00000200
+ mask_write 0XF80007C0 0x00003FFF 0x000002E0
+ mask_write 0XF80007C4 0x00003FFF 0x000002E1
+ mask_write 0XF80007C8 0x00003F01 0x00000201
+ mask_write 0XF80007CC 0x00003FFF 0x00000200
+ mask_write 0XF80007D0 0x00003FFF 0x00000280
+ mask_write 0XF80007D4 0x00003FFF 0x00000280
+ mask_write 0XF8000830 0x003F003F 0x002E0032
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000003E
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x000003FF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00002801
+ mask_write 0XF8000154 0x00003F33 0x00001402
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+ mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00001FC3 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x0001FFFF 0x00000101
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF8006078 0x03FFFFFF 0x00466111
+ mask_write 0XF800607C 0x000FFFFF 0x00032222
+ mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x000007FF 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x0002C000
+ mask_write 0XF8006130 0x000FFFFF 0x0002C400
+ mask_write 0XF8006134 0x000FFFFF 0x0002F003
+ mask_write 0XF8006138 0x000FFFFF 0x0002EC03
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x00000077
+ mask_write 0XF8006158 0x000FFFFF 0x00000077
+ mask_write 0XF800615C 0x000FFFFF 0x00000083
+ mask_write 0XF8006160 0x000FFFFF 0x00000083
+ mask_write 0XF8006168 0x001FFFFF 0x00000105
+ mask_write 0XF800616C 0x001FFFFF 0x00000106
+ mask_write 0XF8006170 0x001FFFFF 0x00000111
+ mask_write 0XF8006174 0x001FFFFF 0x00000110
+ mask_write 0XF800617C 0x000FFFFF 0x000000B7
+ mask_write 0XF8006180 0x000FFFFF 0x000000B7
+ mask_write 0XF8006184 0x000FFFFF 0x000000C3
+ mask_write 0XF8006188 0x000FFFFF 0x000000C3
+ mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000F03FF 0x000803FF
+ mask_write 0XF800620C 0x000F03FF 0x000803FF
+ mask_write 0XF8006210 0x000F03FF 0x000803FF
+ mask_write 0XF8006214 0x000F03FF 0x000803FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF7 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B6C 0x00007FFF 0x00000260
+ mask_write 0XF8000B70 0x00000021 0x00000021
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00000600
+ mask_write 0XF8000704 0x00003FFF 0x00000602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00000600
+ mask_write 0XF8000728 0x00003FFF 0x00000600
+ mask_write 0XF800072C 0x00003FFF 0x00000600
+ mask_write 0XF8000730 0x00003FFF 0x00000600
+ mask_write 0XF8000734 0x00003FFF 0x00000600
+ mask_write 0XF8000738 0x00003FFF 0x00000600
+ mask_write 0XF800073C 0x00003FFF 0x00000600
+ mask_write 0XF8000740 0x00003FFF 0x00000202
+ mask_write 0XF8000744 0x00003FFF 0x00000202
+ mask_write 0XF8000748 0x00003FFF 0x00000202
+ mask_write 0XF800074C 0x00003FFF 0x00000202
+ mask_write 0XF8000750 0x00003FFF 0x00000202
+ mask_write 0XF8000754 0x00003FFF 0x00000202
+ mask_write 0XF8000758 0x00003FFF 0x00000203
+ mask_write 0XF800075C 0x00003FFF 0x00000203
+ mask_write 0XF8000760 0x00003FFF 0x00000203
+ mask_write 0XF8000764 0x00003FFF 0x00000203
+ mask_write 0XF8000768 0x00003FFF 0x00000203
+ mask_write 0XF800076C 0x00003FFF 0x00000203
+ mask_write 0XF8000770 0x00003FFF 0x00000204
+ mask_write 0XF8000774 0x00003FFF 0x00000205
+ mask_write 0XF8000778 0x00003FFF 0x00000204
+ mask_write 0XF800077C 0x00003FFF 0x00000205
+ mask_write 0XF8000780 0x00003FFF 0x00000204
+ mask_write 0XF8000784 0x00003FFF 0x00000204
+ mask_write 0XF8000788 0x00003FFF 0x00000204
+ mask_write 0XF800078C 0x00003FFF 0x00000204
+ mask_write 0XF8000790 0x00003FFF 0x00000205
+ mask_write 0XF8000794 0x00003FFF 0x00000204
+ mask_write 0XF8000798 0x00003FFF 0x00000204
+ mask_write 0XF800079C 0x00003FFF 0x00000204
+ mask_write 0XF80007A0 0x00003FFF 0x00000280
+ mask_write 0XF80007A4 0x00003FFF 0x00000280
+ mask_write 0XF80007A8 0x00003FFF 0x00000280
+ mask_write 0XF80007AC 0x00003FFF 0x00000280
+ mask_write 0XF80007B0 0x00003FFF 0x00000280
+ mask_write 0XF80007B4 0x00003FFF 0x00000280
+ mask_write 0XF80007B8 0x00003F01 0x00000201
+ mask_write 0XF80007BC 0x00003FFF 0x00000200
+ mask_write 0XF80007C0 0x00003FFF 0x000002E0
+ mask_write 0XF80007C4 0x00003FFF 0x000002E1
+ mask_write 0XF80007C8 0x00003F01 0x00000201
+ mask_write 0XF80007CC 0x00003FFF 0x00000200
+ mask_write 0XF80007D0 0x00003FFF 0x00000280
+ mask_write 0XF80007D4 0x00003FFF 0x00000280
+ mask_write 0XF8000830 0x003F003F 0x002E0032
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000003E
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x00000FFF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00002801
+ mask_write 0XF8000154 0x00003F33 0x00001402
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+ mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00001FC3 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x0001FFFF 0x00000101
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x000007FF 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x0002C000
+ mask_write 0XF8006130 0x000FFFFF 0x0002C400
+ mask_write 0XF8006134 0x000FFFFF 0x0002F003
+ mask_write 0XF8006138 0x000FFFFF 0x0002EC03
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x00000077
+ mask_write 0XF8006158 0x000FFFFF 0x00000077
+ mask_write 0XF800615C 0x000FFFFF 0x00000083
+ mask_write 0XF8006160 0x000FFFFF 0x00000083
+ mask_write 0XF8006168 0x001FFFFF 0x00000105
+ mask_write 0XF800616C 0x001FFFFF 0x00000106
+ mask_write 0XF8006170 0x001FFFFF 0x00000111
+ mask_write 0XF8006174 0x001FFFFF 0x00000110
+ mask_write 0XF800617C 0x000FFFFF 0x000000B7
+ mask_write 0XF8006180 0x000FFFFF 0x000000B7
+ mask_write 0XF8006184 0x000FFFFF 0x000000C3
+ mask_write 0XF8006188 0x000FFFFF 0x000000C3
+ mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000F03FF 0x000803FF
+ mask_write 0XF800620C 0x000F03FF 0x000803FF
+ mask_write 0XF8006210 0x000F03FF 0x000803FF
+ mask_write 0XF8006214 0x000F03FF 0x000803FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF7 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+ mask_write 0XF8000B6C 0x000073FF 0x00000260
+ mask_write 0XF8000B70 0x00000021 0x00000021
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00000600
+ mask_write 0XF8000704 0x00003FFF 0x00000602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00000600
+ mask_write 0XF8000728 0x00003FFF 0x00000600
+ mask_write 0XF800072C 0x00003FFF 0x00000600
+ mask_write 0XF8000730 0x00003FFF 0x00000600
+ mask_write 0XF8000734 0x00003FFF 0x00000600
+ mask_write 0XF8000738 0x00003FFF 0x00000600
+ mask_write 0XF800073C 0x00003FFF 0x00000600
+ mask_write 0XF8000740 0x00003FFF 0x00000202
+ mask_write 0XF8000744 0x00003FFF 0x00000202
+ mask_write 0XF8000748 0x00003FFF 0x00000202
+ mask_write 0XF800074C 0x00003FFF 0x00000202
+ mask_write 0XF8000750 0x00003FFF 0x00000202
+ mask_write 0XF8000754 0x00003FFF 0x00000202
+ mask_write 0XF8000758 0x00003FFF 0x00000203
+ mask_write 0XF800075C 0x00003FFF 0x00000203
+ mask_write 0XF8000760 0x00003FFF 0x00000203
+ mask_write 0XF8000764 0x00003FFF 0x00000203
+ mask_write 0XF8000768 0x00003FFF 0x00000203
+ mask_write 0XF800076C 0x00003FFF 0x00000203
+ mask_write 0XF8000770 0x00003FFF 0x00000204
+ mask_write 0XF8000774 0x00003FFF 0x00000205
+ mask_write 0XF8000778 0x00003FFF 0x00000204
+ mask_write 0XF800077C 0x00003FFF 0x00000205
+ mask_write 0XF8000780 0x00003FFF 0x00000204
+ mask_write 0XF8000784 0x00003FFF 0x00000204
+ mask_write 0XF8000788 0x00003FFF 0x00000204
+ mask_write 0XF800078C 0x00003FFF 0x00000204
+ mask_write 0XF8000790 0x00003FFF 0x00000205
+ mask_write 0XF8000794 0x00003FFF 0x00000204
+ mask_write 0XF8000798 0x00003FFF 0x00000204
+ mask_write 0XF800079C 0x00003FFF 0x00000204
+ mask_write 0XF80007A0 0x00003FFF 0x00000280
+ mask_write 0XF80007A4 0x00003FFF 0x00000280
+ mask_write 0XF80007A8 0x00003FFF 0x00000280
+ mask_write 0XF80007AC 0x00003FFF 0x00000280
+ mask_write 0XF80007B0 0x00003FFF 0x00000280
+ mask_write 0XF80007B4 0x00003FFF 0x00000280
+ mask_write 0XF80007B8 0x00003F01 0x00000201
+ mask_write 0XF80007BC 0x00003FFF 0x00000200
+ mask_write 0XF80007C0 0x00003FFF 0x000002E0
+ mask_write 0XF80007C4 0x00003FFF 0x000002E1
+ mask_write 0XF80007C8 0x00003F01 0x00000201
+ mask_write 0XF80007CC 0x00003FFF 0x00000200
+ mask_write 0XF80007D0 0x00003FFF 0x00000280
+ mask_write 0XF80007D4 0x00003FFF 0x00000280
+ mask_write 0XF8000830 0x003F003F 0x002E0032
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000003E
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x00000FFF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ 667000000
+
+
+
+proc mask_poll { addr mask } {
+ set count 1
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval & $mask}]
+ while { $maskedval == 0 } {
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval & $mask}]
+ set count [ expr { $count + 1 } ]
+ if { $count == 100000000 } {
+ puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+ break
+ }
+ }
+}
+
+
+
+proc mask_delay { addr val } {
+ set delay [ get_number_of_cycles_for_delay $val ]
+ perf_reset_and_start_timer
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval < $delay}]
+ while { $maskedval == 1 } {
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval < $delay}]
+ }
+ perf_reset_clock
+}
+
+proc ps_version { } {
+ set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+ set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+ return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_post_config_1_0
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_post_config_2_0
+ } else {
+ ps7_post_config_3_0
+ }
+ configparams force-mem-accesses $saved_mode
+}
+
+proc ps7_debug {} {
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_debug_1_0
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_debug_2_0
+ } else {
+ ps7_debug_3_0
+ }
+}
+proc ps7_init {} {
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_mio_init_data_1_0
+ ps7_pll_init_data_1_0
+ ps7_clock_init_data_1_0
+ ps7_ddr_init_data_1_0
+ ps7_peripherals_init_data_1_0
+ #puts "PCW Silicon Version : 1.0"
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_mio_init_data_2_0
+ ps7_pll_init_data_2_0
+ ps7_clock_init_data_2_0
+ ps7_ddr_init_data_2_0
+ ps7_peripherals_init_data_2_0
+ #puts "PCW Silicon Version : 2.0"
+ } else {
+ ps7_mio_init_data_3_0
+ ps7_pll_init_data_3_0
+ ps7_clock_init_data_3_0
+ ps7_ddr_init_data_3_0
+ ps7_peripherals_init_data_3_0
+ #puts "PCW Silicon Version : 3.0"
+ }
+}
+
+
+# For delay calculation using global timer
+
+# start timer
+ proc perf_start_clock { } {
+
+ #writing SCU_GLOBAL_TIMER_CONTROL register
+
+ mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs
+ proc perf_reset_clock { } {
+ perf_disable_clock
+ mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+ mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+ # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ variable APU_FREQ
+ return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer
+proc perf_disable_clock {} {
+ mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
+}
+
+proc perf_reset_and_start_timer {} {
+ perf_reset_clock
+ perf_start_clock
+}
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.c
new file mode 100644
index 0000000..f8bf803
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.c
@@ -0,0 +1,12080 @@
+/******************************************************************************
+* (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. .. START: AFI2 SECURE REGISTER
+ // .. .. FINISH: AFI2 SECURE REGISTER
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002801U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ {
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.h b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.h
new file mode 100644
index 0000000..564b050
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/ps7_init_gpl.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158730
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 25000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 10000000
+#define FPGA2_FREQ 10000000
+#define FPGA3_FREQ 10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/system.hdf b/pbv3_mass_test_adapter_firmware.linux/project-spec/hw-description/system.hdf
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diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/COPYING.MIT b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/COPYING.MIT
new file mode 100644
index 0000000..89de354
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/COPYING.MIT
@@ -0,0 +1,17 @@
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/README b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/README
new file mode 100644
index 0000000..5a5b9b9
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/README
@@ -0,0 +1,64 @@
+This README file contains information on the contents of the
+meta-user layer.
+
+Please see the corresponding sections below for details.
+
+
+Dependencies
+============
+
+This layer depends on:
+
+ URI: git://git.openembedded.org/bitbake
+ branch: master
+
+ URI: git://git.openembedded.org/openembedded-core
+ layers: meta
+ branch: master
+
+ URI: git://git.yoctoproject.org/xxxx
+ layers: xxxx
+ branch: master
+
+
+Patches
+=======
+
+Please submit any patches against the meta-user layer to the
+xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer:
+
+Maintainer: XXX YYYYYY <xxx.yyyyyy@zzzzz.com>
+
+
+Table of Contents
+=================
+
+ I. Adding the meta-user layer to your build
+ II. Misc
+
+
+I. Adding the meta-user layer to your build
+=================================================
+
+--- replace with specific instructions for the meta-user layer ---
+
+In order to use this layer, you need to make the build system aware of
+it.
+
+Assuming the meta-user layer exists at the top-level of your
+yocto build tree, you can add it to the build system by adding the
+location of the meta-user layer to bblayers.conf, along with any
+other layers needed. e.g.:
+
+ BBLAYERS ?= " \
+ /path/to/yocto/meta \
+ /path/to/yocto/meta-poky \
+ /path/to/yocto/meta-yocto-bsp \
+ /path/to/yocto/meta-meta-user \
+ "
+
+
+II. Misc
+========
+
+--- replace with specific information about the meta-user layer ---
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/layer.conf b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/layer.conf
new file mode 100644
index 0000000..f6b9b5a
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/layer.conf
@@ -0,0 +1,11 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
+ ${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "meta-user"
+BBFILE_PATTERN_meta-user = "^${LAYERDIR}/"
+BBFILE_PRIORITY_meta-user = "6"
+LAYERSERIES_COMPAT_meta-user = "thud"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/petalinuxbsp.conf b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/petalinuxbsp.conf
new file mode 100644
index 0000000..240c1ca
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/conf/petalinuxbsp.conf
@@ -0,0 +1,19 @@
+#User Configuration
+
+#OE_TERMINAL = "tmux"
+
+# Add EXTRA_IMAGEDEPENDS default components
+EXTRA_IMAGEDEPENDS_append_versal = " virtual/psm-firmware virtual/plm arm-trusted-firmware u-boot-zynq-scr"
+EXTRA_IMAGEDEPENDS_append_zynqmp = " virtual/fsbl virtual/pmu-firmware arm-trusted-firmware"
+EXTRA_IMAGEDEPENDS_append_zynq = " virtual/fsbl"
+EXTRA_IMAGEDEPENDS_append_microblaze = " virtual/fsboot virtual/elfrealloc"
+
+# prevent U-Boot from deploying the boot.bin
+SPL_BINARY = ""
+
+#Remove all qemu contents
+IMAGE_CLASSES_remove = "image-types-xilinx-qemu qemuboot-xilinx"
+IMAGE_FSTYPES_remove = "wic.qemu-sd"
+
+EXTRA_IMAGEDEPENDS_remove = "qemu-helper-native virtual/boot-bin"
+SIGGEN_UNLOCKED_RECIPES_append_versal = " initscripts"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile
new file mode 100644
index 0000000..9106be1
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile
@@ -0,0 +1,14 @@
+APP = gpio-demo
+
+# Add any other object files to this list below
+APP_OBJS = gpio-demo.o
+
+all: $(APP)
+
+$(APP): $(APP_OBJS)
+ $(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS)
+
+clean:
+ -rm -f $(APP) *.elf *.gdb *.o
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c
new file mode 100644
index 0000000..4e17779
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c
@@ -0,0 +1,355 @@
+/*
+*
+* gpio-demo app
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <signal.h>
+
+#define GPIO_ROOT "/sys/class/gpio"
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+
+static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE;
+
+static const unsigned long cylon[] = {
+ 0x00000080, 0x00000040, 0x00000020, 0x00000010,
+ 0x00000008, 0x00000004, 0x00000002, 0x00000001,
+ 0x00000002, 0x00000004, 0x00000008,
+ 0x00000010, 0x00000020, 0x00000040, 0x00000080,
+};
+
+static const unsigned long kit[] = {
+ 0x000000e0, 0x00000070, 0x00000038, 0x0000001c,
+ 0x0000000e, 0x00000007, 0x00000003, 0x00000001,
+ 0x00000003, 0x00000007, 0x0000000e,
+ 0x0000001c, 0x00000038, 0x00000070, 0x000000e0,
+};
+
+static int gl_gpio_base = 0;
+
+static void usage (char *argv0)
+{
+ char *basename = strrchr(argv0, '/');
+ if (!basename)
+ basename = argv0;
+
+ fprintf(stderr,
+ "Usage: %s [-g GPIO_BASE] COMMAND\n"
+ "\twhere COMMAND is one of:\n"
+ "\t\t-i\t\tInput value from GPIO and print it\n"
+ "\t\t-o\tVALUE\tOutput value to GPIO\n"
+ "\t\t-c\t\tCylon test pattern\n"
+ "\t\t-k\t\t KIT test pattern\n"
+ "\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n"
+ "\tfound at /sys/class/gpio/gpiochipN).\n"
+ "\tThe highest gpiochipN is the first gpio listed in the dts file, \n"
+ "\tand the lowest gpiochipN is the last gpio listed in the dts file.\n"
+ "\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n"
+ "\tto the LED_8bit gpio, the command should be:\n"
+ "\t\tgpio-demo -g 240 -o 1\n"
+ "\n"
+ "\tgpio-demo written by Xilinx Inc.\n"
+ "\n"
+ , basename);
+ exit(-2);
+}
+
+static int open_gpio_channel(int gpio_base)
+{
+ char gpio_nchan_file[128];
+ int gpio_nchan_fd;
+ int gpio_max;
+ int nchannel;
+ char nchannel_str[5];
+ char *cptr;
+ int c;
+ char channel_str[5];
+
+ char *gpio_export_file = "/sys/class/gpio/export";
+ int export_fd=0;
+
+ /* Check how many channels the GPIO chip has */
+ sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
+ gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
+ if (gpio_nchan_fd < 0) {
+ fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
+ return -1;
+ }
+ read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
+ close(gpio_nchan_fd);
+ nchannel=(int)strtoul(nchannel_str, &cptr, 0);
+ if (cptr == nchannel_str) {
+ fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
+ exit(1);
+ }
+
+ /* Open files for each GPIO channel */
+ export_fd=open(gpio_export_file, O_WRONLY);
+ if (export_fd < 0) {
+ fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base);
+ return -1;
+ }
+
+ gpio_max = gpio_base + nchannel;
+ for(c = gpio_base; c < gpio_max; c++) {
+ sprintf(channel_str, "%d", c);
+ write(export_fd, channel_str, (strlen(channel_str)+1));
+ }
+ close(export_fd);
+ return nchannel;
+}
+
+static int close_gpio_channel(int gpio_base)
+{
+ char gpio_nchan_file[128];
+ int gpio_nchan_fd;
+ int gpio_max;
+ int nchannel;
+ char nchannel_str[5];
+ char *cptr;
+ int c;
+ char channel_str[5];
+
+ char *gpio_unexport_file = "/sys/class/gpio/unexport";
+ int unexport_fd=0;
+
+ /* Check how many channels the GPIO chip has */
+ sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
+ gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
+ if (gpio_nchan_fd < 0) {
+ fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
+ return -1;
+ }
+ read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
+ close(gpio_nchan_fd);
+ nchannel=(int)strtoul(nchannel_str, &cptr, 0);
+ if (cptr == nchannel_str) {
+ fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
+ exit(1);
+ }
+
+ /* Close opened files for each GPIO channel */
+ unexport_fd=open(gpio_unexport_file, O_WRONLY);
+ if (unexport_fd < 0) {
+ fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base);
+ return -1;
+ }
+
+ gpio_max = gpio_base + nchannel;
+ for(c = gpio_base; c < gpio_max; c++) {
+ sprintf(channel_str, "%d", c);
+ write(unexport_fd, channel_str, (strlen(channel_str)+1));
+ }
+ close(unexport_fd);
+ return 0;
+}
+
+static int set_gpio_direction(int gpio_base, int nchannel, char *direction)
+{
+ char gpio_dir_file[128];
+ int direction_fd=0;
+ int gpio_max;
+ int c;
+
+ gpio_max = gpio_base + nchannel;
+ for(c = gpio_base; c < gpio_max; c++) {
+ sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c);
+ direction_fd=open(gpio_dir_file, O_RDWR);
+ if (direction_fd < 0) {
+ fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c);
+ return 1;
+ }
+ write(direction_fd, direction, (strlen(direction)+1));
+ close(direction_fd);
+ }
+ return 0;
+}
+
+static int set_gpio_value(int gpio_base, int nchannel, int value)
+{
+ char gpio_val_file[128];
+ int val_fd=0;
+ int gpio_max;
+ char val_str[2];
+ int c;
+
+ gpio_max = gpio_base + nchannel;
+
+ for(c = gpio_base; c < gpio_max; c++) {
+ sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
+ val_fd=open(gpio_val_file, O_RDWR);
+ if (val_fd < 0) {
+ fprintf(stderr, "Cannot open the value file of GPIO %d\n", c);
+ return -1;
+ }
+ sprintf(val_str,"%d", (value & 1));
+ write(val_fd, val_str, sizeof(val_str));
+ close(val_fd);
+ value >>= 1;
+ }
+ return 0;
+}
+
+static int get_gpio_value(int gpio_base, int nchannel)
+{
+ char gpio_val_file[128];
+ int val_fd=0;
+ int gpio_max;
+ char val_str[2];
+ char *cptr;
+ int value = 0;
+ int c;
+
+ gpio_max = gpio_base + nchannel;
+
+ for(c = gpio_max-1; c >= gpio_base; c--) {
+ sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
+ val_fd=open(gpio_val_file, O_RDWR);
+ if (val_fd < 0) {
+ fprintf(stderr, "Cannot open GPIO to export %d\n", c);
+ return -1;
+ }
+ read(val_fd, val_str, sizeof(val_str));
+ value <<= 1;
+ value += (int)strtoul(val_str, &cptr, 0);
+ if (cptr == optarg) {
+ fprintf(stderr, "Failed to change %s into integer", val_str);
+ }
+ close(val_fd);
+ }
+ return value;
+}
+
+void signal_handler(int sig)
+{
+ switch (sig) {
+ case SIGTERM:
+ case SIGHUP:
+ case SIGQUIT:
+ case SIGINT:
+ close_gpio_channel(gl_gpio_base);
+ exit(0) ;
+ default:
+ break;
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ extern char *optarg;
+ char *cptr;
+ int gpio_value = 0;
+ int nchannel = 0;
+
+ int c;
+ int i;
+
+ opterr = 0;
+
+ while ((c = getopt(argc, argv, "g:io:ck")) != -1) {
+ switch (c) {
+ case 'g':
+ gl_gpio_base = (int)strtoul(optarg, &cptr, 0);
+ if (cptr == optarg)
+ usage(argv[0]);
+ break;
+ case 'i':
+ gpio_opt = IN;
+ break;
+ case 'o':
+ gpio_opt = OUT;
+ gpio_value = (int)strtoul(optarg, &cptr, 0);
+ if (cptr == optarg)
+ usage(argv[0]);
+ break;
+ case 'c':
+ gpio_opt = CYLON;
+ break;
+ case 'k':
+ gpio_opt = KIT;
+ break;
+ case '?':
+ usage(argv[0]);
+ default:
+ usage(argv[0]);
+
+ }
+ }
+
+ if (gl_gpio_base == 0) {
+ usage(argv[0]);
+ }
+
+ nchannel = open_gpio_channel(gl_gpio_base);
+ signal(SIGTERM, signal_handler); /* catch kill signal */
+ signal(SIGHUP, signal_handler); /* catch hang up signal */
+ signal(SIGQUIT, signal_handler); /* catch quit signal */
+ signal(SIGINT, signal_handler); /* catch a CTRL-c signal */
+ switch (gpio_opt) {
+ case IN:
+ set_gpio_direction(gl_gpio_base, nchannel, "in");
+ gpio_value=get_gpio_value(gl_gpio_base, nchannel);
+ fprintf(stdout,"0x%08X\n", gpio_value);
+ break;
+ case OUT:
+ set_gpio_direction(gl_gpio_base, nchannel, "out");
+ set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+ break;
+ case CYLON:
+#define CYLON_DELAY_USECS (10000)
+ set_gpio_direction(gl_gpio_base, nchannel, "out");
+ for (;;) {
+ for(i=0; i < ARRAY_SIZE(cylon); i++) {
+ gpio_value=(int)cylon[i];
+ set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+ }
+ usleep(CYLON_DELAY_USECS);
+ }
+ case KIT:
+#define KIT_DELAY_USECS (10000)
+ set_gpio_direction(gl_gpio_base, nchannel, "out");
+ for (;;) {
+ for (i=0; i<ARRAY_SIZE(kit); i++) {
+ gpio_value=(int)kit[i];
+ set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+ }
+ usleep(KIT_DELAY_USECS);
+ }
+ default:
+ break;
+ }
+ close_gpio_channel(gl_gpio_base);
+ return 0;
+}
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb
new file mode 100644
index 0000000..cb5b431
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb
@@ -0,0 +1,23 @@
+#
+# This is the GPIO-DEMO apllication recipe
+#
+#
+
+SUMMARY = "gpio-demo application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+SRC_URI = "file://gpio-demo.c \
+ file://Makefile \
+ "
+S = "${WORKDIR}"
+CFLAGS_prepend = "-I ${S}/include"
+do_compile() {
+ oe_runmake
+}
+do_install() {
+ install -d ${D}${bindir}
+ install -m 0755 ${S}/gpio-demo ${D}${bindir}
+
+}
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile
new file mode 100644
index 0000000..29fb5cd
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile
@@ -0,0 +1,19 @@
+PEEK = peek
+POKE = poke
+
+# Add any other object files to this list below
+PEEK_OBJS = peek.o
+POKE_OBJS = poke.o
+
+all: $(PEEK) $(POKE)
+
+$(POKE): $(POKE_OBJS)
+ $(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS)
+
+$(PEEK): $(PEEK_OBJS)
+ $(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS)
+
+clean:
+ -rm -f $(POKE) $(PEEK) *.elf *.gdb *.o
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c
new file mode 100644
index 0000000..0891b79
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c
@@ -0,0 +1,77 @@
+/*
+* peek utility - for those who remember the good old days!
+*
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+void usage(char *prog)
+{
+ printf("usage: %s ADDR\n",prog);
+ printf("\n");
+ printf("ADDR may be specified as hex values\n");
+}
+
+
+int main(int argc, char *argv[])
+{
+ int fd;
+ void *ptr;
+ unsigned addr, page_addr, page_offset;
+ unsigned page_size=sysconf(_SC_PAGESIZE);
+
+ if(argc!=2) {
+ usage(argv[0]);
+ exit(-1);
+ }
+
+ fd=open("/dev/mem",O_RDONLY);
+ if(fd<1) {
+ perror(argv[0]);
+ exit(-1);
+ }
+
+ addr=strtoul(argv[1],NULL,0);
+ page_addr=(addr & ~(page_size-1));
+ page_offset=addr-page_addr;
+
+ ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1)));
+ if((int)ptr==-1) {
+ perror(argv[0]);
+ exit(-1);
+ }
+
+ printf("0x%08x\n",*((unsigned *)(ptr+page_offset)));
+ return 0;
+}
+
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c
new file mode 100644
index 0000000..bc670c3
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c
@@ -0,0 +1,77 @@
+/*
+* poke utility - for those who remember the good old days!
+*
+
+* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+void usage(char *prog)
+{
+ printf("usage: %s ADDR VAL\n",prog);
+ printf("\n");
+ printf("ADDR and VAL may be specified as hex values\n");
+}
+
+int main(int argc, char *argv[])
+{
+ int fd;
+ void *ptr;
+ unsigned val;
+ unsigned addr, page_addr, page_offset;
+ unsigned page_size=sysconf(_SC_PAGESIZE);
+
+ fd=open("/dev/mem",O_RDWR);
+ if(fd<1) {
+ perror(argv[0]);
+ exit(-1);
+ }
+
+ if(argc!=3) {
+ usage(argv[0]);
+ exit(-1);
+ }
+
+ addr=strtoul(argv[1],NULL,0);
+ val=strtoul(argv[2],NULL,0);
+
+ page_addr=(addr & ~(page_size-1));
+ page_offset=addr-page_addr;
+
+ ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1)));
+ if((int)ptr==-1) {
+ perror(argv[0]);
+ exit(-1);
+ }
+
+ *((unsigned *)(ptr+page_offset))=val;
+ return 0;
+}
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb
new file mode 100644
index 0000000..bace395
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb
@@ -0,0 +1,25 @@
+#
+# This is the peekpoke apllication recipe
+#
+#
+
+SUMMARY = "peekpoke application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+SRC_URI = "file://peek.c \
+ file://poke.c \
+ file://Makefile \
+ "
+S = "${WORKDIR}"
+CFLAGS_prepend = "-I ${S}/include"
+do_compile() {
+ oe_runmake
+}
+do_install() {
+ install -d ${D}${bindir}
+ install -m 0755 ${S}/peek ${D}${bindir}
+ install -m 0755 ${S}/poke ${D}${bindir}
+
+}
+
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend
new file mode 100644
index 0000000..f25b1f1
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend
@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://system-user.dtsi"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
new file mode 100644
index 0000000..d5e6796
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
@@ -0,0 +1,7 @@
+/include/ "system-conf.dtsi"
+/ {
+};
+
+&endeavour_axi_contro_5 {
+ compatible = "generic-uio";
+};
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h
new file mode 100644
index 0000000..02dd857
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h
@@ -0,0 +1,36 @@
+
+#include <configs/platform-auto.h>
+#define CONFIG_SYS_BOOTM_LEN 0xF000000
+#define DFU_ALT_INFO_RAM \
+ "dfu_ram_info=" \
+ "setenv dfu_alt_info " \
+ "image.ub ram $netstart 0x1e00000\0" \
+ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO_MMC \
+ "dfu_mmc_info=" \
+ "set dfu_alt_info " \
+ "${kernel_image} fat 0 1\\\\;" \
+ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
+ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
+
+
+/*Required for uartless designs */
+#ifndef CONFIG_BAUDRATE
+#define CONFIG_BAUDRATE 115200
+#ifdef CONFIG_DEBUG_UART
+#undef CONFIG_DEBUG_UART
+#endif
+#endif
+
+/*Dependencies for ENV to be stored in EEPROM. Ensure environment fits in eeprom size*/
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
+#define CONFIG_SYS_I2C_MUX_ADDR 0x74
+#define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4
+#endif
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend
new file mode 100644
index 0000000..f6c6bd6
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend
@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://platform-top.h"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend
new file mode 100644
index 0000000..72e0dad
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend
@@ -0,0 +1,4 @@
+#Note: Mention Each package in individual line
+# cascaded representation with line breaks are not valid in this file.
+IMAGE_INSTALL_append = " peekpoke"
+IMAGE_INSTALL_append = " gpio-demo"
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-06-14-00.cfg b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-06-14-00.cfg
new file mode 100644
index 0000000..c2bfd9c
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-06-14-00.cfg
@@ -0,0 +1 @@
+CONFIG_I2C_XILINX=m
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-16-08-00.cfg b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-16-08-00.cfg
new file mode 100644
index 0000000..ee47550
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2019-09-21-16-08-00.cfg
@@ -0,0 +1,22 @@
+CONFIG_DNS_RESOLVER=y
+# CONFIG_ECRYPT_FS is not set
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_KEYS=y
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_OID_REGISTRY=y
diff --git a/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
new file mode 100644
index 0000000..4167c63
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.linux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
@@ -0,0 +1,6 @@
+SRC_URI += "file://user_2019-09-21-06-14-00.cfg \
+ file://user_2019-09-21-16-08-00.cfg \
+ "
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/constrs_1/imports/Downloads/Z7010 or Z7020 MicroZed with MBCC-FMC-PCB-B_v2.xdc b/pbv3_mass_test_adapter_firmware.srcs/constrs_1/imports/Downloads/Z7010 or Z7020 MicroZed with MBCC-FMC-PCB-B_v2.xdc
index ed3f421..b957e5d 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/constrs_1/imports/Downloads/Z7010 or Z7020 MicroZed with MBCC-FMC-PCB-B_v2.xdc
+++ b/pbv3_mass_test_adapter_firmware.srcs/constrs_1/imports/Downloads/Z7010 or Z7020 MicroZed with MBCC-FMC-PCB-B_v2.xdc
@@ -1,250 +1,250 @@
-# ----------------------------------------------------------------------------
-# _____
-# / \
-# /____ \____
-# / \===\ \==/
-# /___\===\___\/ AVNET ELECTRONICS MARKETING
-# \======/ www.em.avnet.com/drc
-# \====/
-# ----------------------------------------------------------------------------
-#
-# Created With Avnet Constraints Generator V0.8.0
-# Date: Tuesday, September 02, 2014
-# Time: 10:33:25 PM
-#
-# This design is the property of Avnet. Publication of this
-# design is not authorized without written consent from Avnet.
-#
-# Please direct any questions to:
-# MicroZed.org Community Forums
-# http://www.microzed.org
-#
-# Disclaimer:
-# Avnet, Inc. makes no warranty for the use of this code or design.
-# This code is provided "As Is". Avnet, Inc assumes no responsibility for
-# any errors, which may appear in this code, nor does it make a commitment
-# to update the information contained herein. Avnet, Inc specifically
-# disclaims any implied warranties of fitness for a particular purpose.
-# Copyright(c) 2014 Avnet, Inc.
-# All rights reserved.
-#
-# ----------------------------------------------------------------------------
-#
-# Notes:
-#
-# 20 April 2015
-# IO standards based upon Bank 34 and Bank 35 (and Bank 13) Vcco supply
-# options of 1.8V, 2.5V, or 3.3V are possible based upon the Vadj
-# jumper (J18) settings. By default, Vadj is expected to be set to
-# 1.8V but if a different voltage is used for a particular design, then
-# the corresponding IO standard within this UCF should also be updated
-# to reflect the actual Vadj jumper selection.
-#
-# Net names are not allowed to contain hyphen characters '-' since this
-# is not a legal VHDL87 or Verilog character within an identifier.
-# HDL net names are adjusted to contain no hyphen characters '-' but
-# rather use underscore '_' characters. Comment net name with the hyphen
-# characters will remain in place since these are intended to match the
-# schematic net names in order to better enable schematic search.
-#
-# The string provided in the comment field provides the Zynq device pin
-# mapping through the expansion connector to the carrier card net name
-# according to the following format:
-#
-# "<Zynq Pin>.<SOM Net>.<Connector Ref>.<Connector Pin>.<Carrier Net>"
-#
-# ----------------------------------------------------------------------------
-
-
-# ----------------------------------------------------------------------------
-# User LEDs - Bank 34
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN R19 [get_ports {LED0}]; # "R19.JX1_SE_0.JX1.9.LED0"
-set_property PACKAGE_PIN V13 [get_ports {LED1}]; # "V13.JX1_LVDS_2_N.JX1.19.LED1"
-
-
-# ----------------------------------------------------------------------------
-# One wire Security EEPROM - Bank 34
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN T19 [get_ports {EEPROM}]; # "T19.JX1_SE_1.JX1.10.EEPROM"
-
-
-# ----------------------------------------------------------------------------
-# JB Pmod - Bank 34
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN T11 [get_ports {JB0_1_P}]; # "T11.JX1_LVDS_0_P.JX1.11.JB0-1_P" - JB - Pin 1
-set_property PACKAGE_PIN T10 [get_ports {JB0_1_N}]; # "T10.JX1_LVDS_0_N.JX1.13.JB0-1_N" - JB - Pin 2
-set_property PACKAGE_PIN T12 [get_ports {JB2_3_P}]; # "T12.JX1_LVDS_1_P.JX1.12.JB2-3_P" - JB - Pin 3
-set_property PACKAGE_PIN U12 [get_ports {JB2_3_N}]; # "U12.JX1_LVDS_1_N.JX1.14.JB2-3_N" - JB - Pin 4
-set_property PACKAGE_PIN V12 [get_ports {JB4_5_P}]; # "V12.JX1_LVDS_3_P.JX1.18.JB4-5_P" - JB - Pin 7
-set_property PACKAGE_PIN W13 [get_ports {JB4_5_N}]; # "W13.JX1_LVDS_3_N.JX1.20.JB4-5_N" - JB - Pin 8
-set_property PACKAGE_PIN T14 [get_ports {JB6_7_P}]; # "T14.JX1_LVDS_4_P.JX1.23.JB6-7_P" - JB - Pin 9
-set_property PACKAGE_PIN T15 [get_ports {JB6_7_N}]; # "T15.JX1_LVDS_4_N.JX1.25.JB6-7_N" - JB - Pin 10
-
-
-# ----------------------------------------------------------------------------
-# FMC Expansion Connector - Bank 34
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN U19 [get_ports {CLK0_M2C_N}]; # "U19.JX1_LVDS_11_N.JX1.44.CLK0_M2C_N"
-set_property PACKAGE_PIN U18 [get_ports {CLK0_M2C_P}]; # "U18.JX1_LVDS_11_P.JX1.42.CLK0_M2C_P"
-set_property PACKAGE_PIN P16 [get_ports {FMC_SCL}]; # "P16.JX1_LVDS_23_N.JX1.84.FMC_SCL"
-set_property PACKAGE_PIN P15 [get_ports {FMC_SDA}]; # "P15.JX1_LVDS_23_P.JX1.82.FMC_SDA"
-set_property PACKAGE_PIN P19 [get_ports {LA00_CC_N}]; # "P19.JX1_LVDS_12_N.JX1.49.LA00_CC_N"
-set_property PACKAGE_PIN N18 [get_ports {LA00_CC_P}]; # "N18.JX1_LVDS_12_P.JX1.47.LA00_CC_P"
-set_property PACKAGE_PIN P20 [get_ports {LA01_CC_N}]; # "P20.JX1_LVDS_13_N.JX1.50.LA01_CC_N"
-set_property PACKAGE_PIN N20 [get_ports {LA01_CC_P}]; # "N20.JX1_LVDS_13_P.JX1.48.LA01_CC_P"
-set_property PACKAGE_PIN R14 [get_ports {LA02_N}]; # "R14.JX1_LVDS_5_N.JX1.26.LA02_N"
-set_property PACKAGE_PIN P14 [get_ports {LA02_P}]; # "P14.JX1_LVDS_5_P.JX1.24.LA02_P"
-set_property PACKAGE_PIN Y17 [get_ports {LA03_N}]; # "Y17.JX1_LVDS_6_N.JX1.31.LA03_N"
-set_property PACKAGE_PIN Y16 [get_ports {LA03_P}]; # "Y16.JX1_LVDS_6_P.JX1.29.LA03_P"
-set_property PACKAGE_PIN Y14 [get_ports {LA04_N}]; # "Y14.JX1_LVDS_7_N.JX1.32.LA04_N"
-set_property PACKAGE_PIN W14 [get_ports {LA04_P}]; # "W14.JX1_LVDS_7_P.JX1.30.LA04_P"
-set_property PACKAGE_PIN U17 [get_ports {LA05_N}]; # "U17.JX1_LVDS_8_N.JX1.37.LA05_N"
-set_property PACKAGE_PIN T16 [get_ports {LA05_P}]; # "T16.JX1_LVDS_8_P.JX1.35.LA05_P"
-set_property PACKAGE_PIN W15 [get_ports {LA06_N}]; # "W15.JX1_LVDS_9_N.JX1.38.LA06_N"
-set_property PACKAGE_PIN V15 [get_ports {LA06_P}]; # "V15.JX1_LVDS_9_P.JX1.36.LA06_P"
-set_property PACKAGE_PIN U15 [get_ports {LA07_N}]; # "U15.JX1_LVDS_10_N.JX1.43.LA07_N"
-set_property PACKAGE_PIN U14 [get_ports {LA07_P}]; # "U14.JX1_LVDS_10_P.JX1.41.LA07_P"
-set_property PACKAGE_PIN U20 [get_ports {LA08_N}]; # "U20.JX1_LVDS_14_N.JX1.55.LA08_N"
-set_property PACKAGE_PIN T20 [get_ports {LA08_P}]; # "T20.JX1_LVDS_14_P.JX1.53.LA08_P"
-set_property PACKAGE_PIN W20 [get_ports {LA09_N}]; # "W20.JX1_LVDS_15_N.JX1.56.LA09_N"
-set_property PACKAGE_PIN V20 [get_ports {LA09_P}]; # "V20.JX1_LVDS_15_P.JX1.54.LA09_P"
-set_property PACKAGE_PIN Y19 [get_ports {LA10_N}]; # "Y19.JX1_LVDS_16_N.JX1.63.LA10_N"
-set_property PACKAGE_PIN Y18 [get_ports {LA10_P}]; # "Y18.JX1_LVDS_16_P.JX1.61.LA10_P"
-set_property PACKAGE_PIN W16 [get_ports {LA11_N}]; # "W16.JX1_LVDS_17_N.JX1.64.LA11_N"
-set_property PACKAGE_PIN V16 [get_ports {LA11_P}]; # "V16.JX1_LVDS_17_P.JX1.62.LA11_P"
-set_property PACKAGE_PIN R17 [get_ports {LA12_N}]; # "R17.JX1_LVDS_18_N.JX1.69.LA12_N"
-set_property PACKAGE_PIN R16 [get_ports {LA12_P}]; # "R16.JX1_LVDS_18_P.JX1.67.LA12_P"
-set_property PACKAGE_PIN R18 [get_ports {LA13_N}]; # "R18.JX1_LVDS_19_N.JX1.70.LA13_N"
-set_property PACKAGE_PIN T17 [get_ports {LA13_P}]; # "T17.JX1_LVDS_19_P.JX1.68.LA13_P"
-set_property PACKAGE_PIN V18 [get_ports {LA14_N}]; # "V18.JX1_LVDS_20_N.JX1.75.LA14_N"
-set_property PACKAGE_PIN V17 [get_ports {LA14_P}]; # "V17.JX1_LVDS_20_P.JX1.73.LA14_P"
-set_property PACKAGE_PIN W19 [get_ports {LA15_N}]; # "W19.JX1_LVDS_21_N.JX1.76.LA15_N"
-set_property PACKAGE_PIN W18 [get_ports {LA15_P}]; # "W18.JX1_LVDS_21_P.JX1.74.LA15_P"
-set_property PACKAGE_PIN P18 [get_ports {LA16_N}]; # "P18.JX1_LVDS_22_N.JX1.83.LA16_N"
-set_property PACKAGE_PIN N17 [get_ports {LA16_P}]; # "N17.JX1_LVDS_22_P.JX1.81.LA16_P"
-
-
-# ----------------------------------------------------------------------------
-# FMC Expansion Connector - Bank 35
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN K18 [get_ports {CLK1_M2C_N}]; # "K18.JX2_LVDS_11_N.JX2.50.CLK1_M2C_N"
-set_property PACKAGE_PIN K17 [get_ports {CLK1_M2C_P}]; # "K17.JX2_LVDS_11_P.JX2.48.CLK1_M2C_P"
-set_property PACKAGE_PIN M14 [get_ports {FMC_PRSNT_L}]; # "M14.JX2_LVDS_22_P.JX2.87.FMC_PRSNT_L"
-set_property PACKAGE_PIN H17 [get_ports {LA17_CC_N}]; # "H17.JX2_LVDS_12_N.JX2.55.LA17_CC_N"
-set_property PACKAGE_PIN H16 [get_ports {LA17_CC_P}]; # "H16.JX2_LVDS_12_P.JX2.53.LA17_CC_P"
-set_property PACKAGE_PIN H18 [get_ports {LA18_CC_N}]; # "H18.JX2_LVDS_13_N.JX2.56.LA18_CC_N"
-set_property PACKAGE_PIN J18 [get_ports {LA18_CC_P}]; # "J18.JX2_LVDS_13_P.JX2.54.LA18_CC_P"
-set_property PACKAGE_PIN D18 [get_ports {LA19_N}]; # "D18.JX2_LVDS_2_N.JX2.25.LA19_N"
-set_property PACKAGE_PIN E17 [get_ports {LA19_P}]; # "E17.JX2_LVDS_2_P.JX2.23.LA19_P"
-set_property PACKAGE_PIN D20 [get_ports {iic_rtl_sda_io}]; # "D20.JX2_LVDS_3_N.JX2.26.LA20_N"
-set_property PACKAGE_PIN D19 [get_ports {iic_rtl_scl_io}]; # "D19.JX2_LVDS_3_P.JX2.24.LA20_P"
-set_property PACKAGE_PIN E19 [get_ports {LA21_N}]; # "E19.JX2_LVDS_4_N.JX2.31.LA21_N"
-set_property PACKAGE_PIN E18 [get_ports {LA21_P}]; # "E18.JX2_LVDS_4_P.JX2.29.LA21_P"
-set_property PACKAGE_PIN F17 [get_ports {LA22_N}]; # "F17.JX2_LVDS_5_N.JX2.32.LA22_N"
-set_property PACKAGE_PIN F16 [get_ports {LA22_P}]; # "F16.JX2_LVDS_5_P.JX2.30.LA22_P"
-set_property PACKAGE_PIN L20 [get_ports {LA23_N}]; # "L20.JX2_LVDS_6_N.JX2.37.LA23_N"
-set_property PACKAGE_PIN L19 [get_ports {LA23_P}]; # "L19.JX2_LVDS_6_P.JX2.35.LA23_P"
-set_property PACKAGE_PIN M20 [get_ports {LA24_N}]; # "M20.JX2_LVDS_7_N.JX2.38.LA24_N"
-set_property PACKAGE_PIN M19 [get_ports {LA24_P}]; # "M19.JX2_LVDS_7_P.JX2.36.LA24_P"
-set_property PACKAGE_PIN M18 [get_ports {LA25_N}]; # "M18.JX2_LVDS_8_N.JX2.43.LA25_N"
-set_property PACKAGE_PIN M17 [get_ports {LA25_P}]; # "M17.JX2_LVDS_8_P.JX2.41.LA25_P"
-set_property PACKAGE_PIN J19 [get_ports {LA26_N}]; # "J19.JX2_LVDS_9_N.JX2.44.LA26_N"
-set_property PACKAGE_PIN K19 [get_ports {LA26_P}]; # "K19.JX2_LVDS_9_P.JX2.42.LA26_P"
-set_property PACKAGE_PIN G18 [get_ports {LA27_N}]; # "G18.JX2_LVDS_14_N.JX2.63.LA27_N"
-set_property PACKAGE_PIN G17 [get_ports {LA27_P}]; # "G17.JX2_LVDS_14_P.JX2.61.LA27_P"
-set_property PACKAGE_PIN F20 [get_ports {LA28_N}]; # "F20.JX2_LVDS_15_N.JX2.64.LA28_N"
-set_property PACKAGE_PIN F19 [get_ports {LA28_P}]; # "F19.JX2_LVDS_15_P.JX2.62.LA28_P"
-set_property PACKAGE_PIN H20 [get_ports {LA29_N}]; # "H20.JX2_LVDS_17_N.JX2.70.LA29_N"
-set_property PACKAGE_PIN J20 [get_ports {LA29_P}]; # "J20.JX2_LVDS_17_P.JX2.68.LA29_P"
-set_property PACKAGE_PIN J14 [get_ports {LA30_N}]; # "J14.JX2_LVDS_18_N.JX2.75.LA30_N"
-set_property PACKAGE_PIN K14 [get_ports {LA30_P}]; # "K14.JX2_LVDS_18_P.JX2.73.LA30_P"
-set_property PACKAGE_PIN G15 [get_ports {LA31_N}]; # "G15.JX2_LVDS_19_N.JX2.76.LA31_N"
-set_property PACKAGE_PIN H15 [get_ports {LA31_P}]; # "H15.JX2_LVDS_19_P.JX2.74.LA31_P"
-set_property PACKAGE_PIN N16 [get_ports {LA32_N}]; # "N16.JX2_LVDS_20_N.JX2.83.LA32_N"
-set_property PACKAGE_PIN N15 [get_ports {LA32_P}]; # "N15.JX2_LVDS_20_P.JX2.81.LA32_P"
-set_property PACKAGE_PIN L15 [get_ports {LA33_N}]; # "L15.JX2_LVDS_21_N.JX2.84.LA33_N"
-set_property PACKAGE_PIN L14 [get_ports {LA33_P}]; # "L14.JX2_LVDS_21_P.JX2.82.LA33_P"
-
-
-# ----------------------------------------------------------------------------
-# User LEDs - Bank 35
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN K16 [get_ports {LED2}]; # "K16.JX2_LVDS_23_P.JX2.88.LED2"
-set_property PACKAGE_PIN M15 [get_ports {LED3}]; # "M15.JX2_LVDS_22_N.JX2.89.LED3"
-
-
-# ----------------------------------------------------------------------------
-# UNI/O MAC ID EEPROM - Bank 35
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN J16 [get_ports {MAC_ID}]; # "J16.JX2_LVDS_23_N.JX2.90.MAC_ID"
-
-
-# ----------------------------------------------------------------------------
-# User Push Buttons - Bank 35
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN G19 [get_ports {PB0}]; # "G19.JX2_LVDS_16_P.JX2.67.PB0"
-set_property PACKAGE_PIN G20 [get_ports {PB1}]; # "G20.JX2_LVDS_16_N.JX2.69.PB1"
-
-
-# ----------------------------------------------------------------------------
-# JA Pmod - Bank 35
-# ----------------------------------------------------------------------------
-set_property PACKAGE_PIN L16 [get_ports {JA0_1_P}]; # "L16.JX2_LVDS_10_P.JX2.47.JA0-1_P" - JA - Pin 1
-set_property PACKAGE_PIN L17 [get_ports {JA0_1_N}]; # "L17.JX2_LVDS_10_N.JX2.49.JA0-1_N" - JA - Pin 2
-set_property PACKAGE_PIN G14 [get_ports {JA2}]; # "G14.JX2_SE_0.JX2.13.JA2" - JA - Pin 3
-set_property PACKAGE_PIN J15 [get_ports {JA3}]; # "J15.JX2_SE_1.JX2.14.JA3" - JA - Pin 4
-set_property PACKAGE_PIN B19 [get_ports {JA4_5_P}]; # "B19.JX2_LVDS_1_P.JX2.18.JA4-5_P" - JA - Pin 7
-set_property PACKAGE_PIN A20 [get_ports {JA4_5_N}]; # "A20.JX2_LVDS_1_N.JX2.20.JA4-5_N" - JA - Pin 8
-set_property PACKAGE_PIN C20 [get_ports {JA6_7_P}]; # "C20.JX2_LVDS_0_P.JX2.17.JA6-7_P" - JA - Pin 9
-set_property PACKAGE_PIN B20 [get_ports {JA6_7_N}]; # "B20.JX2_LVDS_0_N.JX2.19.JA6-7_N" - JA - Pin 10
-
-
-# ----------------------------------------------------------------------------
-# JY Pmod - Bank 13 (Available on Z7020 device only)
-# ----------------------------------------------------------------------------
-# set_property PACKAGE_PIN U7 [get_ports {JY0_1_P}]; # "U7.BANK13_LVDS_0_P.JX1.87.JY0-1_P" - JY - Pin 1
-# set_property PACKAGE_PIN V7 [get_ports {JY0_1_N}]; # "V7.BANK13_LVDS_0_N.JX1.89.JY0-1_N" - JY - Pin 2
-# set_property PACKAGE_PIN T9 [get_ports {JY2_3_P}]; # "T9.BANK13_LVDS_1_P.JX1.88.JY2-3_P" - JY - Pin 3
-# set_property PACKAGE_PIN U10 [get_ports {JY2_3_N}]; # "U10.BANK13_LVDS_1_N.JX1.90.JY2-3_N" - JY - Pin 4
-# set_property PACKAGE_PIN V8 [get_ports {JY4_5_P}]; # "V8.BANK13_LVDS_2_P.JX1.91.JY4-5_P" - JY - Pin 7
-# set_property PACKAGE_PIN W8 [get_ports {JY4_5_N}]; # "W8.BANK13_LVDS_2_N.JX1.93.JY4-5_N" - JY - Pin 8
-# set_property PACKAGE_PIN T5 [get_ports {JY6_7_P}]; # "T5.BANK13_LVDS_3_P.JX1.92.JY6-7_P" - JY - Pin 9
-# set_property PACKAGE_PIN U5 [get_ports {JY6_7_N}]; # "U5.BANK13_LVDS_3_N.JX1.94.JY6-7_N" - JY - Pin 10
-
-
-# ----------------------------------------------------------------------------
-# JZ Pmod - Bank 13 (Available on Z7020 device only)
-# ----------------------------------------------------------------------------
-# set_property PACKAGE_PIN Y12 [get_ports {JZ0_1_P}]; # "Y12.BANK13_LVDS_4_P.JX2.93.JZ0-1_P" - JZ - Pin 1
-# set_property PACKAGE_PIN Y13 [get_ports {JZ0_1_N}]; # "Y13.BANK13_LVDS_4_N.JX2.95.JZ0-1_N" - JZ - Pin 2
-# set_property PACKAGE_PIN V11 [get_ports {JZ2_3_P}]; # "V11.BANK13_LVDS_5_P.JX2.94.JZ2-3_P" - JZ - Pin 3
-# set_property PACKAGE_PIN V10 [get_ports {JZ2_3_N}]; # "V10.BANK13_LVDS_5_N.JX2.96.JZ2-3_N" - JZ - Pin 4
-# set_property PACKAGE_PIN V5 [get_ports {JZ5}]; # "V5.BANK13_SE_0.JX2.100.JZ5" - JZ - Pin 8
-# set_property PACKAGE_PIN V6 [get_ports {JZ6_7_P}]; # "V6.BANK13_LVDS_6_P.JX2.97.JZ6-7_P" - JZ - Pin 9
-# set_property PACKAGE_PIN W6 [get_ports {JZ6_7_N}]; # "W6.BANK13_LVDS_6_N.JX2.99.JZ6-7_N" - JZ - Pin 10
-
-
-# ----------------------------------------------------------------------------
-# IOSTANDARD Constraints
-#
-# Note that these IOSTANDARD constraints are applied to all IOs currently
-# assigned within an I/O bank. If these IOSTANDARD constraints are
-# evaluated prior to other PACKAGE_PIN constraints being applied, then
-# the IOSTANDARD specified will likely not be applied properly to those
-# pins. Therefore, bank wide IOSTANDARD constraints should be placed
-# within the XDC file in a location that is evaluated AFTER all
-# PACKAGE_PIN constraints within the target bank have been evaluated.
-#
-# Un-comment one or more of the following IOSTANDARD constraints according to
-# the bank pin assignments that are required within a design.
-# ----------------------------------------------------------------------------
-
-# Set the bank voltage for IO Bank 34 to 3.3V by default.
-# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
-
-# Set the bank voltage for IO Bank 35 to 3.3V by default.
-# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
-
-# Set the bank voltage for IO Bank 13 to 3.3V by default. (I/O bank available on Z7020 device only)
-# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
+# ----------------------------------------------------------------------------
+# _____
+# / # /____ \____
+# / \===\ \==/
+# /___\===\___\/ AVNET ELECTRONICS MARKETING
+# \======/ www.em.avnet.com/drc
+# \====/
+# ----------------------------------------------------------------------------
+#
+# Created With Avnet Constraints Generator V0.8.0
+# Date: Tuesday, September 02, 2014
+# Time: 10:33:25 PM
+#
+# This design is the property of Avnet. Publication of this
+# design is not authorized without written consent from Avnet.
+#
+# Please direct any questions to:
+# MicroZed.org Community Forums
+# http://www.microzed.org
+#
+# Disclaimer:
+# Avnet, Inc. makes no warranty for the use of this code or design.
+# This code is provided "As Is". Avnet, Inc assumes no responsibility for
+# any errors, which may appear in this code, nor does it make a commitment
+# to update the information contained herein. Avnet, Inc specifically
+# disclaims any implied warranties of fitness for a particular purpose.
+# Copyright(c) 2014 Avnet, Inc.
+# All rights reserved.
+#
+# ----------------------------------------------------------------------------
+#
+# Notes:
+#
+# 20 April 2015
+# IO standards based upon Bank 34 and Bank 35 (and Bank 13) Vcco supply
+# options of 1.8V, 2.5V, or 3.3V are possible based upon the Vadj
+# jumper (J18) settings. By default, Vadj is expected to be set to
+# 1.8V but if a different voltage is used for a particular design, then
+# the corresponding IO standard within this UCF should also be updated
+# to reflect the actual Vadj jumper selection.
+#
+# Net names are not allowed to contain hyphen characters '-' since this
+# is not a legal VHDL87 or Verilog character within an identifier.
+# HDL net names are adjusted to contain no hyphen characters '-' but
+# rather use underscore '_' characters. Comment net name with the hyphen
+# characters will remain in place since these are intended to match the
+# schematic net names in order to better enable schematic search.
+#
+# The string provided in the comment field provides the Zynq device pin
+# mapping through the expansion connector to the carrier card net name
+# according to the following format:
+#
+# "<Zynq Pin>.<SOM Net>.<Connector Ref>.<Connector Pin>.<Carrier Net>"
+#
+# ----------------------------------------------------------------------------
+
+
+# ----------------------------------------------------------------------------
+# User LEDs - Bank 34
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN R19 [get_ports {LED0}]; # "R19.JX1_SE_0.JX1.9.LED0"
+# set_property PACKAGE_PIN V13 [get_ports {LED1}]; # "V13.JX1_LVDS_2_N.JX1.19.LED1"
+
+
+# ----------------------------------------------------------------------------
+# One wire Security EEPROM - Bank 34
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN T19 [get_ports {EEPROM}]; # "T19.JX1_SE_1.JX1.10.EEPROM"
+
+
+# ----------------------------------------------------------------------------
+# JB Pmod - Bank 34
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN T11 [get_ports {JB0_1_P}]; # "T11.JX1_LVDS_0_P.JX1.11.JB0-1_P" - JB - Pin 1
+# set_property PACKAGE_PIN T10 [get_ports {JB0_1_N}]; # "T10.JX1_LVDS_0_N.JX1.13.JB0-1_N" - JB - Pin 2
+# set_property PACKAGE_PIN T12 [get_ports {JB2_3_P}]; # "T12.JX1_LVDS_1_P.JX1.12.JB2-3_P" - JB - Pin 3
+# set_property PACKAGE_PIN U12 [get_ports {JB2_3_N}]; # "U12.JX1_LVDS_1_N.JX1.14.JB2-3_N" - JB - Pin 4
+# set_property PACKAGE_PIN V12 [get_ports {JB4_5_P}]; # "V12.JX1_LVDS_3_P.JX1.18.JB4-5_P" - JB - Pin 7
+# set_property PACKAGE_PIN W13 [get_ports {JB4_5_N}]; # "W13.JX1_LVDS_3_N.JX1.20.JB4-5_N" - JB - Pin 8
+# set_property PACKAGE_PIN T14 [get_ports {JB6_7_P}]; # "T14.JX1_LVDS_4_P.JX1.23.JB6-7_P" - JB - Pin 9
+# set_property PACKAGE_PIN T15 [get_ports {JB6_7_N}]; # "T15.JX1_LVDS_4_N.JX1.25.JB6-7_N" - JB - Pin 10
+
+
+# ----------------------------------------------------------------------------
+# FMC Expansion Connector - Bank 34
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN U19 [get_ports {CLK0_M2C_N}]; # "U19.JX1_LVDS_11_N.JX1.44.CLK0_M2C_N"
+# set_property PACKAGE_PIN U18 [get_ports {CLK0_M2C_P}]; # "U18.JX1_LVDS_11_P.JX1.42.CLK0_M2C_P"
+# set_property PACKAGE_PIN P16 [get_ports {FMC_SCL}]; # "P16.JX1_LVDS_23_N.JX1.84.FMC_SCL"
+# set_property PACKAGE_PIN P15 [get_ports {FMC_SDA}]; # "P15.JX1_LVDS_23_P.JX1.82.FMC_SDA"
+# set_property PACKAGE_PIN P19 [get_ports {LA00_CC_N}]; # "P19.JX1_LVDS_12_N.JX1.49.LA00_CC_N"
+# set_property PACKAGE_PIN N18 [get_ports {LA00_CC_P}]; # "N18.JX1_LVDS_12_P.JX1.47.LA00_CC_P"
+# set_property PACKAGE_PIN P20 [get_ports {LA01_CC_N}]; # "P20.JX1_LVDS_13_N.JX1.50.LA01_CC_N"
+# set_property PACKAGE_PIN N20 [get_ports {LA01_CC_P}]; # "N20.JX1_LVDS_13_P.JX1.48.LA01_CC_P"
+# set_property PACKAGE_PIN R14 [get_ports {LA02_N}]; # "R14.JX1_LVDS_5_N.JX1.26.LA02_N"
+# set_property PACKAGE_PIN P14 [get_ports {LA02_P}]; # "P14.JX1_LVDS_5_P.JX1.24.LA02_P"
+# set_property PACKAGE_PIN Y17 [get_ports {LA03_N}]; # "Y17.JX1_LVDS_6_N.JX1.31.LA03_N"
+# set_property PACKAGE_PIN Y16 [get_ports {LA03_P}]; # "Y16.JX1_LVDS_6_P.JX1.29.LA03_P"
+# set_property PACKAGE_PIN Y14 [get_ports {LA04_N}]; # "Y14.JX1_LVDS_7_N.JX1.32.LA04_N"
+# set_property PACKAGE_PIN W14 [get_ports {LA04_P}]; # "W14.JX1_LVDS_7_P.JX1.30.LA04_P"
+# set_property PACKAGE_PIN U17 [get_ports {LA05_N}]; # "U17.JX1_LVDS_8_N.JX1.37.LA05_N"
+# set_property PACKAGE_PIN T16 [get_ports {LA05_P}]; # "T16.JX1_LVDS_8_P.JX1.35.LA05_P"
+# set_property PACKAGE_PIN W15 [get_ports {LA06_N}]; # "W15.JX1_LVDS_9_N.JX1.38.LA06_N"
+# set_property PACKAGE_PIN V15 [get_ports {LA06_P}]; # "V15.JX1_LVDS_9_P.JX1.36.LA06_P"
+# set_property PACKAGE_PIN U15 [get_ports {LA07_N}]; # "U15.JX1_LVDS_10_N.JX1.43.LA07_N"
+# set_property PACKAGE_PIN U14 [get_ports {LA07_P}]; # "U14.JX1_LVDS_10_P.JX1.41.LA07_P"
+# set_property PACKAGE_PIN U20 [get_ports {LA08_N}]; # "U20.JX1_LVDS_14_N.JX1.55.LA08_N"
+# set_property PACKAGE_PIN T20 [get_ports {LA08_P}]; # "T20.JX1_LVDS_14_P.JX1.53.LA08_P"
+# set_property PACKAGE_PIN W20 [get_ports {LA09_N}]; # "W20.JX1_LVDS_15_N.JX1.56.LA09_N"
+# set_property PACKAGE_PIN V20 [get_ports {LA09_P}]; # "V20.JX1_LVDS_15_P.JX1.54.LA09_P"
+# set_property PACKAGE_PIN Y19 [get_ports {LA10_N}]; # "Y19.JX1_LVDS_16_N.JX1.63.LA10_N"
+# set_property PACKAGE_PIN Y18 [get_ports {LA10_P}]; # "Y18.JX1_LVDS_16_P.JX1.61.LA10_P"
+# set_property PACKAGE_PIN W16 [get_ports {LA11_N}]; # "W16.JX1_LVDS_17_N.JX1.64.LA11_N"
+# set_property PACKAGE_PIN V16 [get_ports {LA11_P}]; # "V16.JX1_LVDS_17_P.JX1.62.LA11_P"
+# set_property PACKAGE_PIN R17 [get_ports {LA12_N}]; # "R17.JX1_LVDS_18_N.JX1.69.LA12_N"
+# set_property PACKAGE_PIN R16 [get_ports {LA12_P}]; # "R16.JX1_LVDS_18_P.JX1.67.LA12_P"
+# set_property PACKAGE_PIN R18 [get_ports {LA13_N}]; # "R18.JX1_LVDS_19_N.JX1.70.LA13_N"
+# set_property PACKAGE_PIN T17 [get_ports {LA13_P}]; # "T17.JX1_LVDS_19_P.JX1.68.LA13_P"
+# set_property PACKAGE_PIN V18 [get_ports {LA14_N}]; # "V18.JX1_LVDS_20_N.JX1.75.LA14_N"
+# set_property PACKAGE_PIN V17 [get_ports {LA14_P}]; # "V17.JX1_LVDS_20_P.JX1.73.LA14_P"
+# set_property PACKAGE_PIN W19 [get_ports {LA15_N}]; # "W19.JX1_LVDS_21_N.JX1.76.LA15_N"
+# set_property PACKAGE_PIN W18 [get_ports {LA15_P}]; # "W18.JX1_LVDS_21_P.JX1.74.LA15_P"
+# set_property PACKAGE_PIN P18 [get_ports {LA16_N}]; # "P18.JX1_LVDS_22_N.JX1.83.LA16_N"
+# set_property PACKAGE_PIN N17 [get_ports {LA16_P}]; # "N17.JX1_LVDS_22_P.JX1.81.LA16_P"
+
+
+# ----------------------------------------------------------------------------
+# FMC Expansion Connector - Bank 35
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN K18 [get_ports {CLK1_M2C_N}]; # "K18.JX2_LVDS_11_N.JX2.50.CLK1_M2C_N"
+# set_property PACKAGE_PIN K17 [get_ports {CLK1_M2C_P}]; # "K17.JX2_LVDS_11_P.JX2.48.CLK1_M2C_P"
+# set_property PACKAGE_PIN M14 [get_ports {FMC_PRSNT_L}]; # "M14.JX2_LVDS_22_P.JX2.87.FMC_PRSNT_L"
+# set_property PACKAGE_PIN H17 [get_ports {LA17_CC_N}]; # "H17.JX2_LVDS_12_N.JX2.55.LA17_CC_N"
+# set_property PACKAGE_PIN H16 [get_ports {LA17_CC_P}]; # "H16.JX2_LVDS_12_P.JX2.53.LA17_CC_P"
+# set_property PACKAGE_PIN H18 [get_ports {LA18_CC_N}]; # "H18.JX2_LVDS_13_N.JX2.56.LA18_CC_N"
+# set_property PACKAGE_PIN J18 [get_ports {LA18_CC_P}]; # "J18.JX2_LVDS_13_P.JX2.54.LA18_CC_P"
+# set_property PACKAGE_PIN D18 [get_ports {LA19_N}]; # "D18.JX2_LVDS_2_N.JX2.25.LA19_N"
+# set_property PACKAGE_PIN E17 [get_ports {LA19_P}]; # "E17.JX2_LVDS_2_P.JX2.23.LA19_P"
+set_property PACKAGE_PIN D20 [get_ports iic_rtl_sda_io]
+set_property PACKAGE_PIN D19 [get_ports iic_rtl_scl_io]
+# set_property PACKAGE_PIN E19 [get_ports {LA21_N}]; # "E19.JX2_LVDS_4_N.JX2.31.LA21_N"
+# set_property PACKAGE_PIN E18 [get_ports {LA21_P}]; # "E18.JX2_LVDS_4_P.JX2.29.LA21_P"
+set_property PACKAGE_PIN F16 [get_ports CMD_IN_P_5]
+set_property PACKAGE_PIN F17 [get_ports CMD_IN_N_5]
+# set_property PACKAGE_PIN L20 [get_ports {LA23_N}]; # "L20.JX2_LVDS_6_N.JX2.37.LA23_N"
+# set_property PACKAGE_PIN L19 [get_ports {LA23_P}]; # "L19.JX2_LVDS_6_P.JX2.35.LA23_P"
+set_property PACKAGE_PIN M19 [get_ports CMD_OUT_P_5]
+set_property PACKAGE_PIN M20 [get_ports CMD_OUT_N_5]
+# set_property PACKAGE_PIN M18 [get_ports {LA25_N}]; # "M18.JX2_LVDS_8_N.JX2.43.LA25_N"
+# set_property PACKAGE_PIN M17 [get_ports {LA25_P}]; # "M17.JX2_LVDS_8_P.JX2.41.LA25_P"
+# set_property PACKAGE_PIN J19 [get_ports {LA26_N}]; # "J19.JX2_LVDS_9_N.JX2.44.LA26_N"
+# set_property PACKAGE_PIN K19 [get_ports {LA26_P}]; # "K19.JX2_LVDS_9_P.JX2.42.LA26_P"
+# set_property PACKAGE_PIN G18 [get_ports {LA27_N}]; # "G18.JX2_LVDS_14_N.JX2.63.LA27_N"
+# set_property PACKAGE_PIN G17 [get_ports {LA27_P}]; # "G17.JX2_LVDS_14_P.JX2.61.LA27_P"
+# set_property PACKAGE_PIN F20 [get_ports {LA28_N}]; # "F20.JX2_LVDS_15_N.JX2.64.LA28_N"
+# set_property PACKAGE_PIN F19 [get_ports {LA28_P}]; # "F19.JX2_LVDS_15_P.JX2.62.LA28_P"
+# set_property PACKAGE_PIN H20 [get_ports {LA29_N}]; # "H20.JX2_LVDS_17_N.JX2.70.LA29_N"
+# set_property PACKAGE_PIN J20 [get_ports {LA29_P}]; # "J20.JX2_LVDS_17_P.JX2.68.LA29_P"
+# set_property PACKAGE_PIN J14 [get_ports {LA30_N}]; # "J14.JX2_LVDS_18_N.JX2.75.LA30_N"
+# set_property PACKAGE_PIN K14 [get_ports {LA30_P}]; # "K14.JX2_LVDS_18_P.JX2.73.LA30_P"
+# set_property PACKAGE_PIN G15 [get_ports {LA31_N}]; # "G15.JX2_LVDS_19_N.JX2.76.LA31_N"
+# set_property PACKAGE_PIN H15 [get_ports {LA31_P}]; # "H15.JX2_LVDS_19_P.JX2.74.LA31_P"
+# set_property PACKAGE_PIN N16 [get_ports {LA32_N}]; # "N16.JX2_LVDS_20_N.JX2.83.LA32_N"
+# set_property PACKAGE_PIN N15 [get_ports {LA32_P}]; # "N15.JX2_LVDS_20_P.JX2.81.LA32_P"
+# set_property PACKAGE_PIN L15 [get_ports {LA33_N}]; # "L15.JX2_LVDS_21_N.JX2.84.LA33_N"
+# set_property PACKAGE_PIN L14 [get_ports {LA33_P}]; # "L14.JX2_LVDS_21_P.JX2.82.LA33_P"
+
+
+# ----------------------------------------------------------------------------
+# User LEDs - Bank 35
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN K16 [get_ports {LED2}]; # "K16.JX2_LVDS_23_P.JX2.88.LED2"
+# set_property PACKAGE_PIN M15 [get_ports {LED3}]; # "M15.JX2_LVDS_22_N.JX2.89.LED3"
+
+
+# ----------------------------------------------------------------------------
+# UNI/O MAC ID EEPROM - Bank 35
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN J16 [get_ports {MAC_ID}]; # "J16.JX2_LVDS_23_N.JX2.90.MAC_ID"
+
+
+# ----------------------------------------------------------------------------
+# User Push Buttons - Bank 35
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN G19 [get_ports {PB0}]; # "G19.JX2_LVDS_16_P.JX2.67.PB0"
+# set_property PACKAGE_PIN G20 [get_ports {PB1}]; # "G20.JX2_LVDS_16_N.JX2.69.PB1"
+
+
+# ----------------------------------------------------------------------------
+# JA Pmod - Bank 35
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN L16 [get_ports {JA0_1_P}]; # "L16.JX2_LVDS_10_P.JX2.47.JA0-1_P" - JA - Pin 1
+# set_property PACKAGE_PIN L17 [get_ports {JA0_1_N}]; # "L17.JX2_LVDS_10_N.JX2.49.JA0-1_N" - JA - Pin 2
+# set_property PACKAGE_PIN G14 [get_ports {JA2}]; # "G14.JX2_SE_0.JX2.13.JA2" - JA - Pin 3
+# set_property PACKAGE_PIN J15 [get_ports {JA3}]; # "J15.JX2_SE_1.JX2.14.JA3" - JA - Pin 4
+# set_property PACKAGE_PIN B19 [get_ports {JA4_5_P}]; # "B19.JX2_LVDS_1_P.JX2.18.JA4-5_P" - JA - Pin 7
+# set_property PACKAGE_PIN A20 [get_ports {JA4_5_N}]; # "A20.JX2_LVDS_1_N.JX2.20.JA4-5_N" - JA - Pin 8
+# set_property PACKAGE_PIN C20 [get_ports {JA6_7_P}]; # "C20.JX2_LVDS_0_P.JX2.17.JA6-7_P" - JA - Pin 9
+# set_property PACKAGE_PIN B20 [get_ports {JA6_7_N}]; # "B20.JX2_LVDS_0_N.JX2.19.JA6-7_N" - JA - Pin 10
+
+
+# ----------------------------------------------------------------------------
+# JY Pmod - Bank 13 (Available on Z7020 device only)
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN U7 [get_ports {JY0_1_P}]; # "U7.BANK13_LVDS_0_P.JX1.87.JY0-1_P" - JY - Pin 1
+# set_property PACKAGE_PIN V7 [get_ports {JY0_1_N}]; # "V7.BANK13_LVDS_0_N.JX1.89.JY0-1_N" - JY - Pin 2
+# set_property PACKAGE_PIN T9 [get_ports {JY2_3_P}]; # "T9.BANK13_LVDS_1_P.JX1.88.JY2-3_P" - JY - Pin 3
+# set_property PACKAGE_PIN U10 [get_ports {JY2_3_N}]; # "U10.BANK13_LVDS_1_N.JX1.90.JY2-3_N" - JY - Pin 4
+# set_property PACKAGE_PIN V8 [get_ports {JY4_5_P}]; # "V8.BANK13_LVDS_2_P.JX1.91.JY4-5_P" - JY - Pin 7
+# set_property PACKAGE_PIN W8 [get_ports {JY4_5_N}]; # "W8.BANK13_LVDS_2_N.JX1.93.JY4-5_N" - JY - Pin 8
+# set_property PACKAGE_PIN T5 [get_ports {JY6_7_P}]; # "T5.BANK13_LVDS_3_P.JX1.92.JY6-7_P" - JY - Pin 9
+# set_property PACKAGE_PIN U5 [get_ports {JY6_7_N}]; # "U5.BANK13_LVDS_3_N.JX1.94.JY6-7_N" - JY - Pin 10
+
+
+# ----------------------------------------------------------------------------
+# JZ Pmod - Bank 13 (Available on Z7020 device only)
+# ----------------------------------------------------------------------------
+# set_property PACKAGE_PIN Y12 [get_ports {JZ0_1_P}]; # "Y12.BANK13_LVDS_4_P.JX2.93.JZ0-1_P" - JZ - Pin 1
+# set_property PACKAGE_PIN Y13 [get_ports {JZ0_1_N}]; # "Y13.BANK13_LVDS_4_N.JX2.95.JZ0-1_N" - JZ - Pin 2
+# set_property PACKAGE_PIN V11 [get_ports {JZ2_3_P}]; # "V11.BANK13_LVDS_5_P.JX2.94.JZ2-3_P" - JZ - Pin 3
+# set_property PACKAGE_PIN V10 [get_ports {JZ2_3_N}]; # "V10.BANK13_LVDS_5_N.JX2.96.JZ2-3_N" - JZ - Pin 4
+# set_property PACKAGE_PIN V5 [get_ports {JZ5}]; # "V5.BANK13_SE_0.JX2.100.JZ5" - JZ - Pin 8
+# set_property PACKAGE_PIN V6 [get_ports {JZ6_7_P}]; # "V6.BANK13_LVDS_6_P.JX2.97.JZ6-7_P" - JZ - Pin 9
+# set_property PACKAGE_PIN W6 [get_ports {JZ6_7_N}]; # "W6.BANK13_LVDS_6_N.JX2.99.JZ6-7_N" - JZ - Pin 10
+
+
+# ----------------------------------------------------------------------------
+# IOSTANDARD Constraints
+#
+# Note that these IOSTANDARD constraints are applied to all IOs currently
+# assigned within an I/O bank. If these IOSTANDARD constraints are
+# evaluated prior to other PACKAGE_PIN constraints being applied, then
+# the IOSTANDARD specified will likely not be applied properly to those
+# pins. Therefore, bank wide IOSTANDARD constraints should be placed
+# within the XDC file in a location that is evaluated AFTER all
+# PACKAGE_PIN constraints within the target bank have been evaluated.
+#
+# Un-comment one or more of the following IOSTANDARD constraints according to
+# the bank pin assignments that are required within a design.
+# ----------------------------------------------------------------------------
+
+# Set the bank voltage for IO Bank 34 to 3.3V by default.
+# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
+
+# Set the bank voltage for IO Bank 35 to 3.3V by default.
+# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
+
+# Set the bank voltage for IO Bank 13 to 3.3V by default. (I/O bank available on Z7020 device only)
+# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/constrs_1/new/pins.xdc b/pbv3_mass_test_adapter_firmware.srcs/constrs_1/new/pins.xdc
index ddca5fe..9c7e13f 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/constrs_1/new/pins.xdc
+++ b/pbv3_mass_test_adapter_firmware.srcs/constrs_1/new/pins.xdc
@@ -1,2 +1,8 @@
set_property IOSTANDARD LVCMOS25 [get_ports iic_rtl_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports iic_rtl_sda_io]
+
+# set_property IOSTANDARD LVDS_25 [get_ports CMD_IN_P_*]
+# set_property DIFF_TERM TRUE [get_ports CMD_IN_P_*]
+set_property IOSTANDARD LVDS_25 [get_ports CMD_OUT_P_*]
+set_property DIFF_TERM true [get_ports CMD_OUT_P_*]
+set_property DIFF_TERM TRUE [get_ports CMD_OUT_N_5]
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bd
deleted file mode 100644
index 4851841..0000000
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bd
+++ /dev/null
@@ -1,11 +0,0 @@
-{
- "design": {
- "design_info": {
- "boundary_crc": "0x0",
- "name": "ActiveBoard",
- "synth_flow_mode": "Hierarchical",
- "tool_version": "2019.1"
- },
- "design_tree": {}
- }
-}
\ No newline at end of file
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bxml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bxml
deleted file mode 100644
index 050128c..0000000
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/ActiveBoard/ActiveBoard.bxml
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Root MajorVersion="0" MinorVersion="37">
- <CompositeFile CompositeFileTopName="ActiveBoard" CanBeSetAsTop="false" CanDisplayChildGraph="true">
- <Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="STALE" Timestamp="1568798960"/>
- <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1568798960"/>
- <Generation Name="SIMULATION" State="STALE" Timestamp="1568798960"/>
- <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1568798960"/>
- <FileCollection Name="SOURCES" Type="SOURCES"/>
- </CompositeFile>
-</Root>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bd
index e43ed7f..e0e3b71 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bd
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bd
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
- "boundary_crc": "0x2A497A1B9224360E",
+ "boundary_crc": "0xB9C7E63B1139A7A1",
"device": "xc7z020clg400-1",
"name": "TopLevel",
"synth_flow_mode": "Hierarchical",
@@ -13,10 +13,14 @@
"rst_ps7_0_100M": "",
"processing_system7_0": "",
"ps7_0_axi_periph": {
+ "xbar": "",
"s00_couplers": {
"auto_pc": ""
- }
- }
+ },
+ "m00_couplers": {},
+ "m01_couplers": {}
+ },
+ "endeavour_axi_contro_5": ""
},
"interface_ports": {
"iic_rtl": {
@@ -88,6 +92,20 @@
}
}
},
+ "ports": {
+ "CMD_IN_P_5": {
+ "direction": "O"
+ },
+ "CMD_IN_N_5": {
+ "direction": "O"
+ },
+ "CMD_OUT_P_5": {
+ "direction": "I"
+ },
+ "CMD_OUT_N_5": {
+ "direction": "I"
+ }
+ },
"components": {
"axi_iic_0": {
"vlnv": "xilinx.com:ip:axi_iic:2.0",
@@ -99,7 +117,7 @@
},
"processing_system7_0": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
- "xci_name": "TopLevel_processing_system7_0_1",
+ "xci_name": "TopLevel_processing_system7_0_0",
"parameters": {
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
"value": "666.666687"
@@ -1047,10 +1065,10 @@
},
"ps7_0_axi_periph": {
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
- "xci_name": "TopLevel_ps7_0_axi_periph_1",
+ "xci_name": "TopLevel_ps7_0_axi_periph_0",
"parameters": {
"NUM_MI": {
- "value": "1"
+ "value": "2"
}
},
"interface_ports": {
@@ -1061,6 +1079,10 @@
"M00_AXI": {
"mode": "Master",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+ },
+ "M01_AXI": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
@@ -1108,9 +1130,40 @@
"M00_ARESETN": {
"type": "rst",
"direction": "I"
+ },
+ "M01_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "M01_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "M01_ARESETN"
+ }
+ }
+ },
+ "M01_ARESETN": {
+ "type": "rst",
+ "direction": "I"
}
},
"components": {
+ "xbar": {
+ "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
+ "xci_name": "TopLevel_xbar_0",
+ "parameters": {
+ "NUM_MI": {
+ "value": "2"
+ },
+ "NUM_SI": {
+ "value": "1"
+ },
+ "STRATEGY": {
+ "value": "0"
+ }
+ }
+ },
"s00_couplers": {
"interface_ports": {
"M_AXI": {
@@ -1159,7 +1212,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
- "xci_name": "TopLevel_auto_pc_2",
+ "xci_name": "TopLevel_auto_pc_0",
"parameters": {
"MI_PROTOCOL": {
"value": "AXI4LITE"
@@ -1198,55 +1251,191 @@
]
}
}
+ },
+ "m00_couplers": {
+ "interface_ports": {
+ "M_AXI": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+ },
+ "S_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+ }
+ },
+ "ports": {
+ "M_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "M_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "M_ARESETN"
+ }
+ }
+ },
+ "M_ARESETN": {
+ "type": "rst",
+ "direction": "I"
+ },
+ "S_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S_ARESETN"
+ }
+ }
+ },
+ "S_ARESETN": {
+ "type": "rst",
+ "direction": "I"
+ }
+ },
+ "interface_nets": {
+ "m00_couplers_to_m00_couplers": {
+ "interface_ports": [
+ "S_AXI",
+ "M_AXI"
+ ]
+ }
+ }
+ },
+ "m01_couplers": {
+ "interface_ports": {
+ "M_AXI": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+ },
+ "S_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+ }
+ },
+ "ports": {
+ "M_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "M_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "M_ARESETN"
+ }
+ }
+ },
+ "M_ARESETN": {
+ "type": "rst",
+ "direction": "I"
+ },
+ "S_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S_ARESETN"
+ }
+ }
+ },
+ "S_ARESETN": {
+ "type": "rst",
+ "direction": "I"
+ }
+ },
+ "interface_nets": {
+ "m01_couplers_to_m01_couplers": {
+ "interface_ports": [
+ "S_AXI",
+ "M_AXI"
+ ]
+ }
+ }
}
},
"interface_nets": {
- "s00_couplers_to_ps7_0_axi_periph": {
+ "ps7_0_axi_periph_to_s00_couplers": {
+ "interface_ports": [
+ "S00_AXI",
+ "s00_couplers/S_AXI"
+ ]
+ },
+ "s00_couplers_to_xbar": {
+ "interface_ports": [
+ "s00_couplers/M_AXI",
+ "xbar/S00_AXI"
+ ]
+ },
+ "m00_couplers_to_ps7_0_axi_periph": {
"interface_ports": [
"M00_AXI",
- "s00_couplers/M_AXI"
+ "m00_couplers/M_AXI"
]
},
- "ps7_0_axi_periph_to_s00_couplers": {
+ "xbar_to_m00_couplers": {
"interface_ports": [
- "S00_AXI",
- "s00_couplers/S_AXI"
+ "xbar/M00_AXI",
+ "m00_couplers/S_AXI"
+ ]
+ },
+ "m01_couplers_to_ps7_0_axi_periph": {
+ "interface_ports": [
+ "M01_AXI",
+ "m01_couplers/M_AXI"
+ ]
+ },
+ "xbar_to_m01_couplers": {
+ "interface_ports": [
+ "xbar/M01_AXI",
+ "m01_couplers/S_AXI"
]
}
},
"nets": {
"ps7_0_axi_periph_ACLK_net": {
"ports": [
- "M00_ACLK",
- "s00_couplers/M_ACLK"
+ "ACLK",
+ "xbar/aclk",
+ "s00_couplers/S_ACLK",
+ "s00_couplers/M_ACLK",
+ "m00_couplers/M_ACLK",
+ "m01_couplers/M_ACLK",
+ "m00_couplers/S_ACLK",
+ "m01_couplers/S_ACLK"
]
},
"ps7_0_axi_periph_ARESETN_net": {
"ports": [
- "M00_ARESETN",
- "s00_couplers/M_ARESETN"
- ]
- },
- "S00_ACLK_1": {
- "ports": [
- "S00_ACLK",
- "s00_couplers/S_ACLK"
- ]
- },
- "S00_ARESETN_1": {
- "ports": [
- "S00_ARESETN",
- "s00_couplers/S_ARESETN"
+ "ARESETN",
+ "xbar/aresetn",
+ "s00_couplers/S_ARESETN",
+ "s00_couplers/M_ARESETN",
+ "m00_couplers/M_ARESETN",
+ "m01_couplers/M_ARESETN",
+ "m00_couplers/S_ARESETN",
+ "m01_couplers/S_ARESETN"
]
}
}
+ },
+ "endeavour_axi_contro_5": {
+ "vlnv": "lbl.gov:endeavour:endeavour_axi_controller:1.0",
+ "xci_name": "TopLevel_endeavour_axi_contro_5_0"
}
},
"interface_nets": {
- "processing_system7_0_DDR": {
+ "processing_system7_0_FIXED_IO": {
"interface_ports": [
- "DDR",
- "processing_system7_0/DDR"
+ "FIXED_IO",
+ "processing_system7_0/FIXED_IO"
]
},
"axi_iic_0_IIC": {
@@ -1255,16 +1444,22 @@
"axi_iic_0/IIC"
]
},
+ "ps7_0_axi_periph_M01_AXI": {
+ "interface_ports": [
+ "ps7_0_axi_periph/M01_AXI",
+ "endeavour_axi_contro_5/S00_AXI"
+ ]
+ },
"processing_system7_0_M_AXI_GP0": {
"interface_ports": [
"processing_system7_0/M_AXI_GP0",
"ps7_0_axi_periph/S00_AXI"
]
},
- "processing_system7_0_FIXED_IO": {
+ "processing_system7_0_DDR": {
"interface_ports": [
- "FIXED_IO",
- "processing_system7_0/FIXED_IO"
+ "DDR",
+ "processing_system7_0/DDR"
]
},
"ps7_0_axi_periph_M00_AXI": {
@@ -1283,7 +1478,9 @@
"processing_system7_0/M_AXI_GP0_ACLK",
"ps7_0_axi_periph/ACLK",
"ps7_0_axi_periph/S00_ACLK",
- "ps7_0_axi_periph/M00_ACLK"
+ "ps7_0_axi_periph/M00_ACLK",
+ "ps7_0_axi_periph/M01_ACLK",
+ "endeavour_axi_contro_5/s00_axi_aclk"
]
},
"rst_ps7_0_100M_peripheral_aresetn": {
@@ -1292,7 +1489,9 @@
"axi_iic_0/s_axi_aresetn",
"ps7_0_axi_periph/S00_ARESETN",
"ps7_0_axi_periph/M00_ARESETN",
- "ps7_0_axi_periph/ARESETN"
+ "ps7_0_axi_periph/ARESETN",
+ "ps7_0_axi_periph/M01_ARESETN",
+ "endeavour_axi_contro_5/s00_axi_aresetn"
]
},
"processing_system7_0_FCLK_RESET0_N": {
@@ -1306,6 +1505,30 @@
"axi_iic_0/iic2intc_irpt",
"processing_system7_0/IRQ_F2P"
]
+ },
+ "endeavour_axi_contro_5_CMD_IN_P": {
+ "ports": [
+ "endeavour_axi_contro_5/CMD_IN_P",
+ "CMD_IN_P_5"
+ ]
+ },
+ "endeavour_axi_contro_5_CMD_IN_N": {
+ "ports": [
+ "endeavour_axi_contro_5/CMD_IN_N",
+ "CMD_IN_N_5"
+ ]
+ },
+ "CMD_OUT_P_0_1": {
+ "ports": [
+ "CMD_OUT_P_5",
+ "endeavour_axi_contro_5/CMD_OUT_P"
+ ]
+ },
+ "CMD_OUT_N_0_1": {
+ "ports": [
+ "CMD_OUT_N_5",
+ "endeavour_axi_contro_5/CMD_OUT_N"
+ ]
}
},
"addressing": {
@@ -1319,6 +1542,11 @@
"address_block": "/axi_iic_0/S_AXI/Reg",
"offset": "0x41600000",
"range": "64K"
+ },
+ "SEG_endeavour_axi_contro_0_S00_AXI_reg": {
+ "address_block": "/endeavour_axi_contro_5/S00_AXI/S00_AXI_reg",
+ "offset": "0x43C00000",
+ "range": "64K"
}
}
}
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bxml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bxml
index dd5b061..7749a5a 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bxml
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel.bxml
@@ -2,11 +2,21 @@
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="TopLevel" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="RESET" Timestamp="1569142638"/>
- <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1569142638"/>
- <Generation Name="SIMULATION" State="RESET" Timestamp="1569142638"/>
- <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1569142638"/>
+ <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1571159177"/>
+ <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1571159177"/>
+ <Generation Name="SIMULATION" State="GENERATED" Timestamp="1571159177"/>
+ <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1571159177"/>
<FileCollection Name="SOURCES" Type="SOURCES">
+ <File Name="synth/TopLevel.vhd" Type="VHDL">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SYNTHESIS"/>
+ </File>
+ <File Name="sim/TopLevel.vhd" Type="VHDL">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SIMULATION"/>
+ </File>
<File Name="ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xci" Type="IP">
<Instance HierarchyPath="axi_iic_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@@ -23,7 +33,7 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
- <File Name="ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xci" Type="IP">
+ <File Name="ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
@@ -31,7 +41,7 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
- <File Name="ip/TopLevel_ps7_0_axi_periph_1/TopLevel_ps7_0_axi_periph_1.xci" Type="IP">
+ <File Name="ip/TopLevel_ps7_0_axi_periph_0/TopLevel_ps7_0_axi_periph_0.xci" Type="IP">
<Instance HierarchyPath="ps7_0_axi_periph"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
@@ -39,7 +49,23 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
- <File Name="ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xci" Type="IP">
+ <File Name="ip/TopLevel_xbar_0/TopLevel_xbar_0.xci" Type="IP">
+ <Instance HierarchyPath="ps7_0_axi_periph/xbar"/>
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SYNTHESIS"/>
+ <UsedIn Val="IMPLEMENTATION"/>
+ <UsedIn Val="SIMULATION"/>
+ </File>
+ <File Name="ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xci" Type="IP">
+ <Instance HierarchyPath="endeavour_axi_contro_5"/>
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SYNTHESIS"/>
+ <UsedIn Val="IMPLEMENTATION"/>
+ <UsedIn Val="SIMULATION"/>
+ </File>
+ <File Name="ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xci" Type="IP">
<Instance HierarchyPath="ps7_0_axi_periph/s00_couplers/auto_pc"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
@@ -47,6 +73,33 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
+ <File Name="TopLevel_ooc.xdc" Type="XDC">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SYNTHESIS"/>
+ <UsedIn Val="IMPLEMENTATION"/>
+ <UsedIn Val="OUT_OF_CONTEXT"/>
+ </File>
+ <File Name="hw_handoff/TopLevel.hwh" Type="HwHandoff">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="HW_HANDOFF"/>
+ </File>
+ <File Name="hw_handoff/TopLevel_bd.tcl">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="HW_HANDOFF"/>
+ </File>
+ <File Name="synth/TopLevel.hwdef">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="HW_HANDOFF"/>
+ </File>
+ <File Name="sim/TopLevel.protoinst">
+ <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+ <Library Name="xil_defaultlib"/>
+ <UsedIn Val="SIMULATION"/>
+ </File>
</FileCollection>
</CompositeFile>
</Root>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel_ooc.xdc b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel_ooc.xdc
new file mode 100644
index 0000000..60c7acf
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/TopLevel_ooc.xdc
@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]
+
+################################################################################
\ No newline at end of file
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hdl/TopLevel_wrapper.vhd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hdl/TopLevel_wrapper.vhd
index 7238074..769fa16 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hdl/TopLevel_wrapper.vhd
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hdl/TopLevel_wrapper.vhd
@@ -1,8 +1,8 @@
--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
---Date : Sat Sep 21 09:51:44 2019
---Host : carl-pc running 64-bit CentOS Linux release 7.6.1810 (Core)
+--Date : Tue Oct 15 10:06:03 2019
+--Host : carl-pc running 64-bit unknown
--Command : generate_target TopLevel_wrapper.bd
--Design : TopLevel_wrapper
--Purpose : IP block netlist
@@ -13,6 +13,10 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity TopLevel_wrapper is
port (
+ CMD_IN_N_5 : out STD_LOGIC;
+ CMD_IN_P_5 : out STD_LOGIC;
+ CMD_OUT_N_5 : in STD_LOGIC;
+ CMD_OUT_P_5 : in STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
@@ -42,6 +46,10 @@ end TopLevel_wrapper;
architecture STRUCTURE of TopLevel_wrapper is
component TopLevel is
port (
+ CMD_IN_P_5 : out STD_LOGIC;
+ CMD_IN_N_5 : out STD_LOGIC;
+ CMD_OUT_P_5 : in STD_LOGIC;
+ CMD_OUT_N_5 : in STD_LOGIC;
iic_rtl_scl_i : in STD_LOGIC;
iic_rtl_scl_o : out STD_LOGIC;
iic_rtl_scl_t : out STD_LOGIC;
@@ -88,6 +96,10 @@ architecture STRUCTURE of TopLevel_wrapper is
begin
TopLevel_i: component TopLevel
port map (
+ CMD_IN_N_5 => CMD_IN_N_5,
+ CMD_IN_P_5 => CMD_IN_P_5,
+ CMD_OUT_N_5 => CMD_OUT_N_5,
+ CMD_OUT_P_5 => CMD_OUT_P_5,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel.hwh b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel.hwh
new file mode 100644
index 0000000..3aa9204
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel.hwh
@@ -0,0 +1,3736 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Oct 15 10:06:17 2019" VIVADOVERSION="2019.1">
+
+ <SYSTEMINFO ARCH="zynq" BOARD="em.avnet.com:microzed_7020:part0:1.1" DEVICE="7z020" NAME="TopLevel" PACKAGE="clg400" SPEEDGRADE="-1"/>
+
+ <EXTERNALPORTS>
+ <PORT DIR="O" NAME="CMD_IN_P_5" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_CMD_IN_P">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="CMD_IN_P"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="CMD_IN_N_5" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_CMD_IN_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="CMD_IN_N"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="CMD_OUT_P_5" SIGIS="undef" SIGNAME="External_Ports_CMD_OUT_P_5">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="CMD_OUT_P"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="CMD_OUT_N_5" SIGIS="undef" SIGNAME="External_Ports_CMD_OUT_N_5">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="CMD_OUT_N"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="iic_rtl_scl_i" SIGIS="undef" SIGNAME="axi_iic_0_scl_i">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="scl_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="iic_rtl_scl_o" SIGIS="undef" SIGNAME="axi_iic_0_scl_o">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="scl_o"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="iic_rtl_scl_t" SIGIS="undef" SIGNAME="axi_iic_0_scl_t">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="scl_t"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="iic_rtl_sda_i" SIGIS="undef" SIGNAME="axi_iic_0_sda_i">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="sda_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="iic_rtl_sda_o" SIGIS="undef" SIGNAME="axi_iic_0_sda_o">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="sda_o"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="iic_rtl_sda_t" SIGIS="undef" SIGNAME="axi_iic_0_sda_t">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="sda_t"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_cke" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CKE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_reset_n" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_odt" SIGIS="undef" SIGNAME="processing_system7_0_DDR_ODT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_RAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_WEB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_BankAddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Addr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DM">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DM"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQ">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="processing_system7_0_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="processing_system7_0_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="processing_system7_0_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
+ </EXTERNALPORTS>
+
+ <EXTERNALINTERFACES>
+ <BUSINTERFACE BUSNAME="axi_iic_0_IIC" NAME="iic_rtl" TYPE="INITIATOR">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="SCL_I" PHYSICAL="iic_rtl_scl_i"/>
+ <PORTMAP LOGICAL="SCL_O" PHYSICAL="iic_rtl_scl_o"/>
+ <PORTMAP LOGICAL="SCL_T" PHYSICAL="iic_rtl_scl_t"/>
+ <PORTMAP LOGICAL="SDA_I" PHYSICAL="iic_rtl_sda_i"/>
+ <PORTMAP LOGICAL="SDA_O" PHYSICAL="iic_rtl_sda_o"/>
+ <PORTMAP LOGICAL="SDA_T" PHYSICAL="iic_rtl_sda_t"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+ <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+ <PARAMETER NAME="MEMORY_PART"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="SLOT" VALUE="Single"/>
+ <PARAMETER NAME="CUSTOM_PARTS"/>
+ <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+ <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+ <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+ <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+ <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
+ <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
+ <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
+ <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
+ <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
+ <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
+ <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
+ <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
+ <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
+ <PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
+ <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
+ <PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
+ <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
+ <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
+ <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
+ <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
+ <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
+ <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
+ <PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
+ <PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </EXTERNALINTERFACES>
+
+ <MODULES>
+ <MODULE COREREVISION="22" FULLNAME="/axi_iic_0" HWVERSION="2.0" INSTANCE="axi_iic_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_iic" VLNV="xilinx.com:ip:axi_iic:2.0">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v2_0;d=pg090-axi-iic.pdf"/>
+ </DOCUMENTS>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
+ <REGISTERS>
+ <REGISTER NAME="GIE">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1c"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="GIE">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable
0 - All Interrupts disabled; no interrupt (even if unmasked in IER) possible from AXI IIC core
1 - Unmasked AXI IIC core interrupts are passed to processor
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="ISR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x020"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0xd0"/>
+ <FIELDS>
+ <FIELD NAME="int0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt0 - Arbitration Lost
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt1 - Transmit Error/Slave Transmit Complete
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int2">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt2 - Transmit FIFO Empty
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int3">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt3 - Recieve FIFO FULL
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int4">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt4 - IIC Bus is Not Busy
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int5">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt5 - Addressed As Slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int6">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt6 - Not Addessed As Slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int7">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt7 - Transmit FIFO Half Empty
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="IER">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Enable Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x028"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="int0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt0 - Arbitration Lost
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt1 - Transmit Error/Slave Transmit Complete
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int2">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt2 - Transmit FIFO Empty
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int3">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt3 - Recieve FIFO FULL
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int4">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt4 - IIC Bus is Not Busy
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int5">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt5 - Addressed As Slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int6">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt6 - Not Addessed As Slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="int7">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt7 - Transmit FIFO Half Empty
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="SOFTR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Soft Reset Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x040"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="RKEY">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Reset Key - Firmware must write a value of 0xA to this field to
 cause a soft reset of the Interrupt registers of AXI IIC controller.
 Writing any other value results in an AXI transaction
 acknowledgement with SLVERR and no reset occurs.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="CR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Control Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x100"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="EN">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit must be set before any other CR bits have any effect
0 - resets and disables the AXI IIC controller but not the registers or FIFOs
1 - enables the AXI IIC controller
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="TX_FIFO Reset">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit must be set to flush the FIFO if either (a) arbitration is lost or (b) if a transmit error occurs
0 - transmit FIFO normal operation
1 - resets the transmit FIFO
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="MSMS">
+ <PROPERTY NAME="DESCRIPTION" VALUE="When this bit is changed from 0 to 1, the
AXI IIC bus interface generates a START condition in master mode. When
this bit is cleared, a STOP condition is generated and the AXI IIC bus
interface switches to slave mode. When this bit is cleared by the
hardware, because arbitration for the bus has been lost, a STOP
condition is not generated
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="TX">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit selects the direction of master/slave transfers.
0 - selects an AXI IIC receive
1 - selects an AXI IIC transmit
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="TXAK">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit specifies the value driven onto
the sda line during acknowledge cycles for both master and slave recievers.
0 - acknowledge
1 - not-acknowledge
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="RSTA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Writing a 1 to this bit generates a repeated START 
condition on the bus if the AXI IIC bus interface is the current bus
master. Attempting a repeated START at the wrong time, if the bus is
owned by another master, results in a loss of arbitration. This bit is reset
when the repeated start occurs. This bit must be set prior to writing the
new address to the TX_FIFO or DTR
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="GC_EN">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Setting this bit High allows the AXI IIC to respond to a general call address.
0 - General Call Disabled
1 - General Call Enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="SR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x104"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="ABGC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit is set to 1 when another master has issued a general call and
the general call enable bit is set to 1, CR(6) = 1.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="AAS">
+ <PROPERTY NAME="DESCRIPTION" VALUE="When the address on the IIC bus matches the slave address in the Address register (ADR), the IIC bus interface
is being addressed as a slave and switches to slave mode. If 10-bit addressing is selected this device only responds to a 10-bit
address or general call if enabled. This bit is cleared when a stop
condition is detected or a repeated start occurs.
0 - indicates not being addressed as a slave
1 - indicates being addressed as a slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="BB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit indicates the status of the IIC bus. This bit is set
when a START condition is detected and cleared when a STOP
condition is detected.
0 - indicates the bus is idle
1 - indicates the bus is busy
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ARW">
+ <PROPERTY NAME="DESCRIPTION" VALUE="When the IIC bus interface has been addressed as a slave (AAS is set), 
this bit indicates the value of the read/write bit sent by the master.
This bit is only valid when a complete transfer has occurred and
no other transfers have been initiated.
0 - indicates master writing to slave
1 - indicates master reading from slave
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="TX_FIFO_Full">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit is set High when the transmit FIFO is full.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="RX_FIFO_Full">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This bit is set High when the receive FIFO is full.
This bit is set only when all 16 locations in the FIFO are full,
regardless of the compare value field of the RX_FIFO_PIRQ register.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="RX_FIFO_Empty">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This is set High when the receive FIFO is empty.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="TX_FIFO_Empty">
+ <PROPERTY NAME="DESCRIPTION" VALUE="This is set High when the transmit FIFO is empty.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TX_FIFO">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x108"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="D7_D0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="If the dynamic stop bit is used and the AXI IIC is a master receiver,
the value is the number of bytes to receive.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="Start">
+ <PROPERTY NAME="DESCRIPTION" VALUE="The dynamic start bit can be used to send a start or repeated start sequence on the
IIC bus. A start sequence is generated if the MSMS = 0, a
repeated start sequence is generated if the MSMS = 1.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Stop">
+ <PROPERTY NAME="DESCRIPTION" VALUE="The dynamic stop bit can be used to send an IIC stop
sequence on the IIC bus after the last byte has been transmitted or received.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="RX_FIFO">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Recieve FIFO Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="D7_D0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="IIC Receive Data
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="ADR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Slave Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x110"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Slave_Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Address used by the IIC bus interface when in slave mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="7"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TX_FIFO_OCY">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO Occupency Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x114"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Occupancy_Value">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit[3] is the MSB. A binary value of 1001 indicates that
10 locations are full in the FIFO
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="RX_FIFO_OCY">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Recieve FIFO Occupency Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x118"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Occupancy_Value">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit[3] is the MSB. A binary value of 1001 indicates that
10 locations are full in the FIFO
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TEN_ADR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Slave Ten Bit Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x11C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="MSB of Slave Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Three MSBs of the 10-bit address used by the AXI IIC bus interface when in slave mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="3"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="RX_FIFO_PIRQ">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Recieve FIFO Programmable Depth Interrupt Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x120"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Compare Value">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit[3] is the MSB. A binary value of 1001 implies that when
10 locations in the receive FIFO are filled, the receive FIFO
interrupt is set.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="GPO">
+ <PROPERTY NAME="DESCRIPTION" VALUE="General Purpose Output Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x124"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="General Purpose Outputs">
+ <PROPERTY NAME="DESCRIPTION" VALUE="The LSB (Bit[0]) is the first bit populated
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TSUSTA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter TSUSTA Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x128"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TSUSTA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Setup time for a repeated START condition.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TSUSTO">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter TSUSTO Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x12C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TSUSTO">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Setup time for a repeated STOP condition.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="THDSTA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter THDSTA Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x130"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="THDSTA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Hold time for a repeated START condition.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TSUDAT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter TSUDAT Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x134"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TSUDAT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data Setup time
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TBUF">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter TBUF Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x138"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TBUF">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bus free time between a STOP and START condition
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="THIGH">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter THIGH Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x13C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="THIGH">
+ <PROPERTY NAME="DESCRIPTION" VALUE="High Period of the scl clock.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TLOW">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter TLOW Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x140"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TLOW">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Low Period of scl clock.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="THDDAT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timing Parameter THDDAT Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x144"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="THDDAT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data Hold time
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ </REGISTERS>
+ </ADDRESSBLOCK>
+ </ADDRESSBLOCKS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
+ <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
+ <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_IIC_FREQ" VALUE="100000"/>
+ <PARAMETER NAME="C_TEN_BIT_ADR" VALUE="0"/>
+ <PARAMETER NAME="C_GPO_WIDTH" VALUE="1"/>
+ <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
+ <PARAMETER NAME="C_SCL_INERTIAL_DELAY" VALUE="0"/>
+ <PARAMETER NAME="C_SDA_INERTIAL_DELAY" VALUE="0"/>
+ <PARAMETER NAME="C_SDA_LEVEL" VALUE="1"/>
+ <PARAMETER NAME="C_SMBUS_PMBUS_HOST" VALUE="0"/>
+ <PARAMETER NAME="C_DEFAULT_VALUE" VALUE="0x00"/>
+ <PARAMETER NAME="Component_Name" VALUE="TopLevel_axi_iic_0_0"/>
+ <PARAMETER NAME="TEN_BIT_ADR" VALUE="7_bit"/>
+ <PARAMETER NAME="AXI_ACLK_FREQ_MHZ" VALUE="100.0"/>
+ <PARAMETER NAME="IIC_FREQ_KHZ" VALUE="100"/>
+ <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+ <PARAMETER NAME="IIC_BOARD_INTERFACE" VALUE="Custom"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_BASEADDR" VALUE="0x41600000"/>
+ <PARAMETER NAME="C_HIGHADDR" VALUE="0x4160FFFF"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="iic2intc_irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_iic_0_iic2intc_irpt">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="sda_i" SIGIS="undef" SIGNAME="axi_iic_0_sda_i">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_sda_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="sda_o" SIGIS="undef" SIGNAME="axi_iic_0_sda_o">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_sda_o"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="sda_t" SIGIS="undef" SIGNAME="axi_iic_0_sda_t">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_sda_t"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="scl_i" SIGIS="undef" SIGNAME="axi_iic_0_scl_i">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_scl_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="scl_o" SIGIS="undef" SIGNAME="axi_iic_0_scl_o">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_scl_o"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="scl_t" SIGIS="undef" SIGNAME="axi_iic_0_scl_t">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="iic_rtl_scl_t"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="gpo" RIGHT="0" SIGIS="undef"/>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="9"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="TopLevel_processing_system7_0_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_iic_0_IIC" NAME="IIC" TYPE="INITIATOR" VLNV="xilinx.com:interface:iic:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="SCL_I" PHYSICAL="scl_i"/>
+ <PORTMAP LOGICAL="SCL_O" PHYSICAL="scl_o"/>
+ <PORTMAP LOGICAL="SCL_T" PHYSICAL="scl_t"/>
+ <PORTMAP LOGICAL="SDA_I" PHYSICAL="sda_i"/>
+ <PORTMAP LOGICAL="SDA_O" PHYSICAL="sda_o"/>
+ <PORTMAP LOGICAL="SDA_T" PHYSICAL="sda_t"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE COREREVISION="5" FULLNAME="/endeavour_axi_contro_5" HWVERSION="1.0" INSTANCE="endeavour_axi_contro_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="endeavour_axi_controller" VLNV="lbl.gov:endeavour:endeavour_axi_controller:1.0">
+ <DOCUMENTS/>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE="register"/>
+ </ADDRESSBLOCKS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_S00_AXI_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_S00_AXI_ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="Component_Name" VALUE="TopLevel_endeavour_axi_contro_5_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_S00_AXI_BASEADDR" VALUE="0x43C00000"/>
+ <PARAMETER NAME="C_S00_AXI_HIGHADDR" VALUE="0x43C0FFFF"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="O" NAME="busy" SIGIS="undef"/>
+ <PORT DIR="O" NAME="datavalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="error" SIGIS="undef"/>
+ <PORT DIR="O" NAME="CMD_IN_P" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_CMD_IN_P">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="CMD_IN_P_5"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="CMD_IN_N" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_CMD_IN_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="CMD_IN_N_5"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="CMD_OUT_P" SIGIS="undef" SIGNAME="External_Ports_CMD_OUT_P_5">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="CMD_OUT_P_5"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="CMD_OUT_N" SIGIS="undef" SIGNAME="External_Ports_CMD_OUT_N_5">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="CMD_OUT_N_5"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="cmd_in" SIGIS="undef"/>
+ <PORT DIR="O" NAME="cmd_out" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="5" NAME="s00_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="s00_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_awvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s00_axi_awready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s00_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s00_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_wvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s00_axi_wready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s00_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s00_axi_bvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_bready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="s00_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="s00_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_arvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s00_axi_arready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s00_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s00_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s00_axi_rvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_rready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s00_axi_aclk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s00_axi_aresetn" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M01_AXI" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="WIZ_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="WIZ_NUM_REG" VALUE="8"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="TopLevel_processing_system7_0_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="s00_axi_awaddr"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="s00_axi_awprot"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="s00_axi_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="s00_axi_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="s00_axi_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="s00_axi_wstrb"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="s00_axi_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="s00_axi_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="s00_axi_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="s00_axi_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="s00_axi_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="s00_axi_araddr"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="s00_axi_arprot"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="s00_axi_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="s00_axi_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="s00_axi_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="s00_axi_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="s00_axi_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="s00_axi_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE CONFIGURABLE="TRUE" COREREVISION="6" FULLNAME="/processing_system7_0" HWVERSION="5.5" INSTANCE="processing_system7_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="processing_system7" VLNV="xilinx.com:ip:processing_system7:5.5">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=processing_system7;v=v5_3;d=pg082-processing-system7.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_EN_EMIO_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_ENET0" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_ENET1" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
+ <PARAMETER NAME="C_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+ <PARAMETER NAME="C_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+ <PARAMETER NAME="USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+ <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="C_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+ <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+ <PARAMETER NAME="C_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+ <PARAMETER NAME="C_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="C_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="C_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="C_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="C_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+ <PARAMETER NAME="C_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+ <PARAMETER NAME="C_IRQ_F2P_MODE" VALUE="DIRECT"/>
+ <PARAMETER NAME="C_DQ_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_DQS_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_DM_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_MIO_PRIMITIVE" VALUE="54"/>
+ <PARAMETER NAME="C_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+ <PARAMETER NAME="C_USE_AXI_NONSECURE" VALUE="0"/>
+ <PARAMETER NAME="C_USE_M_AXI_GP0" VALUE="1"/>
+ <PARAMETER NAME="C_USE_M_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_GP0" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP0" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP2" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="0"/>
+ <PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/>
+ <PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="TRUE"/>
+ <PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_PACKAGE_NAME" VALUE="clg400"/>
+ <PARAMETER NAME="C_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="C_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_DDR_RAM_BASEADDR" VALUE="0x00100000"/>
+ <PARAMETER NAME="PCW_DDR_RAM_HIGHADDR" VALUE="0x3FFFFFFF"/>
+ <PARAMETER NAME="PCW_UART0_BASEADDR" VALUE="0xE0000000"/>
+ <PARAMETER NAME="PCW_UART0_HIGHADDR" VALUE="0xE0000FFF"/>
+ <PARAMETER NAME="PCW_UART1_BASEADDR" VALUE="0xE0001000"/>
+ <PARAMETER NAME="PCW_UART1_HIGHADDR" VALUE="0xE0001FFF"/>
+ <PARAMETER NAME="PCW_I2C0_BASEADDR" VALUE="0xE0004000"/>
+ <PARAMETER NAME="PCW_I2C0_HIGHADDR" VALUE="0xE0004FFF"/>
+ <PARAMETER NAME="PCW_I2C1_BASEADDR" VALUE="0xE0005000"/>
+ <PARAMETER NAME="PCW_I2C1_HIGHADDR" VALUE="0xE0005FFF"/>
+ <PARAMETER NAME="PCW_SPI0_BASEADDR" VALUE="0xE0006000"/>
+ <PARAMETER NAME="PCW_SPI0_HIGHADDR" VALUE="0xE0006FFF"/>
+ <PARAMETER NAME="PCW_SPI1_BASEADDR" VALUE="0xE0007000"/>
+ <PARAMETER NAME="PCW_SPI1_HIGHADDR" VALUE="0xE0007FFF"/>
+ <PARAMETER NAME="PCW_CAN0_BASEADDR" VALUE="0xE0008000"/>
+ <PARAMETER NAME="PCW_CAN0_HIGHADDR" VALUE="0xE0008FFF"/>
+ <PARAMETER NAME="PCW_CAN1_BASEADDR" VALUE="0xE0009000"/>
+ <PARAMETER NAME="PCW_CAN1_HIGHADDR" VALUE="0xE0009FFF"/>
+ <PARAMETER NAME="PCW_GPIO_BASEADDR" VALUE="0xE000A000"/>
+ <PARAMETER NAME="PCW_GPIO_HIGHADDR" VALUE="0xE000AFFF"/>
+ <PARAMETER NAME="PCW_ENET0_BASEADDR" VALUE="0xE000B000"/>
+ <PARAMETER NAME="PCW_ENET0_HIGHADDR" VALUE="0xE000BFFF"/>
+ <PARAMETER NAME="PCW_ENET1_BASEADDR" VALUE="0xE000C000"/>
+ <PARAMETER NAME="PCW_ENET1_HIGHADDR" VALUE="0xE000CFFF"/>
+ <PARAMETER NAME="PCW_SDIO0_BASEADDR" VALUE="0xE0100000"/>
+ <PARAMETER NAME="PCW_SDIO0_HIGHADDR" VALUE="0xE0100FFF"/>
+ <PARAMETER NAME="PCW_SDIO1_BASEADDR" VALUE="0xE0101000"/>
+ <PARAMETER NAME="PCW_SDIO1_HIGHADDR" VALUE="0xE0101FFF"/>
+ <PARAMETER NAME="PCW_USB0_BASEADDR" VALUE="0xE0102000"/>
+ <PARAMETER NAME="PCW_USB0_HIGHADDR" VALUE="0xE0102fff"/>
+ <PARAMETER NAME="PCW_USB1_BASEADDR" VALUE="0xE0103000"/>
+ <PARAMETER NAME="PCW_USB1_HIGHADDR" VALUE="0xE0103fff"/>
+ <PARAMETER NAME="PCW_TTC0_BASEADDR" VALUE="0xE0104000"/>
+ <PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/>
+ <PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/>
+ <PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/>
+ <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.073"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="-0.072"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.024"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.023"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.294"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.298"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.338"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.334"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="50.05"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="50.43"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="50.10"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="50.01"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="49.59"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="51.74"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="50.32"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="48.55"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="54.14"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="54.14"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="39.7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="39.7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.001"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.037"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.074"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.098"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY0" VALUE="0.416"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY1" VALUE="0.408"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY2" VALUE="0.369"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.370"/>
+ <PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/>
+ <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333"/>
+ <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="25"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+ <PARAMETER NAME="PCW_I2C_PERIPHERAL_FREQMHZ" VALUE="25"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200"/>
+ <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="33.333333"/>
+ <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="666.666687"/>
+ <PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="533.333374"/>
+ <PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.158730"/>
+ <PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="125.000000"/>
+ <PARAMETER NAME="PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_ACT_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" VALUE="25.000000"/>
+ <PARAMETER NAME="PCW_ACT_UART_PERIPHERAL_FREQMHZ" VALUE="50.000000"/>
+ <PARAMETER NAME="PCW_ACT_SPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_CAN_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+ <PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+ <PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_CLK0_FREQ" VALUE="100000000"/>
+ <PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/>
+ <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2"/>
+ <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="40"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="20"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40"/>
+ <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30"/>
+ <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32"/>
+ <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333"/>
+ <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000"/>
+ <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="1"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_VALID" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CAN0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CAN1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_ENET0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PTP_ENET0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PTP_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_GPIO" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_I2C0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_I2C1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SPI0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SPI1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TTC0" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TTC1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WDT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_GP0_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_GP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_USE_DMA0" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA2" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA3" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="PCW_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+ <PARAMETER NAME="PCW_USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+ <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_USE_DEBUG" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_CR_FABRIC" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_AXI_FABRIC_IDLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DDR_BYPASS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_FABRIC_INTERRUPT" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_PROC_EVENT_BUS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_EXPANDED_IOP" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_HIGH_OCM" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_PS_SLCR_REGISTERS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_EXPANDED_PS_SLCR_REGISTERS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_CORESIGHT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SRAM_INT" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_GP0_NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP0_NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP1_NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP1_NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200"/>
+ <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200"/>
+ <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+ <PARAMETER NAME="PCW_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_DDR" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_SMC" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_QSPI" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_CAN0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_ENET0" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_GPIO" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_I2C0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SDIO0" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SPI0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SPI1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_UART1" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_MODEM_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_MODEM_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_TTC0" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_TTC1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_WDT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_USB0" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_USB1" VALUE="0"/>
+ <PARAMETER NAME="PCW_DQ_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/>
+ <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG0_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC_ABORT_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC2_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC3_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC4_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC5_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC6_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC7_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SMC_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_QSPI_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CTI_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_GPIO_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_USB0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_ENET0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SDIO0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_I2C0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SPI0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_UART0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CAN0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_USB1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_ENET1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SDIO1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_I2C1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SPI1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_UART1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CAN1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_IRQ_F2P_INTR" VALUE="1"/>
+ <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT"/>
+ <PARAMETER NAME="PCW_CORE0_FIQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE0_IRQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE1_FIQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE1_IRQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_VALUE_SILVERSION" VALUE="3"/>
+ <PARAMETER NAME="PCW_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_IMPORT_BOARD_PRESET" VALUE="None"/>
+ <PARAMETER NAME="PCW_PERIPHERAL_BOARD_PRESET" VALUE="part0"/>
+ <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)"/>
+ <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+ <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15"/>
+ <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+ <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4"/>
+ <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8"/>
+ <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27"/>
+ <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53"/>
+ <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45"/>
+ <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 46"/>
+ <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 50"/>
+ <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49"/>
+ <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO"/>
+ <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39"/>
+ <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+ <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL"/>
+ <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="in"/>
+ <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out"/>
+ <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="disabled"/>
+ <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V"/>
+ <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout"/>
+ <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow"/>
+ <PARAMETER NAME="preset" VALUE="None"/>
+ <PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/>
+ <PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#UART 1#UART 1#SD 0#GPIO#Enet 0#Enet 0"/>
+ <PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio"/>
+ <PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T0" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T1" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T2" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T3" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T4" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T5" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T6" VALUE="NA"/>
+ <PARAMETER NAME="PCW_PACKAGE_NAME" VALUE="clg400"/>
+ <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="TopLevel_processing_system7_0_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="O" NAME="TTC0_WAVE0_OUT" SIGIS="undef"/>
+ <PORT DIR="O" NAME="TTC0_WAVE1_OUT" SIGIS="undef"/>
+ <PORT DIR="O" NAME="TTC0_WAVE2_OUT" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="O" NAME="USB0_VBUS_PWRSELECT" SIGIS="undef"/>
+ <PORT DIR="I" NAME="USB0_VBUS_PWRFAULT" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M_AXI_GP0_ARVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_AWVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_BREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_RREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_WLAST" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_WVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_WID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="I" NAME="M_AXI_GP0_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_ARREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_AWREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_BVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_RLAST" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_RVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_WREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_BID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_RID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="IRQ_F2P" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_iic_0_iic2intc_irpt">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="iic2intc_irpt"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="O" NAME="FCLK_CLK0" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="slowest_sync_clk"/>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_aclk"/>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ACLK"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="ACLK"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_ACLK"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_ACLK"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_ACLK"/>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_aclk"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="FCLK_RESET0_N" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="ext_reset_in"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_mio"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CAS_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_cas_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CKE" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CKE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_cke"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_Clk_n" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_ck_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_Clk" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_ck_p"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CS_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_cs_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_DRSTB" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_reset_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_ODT" SIGIS="undef" SIGNAME="processing_system7_0_DDR_ODT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_odt"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_RAS_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_RAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_ras_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_WEB" SIGIS="undef" SIGNAME="processing_system7_0_DDR_WEB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_we_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="2" NAME="DDR_BankAddr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_BankAddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_ba"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="14" NAME="DDR_Addr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Addr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_addr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_VRN" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_ddr_vrn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_VRP" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_ddr_vrp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DM" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DM">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_dm"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="31" NAME="DDR_DQ" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQ">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_dq"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DQS_n" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_dqs_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DQS" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="DDR_dqs_p"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_SRSTB" SIGIS="undef" SIGNAME="processing_system7_0_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_ps_srstb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_CLK" SIGIS="undef" SIGNAME="processing_system7_0_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_ps_clk"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_PORB" SIGIS="undef" SIGNAME="processing_system7_0_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="TopLevel_imp" PORT="FIXED_IO_ps_porb"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR" VLNV="xilinx.com:interface:ddrx:1.0">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+ <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+ <PARAMETER NAME="MEMORY_PART"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="SLOT" VALUE="Single"/>
+ <PARAMETER NAME="CUSTOM_PARTS"/>
+ <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+ <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+ <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+ <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+ <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_CAS_n"/>
+ <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_CKE"/>
+ <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_Clk_n"/>
+ <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_Clk"/>
+ <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_CS_n"/>
+ <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_DRSTB"/>
+ <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_ODT"/>
+ <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_RAS_n"/>
+ <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_WEB"/>
+ <PORTMAP LOGICAL="BA" PHYSICAL="DDR_BankAddr"/>
+ <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_Addr"/>
+ <PORTMAP LOGICAL="DM" PHYSICAL="DDR_DM"/>
+ <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_DQ"/>
+ <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_DQS_n"/>
+ <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_DQS"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:fixedio:1.0">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="MIO" PHYSICAL="MIO"/>
+ <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="DDR_VRN"/>
+ <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="DDR_VRP"/>
+ <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="PS_SRSTB"/>
+ <PORTMAP LOGICAL="PS_CLK" PHYSICAL="PS_CLK"/>
+ <PORTMAP LOGICAL="PS_PORB" PHYSICAL="PS_PORB"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="__NOC__" NAME="USBIND_0" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:usbctrl:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="PORT_INDCTL" PHYSICAL="USB0_PORT_INDCTL"/>
+ <PORTMAP LOGICAL="VBUS_PWRSELECT" PHYSICAL="USB0_VBUS_PWRSELECT"/>
+ <PORTMAP LOGICAL="VBUS_PWRFAULT" PHYSICAL="USB0_VBUS_PWRFAULT"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="processing_system7_0_M_AXI_GP0" DATAWIDTH="32" NAME="M_AXI_GP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="TopLevel_processing_system7_0_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_GP0_ARVALID"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_GP0_AWVALID"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_GP0_BREADY"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_GP0_RREADY"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_GP0_WLAST"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_GP0_WVALID"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="M_AXI_GP0_ARID"/>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="M_AXI_GP0_AWID"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="M_AXI_GP0_WID"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_GP0_ARBURST"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_GP0_ARLOCK"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_GP0_ARSIZE"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_GP0_AWBURST"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_GP0_AWLOCK"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_GP0_AWSIZE"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_GP0_ARPROT"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_GP0_AWPROT"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_GP0_ARADDR"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_GP0_AWADDR"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_GP0_WDATA"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_GP0_ARCACHE"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_GP0_ARLEN"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_GP0_ARQOS"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_GP0_AWCACHE"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_GP0_AWLEN"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_GP0_AWQOS"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_GP0_WSTRB"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_GP0_ARREADY"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_GP0_AWREADY"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_GP0_BVALID"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_GP0_RLAST"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_GP0_RVALID"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_GP0_WREADY"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="M_AXI_GP0_BID"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="M_AXI_GP0_RID"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_GP0_BRESP"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_GP0_RRESP"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_GP0_RDATA"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ <MEMORYMAP>
+ <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41600000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4160FFFF" INSTANCE="axi_iic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+ <MEMRANGE ADDRESSBLOCK="S00_AXI_reg" BASENAME="C_S00_AXI_BASEADDR" BASEVALUE="0x43C00000" HIGHNAME="C_S00_AXI_HIGHADDR" HIGHVALUE="0x43C0FFFF" INSTANCE="endeavour_axi_contro_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S00_AXI"/>
+ </MEMORYMAP>
+ <PERIPHERALS>
+ <PERIPHERAL INSTANCE="axi_iic_0"/>
+ <PERIPHERAL INSTANCE="endeavour_axi_contro_5"/>
+ </PERIPHERALS>
+ </MODULE>
+ <MODULE COREREVISION="20" FULLNAME="/ps7_0_axi_periph" HWVERSION="2.1" INSTANCE="ps7_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="NUM_SI" VALUE="1"/>
+ <PARAMETER NAME="NUM_MI" VALUE="2"/>
+ <PARAMETER NAME="STRATEGY" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+ <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+ <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+ <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
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+ <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
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+ <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+ <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="TopLevel_ps7_0_axi_periph_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_iic_0_s_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="2" NAME="M01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="2" NAME="M01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef" SIGNAME="endeavour_axi_contro_5_s00_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WID"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="processing_system7_0_M_AXI_GP0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="S00_AXI_wid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M01_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M01_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M01_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M01_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M01_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREGION" PHYSICAL="M01_AXI_awregion"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M01_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M01_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M01_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M01_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M01_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M01_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M01_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREGION" PHYSICAL="M01_AXI_arregion"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M01_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M01_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE COREREVISION="13" FULLNAME="/rst_ps7_0_100M" HWVERSION="5.0" INSTANCE="rst_ps7_0_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
+ <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
+ <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+ <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+ <PARAMETER NAME="Component_Name" VALUE="TopLevel_rst_ps7_0_100M_0"/>
+ <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+ <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ext_reset_in" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET0_N"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="aux_reset_in" SIGIS="rst"/>
+ <PORT DIR="I" NAME="mb_debug_sys_rst" SIGIS="rst"/>
+ <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
+ <PORT DIR="O" NAME="mb_reset" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="peripheral_reset" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_iic_0" PORT="s_axi_aresetn"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_ARESETN"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_ARESETN"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="ARESETN"/>
+ <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M01_ARESETN"/>
+ <CONNECTION INSTANCE="endeavour_axi_contro_5" PORT="s00_axi_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES/>
+ </MODULE>
+ </MODULES>
+
+</EDKSYSTEM>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel_bd.tcl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel_bd.tcl
new file mode 100644
index 0000000..469902d
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/hw_handoff/TopLevel_bd.tcl
@@ -0,0 +1,676 @@
+
+################################################################
+# This is a generated script based on design: TopLevel
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2019.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source TopLevel_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xc7z020clg400-1
+ set_property BOARD_PART em.avnet.com:microzed_7020:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name TopLevel
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+ return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+ set iic_rtl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_rtl ]
+
+
+ # Create ports
+ set CMD_IN_N_5 [ create_bd_port -dir O CMD_IN_N_5 ]
+ set CMD_IN_P_5 [ create_bd_port -dir O CMD_IN_P_5 ]
+ set CMD_OUT_N_5 [ create_bd_port -dir I CMD_OUT_N_5 ]
+ set CMD_OUT_P_5 [ create_bd_port -dir I CMD_OUT_P_5 ]
+
+ # Create instance: axi_iic_0, and set properties
+ set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
+
+ # Create instance: endeavour_axi_contro_5, and set properties
+ set endeavour_axi_contro_5 [ create_bd_cell -type ip -vlnv lbl.gov:endeavour:endeavour_axi_controller:1.0 endeavour_axi_contro_5 ]
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {100000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
+ CONFIG.PCW_DM_WIDTH {4} \
+ CONFIG.PCW_DQS_WIDTH {4} \
+ CONFIG.PCW_DQ_WIDTH {32} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+ CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {0} \
+ CONFIG.PCW_EN_CLK0_PORT {1} \
+ CONFIG.PCW_EN_CLK1_PORT {0} \
+ CONFIG.PCW_EN_CLK2_PORT {0} \
+ CONFIG.PCW_EN_CLK3_PORT {0} \
+ CONFIG.PCW_EN_DDR {1} \
+ CONFIG.PCW_EN_EMIO_TTC0 {1} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_RST0_PORT {1} \
+ CONFIG.PCW_EN_RST1_PORT {0} \
+ CONFIG.PCW_EN_RST2_PORT {0} \
+ CONFIG.PCW_EN_RST3_PORT {0} \
+ CONFIG.PCW_EN_SDIO0 {1} \
+ CONFIG.PCW_EN_TTC0 {1} \
+ CONFIG.PCW_EN_UART1 {1} \
+ CONFIG.PCW_EN_USB0 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+ CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+ CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+ CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {33.333333} \
+ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_I2C_RESET_ENABLE {0} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
+ CONFIG.PCW_MIO_0_DIRECTION {inout} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {disabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_DIRECTION {inout} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {disabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_DIRECTION {inout} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {disabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_DIRECTION {inout} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {disabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_DIRECTION {inout} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {disabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_DIRECTION {inout} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {disabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_DIRECTION {inout} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {disabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_DIRECTION {out} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_16_PULLUP {disabled} \
+ CONFIG.PCW_MIO_16_SLEW {slow} \
+ CONFIG.PCW_MIO_17_DIRECTION {out} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_17_PULLUP {disabled} \
+ CONFIG.PCW_MIO_17_SLEW {slow} \
+ CONFIG.PCW_MIO_18_DIRECTION {out} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_18_PULLUP {disabled} \
+ CONFIG.PCW_MIO_18_SLEW {slow} \
+ CONFIG.PCW_MIO_19_DIRECTION {out} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_19_PULLUP {disabled} \
+ CONFIG.PCW_MIO_19_SLEW {slow} \
+ CONFIG.PCW_MIO_1_DIRECTION {out} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {disabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_DIRECTION {out} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_20_PULLUP {disabled} \
+ CONFIG.PCW_MIO_20_SLEW {slow} \
+ CONFIG.PCW_MIO_21_DIRECTION {out} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_21_PULLUP {disabled} \
+ CONFIG.PCW_MIO_21_SLEW {slow} \
+ CONFIG.PCW_MIO_22_DIRECTION {in} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_22_PULLUP {disabled} \
+ CONFIG.PCW_MIO_22_SLEW {slow} \
+ CONFIG.PCW_MIO_23_DIRECTION {in} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_23_PULLUP {disabled} \
+ CONFIG.PCW_MIO_23_SLEW {slow} \
+ CONFIG.PCW_MIO_24_DIRECTION {in} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_24_PULLUP {disabled} \
+ CONFIG.PCW_MIO_24_SLEW {slow} \
+ CONFIG.PCW_MIO_25_DIRECTION {in} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_25_PULLUP {disabled} \
+ CONFIG.PCW_MIO_25_SLEW {slow} \
+ CONFIG.PCW_MIO_26_DIRECTION {in} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_26_PULLUP {disabled} \
+ CONFIG.PCW_MIO_26_SLEW {slow} \
+ CONFIG.PCW_MIO_27_DIRECTION {in} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_27_PULLUP {disabled} \
+ CONFIG.PCW_MIO_27_SLEW {slow} \
+ CONFIG.PCW_MIO_28_DIRECTION {inout} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_28_PULLUP {disabled} \
+ CONFIG.PCW_MIO_28_SLEW {slow} \
+ CONFIG.PCW_MIO_29_DIRECTION {in} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_29_PULLUP {disabled} \
+ CONFIG.PCW_MIO_29_SLEW {slow} \
+ CONFIG.PCW_MIO_2_DIRECTION {inout} \
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_PULLUP {disabled} \
+ CONFIG.PCW_MIO_2_SLEW {slow} \
+ CONFIG.PCW_MIO_30_DIRECTION {out} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_30_PULLUP {disabled} \
+ CONFIG.PCW_MIO_30_SLEW {slow} \
+ CONFIG.PCW_MIO_31_DIRECTION {in} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_31_PULLUP {disabled} \
+ CONFIG.PCW_MIO_31_SLEW {slow} \
+ CONFIG.PCW_MIO_32_DIRECTION {inout} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_32_PULLUP {disabled} \
+ CONFIG.PCW_MIO_32_SLEW {slow} \
+ CONFIG.PCW_MIO_33_DIRECTION {inout} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_33_PULLUP {disabled} \
+ CONFIG.PCW_MIO_33_SLEW {slow} \
+ CONFIG.PCW_MIO_34_DIRECTION {inout} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_34_PULLUP {disabled} \
+ CONFIG.PCW_MIO_34_SLEW {slow} \
+ CONFIG.PCW_MIO_35_DIRECTION {inout} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_35_PULLUP {disabled} \
+ CONFIG.PCW_MIO_35_SLEW {slow} \
+ CONFIG.PCW_MIO_36_DIRECTION {in} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_36_PULLUP {disabled} \
+ CONFIG.PCW_MIO_36_SLEW {slow} \
+ CONFIG.PCW_MIO_37_DIRECTION {inout} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_37_PULLUP {disabled} \
+ CONFIG.PCW_MIO_37_SLEW {slow} \
+ CONFIG.PCW_MIO_38_DIRECTION {inout} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_38_PULLUP {disabled} \
+ CONFIG.PCW_MIO_38_SLEW {slow} \
+ CONFIG.PCW_MIO_39_DIRECTION {inout} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_39_PULLUP {disabled} \
+ CONFIG.PCW_MIO_39_SLEW {slow} \
+ CONFIG.PCW_MIO_3_DIRECTION {inout} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_PULLUP {disabled} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_DIRECTION {inout} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_40_PULLUP {disabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_DIRECTION {inout} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_41_PULLUP {disabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_DIRECTION {inout} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_42_PULLUP {disabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_DIRECTION {inout} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_43_PULLUP {disabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_DIRECTION {inout} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_44_PULLUP {disabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_DIRECTION {inout} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_45_PULLUP {disabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_DIRECTION {in} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_46_PULLUP {disabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_DIRECTION {inout} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_47_PULLUP {disabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_DIRECTION {out} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_48_PULLUP {disabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_DIRECTION {in} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_49_PULLUP {disabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_DIRECTION {inout} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_PULLUP {disabled} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_DIRECTION {in} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_50_PULLUP {disabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_DIRECTION {inout} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_51_PULLUP {disabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_DIRECTION {out} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_52_PULLUP {disabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_DIRECTION {inout} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_53_PULLUP {disabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_DIRECTION {inout} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_PULLUP {disabled} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_DIRECTION {out} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_PULLUP {disabled} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_DIRECTION {out} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_PULLUP {disabled} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_DIRECTION {out} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_PULLUP {disabled} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_DIRECTION {inout} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {disabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_PRIMITIVE {54} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#UART 1#UART 1#SD 0#GPIO#Enet 0#Enet 0} \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio} \
+ CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+ CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+ CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.416} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.408} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.369} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.370} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.001} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.037} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.074} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.098} \
+ CONFIG.PCW_PACKAGE_NAME {clg400} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \
+ CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
+ CONFIG.PCW_SD0_GRP_WP_IO {MIO 50} \
+ CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {40} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+ CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
+ CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+ CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \
+ CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.294} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.298} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.338} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.334} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CL {7} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {54.14} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {54.14} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {39.7} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {39.7} \
+ CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+ CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+ CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {50.05} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {50.43} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {50.10} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {50.01} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.072} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.024} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.023} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {49.59} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {51.74} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {50.32} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {48.55} \
+ CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+ CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
+ CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+ CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+ CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+ CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+ CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_USB0_RESET_ENABLE {0} \
+ CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+ CONFIG.PCW_USB1_RESET_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {0} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_USE_M_AXI_GP0 {1} \
+ CONFIG.PCW_USE_M_AXI_GP1 {0} \
+ ] $processing_system7_0
+
+ # Create instance: ps7_0_axi_periph, and set properties
+ set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+ # Create instance: rst_ps7_0_100M, and set properties
+ set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports iic_rtl] [get_bd_intf_pins axi_iic_0/IIC]
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins endeavour_axi_contro_5/S00_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+
+ # Create port connections
+ connect_bd_net -net CMD_OUT_N_0_1 [get_bd_ports CMD_OUT_N_5] [get_bd_pins endeavour_axi_contro_5/CMD_OUT_N]
+ connect_bd_net -net CMD_OUT_P_0_1 [get_bd_ports CMD_OUT_P_5] [get_bd_pins endeavour_axi_contro_5/CMD_OUT_P]
+ connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins processing_system7_0/IRQ_F2P]
+ connect_bd_net -net endeavour_axi_contro_5_CMD_IN_N [get_bd_ports CMD_IN_N_5] [get_bd_pins endeavour_axi_contro_5/CMD_IN_N]
+ connect_bd_net -net endeavour_axi_contro_5_CMD_IN_P [get_bd_ports CMD_IN_P_5] [get_bd_pins endeavour_axi_contro_5/CMD_IN_P]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins endeavour_axi_contro_5/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
+ connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins endeavour_axi_contro_5/s00_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
+
+ # Create address segments
+ create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs endeavour_axi_contro_5/S00_AXI/S00_AXI_reg] SEG_endeavour_axi_contro_0_S00_AXI_reg
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.dcp b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.dcp
new file mode 100755
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literal 0
HcmV?d00001
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xci b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xci
similarity index 97%
rename from pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xci
rename to pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xci
index b81433e..b291317 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xci
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xci
@@ -6,12 +6,12 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
- <spirit:instanceName>TopLevel_auto_pc_2</spirit:instanceName>
+ <spirit:instanceName>TopLevel_auto_pc_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
@@ -19,7 +19,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
@@ -53,7 +53,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
@@ -100,7 +100,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">TopLevel_auto_pc_2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">TopLevel_auto_pc_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
@@ -147,11 +147,11 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xml
similarity index 82%
rename from pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xml
rename to pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xml
index 07ebd00..a43c54a 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_2/TopLevel_auto_pc_2.xml
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0.xml
@@ -2,7 +2,7 @@
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
- <spirit:name>TopLevel_auto_pc_2</spirit:name>
+ <spirit:name>TopLevel_auto_pc_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -601,7 +601,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1251,7 +1251,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1339,7 +1339,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1423,6 +1423,157 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>axi_protocol_converter_v2_1_19_axi_protocol_converter</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:17 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:dec6db2a</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_synthesisconstraints</spirit:name>
+ <spirit:displayName>Synthesis Constraints</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:17 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:dec6db2a</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+ <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>TopLevel_auto_pc_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:17 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:dec6db2a</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>axi_protocol_converter_v2_1_19_axi_protocol_converter</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 00:12:06 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:951ca8a3</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
+ <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>TopLevel_auto_pc_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:17 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:951ca8a3</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_externalfiles</spirit:name>
+ <spirit:displayName>External Files</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:18 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:dec6db2a</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>aclk</spirit:name>
@@ -1431,7 +1582,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1443,7 +1595,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1459,7 +1612,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1485,7 +1639,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1511,7 +1666,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1537,7 +1693,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1563,7 +1720,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1589,7 +1747,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1615,7 +1774,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1641,7 +1801,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1667,7 +1828,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1693,7 +1855,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1719,7 +1882,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1741,7 +1905,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1763,7 +1928,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1786,7 +1952,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1812,7 +1979,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1838,7 +2006,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1860,7 +2029,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1886,7 +2056,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1908,7 +2079,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1930,7 +2102,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1953,7 +2126,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1976,7 +2150,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1999,7 +2174,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2018,7 +2194,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2037,7 +2214,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2063,7 +2241,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2089,7 +2268,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2115,7 +2295,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2141,7 +2322,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2167,7 +2349,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2193,7 +2376,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2219,7 +2403,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2245,7 +2430,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2271,7 +2457,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2297,7 +2484,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2323,7 +2511,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2345,7 +2534,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2367,7 +2557,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2390,7 +2581,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2413,7 +2605,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2436,7 +2629,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2455,7 +2649,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2478,7 +2673,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2497,7 +2693,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2516,7 +2713,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2542,7 +2740,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2565,7 +2764,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2588,7 +2788,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2611,7 +2812,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2634,7 +2836,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2657,7 +2860,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2680,7 +2884,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2703,7 +2908,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2726,7 +2932,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2749,7 +2956,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:wire>
@@ -2772,7 +2980,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -2791,7 +3000,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2810,7 +3020,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2836,7 +3047,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -2859,7 +3071,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2882,7 +3095,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:wire>
@@ -2901,7 +3115,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2924,7 +3139,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2943,7 +3159,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2962,7 +3179,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -2988,7 +3206,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -3014,7 +3233,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -3040,7 +3260,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -3062,7 +3283,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -3084,7 +3306,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3107,7 +3330,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3130,7 +3354,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3153,7 +3378,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3176,7 +3402,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3199,7 +3426,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3222,7 +3450,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -3245,7 +3474,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3268,7 +3498,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3291,7 +3522,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3314,7 +3546,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3337,7 +3570,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3356,7 +3590,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3375,7 +3610,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3401,7 +3637,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3427,7 +3664,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3453,7 +3691,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3475,7 +3714,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3501,7 +3741,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3523,7 +3764,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3545,7 +3787,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3654,6 +3897,290 @@
<spirit:enumeration spirit:text="Unprotected: Master must be well-behaved">0</spirit:enumeration>
</spirit:choice>
</spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="generic_baseblocks" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="31e101ba">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/c001/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>blk_mem_gen_v8_4_3</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="blk_mem_gen" xilinx:version="8.4" xilinx:isGenerated="true" xilinx:checksum="0137cb81">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/1f5a/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>fifo_generator_v13_2_4</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="fifo_generator" xilinx:version="13.2" xilinx:isGenerated="true" xilinx:checksum="4cf1d7db">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/5b9c/hdl/axi_data_fifo_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>axi_data_fifo_v2_1_18</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_data_fifo" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="9de199f1">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="5a88adbb">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>axi_register_slice_v2_1_19</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_register_slice" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="ae6d93d3">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>axi_protocol_converter_v2_1_19</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>synth/TopLevel_auto_pc_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="generic_baseblocks" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="31e101ba">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/1f5a/simulation/fifo_generator_vlog_beh.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>fifo_generator_v13_2_4</spirit:logicalName>
+ <spirit:exportedName>fifo_generator_vlog_beh</spirit:exportedName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>fifo_generator_v13_2_4</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>fifo_generator_v13_2_4</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="fifo_generator" xilinx:version="13.2" xilinx:isGenerated="true" xilinx:checksum="8622a6bf">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/5b9c/hdl/axi_data_fifo_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_data_fifo_v2_1_18</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_data_fifo" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="36baddbb">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="5a88adbb">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_register_slice_v2_1_19</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_register_slice" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="ae6d93d3">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_protocol_converter_v2_1_19</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>sim/TopLevel_auto_pc_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_auto_pc_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
<spirit:description>The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3.</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -3718,7 +4245,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">TopLevel_auto_pc_2</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">TopLevel_auto_pc_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
@@ -3743,11 +4270,11 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_ooc.xdc b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_ooc.xdc
new file mode 100644
index 0000000..f9a2d6c
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_ooc.xdc
@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2019 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name aclk [get_ports aclk]
+
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.v
new file mode 100644
index 0000000..90cf337
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.v
@@ -0,0 +1,12751 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Mon Oct 14 17:17:36 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode funcsim -rename_top TopLevel_auto_pc_0 -prefix
+// TopLevel_auto_pc_0_ TopLevel_auto_pc_0_sim_netlist.v
+// Design : TopLevel_auto_pc_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "TopLevel_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1" *)
+(* NotValidForBitStream *)
+module TopLevel_auto_pc_0
+ (aclk,
+ aresetn,
+ s_axi_awid,
+ s_axi_awaddr,
+ s_axi_awlen,
+ s_axi_awsize,
+ s_axi_awburst,
+ s_axi_awlock,
+ s_axi_awcache,
+ s_axi_awprot,
+ s_axi_awqos,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wid,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wlast,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bid,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_arid,
+ s_axi_araddr,
+ s_axi_arlen,
+ s_axi_arsize,
+ s_axi_arburst,
+ s_axi_arlock,
+ s_axi_arcache,
+ s_axi_arprot,
+ s_axi_arqos,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rid,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rlast,
+ s_axi_rvalid,
+ s_axi_rready,
+ m_axi_awaddr,
+ m_axi_awprot,
+ m_axi_awvalid,
+ m_axi_awready,
+ m_axi_wdata,
+ m_axi_wstrb,
+ m_axi_wvalid,
+ m_axi_wready,
+ m_axi_bresp,
+ m_axi_bvalid,
+ m_axi_bready,
+ m_axi_araddr,
+ m_axi_arprot,
+ m_axi_arvalid,
+ m_axi_arready,
+ m_axi_rdata,
+ m_axi_rresp,
+ m_axi_rvalid,
+ m_axi_rready);
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
+
+ wire aclk;
+ wire aresetn;
+ wire [31:0]m_axi_araddr;
+ wire [2:0]m_axi_arprot;
+ wire m_axi_arready;
+ wire m_axi_arvalid;
+ wire [31:0]m_axi_awaddr;
+ wire [2:0]m_axi_awprot;
+ wire m_axi_awready;
+ wire m_axi_awvalid;
+ wire m_axi_bready;
+ wire [1:0]m_axi_bresp;
+ wire m_axi_bvalid;
+ wire [31:0]m_axi_rdata;
+ wire m_axi_rready;
+ wire [1:0]m_axi_rresp;
+ wire m_axi_rvalid;
+ wire [31:0]m_axi_wdata;
+ wire m_axi_wready;
+ wire [3:0]m_axi_wstrb;
+ wire m_axi_wvalid;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [3:0]s_axi_arcache;
+ wire [11:0]s_axi_arid;
+ wire [3:0]s_axi_arlen;
+ wire [1:0]s_axi_arlock;
+ wire [2:0]s_axi_arprot;
+ wire [3:0]s_axi_arqos;
+ wire s_axi_arready;
+ wire [2:0]s_axi_arsize;
+ wire s_axi_arvalid;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [3:0]s_axi_awcache;
+ wire [11:0]s_axi_awid;
+ wire [3:0]s_axi_awlen;
+ wire [1:0]s_axi_awlock;
+ wire [2:0]s_axi_awprot;
+ wire [3:0]s_axi_awqos;
+ wire s_axi_awready;
+ wire [2:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire [11:0]s_axi_bid;
+ wire s_axi_bready;
+ wire [1:0]s_axi_bresp;
+ wire s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire [11:0]s_axi_rid;
+ wire s_axi_rlast;
+ wire s_axi_rready;
+ wire [1:0]s_axi_rresp;
+ wire s_axi_rvalid;
+ wire [31:0]s_axi_wdata;
+ wire [11:0]s_axi_wid;
+ wire s_axi_wlast;
+ wire s_axi_wready;
+ wire [3:0]s_axi_wstrb;
+ wire s_axi_wvalid;
+ wire NLW_inst_m_axi_wlast_UNCONNECTED;
+ wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+ wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
+ wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+ wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+ wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+ wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+ wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+ wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
+ wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+ wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+ wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+ wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+ wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
+ wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+ (* C_AXI_ADDR_WIDTH = "32" *)
+ (* C_AXI_ARUSER_WIDTH = "1" *)
+ (* C_AXI_AWUSER_WIDTH = "1" *)
+ (* C_AXI_BUSER_WIDTH = "1" *)
+ (* C_AXI_DATA_WIDTH = "32" *)
+ (* C_AXI_ID_WIDTH = "12" *)
+ (* C_AXI_RUSER_WIDTH = "1" *)
+ (* C_AXI_SUPPORTS_READ = "1" *)
+ (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
+ (* C_AXI_SUPPORTS_WRITE = "1" *)
+ (* C_AXI_WUSER_WIDTH = "1" *)
+ (* C_FAMILY = "zynq" *)
+ (* C_IGNORE_ID = "0" *)
+ (* C_M_AXI_PROTOCOL = "2" *)
+ (* C_S_AXI_PROTOCOL = "1" *)
+ (* C_TRANSLATION_MODE = "2" *)
+ (* DowngradeIPIdentifiedWarnings = "yes" *)
+ (* P_AXI3 = "1" *)
+ (* P_AXI4 = "0" *)
+ (* P_AXILITE = "2" *)
+ (* P_AXILITE_SIZE = "3'b010" *)
+ (* P_CONVERSION = "2" *)
+ (* P_DECERR = "2'b11" *)
+ (* P_INCR = "2'b01" *)
+ (* P_PROTECTION = "1" *)
+ (* P_SLVERR = "2'b10" *)
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter inst
+ (.aclk(aclk),
+ .aresetn(aresetn),
+ .m_axi_araddr(m_axi_araddr),
+ .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
+ .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
+ .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
+ .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
+ .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
+ .m_axi_arprot(m_axi_arprot),
+ .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
+ .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
+ .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_axi_awaddr(m_axi_awaddr),
+ .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
+ .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
+ .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
+ .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
+ .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
+ .m_axi_awprot(m_axi_awprot),
+ .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
+ .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
+ .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_buser(1'b0),
+ .m_axi_bvalid(m_axi_bvalid),
+ .m_axi_rdata(m_axi_rdata),
+ .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_rlast(1'b1),
+ .m_axi_rready(m_axi_rready),
+ .m_axi_rresp(m_axi_rresp),
+ .m_axi_ruser(1'b0),
+ .m_axi_rvalid(m_axi_rvalid),
+ .m_axi_wdata(m_axi_wdata),
+ .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
+ .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
+ .m_axi_wready(m_axi_wready),
+ .m_axi_wstrb(m_axi_wstrb),
+ .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
+ .m_axi_wvalid(m_axi_wvalid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arcache(s_axi_arcache),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arlock(s_axi_arlock),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arqos(s_axi_arqos),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arsize(s_axi_arsize),
+ .s_axi_aruser(1'b0),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awcache(s_axi_awcache),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awlock(s_axi_awlock),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awqos(s_axi_awqos),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awsize(s_axi_awsize),
+ .s_axi_awuser(1'b0),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bid(s_axi_bid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rid(s_axi_rid),
+ .s_axi_rlast(s_axi_rlast),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_wdata(s_axi_wdata),
+ .s_axi_wid(s_axi_wid),
+ .s_axi_wlast(s_axi_wlast),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wstrb(s_axi_wstrb),
+ .s_axi_wuser(1'b0),
+ .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
+(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
+(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
+(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
+(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
+(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
+(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
+(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
+(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter
+ (aclk,
+ aresetn,
+ s_axi_awid,
+ s_axi_awaddr,
+ s_axi_awlen,
+ s_axi_awsize,
+ s_axi_awburst,
+ s_axi_awlock,
+ s_axi_awcache,
+ s_axi_awprot,
+ s_axi_awregion,
+ s_axi_awqos,
+ s_axi_awuser,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wid,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wlast,
+ s_axi_wuser,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bid,
+ s_axi_bresp,
+ s_axi_buser,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_arid,
+ s_axi_araddr,
+ s_axi_arlen,
+ s_axi_arsize,
+ s_axi_arburst,
+ s_axi_arlock,
+ s_axi_arcache,
+ s_axi_arprot,
+ s_axi_arregion,
+ s_axi_arqos,
+ s_axi_aruser,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rid,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rlast,
+ s_axi_ruser,
+ s_axi_rvalid,
+ s_axi_rready,
+ m_axi_awid,
+ m_axi_awaddr,
+ m_axi_awlen,
+ m_axi_awsize,
+ m_axi_awburst,
+ m_axi_awlock,
+ m_axi_awcache,
+ m_axi_awprot,
+ m_axi_awregion,
+ m_axi_awqos,
+ m_axi_awuser,
+ m_axi_awvalid,
+ m_axi_awready,
+ m_axi_wid,
+ m_axi_wdata,
+ m_axi_wstrb,
+ m_axi_wlast,
+ m_axi_wuser,
+ m_axi_wvalid,
+ m_axi_wready,
+ m_axi_bid,
+ m_axi_bresp,
+ m_axi_buser,
+ m_axi_bvalid,
+ m_axi_bready,
+ m_axi_arid,
+ m_axi_araddr,
+ m_axi_arlen,
+ m_axi_arsize,
+ m_axi_arburst,
+ m_axi_arlock,
+ m_axi_arcache,
+ m_axi_arprot,
+ m_axi_arregion,
+ m_axi_arqos,
+ m_axi_aruser,
+ m_axi_arvalid,
+ m_axi_arready,
+ m_axi_rid,
+ m_axi_rdata,
+ m_axi_rresp,
+ m_axi_rlast,
+ m_axi_ruser,
+ m_axi_rvalid,
+ m_axi_rready);
+ input aclk;
+ input aresetn;
+ input [11:0]s_axi_awid;
+ input [31:0]s_axi_awaddr;
+ input [3:0]s_axi_awlen;
+ input [2:0]s_axi_awsize;
+ input [1:0]s_axi_awburst;
+ input [1:0]s_axi_awlock;
+ input [3:0]s_axi_awcache;
+ input [2:0]s_axi_awprot;
+ input [3:0]s_axi_awregion;
+ input [3:0]s_axi_awqos;
+ input [0:0]s_axi_awuser;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [11:0]s_axi_wid;
+ input [31:0]s_axi_wdata;
+ input [3:0]s_axi_wstrb;
+ input s_axi_wlast;
+ input [0:0]s_axi_wuser;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [11:0]s_axi_bid;
+ output [1:0]s_axi_bresp;
+ output [0:0]s_axi_buser;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [11:0]s_axi_arid;
+ input [31:0]s_axi_araddr;
+ input [3:0]s_axi_arlen;
+ input [2:0]s_axi_arsize;
+ input [1:0]s_axi_arburst;
+ input [1:0]s_axi_arlock;
+ input [3:0]s_axi_arcache;
+ input [2:0]s_axi_arprot;
+ input [3:0]s_axi_arregion;
+ input [3:0]s_axi_arqos;
+ input [0:0]s_axi_aruser;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [11:0]s_axi_rid;
+ output [31:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rlast;
+ output [0:0]s_axi_ruser;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ output [11:0]m_axi_awid;
+ output [31:0]m_axi_awaddr;
+ output [7:0]m_axi_awlen;
+ output [2:0]m_axi_awsize;
+ output [1:0]m_axi_awburst;
+ output [0:0]m_axi_awlock;
+ output [3:0]m_axi_awcache;
+ output [2:0]m_axi_awprot;
+ output [3:0]m_axi_awregion;
+ output [3:0]m_axi_awqos;
+ output [0:0]m_axi_awuser;
+ output m_axi_awvalid;
+ input m_axi_awready;
+ output [11:0]m_axi_wid;
+ output [31:0]m_axi_wdata;
+ output [3:0]m_axi_wstrb;
+ output m_axi_wlast;
+ output [0:0]m_axi_wuser;
+ output m_axi_wvalid;
+ input m_axi_wready;
+ input [11:0]m_axi_bid;
+ input [1:0]m_axi_bresp;
+ input [0:0]m_axi_buser;
+ input m_axi_bvalid;
+ output m_axi_bready;
+ output [11:0]m_axi_arid;
+ output [31:0]m_axi_araddr;
+ output [7:0]m_axi_arlen;
+ output [2:0]m_axi_arsize;
+ output [1:0]m_axi_arburst;
+ output [0:0]m_axi_arlock;
+ output [3:0]m_axi_arcache;
+ output [2:0]m_axi_arprot;
+ output [3:0]m_axi_arregion;
+ output [3:0]m_axi_arqos;
+ output [0:0]m_axi_aruser;
+ output m_axi_arvalid;
+ input m_axi_arready;
+ input [11:0]m_axi_rid;
+ input [31:0]m_axi_rdata;
+ input [1:0]m_axi_rresp;
+ input m_axi_rlast;
+ input [0:0]m_axi_ruser;
+ input m_axi_rvalid;
+ output m_axi_rready;
+
+ wire \<const0> ;
+ wire \<const1> ;
+ wire aclk;
+ wire aresetn;
+ wire [31:0]m_axi_araddr;
+ wire [2:0]m_axi_arprot;
+ wire m_axi_arready;
+ wire m_axi_arvalid;
+ wire [31:0]m_axi_awaddr;
+ wire [2:0]m_axi_awprot;
+ wire m_axi_awready;
+ wire m_axi_awvalid;
+ wire m_axi_bready;
+ wire [1:0]m_axi_bresp;
+ wire m_axi_bvalid;
+ wire [31:0]m_axi_rdata;
+ wire m_axi_rready;
+ wire [1:0]m_axi_rresp;
+ wire m_axi_rvalid;
+ wire m_axi_wready;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [11:0]s_axi_arid;
+ wire [3:0]s_axi_arlen;
+ wire [2:0]s_axi_arprot;
+ wire s_axi_arready;
+ wire [2:0]s_axi_arsize;
+ wire s_axi_arvalid;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [11:0]s_axi_awid;
+ wire [3:0]s_axi_awlen;
+ wire [2:0]s_axi_awprot;
+ wire s_axi_awready;
+ wire [2:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire [11:0]s_axi_bid;
+ wire s_axi_bready;
+ wire [1:0]s_axi_bresp;
+ wire s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire [11:0]s_axi_rid;
+ wire s_axi_rlast;
+ wire s_axi_rready;
+ wire [1:0]s_axi_rresp;
+ wire s_axi_rvalid;
+ wire [31:0]s_axi_wdata;
+ wire [3:0]s_axi_wstrb;
+ wire s_axi_wvalid;
+
+ assign m_axi_arburst[1] = \<const0> ;
+ assign m_axi_arburst[0] = \<const1> ;
+ assign m_axi_arcache[3] = \<const0> ;
+ assign m_axi_arcache[2] = \<const0> ;
+ assign m_axi_arcache[1] = \<const0> ;
+ assign m_axi_arcache[0] = \<const0> ;
+ assign m_axi_arid[11] = \<const0> ;
+ assign m_axi_arid[10] = \<const0> ;
+ assign m_axi_arid[9] = \<const0> ;
+ assign m_axi_arid[8] = \<const0> ;
+ assign m_axi_arid[7] = \<const0> ;
+ assign m_axi_arid[6] = \<const0> ;
+ assign m_axi_arid[5] = \<const0> ;
+ assign m_axi_arid[4] = \<const0> ;
+ assign m_axi_arid[3] = \<const0> ;
+ assign m_axi_arid[2] = \<const0> ;
+ assign m_axi_arid[1] = \<const0> ;
+ assign m_axi_arid[0] = \<const0> ;
+ assign m_axi_arlen[7] = \<const0> ;
+ assign m_axi_arlen[6] = \<const0> ;
+ assign m_axi_arlen[5] = \<const0> ;
+ assign m_axi_arlen[4] = \<const0> ;
+ assign m_axi_arlen[3] = \<const0> ;
+ assign m_axi_arlen[2] = \<const0> ;
+ assign m_axi_arlen[1] = \<const0> ;
+ assign m_axi_arlen[0] = \<const0> ;
+ assign m_axi_arlock[0] = \<const0> ;
+ assign m_axi_arqos[3] = \<const0> ;
+ assign m_axi_arqos[2] = \<const0> ;
+ assign m_axi_arqos[1] = \<const0> ;
+ assign m_axi_arqos[0] = \<const0> ;
+ assign m_axi_arregion[3] = \<const0> ;
+ assign m_axi_arregion[2] = \<const0> ;
+ assign m_axi_arregion[1] = \<const0> ;
+ assign m_axi_arregion[0] = \<const0> ;
+ assign m_axi_arsize[2] = \<const0> ;
+ assign m_axi_arsize[1] = \<const1> ;
+ assign m_axi_arsize[0] = \<const0> ;
+ assign m_axi_aruser[0] = \<const0> ;
+ assign m_axi_awburst[1] = \<const0> ;
+ assign m_axi_awburst[0] = \<const1> ;
+ assign m_axi_awcache[3] = \<const0> ;
+ assign m_axi_awcache[2] = \<const0> ;
+ assign m_axi_awcache[1] = \<const0> ;
+ assign m_axi_awcache[0] = \<const0> ;
+ assign m_axi_awid[11] = \<const0> ;
+ assign m_axi_awid[10] = \<const0> ;
+ assign m_axi_awid[9] = \<const0> ;
+ assign m_axi_awid[8] = \<const0> ;
+ assign m_axi_awid[7] = \<const0> ;
+ assign m_axi_awid[6] = \<const0> ;
+ assign m_axi_awid[5] = \<const0> ;
+ assign m_axi_awid[4] = \<const0> ;
+ assign m_axi_awid[3] = \<const0> ;
+ assign m_axi_awid[2] = \<const0> ;
+ assign m_axi_awid[1] = \<const0> ;
+ assign m_axi_awid[0] = \<const0> ;
+ assign m_axi_awlen[7] = \<const0> ;
+ assign m_axi_awlen[6] = \<const0> ;
+ assign m_axi_awlen[5] = \<const0> ;
+ assign m_axi_awlen[4] = \<const0> ;
+ assign m_axi_awlen[3] = \<const0> ;
+ assign m_axi_awlen[2] = \<const0> ;
+ assign m_axi_awlen[1] = \<const0> ;
+ assign m_axi_awlen[0] = \<const0> ;
+ assign m_axi_awlock[0] = \<const0> ;
+ assign m_axi_awqos[3] = \<const0> ;
+ assign m_axi_awqos[2] = \<const0> ;
+ assign m_axi_awqos[1] = \<const0> ;
+ assign m_axi_awqos[0] = \<const0> ;
+ assign m_axi_awregion[3] = \<const0> ;
+ assign m_axi_awregion[2] = \<const0> ;
+ assign m_axi_awregion[1] = \<const0> ;
+ assign m_axi_awregion[0] = \<const0> ;
+ assign m_axi_awsize[2] = \<const0> ;
+ assign m_axi_awsize[1] = \<const1> ;
+ assign m_axi_awsize[0] = \<const0> ;
+ assign m_axi_awuser[0] = \<const0> ;
+ assign m_axi_wdata[31:0] = s_axi_wdata;
+ assign m_axi_wid[11] = \<const0> ;
+ assign m_axi_wid[10] = \<const0> ;
+ assign m_axi_wid[9] = \<const0> ;
+ assign m_axi_wid[8] = \<const0> ;
+ assign m_axi_wid[7] = \<const0> ;
+ assign m_axi_wid[6] = \<const0> ;
+ assign m_axi_wid[5] = \<const0> ;
+ assign m_axi_wid[4] = \<const0> ;
+ assign m_axi_wid[3] = \<const0> ;
+ assign m_axi_wid[2] = \<const0> ;
+ assign m_axi_wid[1] = \<const0> ;
+ assign m_axi_wid[0] = \<const0> ;
+ assign m_axi_wlast = \<const1> ;
+ assign m_axi_wstrb[3:0] = s_axi_wstrb;
+ assign m_axi_wuser[0] = \<const0> ;
+ assign m_axi_wvalid = s_axi_wvalid;
+ assign s_axi_buser[0] = \<const0> ;
+ assign s_axi_ruser[0] = \<const0> ;
+ assign s_axi_wready = m_axi_wready;
+ GND GND
+ (.G(\<const0> ));
+ VCC VCC
+ (.P(\<const1> ));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
+ (.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .in({m_axi_rresp,m_axi_rdata}),
+ .m_axi_araddr(m_axi_araddr[11:0]),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_axi_awaddr(m_axi_awaddr[11:0]),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_bvalid(m_axi_bvalid),
+ .m_axi_rready(m_axi_rready),
+ .m_axi_rvalid(m_axi_rvalid),
+ .\m_payload_i_reg[13] ({s_axi_bid,s_axi_bresp}),
+ .\m_payload_i_reg[34] ({m_axi_arprot,m_axi_araddr[31:12]}),
+ .\m_payload_i_reg[46] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_arsize(s_axi_arsize[1:0]),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awsize(s_axi_awsize[1:0]),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rvalid(s_axi_rvalid));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s
+ (s_axi_awready,
+ s_axi_arready,
+ Q,
+ \m_payload_i_reg[34] ,
+ s_axi_bvalid,
+ \m_payload_i_reg[13] ,
+ s_axi_rvalid,
+ \m_payload_i_reg[46] ,
+ m_axi_awvalid,
+ m_axi_bready,
+ m_axi_arvalid,
+ m_axi_rready,
+ m_axi_awaddr,
+ m_axi_araddr,
+ m_axi_arready,
+ s_axi_awvalid,
+ s_axi_arvalid,
+ aclk,
+ in,
+ s_axi_awid,
+ s_axi_awlen,
+ s_axi_awburst,
+ s_axi_awsize,
+ s_axi_awprot,
+ s_axi_awaddr,
+ m_axi_bresp,
+ s_axi_arid,
+ s_axi_arlen,
+ s_axi_arburst,
+ s_axi_arsize,
+ s_axi_arprot,
+ s_axi_araddr,
+ m_axi_awready,
+ m_axi_bvalid,
+ m_axi_rvalid,
+ s_axi_rready,
+ s_axi_bready,
+ aresetn);
+ output s_axi_awready;
+ output s_axi_arready;
+ output [22:0]Q;
+ output [22:0]\m_payload_i_reg[34] ;
+ output s_axi_bvalid;
+ output [13:0]\m_payload_i_reg[13] ;
+ output s_axi_rvalid;
+ output [46:0]\m_payload_i_reg[46] ;
+ output m_axi_awvalid;
+ output m_axi_bready;
+ output m_axi_arvalid;
+ output m_axi_rready;
+ output [11:0]m_axi_awaddr;
+ output [11:0]m_axi_araddr;
+ input m_axi_arready;
+ input s_axi_awvalid;
+ input s_axi_arvalid;
+ input aclk;
+ input [33:0]in;
+ input [11:0]s_axi_awid;
+ input [3:0]s_axi_awlen;
+ input [1:0]s_axi_awburst;
+ input [1:0]s_axi_awsize;
+ input [2:0]s_axi_awprot;
+ input [31:0]s_axi_awaddr;
+ input [1:0]m_axi_bresp;
+ input [11:0]s_axi_arid;
+ input [3:0]s_axi_arlen;
+ input [1:0]s_axi_arburst;
+ input [1:0]s_axi_arsize;
+ input [2:0]s_axi_arprot;
+ input [31:0]s_axi_araddr;
+ input m_axi_awready;
+ input m_axi_bvalid;
+ input m_axi_rvalid;
+ input s_axi_rready;
+ input s_axi_bready;
+ input aresetn;
+
+ wire [22:0]Q;
+ wire \RD.ar_channel_0_n_1 ;
+ wire \RD.ar_channel_0_n_23 ;
+ wire \RD.ar_channel_0_n_45 ;
+ wire \RD.ar_channel_0_n_46 ;
+ wire \RD.ar_channel_0_n_47 ;
+ wire \RD.ar_channel_0_n_48 ;
+ wire \RD.ar_channel_0_n_6 ;
+ wire \RD.ar_channel_0_n_7 ;
+ wire \RD.ar_channel_0_n_8 ;
+ wire SI_REG_n_108;
+ wire SI_REG_n_109;
+ wire SI_REG_n_127;
+ wire SI_REG_n_128;
+ wire SI_REG_n_129;
+ wire SI_REG_n_16;
+ wire SI_REG_n_169;
+ wire SI_REG_n_17;
+ wire SI_REG_n_170;
+ wire SI_REG_n_171;
+ wire SI_REG_n_172;
+ wire SI_REG_n_173;
+ wire SI_REG_n_174;
+ wire SI_REG_n_175;
+ wire SI_REG_n_176;
+ wire SI_REG_n_177;
+ wire SI_REG_n_178;
+ wire SI_REG_n_179;
+ wire SI_REG_n_18;
+ wire SI_REG_n_180;
+ wire SI_REG_n_181;
+ wire SI_REG_n_182;
+ wire SI_REG_n_183;
+ wire SI_REG_n_185;
+ wire SI_REG_n_186;
+ wire SI_REG_n_188;
+ wire SI_REG_n_189;
+ wire SI_REG_n_19;
+ wire SI_REG_n_36;
+ wire SI_REG_n_37;
+ wire SI_REG_n_38;
+ wire SI_REG_n_39;
+ wire SI_REG_n_40;
+ wire SI_REG_n_41;
+ wire SI_REG_n_42;
+ wire SI_REG_n_43;
+ wire SI_REG_n_44;
+ wire SI_REG_n_45;
+ wire SI_REG_n_46;
+ wire SI_REG_n_47;
+ wire SI_REG_n_48;
+ wire SI_REG_n_66;
+ wire \WR.aw_channel_0_n_21 ;
+ wire \WR.aw_channel_0_n_46 ;
+ wire \WR.aw_channel_0_n_47 ;
+ wire \WR.aw_channel_0_n_48 ;
+ wire \WR.aw_channel_0_n_49 ;
+ wire \WR.aw_channel_0_n_5 ;
+ wire \WR.aw_channel_0_n_6 ;
+ wire aclk;
+ wire \ar.ar_pipe/m_valid_i0 ;
+ wire \ar.ar_pipe/p_1_in ;
+ wire \ar.ar_pipe/s_ready_i0 ;
+ wire [1:0]\ar_cmd_fsm_0/state ;
+ wire areset_d1;
+ wire areset_d1_i_1_n_0;
+ wire aresetn;
+ wire \aw.aw_pipe/p_1_in ;
+ wire [1:0]\aw_cmd_fsm_0/state ;
+ wire [11:0]axaddr_incr;
+ wire [11:11]axaddr_wrap;
+ wire [1:0]axsize;
+ wire [11:0]b_awid;
+ wire [3:0]b_awlen;
+ wire b_full;
+ wire b_push;
+ wire [1:0]\bid_fifo_0/cnt_read ;
+ wire \cmd_translator_0/incr_cmd_0/sel_first ;
+ wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_1 ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_0 ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
+ wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
+ wire [33:0]in;
+ wire [11:0]m_axi_araddr;
+ wire m_axi_arready;
+ wire m_axi_arvalid;
+ wire [11:0]m_axi_awaddr;
+ wire m_axi_awready;
+ wire m_axi_awvalid;
+ wire m_axi_bready;
+ wire [1:0]m_axi_bresp;
+ wire m_axi_bvalid;
+ wire m_axi_rready;
+ wire m_axi_rvalid;
+ wire [13:0]\m_payload_i_reg[13] ;
+ wire [22:0]\m_payload_i_reg[34] ;
+ wire [46:0]\m_payload_i_reg[46] ;
+ wire r_full;
+ wire r_push;
+ wire r_rlast;
+ wire [11:0]s_arid;
+ wire [11:0]s_arid_r;
+ wire [11:0]s_awid;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [11:0]s_axi_arid;
+ wire [3:0]s_axi_arlen;
+ wire [2:0]s_axi_arprot;
+ wire s_axi_arready;
+ wire [1:0]s_axi_arsize;
+ wire s_axi_arvalid;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [11:0]s_axi_awid;
+ wire [3:0]s_axi_awlen;
+ wire [2:0]s_axi_awprot;
+ wire s_axi_awready;
+ wire [1:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_bvalid;
+ wire s_axi_rready;
+ wire s_axi_rvalid;
+ wire sel_first;
+ wire [11:0]si_rs_araddr;
+ wire [1:1]si_rs_arburst;
+ wire [3:0]si_rs_arlen;
+ wire si_rs_arvalid;
+ wire [11:0]si_rs_awaddr;
+ wire [1:1]si_rs_awburst;
+ wire [3:0]si_rs_awlen;
+ wire si_rs_awvalid;
+ wire [11:0]si_rs_bid;
+ wire si_rs_bready;
+ wire [1:0]si_rs_bresp;
+ wire si_rs_bvalid;
+ wire [31:0]si_rs_rdata;
+ wire [11:0]si_rs_rid;
+ wire si_rs_rlast;
+ wire si_rs_rready;
+ wire [1:0]si_rs_rresp;
+ wire si_rs_rvalid;
+ wire [3:0]wrap_cnt;
+
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel \RD.ar_channel_0
+ (.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+ .E(\ar.ar_pipe/p_1_in ),
+ .\FSM_sequential_state_reg[1] (\RD.ar_channel_0_n_8 ),
+ .O({SI_REG_n_44,SI_REG_n_45,SI_REG_n_46,SI_REG_n_47}),
+ .Q(\ar_cmd_fsm_0/state ),
+ .S({\RD.ar_channel_0_n_45 ,\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 }),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .\axaddr_incr_reg[11] (\RD.ar_channel_0_n_7 ),
+ .\axaddr_incr_reg[3] ({SI_REG_n_36,SI_REG_n_37,SI_REG_n_38,SI_REG_n_39}),
+ .\axaddr_incr_reg[7] ({SI_REG_n_40,SI_REG_n_41,SI_REG_n_42,SI_REG_n_43}),
+ .axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
+ .\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+ .\axaddr_wrap_reg[11] (\RD.ar_channel_0_n_6 ),
+ .\axlen_cnt_reg[3] (SI_REG_n_169),
+ .m_axi_araddr(m_axi_araddr[10:0]),
+ .\m_axi_araddr[0]_0 (SI_REG_n_189),
+ .m_axi_araddr_0_sp_1(SI_REG_n_188),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
+ .next_pending_r_reg(SI_REG_n_109),
+ .r_full(r_full),
+ .r_push(r_push),
+ .r_rlast(r_rlast),
+ .\s_arid_r_reg[11]_0 (s_arid_r),
+ .\s_arid_r_reg[11]_1 ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_127,SI_REG_n_128,SI_REG_n_129,si_rs_araddr}),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
+ .s_ready_i_reg(s_axi_arready),
+ .sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
+ .sel_first_reg(\RD.ar_channel_0_n_1 ),
+ .sel_first_reg_0(\RD.ar_channel_0_n_23 ),
+ .si_rs_arvalid(si_rs_arvalid),
+ .\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183}),
+ .\wrap_cnt_r_reg[3] ({SI_REG_n_16,SI_REG_n_17,SI_REG_n_18,SI_REG_n_19}),
+ .\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel \RD.r_channel_0
+ (.D(s_arid_r),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .in(in),
+ .m_axi_rready(m_axi_rready),
+ .m_axi_rvalid(m_axi_rvalid),
+ .out({si_rs_rresp,si_rs_rdata}),
+ .r_full(r_full),
+ .r_push(r_push),
+ .r_push_r_reg_0({si_rs_rid,si_rs_rlast}),
+ .r_rlast(r_rlast),
+ .si_rs_rready(si_rs_rready),
+ .si_rs_rvalid(si_rs_rvalid));
+ TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice SI_REG
+ (.D(wrap_cnt),
+ .E(\aw.aw_pipe/p_1_in ),
+ .O({SI_REG_n_44,SI_REG_n_45,SI_REG_n_46,SI_REG_n_47}),
+ .Q(\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
+ .S({\WR.aw_channel_0_n_46 ,\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 }),
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .axaddr_incr(axaddr_incr),
+ .\axaddr_incr_reg[3] ({\RD.ar_channel_0_n_45 ,\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 }),
+ .axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_1 ),
+ .axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
+ .\axaddr_offset_r_reg[0] (\aw_cmd_fsm_0/state ),
+ .\axaddr_offset_r_reg[0]_0 (\ar_cmd_fsm_0/state ),
+ .\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+ .\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+ .b_push(b_push),
+ .m_axi_araddr(m_axi_araddr[11]),
+ .\m_axi_araddr[11] (\RD.ar_channel_0_n_6 ),
+ .\m_axi_araddr[11]_0 (\RD.ar_channel_0_n_7 ),
+ .\m_axi_araddr[11]_1 (\RD.ar_channel_0_n_23 ),
+ .\m_axi_araddr[11]_2 (\RD.ar_channel_0_n_1 ),
+ .m_axi_awaddr(m_axi_awaddr[11]),
+ .\m_axi_awaddr[11] (axaddr_wrap),
+ .\m_axi_awaddr[11]_0 (\WR.aw_channel_0_n_5 ),
+ .\m_axi_awaddr[11]_1 (\WR.aw_channel_0_n_21 ),
+ .\m_payload_i_reg[0] (\ar.ar_pipe/p_1_in ),
+ .\m_payload_i_reg[13] (\m_payload_i_reg[13] ),
+ .\m_payload_i_reg[38] (SI_REG_n_186),
+ .\m_payload_i_reg[38]_0 (SI_REG_n_189),
+ .\m_payload_i_reg[39] (SI_REG_n_185),
+ .\m_payload_i_reg[39]_0 (SI_REG_n_188),
+ .\m_payload_i_reg[3] ({SI_REG_n_36,SI_REG_n_37,SI_REG_n_38,SI_REG_n_39}),
+ .\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
+ .\m_payload_i_reg[47] (SI_REG_n_48),
+ .\m_payload_i_reg[47]_0 (SI_REG_n_108),
+ .\m_payload_i_reg[47]_1 (SI_REG_n_109),
+ .\m_payload_i_reg[47]_2 (SI_REG_n_169),
+ .\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_66,axsize,Q,si_rs_awaddr}),
+ .\m_payload_i_reg[61]_0 ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_127,SI_REG_n_128,SI_REG_n_129,\m_payload_i_reg[34] ,si_rs_araddr}),
+ .\m_payload_i_reg[6] ({SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175,SI_REG_n_176}),
+ .\m_payload_i_reg[6]_0 ({SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183}),
+ .\m_payload_i_reg[7] ({SI_REG_n_40,SI_REG_n_41,SI_REG_n_42,SI_REG_n_43}),
+ .m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
+ .m_valid_i_reg(s_axi_bvalid),
+ .m_valid_i_reg_0(s_axi_rvalid),
+ .out(si_rs_bid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arsize(s_axi_arsize),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awsize(s_axi_awsize),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_rready(s_axi_rready),
+ .s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
+ .s_ready_i_reg(s_axi_awready),
+ .s_ready_i_reg_0(s_axi_arready),
+ .sel_first(sel_first),
+ .sel_first_1(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+ .sel_first_2(\cmd_translator_0/incr_cmd_0/sel_first ),
+ .si_rs_arvalid(si_rs_arvalid),
+ .si_rs_awvalid(si_rs_awvalid),
+ .si_rs_bready(si_rs_bready),
+ .si_rs_bvalid(si_rs_bvalid),
+ .si_rs_rready(si_rs_rready),
+ .si_rs_rvalid(si_rs_rvalid),
+ .\skid_buffer_reg[1] (si_rs_bresp),
+ .\skid_buffer_reg[33] ({si_rs_rresp,si_rs_rdata}),
+ .\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
+ .\wrap_cnt_r_reg[0] (\WR.aw_channel_0_n_6 ),
+ .\wrap_cnt_r_reg[0]_0 (\RD.ar_channel_0_n_8 ),
+ .wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_0 ),
+ .\wrap_second_len_r_reg[1] ({SI_REG_n_16,SI_REG_n_17,SI_REG_n_18,SI_REG_n_19}),
+ .\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+ .\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel \WR.aw_channel_0
+ (.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_1 ),
+ .E(\aw.aw_pipe/p_1_in ),
+ .Q(\aw_cmd_fsm_0/state ),
+ .S({\WR.aw_channel_0_n_46 ,\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 }),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .axaddr_incr(axaddr_incr),
+ .\axaddr_incr_reg[11] (\WR.aw_channel_0_n_5 ),
+ .\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+ .\axaddr_wrap_reg[11] (axaddr_wrap),
+ .\axlen_cnt_reg[3] (SI_REG_n_108),
+ .b_full(b_full),
+ .b_push(b_push),
+ .cnt_read(\bid_fifo_0/cnt_read ),
+ .in({b_awid,b_awlen}),
+ .m_axi_awaddr(m_axi_awaddr[10:0]),
+ .\m_axi_awaddr[0]_0 (SI_REG_n_186),
+ .m_axi_awaddr_0_sp_1(SI_REG_n_185),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_awvalid(m_axi_awvalid),
+ .next_pending_r_reg(SI_REG_n_48),
+ .\s_awid_r_reg[11]_0 ({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_66,axsize,si_rs_awaddr}),
+ .sel_first(sel_first),
+ .sel_first_0(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+ .sel_first_reg(\WR.aw_channel_0_n_21 ),
+ .si_rs_awvalid(si_rs_awvalid),
+ .\state_reg[1] (\WR.aw_channel_0_n_6 ),
+ .\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175,SI_REG_n_176}),
+ .\wrap_cnt_r_reg[3] (wrap_cnt),
+ .\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
+ .\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_0 ));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel \WR.b_channel_0
+ (.aclk(aclk),
+ .areset_d1(areset_d1),
+ .b_full(b_full),
+ .b_push(b_push),
+ .cnt_read(\bid_fifo_0/cnt_read ),
+ .in({b_awid,b_awlen}),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_bvalid(m_axi_bvalid),
+ .out(si_rs_bid),
+ .\s_bresp_acc_reg[1]_0 (si_rs_bresp),
+ .si_rs_bready(si_rs_bready),
+ .si_rs_bvalid(si_rs_bvalid));
+ LUT1 #(
+ .INIT(2'h1))
+ areset_d1_i_1
+ (.I0(aresetn),
+ .O(areset_d1_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ areset_d1_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(areset_d1_i_1_n_0),
+ .Q(areset_d1),
+ .R(1'b0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel
+ (sel_first,
+ sel_first_reg,
+ Q,
+ s_ready_i0,
+ m_valid_i0,
+ \axaddr_wrap_reg[11] ,
+ \axaddr_incr_reg[11] ,
+ \FSM_sequential_state_reg[1] ,
+ r_push,
+ m_axi_arvalid,
+ r_rlast,
+ m_axi_araddr,
+ sel_first_reg_0,
+ E,
+ \axaddr_offset_r_reg[3] ,
+ \wrap_second_len_r_reg[3] ,
+ \s_arid_r_reg[11]_0 ,
+ S,
+ aclk,
+ si_rs_arvalid,
+ m_axi_arready,
+ s_axi_arvalid,
+ s_ready_i_reg,
+ \s_arid_r_reg[11]_1 ,
+ next_pending_r_reg,
+ areset_d1,
+ \axlen_cnt_reg[3] ,
+ r_full,
+ O,
+ \axaddr_incr_reg[7] ,
+ \axaddr_incr_reg[3] ,
+ m_axi_araddr_0_sp_1,
+ \m_axi_araddr[0]_0 ,
+ axaddr_offset,
+ D,
+ \wrap_cnt_r_reg[3] ,
+ \wrap_boundary_axaddr_r_reg[6] );
+ output sel_first;
+ output sel_first_reg;
+ output [1:0]Q;
+ output s_ready_i0;
+ output m_valid_i0;
+ output [0:0]\axaddr_wrap_reg[11] ;
+ output [0:0]\axaddr_incr_reg[11] ;
+ output \FSM_sequential_state_reg[1] ;
+ output r_push;
+ output m_axi_arvalid;
+ output r_rlast;
+ output [10:0]m_axi_araddr;
+ output sel_first_reg_0;
+ output [0:0]E;
+ output [3:0]\axaddr_offset_r_reg[3] ;
+ output [3:0]\wrap_second_len_r_reg[3] ;
+ output [11:0]\s_arid_r_reg[11]_0 ;
+ output [3:0]S;
+ input aclk;
+ input si_rs_arvalid;
+ input m_axi_arready;
+ input s_axi_arvalid;
+ input s_ready_i_reg;
+ input [31:0]\s_arid_r_reg[11]_1 ;
+ input next_pending_r_reg;
+ input areset_d1;
+ input \axlen_cnt_reg[3] ;
+ input r_full;
+ input [3:0]O;
+ input [3:0]\axaddr_incr_reg[7] ;
+ input [3:0]\axaddr_incr_reg[3] ;
+ input m_axi_araddr_0_sp_1;
+ input \m_axi_araddr[0]_0 ;
+ input [3:0]axaddr_offset;
+ input [3:0]D;
+ input [3:0]\wrap_cnt_r_reg[3] ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_state_reg[1] ;
+ wire [3:0]O;
+ wire [1:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire ar_cmd_fsm_0_n_0;
+ wire ar_cmd_fsm_0_n_10;
+ wire ar_cmd_fsm_0_n_11;
+ wire ar_cmd_fsm_0_n_12;
+ wire ar_cmd_fsm_0_n_13;
+ wire ar_cmd_fsm_0_n_14;
+ wire ar_cmd_fsm_0_n_15;
+ wire ar_cmd_fsm_0_n_16;
+ wire ar_cmd_fsm_0_n_17;
+ wire ar_cmd_fsm_0_n_18;
+ wire ar_cmd_fsm_0_n_19;
+ wire ar_cmd_fsm_0_n_20;
+ wire ar_cmd_fsm_0_n_21;
+ wire ar_cmd_fsm_0_n_22;
+ wire ar_cmd_fsm_0_n_5;
+ wire ar_cmd_fsm_0_n_6;
+ wire ar_cmd_fsm_0_n_7;
+ wire areset_d1;
+ wire [0:0]\axaddr_incr_reg[11] ;
+ wire [3:0]\axaddr_incr_reg[3] ;
+ wire [3:0]\axaddr_incr_reg[7] ;
+ wire [3:0]axaddr_offset;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire [0:0]\axaddr_wrap_reg[11] ;
+ wire \axlen_cnt_reg[3] ;
+ wire cmd_translator_0_n_0;
+ wire cmd_translator_0_n_10;
+ wire cmd_translator_0_n_11;
+ wire cmd_translator_0_n_12;
+ wire cmd_translator_0_n_13;
+ wire cmd_translator_0_n_14;
+ wire cmd_translator_0_n_17;
+ wire cmd_translator_0_n_20;
+ wire cmd_translator_0_n_3;
+ wire cmd_translator_0_n_4;
+ wire cmd_translator_0_n_41;
+ wire cmd_translator_0_n_42;
+ wire cmd_translator_0_n_43;
+ wire cmd_translator_0_n_44;
+ wire cmd_translator_0_n_45;
+ wire cmd_translator_0_n_46;
+ wire cmd_translator_0_n_47;
+ wire cmd_translator_0_n_48;
+ wire cmd_translator_0_n_49;
+ wire cmd_translator_0_n_5;
+ wire cmd_translator_0_n_50;
+ wire cmd_translator_0_n_51;
+ wire cmd_translator_0_n_52;
+ wire cmd_translator_0_n_6;
+ wire cmd_translator_0_n_7;
+ wire cmd_translator_0_n_8;
+ wire cmd_translator_0_n_9;
+ wire [10:0]m_axi_araddr;
+ wire \m_axi_araddr[0]_0 ;
+ wire m_axi_araddr_0_sn_1;
+ wire m_axi_arready;
+ wire m_axi_arvalid;
+ wire m_valid_i0;
+ wire next_pending;
+ wire next_pending_r_reg;
+ wire r_full;
+ wire r_push;
+ wire r_rlast;
+ wire [11:0]\s_arid_r_reg[11]_0 ;
+ wire [31:0]\s_arid_r_reg[11]_1 ;
+ wire s_axi_arvalid;
+ wire s_ready_i0;
+ wire s_ready_i_reg;
+ wire sel_first;
+ wire sel_first_i;
+ wire sel_first_reg;
+ wire sel_first_reg_0;
+ wire si_rs_arvalid;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+ wire [3:0]\wrap_cnt_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3] ;
+
+ assign m_axi_araddr_0_sn_1 = m_axi_araddr_0_sp_1;
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm ar_cmd_fsm_0
+ (.D({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13,ar_cmd_fsm_0_n_14,ar_cmd_fsm_0_n_15,ar_cmd_fsm_0_n_16,ar_cmd_fsm_0_n_17,ar_cmd_fsm_0_n_18,ar_cmd_fsm_0_n_19,ar_cmd_fsm_0_n_20,ar_cmd_fsm_0_n_21,ar_cmd_fsm_0_n_22}),
+ .E(\FSM_sequential_state_reg[1] ),
+ .\FSM_sequential_state_reg[1]_0 (ar_cmd_fsm_0_n_0),
+ .\FSM_sequential_state_reg[1]_1 (E),
+ .O({cmd_translator_0_n_3,cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6}),
+ .Q(Q),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .\axaddr_incr_reg[0] (sel_first),
+ .\axaddr_wrap_reg[11] (\s_arid_r_reg[11]_1 [11:0]),
+ .\axaddr_wrap_reg[11]_0 ({cmd_translator_0_n_41,cmd_translator_0_n_42,cmd_translator_0_n_43,cmd_translator_0_n_44,cmd_translator_0_n_45,cmd_translator_0_n_46,cmd_translator_0_n_47,cmd_translator_0_n_48,cmd_translator_0_n_49,cmd_translator_0_n_50,cmd_translator_0_n_51,cmd_translator_0_n_52}),
+ .\axaddr_wrap_reg[11]_1 ({cmd_translator_0_n_11,cmd_translator_0_n_12,cmd_translator_0_n_13,cmd_translator_0_n_14}),
+ .\axaddr_wrap_reg[11]_2 (cmd_translator_0_n_20),
+ .\axaddr_wrap_reg[7] ({cmd_translator_0_n_7,cmd_translator_0_n_8,cmd_translator_0_n_9,cmd_translator_0_n_10}),
+ .\axlen_cnt_reg[8] (cmd_translator_0_n_17),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_arready_0(ar_cmd_fsm_0_n_5),
+ .m_axi_arready_1(ar_cmd_fsm_0_n_6),
+ .m_axi_arready_2(ar_cmd_fsm_0_n_7),
+ .m_axi_arready_3(r_push),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_valid_i0(m_valid_i0),
+ .next_pending(next_pending),
+ .r_full(r_full),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_ready_i0(s_ready_i0),
+ .s_ready_i_reg(s_ready_i_reg),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg(ar_cmd_fsm_0_n_10),
+ .sel_first_reg_0(sel_first_reg),
+ .sel_first_reg_1(cmd_translator_0_n_0),
+ .si_rs_arvalid(si_rs_arvalid));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1 cmd_translator_0
+ (.D(D),
+ .E(\FSM_sequential_state_reg[1] ),
+ .O({cmd_translator_0_n_3,cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6}),
+ .Q(Q),
+ .S(S),
+ .aclk(aclk),
+ .\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_10),
+ .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
+ .\axaddr_incr_reg[11]_0 (O),
+ .\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
+ .\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
+ .axaddr_offset(axaddr_offset),
+ .\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
+ .\axaddr_wrap_reg[0] (ar_cmd_fsm_0_n_5),
+ .\axaddr_wrap_reg[11] ({cmd_translator_0_n_11,cmd_translator_0_n_12,cmd_translator_0_n_13,cmd_translator_0_n_14}),
+ .\axaddr_wrap_reg[11]_0 (\axaddr_wrap_reg[11] ),
+ .\axaddr_wrap_reg[11]_1 ({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13,ar_cmd_fsm_0_n_14,ar_cmd_fsm_0_n_15,ar_cmd_fsm_0_n_16,ar_cmd_fsm_0_n_17,ar_cmd_fsm_0_n_18,ar_cmd_fsm_0_n_19,ar_cmd_fsm_0_n_20,ar_cmd_fsm_0_n_21,ar_cmd_fsm_0_n_22}),
+ .\axaddr_wrap_reg[7] ({cmd_translator_0_n_7,cmd_translator_0_n_8,cmd_translator_0_n_9,cmd_translator_0_n_10}),
+ .\axlen_cnt_reg[2] (cmd_translator_0_n_17),
+ .\axlen_cnt_reg[3] (\s_arid_r_reg[11]_1 [19:0]),
+ .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ),
+ .\axlen_cnt_reg[4] (cmd_translator_0_n_20),
+ .\axlen_cnt_reg[8] (ar_cmd_fsm_0_n_0),
+ .m_axi_araddr(m_axi_araddr),
+ .\m_axi_araddr[0]_0 (\m_axi_araddr[0]_0 ),
+ .m_axi_araddr_0_sp_1(m_axi_araddr_0_sn_1),
+ .m_axi_arready(m_axi_arready),
+ .next_pending(next_pending),
+ .next_pending_r_reg(next_pending_r_reg),
+ .r_push(r_push),
+ .r_rlast(r_rlast),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(cmd_translator_0_n_0),
+ .sel_first_reg_1(sel_first),
+ .sel_first_reg_2(sel_first_reg),
+ .sel_first_reg_3(sel_first_reg_0),
+ .sel_first_reg_4(ar_cmd_fsm_0_n_7),
+ .sel_first_reg_5(ar_cmd_fsm_0_n_6),
+ .si_rs_arvalid(si_rs_arvalid),
+ .\wrap_boundary_axaddr_r_reg[11] ({cmd_translator_0_n_41,cmd_translator_0_n_42,cmd_translator_0_n_43,cmd_translator_0_n_44,cmd_translator_0_n_45,cmd_translator_0_n_46,cmd_translator_0_n_47,cmd_translator_0_n_48,cmd_translator_0_n_49,cmd_translator_0_n_50,cmd_translator_0_n_51,cmd_translator_0_n_52}),
+ .\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
+ .\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
+ .\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
+ FDRE \s_arid_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [20]),
+ .Q(\s_arid_r_reg[11]_0 [0]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[10]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [30]),
+ .Q(\s_arid_r_reg[11]_0 [10]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[11]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [31]),
+ .Q(\s_arid_r_reg[11]_0 [11]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [21]),
+ .Q(\s_arid_r_reg[11]_0 [1]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [22]),
+ .Q(\s_arid_r_reg[11]_0 [2]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [23]),
+ .Q(\s_arid_r_reg[11]_0 [3]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[4]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [24]),
+ .Q(\s_arid_r_reg[11]_0 [4]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[5]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [25]),
+ .Q(\s_arid_r_reg[11]_0 [5]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[6]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [26]),
+ .Q(\s_arid_r_reg[11]_0 [6]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[7]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [27]),
+ .Q(\s_arid_r_reg[11]_0 [7]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[8]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [28]),
+ .Q(\s_arid_r_reg[11]_0 [8]),
+ .R(1'b0));
+ FDRE \s_arid_r_reg[9]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_arid_r_reg[11]_1 [29]),
+ .Q(\s_arid_r_reg[11]_0 [9]),
+ .R(1'b0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel
+ (sel_first_0,
+ sel_first,
+ Q,
+ \axaddr_wrap_reg[11] ,
+ \axaddr_incr_reg[11] ,
+ \state_reg[1] ,
+ E,
+ b_push,
+ m_axi_awvalid,
+ m_axi_awaddr,
+ sel_first_reg,
+ \axaddr_offset_r_reg[3] ,
+ \wrap_second_len_r_reg[3] ,
+ in,
+ S,
+ aclk,
+ si_rs_awvalid,
+ \s_awid_r_reg[11]_0 ,
+ next_pending_r_reg,
+ areset_d1,
+ \axlen_cnt_reg[3] ,
+ m_axi_awready,
+ b_full,
+ cnt_read,
+ axaddr_incr,
+ m_axi_awaddr_0_sp_1,
+ \m_axi_awaddr[0]_0 ,
+ D,
+ \wrap_second_len_r_reg[3]_0 ,
+ \wrap_cnt_r_reg[3] ,
+ \wrap_boundary_axaddr_r_reg[6] );
+ output sel_first_0;
+ output sel_first;
+ output [1:0]Q;
+ output [0:0]\axaddr_wrap_reg[11] ;
+ output [0:0]\axaddr_incr_reg[11] ;
+ output \state_reg[1] ;
+ output [0:0]E;
+ output b_push;
+ output m_axi_awvalid;
+ output [10:0]m_axi_awaddr;
+ output sel_first_reg;
+ output [3:0]\axaddr_offset_r_reg[3] ;
+ output [3:0]\wrap_second_len_r_reg[3] ;
+ output [15:0]in;
+ output [3:0]S;
+ input aclk;
+ input si_rs_awvalid;
+ input [31:0]\s_awid_r_reg[11]_0 ;
+ input next_pending_r_reg;
+ input areset_d1;
+ input \axlen_cnt_reg[3] ;
+ input m_axi_awready;
+ input b_full;
+ input [1:0]cnt_read;
+ input [11:0]axaddr_incr;
+ input m_axi_awaddr_0_sp_1;
+ input \m_axi_awaddr[0]_0 ;
+ input [3:0]D;
+ input [3:0]\wrap_second_len_r_reg[3]_0 ;
+ input [3:0]\wrap_cnt_r_reg[3] ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [1:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire areset_d1;
+ wire aw_cmd_fsm_0_n_0;
+ wire aw_cmd_fsm_0_n_4;
+ wire aw_cmd_fsm_0_n_5;
+ wire aw_cmd_fsm_0_n_6;
+ wire aw_cmd_fsm_0_n_8;
+ wire aw_cmd_fsm_0_n_9;
+ wire [11:0]axaddr_incr;
+ wire [0:0]\axaddr_incr_reg[11] ;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire [0:0]\axaddr_wrap_reg[11] ;
+ wire \axlen_cnt_reg[3] ;
+ wire b_full;
+ wire b_push;
+ wire cmd_translator_0_n_0;
+ wire cmd_translator_0_n_5;
+ wire cmd_translator_0_n_6;
+ wire cmd_translator_0_n_7;
+ wire cmd_translator_0_n_9;
+ wire [1:0]cnt_read;
+ wire [15:0]in;
+ wire [10:0]m_axi_awaddr;
+ wire \m_axi_awaddr[0]_0 ;
+ wire m_axi_awaddr_0_sn_1;
+ wire m_axi_awready;
+ wire m_axi_awvalid;
+ wire next;
+ wire next_pending;
+ wire next_pending_r_reg;
+ wire [31:0]\s_awid_r_reg[11]_0 ;
+ wire sel_first;
+ wire sel_first_0;
+ wire sel_first_i;
+ wire sel_first_reg;
+ wire si_rs_awvalid;
+ wire \state_reg[1] ;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+ wire [3:0]\wrap_cnt_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+
+ assign m_axi_awaddr_0_sn_1 = m_axi_awaddr_0_sp_1;
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm aw_cmd_fsm_0
+ (.D({aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9}),
+ .E(\state_reg[1] ),
+ .Q(Q),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .\axlen_cnt_reg[0] (cmd_translator_0_n_6),
+ .\axlen_cnt_reg[0]_0 (cmd_translator_0_n_7),
+ .\axlen_cnt_reg[3] ({\s_awid_r_reg[11]_0 [19],\s_awid_r_reg[11]_0 [16]}),
+ .\axlen_cnt_reg[3]_0 (cmd_translator_0_n_9),
+ .\axlen_cnt_reg[8] (cmd_translator_0_n_5),
+ .b_full(b_full),
+ .b_push(b_push),
+ .cnt_read(cnt_read),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_valid_i_reg(aw_cmd_fsm_0_n_0),
+ .m_valid_i_reg_0(aw_cmd_fsm_0_n_4),
+ .m_valid_i_reg_1(E),
+ .next(next),
+ .next_pending(next_pending),
+ .sel_first(sel_first),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg(aw_cmd_fsm_0_n_5),
+ .sel_first_reg_0(aw_cmd_fsm_0_n_6),
+ .sel_first_reg_1(sel_first_0),
+ .sel_first_reg_2(cmd_translator_0_n_0),
+ .si_rs_awvalid(si_rs_awvalid));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator cmd_translator_0
+ (.D(D),
+ .E(\state_reg[1] ),
+ .Q(cmd_translator_0_n_6),
+ .S(S),
+ .aclk(aclk),
+ .axaddr_incr(axaddr_incr),
+ .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
+ .\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
+ .\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_4),
+ .\axaddr_wrap_reg[11] (\axaddr_wrap_reg[11] ),
+ .\axlen_cnt_reg[0] (Q),
+ .\axlen_cnt_reg[2] (cmd_translator_0_n_5),
+ .\axlen_cnt_reg[2]_0 (cmd_translator_0_n_9),
+ .\axlen_cnt_reg[2]_1 (\s_awid_r_reg[11]_0 [18:0]),
+ .\axlen_cnt_reg[3] (cmd_translator_0_n_7),
+ .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ),
+ .\axlen_cnt_reg[3]_1 ({aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9}),
+ .\axlen_cnt_reg[8] (aw_cmd_fsm_0_n_0),
+ .m_axi_awaddr(m_axi_awaddr),
+ .\m_axi_awaddr[0]_0 (\m_axi_awaddr[0]_0 ),
+ .m_axi_awaddr_0_sp_1(m_axi_awaddr_0_sn_1),
+ .next(next),
+ .next_pending(next_pending),
+ .next_pending_r_reg(next_pending_r_reg),
+ .sel_first(sel_first),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(cmd_translator_0_n_0),
+ .sel_first_reg_1(sel_first_0),
+ .sel_first_reg_2(sel_first_reg),
+ .sel_first_reg_3(aw_cmd_fsm_0_n_6),
+ .sel_first_reg_4(aw_cmd_fsm_0_n_5),
+ .si_rs_awvalid(si_rs_awvalid),
+ .\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
+ .\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
+ .\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
+ .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_0 ));
+ FDRE \s_awid_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [20]),
+ .Q(in[4]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[10]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [30]),
+ .Q(in[14]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[11]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [31]),
+ .Q(in[15]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [21]),
+ .Q(in[5]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [22]),
+ .Q(in[6]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [23]),
+ .Q(in[7]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[4]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [24]),
+ .Q(in[8]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[5]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [25]),
+ .Q(in[9]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[6]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [26]),
+ .Q(in[10]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[7]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [27]),
+ .Q(in[11]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[8]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [28]),
+ .Q(in[12]),
+ .R(1'b0));
+ FDRE \s_awid_r_reg[9]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [29]),
+ .Q(in[13]),
+ .R(1'b0));
+ FDRE \s_awlen_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [16]),
+ .Q(in[0]),
+ .R(1'b0));
+ FDRE \s_awlen_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [17]),
+ .Q(in[1]),
+ .R(1'b0));
+ FDRE \s_awlen_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [18]),
+ .Q(in[2]),
+ .R(1'b0));
+ FDRE \s_awlen_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_awid_r_reg[11]_0 [19]),
+ .Q(in[3]),
+ .R(1'b0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel
+ (si_rs_bvalid,
+ b_full,
+ cnt_read,
+ m_axi_bready,
+ out,
+ \s_bresp_acc_reg[1]_0 ,
+ areset_d1,
+ aclk,
+ si_rs_bready,
+ m_axi_bvalid,
+ b_push,
+ in,
+ m_axi_bresp);
+ output si_rs_bvalid;
+ output b_full;
+ output [1:0]cnt_read;
+ output m_axi_bready;
+ output [11:0]out;
+ output [1:0]\s_bresp_acc_reg[1]_0 ;
+ input areset_d1;
+ input aclk;
+ input si_rs_bready;
+ input m_axi_bvalid;
+ input b_push;
+ input [15:0]in;
+ input [1:0]m_axi_bresp;
+
+ wire aclk;
+ wire areset_d1;
+ wire b_full;
+ wire b_push;
+ wire bid_fifo_0_n_5;
+ wire \bresp_cnt[7]_i_3_n_0 ;
+ wire [7:0]bresp_cnt_reg;
+ wire bresp_empty;
+ wire bresp_push;
+ wire [1:0]cnt_read;
+ wire [15:0]in;
+ wire m_axi_bready;
+ wire [1:0]m_axi_bresp;
+ wire m_axi_bvalid;
+ wire mhandshake;
+ wire mhandshake_r;
+ wire [11:0]out;
+ wire [7:0]p_0_in;
+ wire s_bresp_acc0;
+ wire \s_bresp_acc[0]_i_1_n_0 ;
+ wire \s_bresp_acc[1]_i_1_n_0 ;
+ wire [1:0]\s_bresp_acc_reg[1]_0 ;
+ wire \s_bresp_acc_reg_n_0_[0] ;
+ wire \s_bresp_acc_reg_n_0_[1] ;
+ wire shandshake;
+ wire shandshake_r;
+ wire si_rs_bready;
+ wire si_rs_bvalid;
+
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo bid_fifo_0
+ (.Q(bresp_cnt_reg),
+ .SR(s_bresp_acc0),
+ .aclk(aclk),
+ .addr(cnt_read),
+ .areset_d1(areset_d1),
+ .b_full(b_full),
+ .b_push(b_push),
+ .bresp_empty(bresp_empty),
+ .bresp_push(bresp_push),
+ .in(in),
+ .mhandshake_r(mhandshake_r),
+ .out(out),
+ .shandshake_r(shandshake_r),
+ .shandshake_r_reg(bid_fifo_0_n_5),
+ .si_rs_bready(si_rs_bready),
+ .si_rs_bvalid(si_rs_bvalid));
+ LUT1 #(
+ .INIT(2'h1))
+ \bresp_cnt[0]_i_1
+ (.I0(bresp_cnt_reg[0]),
+ .O(p_0_in[0]));
+ (* SOFT_HLUTNM = "soft_lutpair133" *)
+ LUT2 #(
+ .INIT(4'h6))
+ \bresp_cnt[1]_i_1
+ (.I0(bresp_cnt_reg[0]),
+ .I1(bresp_cnt_reg[1]),
+ .O(p_0_in[1]));
+ (* SOFT_HLUTNM = "soft_lutpair133" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \bresp_cnt[2]_i_1
+ (.I0(bresp_cnt_reg[0]),
+ .I1(bresp_cnt_reg[1]),
+ .I2(bresp_cnt_reg[2]),
+ .O(p_0_in[2]));
+ (* SOFT_HLUTNM = "soft_lutpair132" *)
+ LUT4 #(
+ .INIT(16'h7F80))
+ \bresp_cnt[3]_i_1
+ (.I0(bresp_cnt_reg[1]),
+ .I1(bresp_cnt_reg[0]),
+ .I2(bresp_cnt_reg[2]),
+ .I3(bresp_cnt_reg[3]),
+ .O(p_0_in[3]));
+ (* SOFT_HLUTNM = "soft_lutpair132" *)
+ LUT5 #(
+ .INIT(32'h7FFF8000))
+ \bresp_cnt[4]_i_1
+ (.I0(bresp_cnt_reg[2]),
+ .I1(bresp_cnt_reg[0]),
+ .I2(bresp_cnt_reg[1]),
+ .I3(bresp_cnt_reg[3]),
+ .I4(bresp_cnt_reg[4]),
+ .O(p_0_in[4]));
+ LUT6 #(
+ .INIT(64'h7FFFFFFF80000000))
+ \bresp_cnt[5]_i_1
+ (.I0(bresp_cnt_reg[3]),
+ .I1(bresp_cnt_reg[1]),
+ .I2(bresp_cnt_reg[0]),
+ .I3(bresp_cnt_reg[2]),
+ .I4(bresp_cnt_reg[4]),
+ .I5(bresp_cnt_reg[5]),
+ .O(p_0_in[5]));
+ (* SOFT_HLUTNM = "soft_lutpair134" *)
+ LUT2 #(
+ .INIT(4'h6))
+ \bresp_cnt[6]_i_1
+ (.I0(\bresp_cnt[7]_i_3_n_0 ),
+ .I1(bresp_cnt_reg[6]),
+ .O(p_0_in[6]));
+ (* SOFT_HLUTNM = "soft_lutpair134" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \bresp_cnt[7]_i_2
+ (.I0(\bresp_cnt[7]_i_3_n_0 ),
+ .I1(bresp_cnt_reg[6]),
+ .I2(bresp_cnt_reg[7]),
+ .O(p_0_in[7]));
+ LUT6 #(
+ .INIT(64'h8000000000000000))
+ \bresp_cnt[7]_i_3
+ (.I0(bresp_cnt_reg[5]),
+ .I1(bresp_cnt_reg[3]),
+ .I2(bresp_cnt_reg[1]),
+ .I3(bresp_cnt_reg[0]),
+ .I4(bresp_cnt_reg[2]),
+ .I5(bresp_cnt_reg[4]),
+ .O(\bresp_cnt[7]_i_3_n_0 ));
+ FDRE \bresp_cnt_reg[0]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[0]),
+ .Q(bresp_cnt_reg[0]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[1]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[1]),
+ .Q(bresp_cnt_reg[1]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[2]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[2]),
+ .Q(bresp_cnt_reg[2]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[3]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[3]),
+ .Q(bresp_cnt_reg[3]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[4]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[4]),
+ .Q(bresp_cnt_reg[4]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[5]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[5]),
+ .Q(bresp_cnt_reg[5]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[6]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[6]),
+ .Q(bresp_cnt_reg[6]),
+ .R(s_bresp_acc0));
+ FDRE \bresp_cnt_reg[7]
+ (.C(aclk),
+ .CE(mhandshake_r),
+ .D(p_0_in[7]),
+ .Q(bresp_cnt_reg[7]),
+ .R(s_bresp_acc0));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0 bresp_fifo_0
+ (.aclk(aclk),
+ .areset_d1(areset_d1),
+ .bresp_empty(bresp_empty),
+ .bresp_push(bresp_push),
+ .in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_bvalid(m_axi_bvalid),
+ .mhandshake(mhandshake),
+ .mhandshake_r(mhandshake_r),
+ .\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1]_0 ),
+ .shandshake_r(shandshake_r));
+ FDRE #(
+ .INIT(1'b0))
+ bvalid_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(bid_fifo_0_n_5),
+ .Q(si_rs_bvalid),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ mhandshake_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(mhandshake),
+ .Q(mhandshake_r),
+ .R(areset_d1));
+ LUT6 #(
+ .INIT(64'h00000000EACECCCC))
+ \s_bresp_acc[0]_i_1
+ (.I0(m_axi_bresp[0]),
+ .I1(\s_bresp_acc_reg_n_0_[0] ),
+ .I2(\s_bresp_acc_reg_n_0_[1] ),
+ .I3(m_axi_bresp[1]),
+ .I4(mhandshake),
+ .I5(s_bresp_acc0),
+ .O(\s_bresp_acc[0]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h00EA))
+ \s_bresp_acc[1]_i_1
+ (.I0(\s_bresp_acc_reg_n_0_[1] ),
+ .I1(m_axi_bresp[1]),
+ .I2(mhandshake),
+ .I3(s_bresp_acc0),
+ .O(\s_bresp_acc[1]_i_1_n_0 ));
+ FDRE \s_bresp_acc_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_bresp_acc[0]_i_1_n_0 ),
+ .Q(\s_bresp_acc_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \s_bresp_acc_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\s_bresp_acc[1]_i_1_n_0 ),
+ .Q(\s_bresp_acc_reg_n_0_[1] ),
+ .R(1'b0));
+ LUT2 #(
+ .INIT(4'h8))
+ shandshake_r_i_1
+ (.I0(si_rs_bvalid),
+ .I1(si_rs_bready),
+ .O(shandshake));
+ FDRE #(
+ .INIT(1'b0))
+ shandshake_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(shandshake),
+ .Q(shandshake_r),
+ .R(areset_d1));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator
+ (sel_first_reg_0,
+ sel_first_reg_1,
+ sel_first,
+ \axaddr_wrap_reg[11] ,
+ \axaddr_incr_reg[11] ,
+ \axlen_cnt_reg[2] ,
+ Q,
+ \axlen_cnt_reg[3] ,
+ next_pending,
+ \axlen_cnt_reg[2]_0 ,
+ m_axi_awaddr,
+ sel_first_reg_2,
+ \axaddr_offset_r_reg[3] ,
+ \wrap_second_len_r_reg[3] ,
+ S,
+ aclk,
+ sel_first_i,
+ sel_first_reg_3,
+ sel_first_reg_4,
+ next,
+ \axlen_cnt_reg[2]_1 ,
+ next_pending_r_reg,
+ E,
+ \axlen_cnt_reg[0] ,
+ si_rs_awvalid,
+ \axlen_cnt_reg[3]_0 ,
+ axaddr_incr,
+ m_axi_awaddr_0_sp_1,
+ \m_axi_awaddr[0]_0 ,
+ \axaddr_wrap_reg[0] ,
+ \axlen_cnt_reg[8] ,
+ D,
+ \wrap_second_len_r_reg[3]_0 ,
+ \axlen_cnt_reg[3]_1 ,
+ \wrap_cnt_r_reg[3] ,
+ \wrap_boundary_axaddr_r_reg[6] );
+ output sel_first_reg_0;
+ output sel_first_reg_1;
+ output sel_first;
+ output [0:0]\axaddr_wrap_reg[11] ;
+ output [0:0]\axaddr_incr_reg[11] ;
+ output \axlen_cnt_reg[2] ;
+ output [0:0]Q;
+ output \axlen_cnt_reg[3] ;
+ output next_pending;
+ output \axlen_cnt_reg[2]_0 ;
+ output [10:0]m_axi_awaddr;
+ output sel_first_reg_2;
+ output [3:0]\axaddr_offset_r_reg[3] ;
+ output [3:0]\wrap_second_len_r_reg[3] ;
+ output [3:0]S;
+ input aclk;
+ input sel_first_i;
+ input sel_first_reg_3;
+ input sel_first_reg_4;
+ input next;
+ input [18:0]\axlen_cnt_reg[2]_1 ;
+ input next_pending_r_reg;
+ input [0:0]E;
+ input [1:0]\axlen_cnt_reg[0] ;
+ input si_rs_awvalid;
+ input \axlen_cnt_reg[3]_0 ;
+ input [11:0]axaddr_incr;
+ input m_axi_awaddr_0_sp_1;
+ input \m_axi_awaddr[0]_0 ;
+ input \axaddr_wrap_reg[0] ;
+ input \axlen_cnt_reg[8] ;
+ input [3:0]D;
+ input [3:0]\wrap_second_len_r_reg[3]_0 ;
+ input [1:0]\axlen_cnt_reg[3]_1 ;
+ input [3:0]\wrap_cnt_r_reg[3] ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [0:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire [11:0]axaddr_incr;
+ wire [0:0]\axaddr_incr_reg[11] ;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire [10:0]axaddr_wrap;
+ wire \axaddr_wrap_reg[0] ;
+ wire [0:0]\axaddr_wrap_reg[11] ;
+ wire [1:0]\axlen_cnt_reg[0] ;
+ wire \axlen_cnt_reg[2] ;
+ wire \axlen_cnt_reg[2]_0 ;
+ wire [18:0]\axlen_cnt_reg[2]_1 ;
+ wire \axlen_cnt_reg[3] ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire [1:0]\axlen_cnt_reg[3]_1 ;
+ wire \axlen_cnt_reg[8] ;
+ wire incr_cmd_0_n_3;
+ wire incr_next_pending;
+ wire [10:0]m_axi_awaddr;
+ wire \m_axi_awaddr[0]_0 ;
+ wire m_axi_awaddr_0_sn_1;
+ wire next;
+ wire next_pending;
+ wire next_pending_r_reg;
+ wire s_axburst_eq0;
+ wire s_axburst_eq1;
+ wire sel_first;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire sel_first_reg_2;
+ wire sel_first_reg_3;
+ wire sel_first_reg_4;
+ wire si_rs_awvalid;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+ wire wrap_cmd_0_n_14;
+ wire [3:0]\wrap_cnt_r_reg[3] ;
+ wire wrap_next_pending;
+ wire [3:0]\wrap_second_len_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+
+ assign m_axi_awaddr_0_sn_1 = m_axi_awaddr_0_sp_1;
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd incr_cmd_0
+ (.E(E),
+ .Q(axaddr_wrap),
+ .S(S),
+ .aclk(aclk),
+ .axaddr_incr(axaddr_incr),
+ .\axaddr_incr_reg[11]_0 (\axaddr_incr_reg[11] ),
+ .\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
+ .\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ),
+ .\axlen_cnt_reg[2]_1 ({\axlen_cnt_reg[2]_1 [18:12],\axlen_cnt_reg[2]_1 [10:0]}),
+ .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3]_0 ),
+ .\axlen_cnt_reg[4]_0 (\axaddr_wrap_reg[0] ),
+ .\axlen_cnt_reg[8]_0 (\axlen_cnt_reg[8] ),
+ .incr_next_pending(incr_next_pending),
+ .m_axi_awaddr(m_axi_awaddr),
+ .\m_axi_awaddr[0]_0 (\m_axi_awaddr[0]_0 ),
+ .m_axi_awaddr_0_sp_1(m_axi_awaddr_0_sn_1),
+ .\m_payload_i_reg[39] (incr_cmd_0_n_3),
+ .next(next),
+ .next_pending_r_reg_0(next_pending_r_reg),
+ .sel_first(sel_first),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(sel_first_reg_1),
+ .sel_first_reg_1(sel_first_reg_2),
+ .sel_first_reg_2(sel_first_reg_3),
+ .si_rs_awvalid(si_rs_awvalid),
+ .wrap_next_pending(wrap_next_pending));
+ LUT3 #(
+ .INIT(8'hB8))
+ \memory_reg[3][0]_srl4_i_3
+ (.I0(s_axburst_eq1),
+ .I1(\axlen_cnt_reg[2]_1 [15]),
+ .I2(s_axburst_eq0),
+ .O(next_pending));
+ FDRE s_axburst_eq0_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(incr_cmd_0_n_3),
+ .Q(s_axburst_eq0),
+ .R(1'b0));
+ FDRE s_axburst_eq1_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(wrap_cmd_0_n_14),
+ .Q(s_axburst_eq1),
+ .R(1'b0));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_i),
+ .Q(sel_first_reg_0),
+ .R(1'b0));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd wrap_cmd_0
+ (.D(D),
+ .E(E),
+ .Q({\axaddr_wrap_reg[11] ,axaddr_wrap}),
+ .aclk(aclk),
+ .\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
+ .\axaddr_wrap_reg[0]_0 (\axaddr_wrap_reg[0] ),
+ .\axlen_cnt_reg[0]_0 (Q),
+ .\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2]_0 ),
+ .\axlen_cnt_reg[2]_1 ({\axlen_cnt_reg[2]_1 [18:17],\axlen_cnt_reg[2]_1 [15],\axlen_cnt_reg[2]_1 [13:0]}),
+ .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ),
+ .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_1 ),
+ .incr_next_pending(incr_next_pending),
+ .\m_payload_i_reg[39] (wrap_cmd_0_n_14),
+ .next(next),
+ .next_pending_r_reg_0(next_pending_r_reg),
+ .sel_first(sel_first),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(sel_first_reg_4),
+ .\wrap_boundary_axaddr_r_reg[6]_0 (\wrap_boundary_axaddr_r_reg[6] ),
+ .\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
+ .wrap_next_pending(wrap_next_pending),
+ .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
+ .\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_cmd_translator" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1
+ (sel_first_reg_0,
+ sel_first_reg_1,
+ sel_first_reg_2,
+ O,
+ \axaddr_wrap_reg[7] ,
+ \axaddr_wrap_reg[11] ,
+ \axaddr_wrap_reg[11]_0 ,
+ \axaddr_incr_reg[11] ,
+ \axlen_cnt_reg[2] ,
+ r_rlast,
+ next_pending,
+ \axlen_cnt_reg[4] ,
+ m_axi_araddr,
+ sel_first_reg_3,
+ \axaddr_offset_r_reg[3] ,
+ \wrap_second_len_r_reg[3] ,
+ \wrap_boundary_axaddr_r_reg[11] ,
+ S,
+ aclk,
+ sel_first_i,
+ sel_first_reg_4,
+ sel_first_reg_5,
+ \axlen_cnt_reg[3] ,
+ next_pending_r_reg,
+ E,
+ r_push,
+ \axlen_cnt_reg[3]_0 ,
+ \axaddr_incr_reg[11]_0 ,
+ \axaddr_incr_reg[7] ,
+ \axaddr_incr_reg[3] ,
+ m_axi_araddr_0_sp_1,
+ \m_axi_araddr[0]_0 ,
+ Q,
+ si_rs_arvalid,
+ \axaddr_wrap_reg[0] ,
+ \axlen_cnt_reg[8] ,
+ axaddr_offset,
+ D,
+ \wrap_cnt_r_reg[3] ,
+ \wrap_boundary_axaddr_r_reg[6] ,
+ \axaddr_wrap_reg[11]_1 ,
+ \axaddr_incr_reg[0] ,
+ m_axi_arready);
+ output sel_first_reg_0;
+ output sel_first_reg_1;
+ output sel_first_reg_2;
+ output [3:0]O;
+ output [3:0]\axaddr_wrap_reg[7] ;
+ output [3:0]\axaddr_wrap_reg[11] ;
+ output [0:0]\axaddr_wrap_reg[11]_0 ;
+ output [0:0]\axaddr_incr_reg[11] ;
+ output \axlen_cnt_reg[2] ;
+ output r_rlast;
+ output next_pending;
+ output \axlen_cnt_reg[4] ;
+ output [10:0]m_axi_araddr;
+ output sel_first_reg_3;
+ output [3:0]\axaddr_offset_r_reg[3] ;
+ output [3:0]\wrap_second_len_r_reg[3] ;
+ output [11:0]\wrap_boundary_axaddr_r_reg[11] ;
+ output [3:0]S;
+ input aclk;
+ input sel_first_i;
+ input sel_first_reg_4;
+ input sel_first_reg_5;
+ input [19:0]\axlen_cnt_reg[3] ;
+ input next_pending_r_reg;
+ input [0:0]E;
+ input r_push;
+ input \axlen_cnt_reg[3]_0 ;
+ input [3:0]\axaddr_incr_reg[11]_0 ;
+ input [3:0]\axaddr_incr_reg[7] ;
+ input [3:0]\axaddr_incr_reg[3] ;
+ input m_axi_araddr_0_sp_1;
+ input \m_axi_araddr[0]_0 ;
+ input [1:0]Q;
+ input si_rs_arvalid;
+ input \axaddr_wrap_reg[0] ;
+ input \axlen_cnt_reg[8] ;
+ input [3:0]axaddr_offset;
+ input [3:0]D;
+ input [3:0]\wrap_cnt_r_reg[3] ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+ input [11:0]\axaddr_wrap_reg[11]_1 ;
+ input [0:0]\axaddr_incr_reg[0] ;
+ input m_axi_arready;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [3:0]O;
+ wire [1:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire [0:0]\axaddr_incr_reg[0] ;
+ wire [0:0]\axaddr_incr_reg[11] ;
+ wire [3:0]\axaddr_incr_reg[11]_0 ;
+ wire [3:0]\axaddr_incr_reg[3] ;
+ wire [3:0]\axaddr_incr_reg[7] ;
+ wire [3:0]axaddr_offset;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire \axaddr_wrap_reg[0] ;
+ wire [3:0]\axaddr_wrap_reg[11] ;
+ wire [0:0]\axaddr_wrap_reg[11]_0 ;
+ wire [11:0]\axaddr_wrap_reg[11]_1 ;
+ wire [3:0]\axaddr_wrap_reg[7] ;
+ wire \axlen_cnt_reg[2] ;
+ wire [19:0]\axlen_cnt_reg[3] ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire \axlen_cnt_reg[4] ;
+ wire \axlen_cnt_reg[8] ;
+ wire incr_cmd_0_n_3;
+ wire incr_next_pending;
+ wire [10:0]m_axi_araddr;
+ wire \m_axi_araddr[0]_0 ;
+ wire m_axi_araddr_0_sn_1;
+ wire m_axi_arready;
+ wire next_pending;
+ wire next_pending_r_reg;
+ wire r_push;
+ wire r_rlast;
+ wire s_axburst_eq0;
+ wire s_axburst_eq1;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire sel_first_reg_2;
+ wire sel_first_reg_3;
+ wire sel_first_reg_4;
+ wire sel_first_reg_5;
+ wire si_rs_arvalid;
+ wire [11:0]\wrap_boundary_axaddr_r_reg[11] ;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
+ wire wrap_cmd_0_n_10;
+ wire wrap_cmd_0_n_11;
+ wire wrap_cmd_0_n_12;
+ wire wrap_cmd_0_n_13;
+ wire wrap_cmd_0_n_14;
+ wire wrap_cmd_0_n_15;
+ wire wrap_cmd_0_n_16;
+ wire wrap_cmd_0_n_17;
+ wire wrap_cmd_0_n_26;
+ wire wrap_cmd_0_n_7;
+ wire wrap_cmd_0_n_8;
+ wire wrap_cmd_0_n_9;
+ wire [3:0]\wrap_cnt_r_reg[3] ;
+ wire wrap_next_pending;
+ wire [3:0]\wrap_second_len_r_reg[3] ;
+
+ assign m_axi_araddr_0_sn_1 = m_axi_araddr_0_sp_1;
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \FSM_sequential_state[1]_i_2
+ (.I0(s_axburst_eq1),
+ .I1(\axlen_cnt_reg[3] [15]),
+ .I2(s_axburst_eq0),
+ .O(next_pending));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2 incr_cmd_0
+ (.E(E),
+ .Q({wrap_cmd_0_n_7,wrap_cmd_0_n_8,wrap_cmd_0_n_9,wrap_cmd_0_n_10,wrap_cmd_0_n_11,wrap_cmd_0_n_12,wrap_cmd_0_n_13,wrap_cmd_0_n_14,wrap_cmd_0_n_15,wrap_cmd_0_n_16,wrap_cmd_0_n_17}),
+ .S(S),
+ .aclk(aclk),
+ .\axaddr_incr_reg[0]_0 (\axaddr_incr_reg[0] ),
+ .\axaddr_incr_reg[11]_0 (\axaddr_incr_reg[11] ),
+ .\axaddr_incr_reg[11]_1 (\axaddr_incr_reg[11]_0 ),
+ .\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
+ .\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7] ),
+ .\axlen_cnt_reg[0]_0 (Q),
+ .\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ),
+ .\axlen_cnt_reg[2]_1 ({\axlen_cnt_reg[3] [18:12],\axlen_cnt_reg[3] [10:0]}),
+ .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3]_0 ),
+ .\axlen_cnt_reg[4]_0 (\axaddr_wrap_reg[0] ),
+ .\axlen_cnt_reg[8]_0 (\axlen_cnt_reg[8] ),
+ .incr_next_pending(incr_next_pending),
+ .m_axi_araddr(m_axi_araddr),
+ .\m_axi_araddr[0]_0 (\m_axi_araddr[0]_0 ),
+ .\m_axi_araddr[0]_1 (sel_first_reg_2),
+ .m_axi_araddr_0_sp_1(m_axi_araddr_0_sn_1),
+ .m_axi_arready(m_axi_arready),
+ .\m_payload_i_reg[39] (incr_cmd_0_n_3),
+ .next_pending_r_reg_0(next_pending_r_reg),
+ .r_push(r_push),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(sel_first_reg_1),
+ .sel_first_reg_1(sel_first_reg_3),
+ .sel_first_reg_2(sel_first_reg_4),
+ .si_rs_arvalid(si_rs_arvalid),
+ .wrap_next_pending(wrap_next_pending));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT3 #(
+ .INIT(8'h1D))
+ r_rlast_r_i_1
+ (.I0(s_axburst_eq0),
+ .I1(\axlen_cnt_reg[3] [15]),
+ .I2(s_axburst_eq1),
+ .O(r_rlast));
+ FDRE s_axburst_eq0_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(incr_cmd_0_n_3),
+ .Q(s_axburst_eq0),
+ .R(1'b0));
+ FDRE s_axburst_eq1_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(wrap_cmd_0_n_26),
+ .Q(s_axburst_eq1),
+ .R(1'b0));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_i),
+ .Q(sel_first_reg_0),
+ .R(1'b0));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3 wrap_cmd_0
+ (.D(D),
+ .E(E),
+ .O(O),
+ .Q({\axaddr_wrap_reg[11]_0 ,wrap_cmd_0_n_7,wrap_cmd_0_n_8,wrap_cmd_0_n_9,wrap_cmd_0_n_10,wrap_cmd_0_n_11,wrap_cmd_0_n_12,wrap_cmd_0_n_13,wrap_cmd_0_n_14,wrap_cmd_0_n_15,wrap_cmd_0_n_16,wrap_cmd_0_n_17}),
+ .aclk(aclk),
+ .axaddr_offset(axaddr_offset),
+ .\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
+ .\axaddr_wrap_reg[0]_0 (\axaddr_wrap_reg[0] ),
+ .\axaddr_wrap_reg[11]_0 (\axaddr_wrap_reg[11] ),
+ .\axaddr_wrap_reg[11]_1 (\axaddr_wrap_reg[11]_1 ),
+ .\axaddr_wrap_reg[7]_0 (\axaddr_wrap_reg[7] ),
+ .\axlen_cnt_reg[3]_0 ({\axlen_cnt_reg[3] [19:15],\axlen_cnt_reg[3] [13:7]}),
+ .\axlen_cnt_reg[3]_1 (Q[1]),
+ .\axlen_cnt_reg[4]_0 (\axlen_cnt_reg[4] ),
+ .incr_next_pending(incr_next_pending),
+ .\m_payload_i_reg[39] (wrap_cmd_0_n_26),
+ .next_pending_r_reg_0(next_pending_r_reg),
+ .r_push(r_push),
+ .sel_first_i(sel_first_i),
+ .sel_first_reg_0(sel_first_reg_2),
+ .sel_first_reg_1(sel_first_reg_5),
+ .si_rs_arvalid(si_rs_arvalid),
+ .\wrap_boundary_axaddr_r_reg[11]_0 (\wrap_boundary_axaddr_r_reg[11] ),
+ .\wrap_boundary_axaddr_r_reg[6]_0 (\wrap_boundary_axaddr_r_reg[6] ),
+ .\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
+ .wrap_next_pending(wrap_next_pending),
+ .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd
+ (incr_next_pending,
+ sel_first_reg_0,
+ \axaddr_incr_reg[11]_0 ,
+ \m_payload_i_reg[39] ,
+ \axlen_cnt_reg[2]_0 ,
+ m_axi_awaddr,
+ sel_first_reg_1,
+ S,
+ aclk,
+ sel_first_reg_2,
+ sel_first_i,
+ \axlen_cnt_reg[2]_1 ,
+ wrap_next_pending,
+ E,
+ next_pending_r_reg_0,
+ next,
+ \axlen_cnt_reg[0]_0 ,
+ si_rs_awvalid,
+ \axlen_cnt_reg[3]_0 ,
+ axaddr_incr,
+ Q,
+ m_axi_awaddr_0_sp_1,
+ \m_axi_awaddr[0]_0 ,
+ sel_first,
+ \axlen_cnt_reg[4]_0 ,
+ \axlen_cnt_reg[8]_0 );
+ output incr_next_pending;
+ output sel_first_reg_0;
+ output [0:0]\axaddr_incr_reg[11]_0 ;
+ output \m_payload_i_reg[39] ;
+ output \axlen_cnt_reg[2]_0 ;
+ output [10:0]m_axi_awaddr;
+ output sel_first_reg_1;
+ output [3:0]S;
+ input aclk;
+ input sel_first_reg_2;
+ input sel_first_i;
+ input [17:0]\axlen_cnt_reg[2]_1 ;
+ input wrap_next_pending;
+ input [0:0]E;
+ input next_pending_r_reg_0;
+ input next;
+ input [1:0]\axlen_cnt_reg[0]_0 ;
+ input si_rs_awvalid;
+ input \axlen_cnt_reg[3]_0 ;
+ input [11:0]axaddr_incr;
+ input [10:0]Q;
+ input m_axi_awaddr_0_sp_1;
+ input \m_axi_awaddr[0]_0 ;
+ input sel_first;
+ input \axlen_cnt_reg[4]_0 ;
+ input \axlen_cnt_reg[8]_0 ;
+
+ wire [0:0]E;
+ wire [10:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire [11:0]axaddr_incr;
+ wire \axaddr_incr[11]_i_1_n_0 ;
+ wire \axaddr_incr[3]_i_12_n_0 ;
+ wire \axaddr_incr[3]_i_13_n_0 ;
+ wire \axaddr_incr[3]_i_14_n_0 ;
+ wire \axaddr_incr[3]_i_15_n_0 ;
+ wire [0:0]\axaddr_incr_reg[11]_0 ;
+ wire \axaddr_incr_reg[11]_i_4_n_1 ;
+ wire \axaddr_incr_reg[11]_i_4_n_2 ;
+ wire \axaddr_incr_reg[11]_i_4_n_3 ;
+ wire \axaddr_incr_reg[11]_i_4_n_4 ;
+ wire \axaddr_incr_reg[11]_i_4_n_5 ;
+ wire \axaddr_incr_reg[11]_i_4_n_6 ;
+ wire \axaddr_incr_reg[11]_i_4_n_7 ;
+ wire \axaddr_incr_reg[3]_i_3_n_0 ;
+ wire \axaddr_incr_reg[3]_i_3_n_1 ;
+ wire \axaddr_incr_reg[3]_i_3_n_2 ;
+ wire \axaddr_incr_reg[3]_i_3_n_3 ;
+ wire \axaddr_incr_reg[3]_i_3_n_4 ;
+ wire \axaddr_incr_reg[3]_i_3_n_5 ;
+ wire \axaddr_incr_reg[3]_i_3_n_6 ;
+ wire \axaddr_incr_reg[3]_i_3_n_7 ;
+ wire \axaddr_incr_reg[7]_i_3_n_0 ;
+ wire \axaddr_incr_reg[7]_i_3_n_1 ;
+ wire \axaddr_incr_reg[7]_i_3_n_2 ;
+ wire \axaddr_incr_reg[7]_i_3_n_3 ;
+ wire \axaddr_incr_reg[7]_i_3_n_4 ;
+ wire \axaddr_incr_reg[7]_i_3_n_5 ;
+ wire \axaddr_incr_reg[7]_i_3_n_6 ;
+ wire \axaddr_incr_reg[7]_i_3_n_7 ;
+ wire \axaddr_incr_reg_n_0_[0] ;
+ wire \axaddr_incr_reg_n_0_[10] ;
+ wire \axaddr_incr_reg_n_0_[1] ;
+ wire \axaddr_incr_reg_n_0_[2] ;
+ wire \axaddr_incr_reg_n_0_[3] ;
+ wire \axaddr_incr_reg_n_0_[4] ;
+ wire \axaddr_incr_reg_n_0_[5] ;
+ wire \axaddr_incr_reg_n_0_[6] ;
+ wire \axaddr_incr_reg_n_0_[7] ;
+ wire \axaddr_incr_reg_n_0_[8] ;
+ wire \axaddr_incr_reg_n_0_[9] ;
+ wire [8:0]axlen_cnt;
+ wire \axlen_cnt[0]_i_1__0_n_0 ;
+ wire \axlen_cnt[1]_i_1__0_n_0 ;
+ wire \axlen_cnt[2]_i_1__0_n_0 ;
+ wire \axlen_cnt[3]_i_2_n_0 ;
+ wire \axlen_cnt[4]_i_1__0_n_0 ;
+ wire \axlen_cnt[5]_i_1_n_0 ;
+ wire \axlen_cnt[6]_i_1_n_0 ;
+ wire \axlen_cnt[7]_i_1_n_0 ;
+ wire \axlen_cnt[8]_i_2_n_0 ;
+ wire \axlen_cnt[8]_i_3_n_0 ;
+ wire [1:0]\axlen_cnt_reg[0]_0 ;
+ wire \axlen_cnt_reg[2]_0 ;
+ wire [17:0]\axlen_cnt_reg[2]_1 ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire \axlen_cnt_reg[4]_0 ;
+ wire \axlen_cnt_reg[8]_0 ;
+ wire incr_next_pending;
+ wire [10:0]m_axi_awaddr;
+ wire \m_axi_awaddr[0]_0 ;
+ wire m_axi_awaddr_0_sn_1;
+ wire \m_payload_i_reg[39] ;
+ wire next;
+ wire next_pending_r_i_3_n_0;
+ wire next_pending_r_i_6_n_0;
+ wire next_pending_r_i_7_n_0;
+ wire next_pending_r_i_8_n_0;
+ wire next_pending_r_reg_0;
+ wire next_pending_r_reg_n_0;
+ wire [11:0]p_1_in;
+ wire sel_first;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire sel_first_reg_2;
+ wire si_rs_awvalid;
+ wire wrap_next_pending;
+ wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
+
+ assign m_axi_awaddr_0_sn_1 = m_axi_awaddr_0_sp_1;
+ (* SOFT_HLUTNM = "soft_lutpair123" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[0]_i_1
+ (.I0(axaddr_incr[0]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3_n_7 ),
+ .O(p_1_in[0]));
+ (* SOFT_HLUTNM = "soft_lutpair123" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[10]_i_1
+ (.I0(axaddr_incr[10]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4_n_5 ),
+ .O(p_1_in[10]));
+ LUT2 #(
+ .INIT(4'hE))
+ \axaddr_incr[11]_i_1
+ (.I0(sel_first_reg_0),
+ .I1(next),
+ .O(\axaddr_incr[11]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair122" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[11]_i_2
+ (.I0(axaddr_incr[11]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4_n_4 ),
+ .O(p_1_in[11]));
+ (* SOFT_HLUTNM = "soft_lutpair124" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[1]_i_1
+ (.I0(axaddr_incr[1]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3_n_6 ),
+ .O(p_1_in[1]));
+ (* SOFT_HLUTNM = "soft_lutpair125" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[2]_i_1
+ (.I0(axaddr_incr[2]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3_n_5 ),
+ .O(p_1_in[2]));
+ (* SOFT_HLUTNM = "soft_lutpair126" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[3]_i_1
+ (.I0(axaddr_incr[3]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3_n_4 ),
+ .O(p_1_in[3]));
+ LUT4 #(
+ .INIT(16'h060A))
+ \axaddr_incr[3]_i_10
+ (.I0(\axlen_cnt_reg[2]_1 [1]),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .I3(next),
+ .O(S[1]));
+ LUT4 #(
+ .INIT(16'h0102))
+ \axaddr_incr[3]_i_11
+ (.I0(\axlen_cnt_reg[2]_1 [0]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .I3(next),
+ .O(S[0]));
+ LUT3 #(
+ .INIT(8'h6A))
+ \axaddr_incr[3]_i_12
+ (.I0(\axaddr_incr_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .O(\axaddr_incr[3]_i_12_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_incr[3]_i_13
+ (.I0(\axaddr_incr_reg_n_0_[2] ),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_incr[3]_i_13_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_incr[3]_i_14
+ (.I0(\axaddr_incr_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .O(\axaddr_incr[3]_i_14_n_0 ));
+ LUT3 #(
+ .INIT(8'hA9))
+ \axaddr_incr[3]_i_15
+ (.I0(\axaddr_incr_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_incr[3]_i_15_n_0 ));
+ LUT4 #(
+ .INIT(16'h6AAA))
+ \axaddr_incr[3]_i_8
+ (.I0(\axlen_cnt_reg[2]_1 [3]),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .I3(next),
+ .O(S[3]));
+ LUT4 #(
+ .INIT(16'h262A))
+ \axaddr_incr[3]_i_9
+ (.I0(\axlen_cnt_reg[2]_1 [2]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .I3(next),
+ .O(S[2]));
+ (* SOFT_HLUTNM = "soft_lutpair121" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[4]_i_1
+ (.I0(axaddr_incr[4]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3_n_7 ),
+ .O(p_1_in[4]));
+ (* SOFT_HLUTNM = "soft_lutpair125" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[5]_i_1
+ (.I0(axaddr_incr[5]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3_n_6 ),
+ .O(p_1_in[5]));
+ (* SOFT_HLUTNM = "soft_lutpair122" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[6]_i_1
+ (.I0(axaddr_incr[6]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3_n_5 ),
+ .O(p_1_in[6]));
+ (* SOFT_HLUTNM = "soft_lutpair126" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[7]_i_1
+ (.I0(axaddr_incr[7]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3_n_4 ),
+ .O(p_1_in[7]));
+ (* SOFT_HLUTNM = "soft_lutpair124" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[8]_i_1
+ (.I0(axaddr_incr[8]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4_n_7 ),
+ .O(p_1_in[8]));
+ (* SOFT_HLUTNM = "soft_lutpair121" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[9]_i_1
+ (.I0(axaddr_incr[9]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4_n_6 ),
+ .O(p_1_in[9]));
+ FDRE \axaddr_incr_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[0]),
+ .Q(\axaddr_incr_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[10]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[10]),
+ .Q(\axaddr_incr_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[11]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[11]),
+ .Q(\axaddr_incr_reg[11]_0 ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[11]_i_4
+ (.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
+ .CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
+ .S({\axaddr_incr_reg[11]_0 ,\axaddr_incr_reg_n_0_[10] ,\axaddr_incr_reg_n_0_[9] ,\axaddr_incr_reg_n_0_[8] }));
+ FDRE \axaddr_incr_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[1]),
+ .Q(\axaddr_incr_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[2]),
+ .Q(\axaddr_incr_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[3]),
+ .Q(\axaddr_incr_reg_n_0_[3] ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[3]_i_3
+ (.CI(1'b0),
+ .CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg_n_0_[1] ,\axaddr_incr_reg_n_0_[0] }),
+ .O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
+ .S({\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 ,\axaddr_incr[3]_i_15_n_0 }));
+ FDRE \axaddr_incr_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[4]),
+ .Q(\axaddr_incr_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[5]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[5]),
+ .Q(\axaddr_incr_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[6]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[6]),
+ .Q(\axaddr_incr_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[7]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[7]),
+ .Q(\axaddr_incr_reg_n_0_[7] ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[7]_i_3
+ (.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
+ .CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
+ .S({\axaddr_incr_reg_n_0_[7] ,\axaddr_incr_reg_n_0_[6] ,\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg_n_0_[4] }));
+ FDRE \axaddr_incr_reg[8]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[8]),
+ .Q(\axaddr_incr_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[9]
+ (.C(aclk),
+ .CE(\axaddr_incr[11]_i_1_n_0 ),
+ .D(p_1_in[9]),
+ .Q(\axaddr_incr_reg_n_0_[9] ),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h444F444444444444))
+ \axlen_cnt[0]_i_1__0
+ (.I0(axlen_cnt[0]),
+ .I1(\axlen_cnt_reg[2]_0 ),
+ .I2(\axlen_cnt_reg[0]_0 [1]),
+ .I3(\axlen_cnt_reg[0]_0 [0]),
+ .I4(si_rs_awvalid),
+ .I5(\axlen_cnt_reg[2]_1 [15]),
+ .O(\axlen_cnt[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair118" *)
+ LUT5 #(
+ .INIT(32'hFF909090))
+ \axlen_cnt[1]_i_1__0
+ (.I0(axlen_cnt[0]),
+ .I1(axlen_cnt[1]),
+ .I2(\axlen_cnt_reg[2]_0 ),
+ .I3(E),
+ .I4(\axlen_cnt_reg[2]_1 [16]),
+ .O(\axlen_cnt[1]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFE100E100E100))
+ \axlen_cnt[2]_i_1__0
+ (.I0(axlen_cnt[1]),
+ .I1(axlen_cnt[0]),
+ .I2(axlen_cnt[2]),
+ .I3(\axlen_cnt_reg[2]_0 ),
+ .I4(E),
+ .I5(\axlen_cnt_reg[2]_1 [17]),
+ .O(\axlen_cnt[2]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFE010000))
+ \axlen_cnt[3]_i_2
+ (.I0(axlen_cnt[2]),
+ .I1(axlen_cnt[0]),
+ .I2(axlen_cnt[1]),
+ .I3(axlen_cnt[3]),
+ .I4(\axlen_cnt_reg[2]_0 ),
+ .I5(\axlen_cnt_reg[3]_0 ),
+ .O(\axlen_cnt[3]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFE0001))
+ \axlen_cnt[4]_i_1__0
+ (.I0(axlen_cnt[3]),
+ .I1(axlen_cnt[1]),
+ .I2(axlen_cnt[0]),
+ .I3(axlen_cnt[2]),
+ .I4(axlen_cnt[4]),
+ .O(\axlen_cnt[4]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFE00000001))
+ \axlen_cnt[5]_i_1
+ (.I0(axlen_cnt[4]),
+ .I1(axlen_cnt[2]),
+ .I2(axlen_cnt[0]),
+ .I3(axlen_cnt[1]),
+ .I4(axlen_cnt[3]),
+ .I5(axlen_cnt[5]),
+ .O(\axlen_cnt[5]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair120" *)
+ LUT2 #(
+ .INIT(4'h9))
+ \axlen_cnt[6]_i_1
+ (.I0(\axlen_cnt[8]_i_3_n_0 ),
+ .I1(axlen_cnt[6]),
+ .O(\axlen_cnt[6]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair120" *)
+ LUT3 #(
+ .INIT(8'hE1))
+ \axlen_cnt[7]_i_1
+ (.I0(axlen_cnt[6]),
+ .I1(\axlen_cnt[8]_i_3_n_0 ),
+ .I2(axlen_cnt[7]),
+ .O(\axlen_cnt[7]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair119" *)
+ LUT4 #(
+ .INIT(16'hFE01))
+ \axlen_cnt[8]_i_2
+ (.I0(axlen_cnt[7]),
+ .I1(\axlen_cnt[8]_i_3_n_0 ),
+ .I2(axlen_cnt[6]),
+ .I3(axlen_cnt[8]),
+ .O(\axlen_cnt[8]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFFE))
+ \axlen_cnt[8]_i_3
+ (.I0(axlen_cnt[4]),
+ .I1(axlen_cnt[2]),
+ .I2(axlen_cnt[0]),
+ .I3(axlen_cnt[1]),
+ .I4(axlen_cnt[3]),
+ .I5(axlen_cnt[5]),
+ .O(\axlen_cnt[8]_i_3_n_0 ));
+ FDRE \axlen_cnt_reg[0]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[0]_i_1__0_n_0 ),
+ .Q(axlen_cnt[0]),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[1]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[1]_i_1__0_n_0 ),
+ .Q(axlen_cnt[1]),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[2]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[2]_i_1__0_n_0 ),
+ .Q(axlen_cnt[2]),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[3]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[3]_i_2_n_0 ),
+ .Q(axlen_cnt[3]),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[4]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[4]_i_1__0_n_0 ),
+ .Q(axlen_cnt[4]),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[5]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[5]_i_1_n_0 ),
+ .Q(axlen_cnt[5]),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[6]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[6]_i_1_n_0 ),
+ .Q(axlen_cnt[6]),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[7]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[7]_i_1_n_0 ),
+ .Q(axlen_cnt[7]),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[8]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[8]_i_2_n_0 ),
+ .Q(axlen_cnt[8]),
+ .R(\axlen_cnt_reg[8]_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[0]_INST_0
+ (.I0(Q[0]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[0] ),
+ .I4(\axlen_cnt_reg[2]_1 [0]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[0]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[10]_INST_0
+ (.I0(Q[10]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[10] ),
+ .I4(\axlen_cnt_reg[2]_1 [10]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[10]));
+ LUT4 #(
+ .INIT(16'hFB0B))
+ \m_axi_awaddr[11]_INST_0_i_3
+ (.I0(sel_first_reg_0),
+ .I1(\axlen_cnt_reg[2]_1 [13]),
+ .I2(\axlen_cnt_reg[2]_1 [14]),
+ .I3(sel_first),
+ .O(sel_first_reg_1));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[1]_INST_0
+ (.I0(Q[1]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[1] ),
+ .I4(\axlen_cnt_reg[2]_1 [1]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[1]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[2]_INST_0
+ (.I0(Q[2]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[2] ),
+ .I4(\axlen_cnt_reg[2]_1 [2]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[2]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[3] ),
+ .I4(\axlen_cnt_reg[2]_1 [3]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[3]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[4] ),
+ .I4(\axlen_cnt_reg[2]_1 [4]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[4]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[5]_INST_0
+ (.I0(Q[5]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[5] ),
+ .I4(\axlen_cnt_reg[2]_1 [5]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[5]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[6]_INST_0
+ (.I0(Q[6]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[6] ),
+ .I4(\axlen_cnt_reg[2]_1 [6]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[6]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[7]_INST_0
+ (.I0(Q[7]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[7] ),
+ .I4(\axlen_cnt_reg[2]_1 [7]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[7]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[8]_INST_0
+ (.I0(Q[8]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[8] ),
+ .I4(\axlen_cnt_reg[2]_1 [8]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[8]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[9]_INST_0
+ (.I0(Q[9]),
+ .I1(m_axi_awaddr_0_sn_1),
+ .I2(\m_axi_awaddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[9] ),
+ .I4(\axlen_cnt_reg[2]_1 [9]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_awaddr[9]));
+ LUT6 #(
+ .INIT(64'hFFF0F2F2F0F0F2F2))
+ next_pending_r_i_1__0
+ (.I0(next_pending_r_reg_n_0),
+ .I1(E),
+ .I2(next_pending_r_reg_0),
+ .I3(next_pending_r_i_3_n_0),
+ .I4(next),
+ .I5(\axlen_cnt_reg[2]_0 ),
+ .O(incr_next_pending));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFEEF))
+ next_pending_r_i_3
+ (.I0(next_pending_r_i_6_n_0),
+ .I1(axlen_cnt[7]),
+ .I2(\axlen_cnt[8]_i_3_n_0 ),
+ .I3(axlen_cnt[6]),
+ .I4(axlen_cnt[8]),
+ .I5(next_pending_r_i_7_n_0),
+ .O(next_pending_r_i_3_n_0));
+ LUT6 #(
+ .INIT(64'h00000000FFFFFFFE))
+ next_pending_r_i_5
+ (.I0(next_pending_r_i_8_n_0),
+ .I1(axlen_cnt[2]),
+ .I2(axlen_cnt[1]),
+ .I3(axlen_cnt[4]),
+ .I4(axlen_cnt[3]),
+ .I5(E),
+ .O(\axlen_cnt_reg[2]_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFEEEB))
+ next_pending_r_i_6
+ (.I0(axlen_cnt[4]),
+ .I1(axlen_cnt[2]),
+ .I2(axlen_cnt[0]),
+ .I3(axlen_cnt[1]),
+ .I4(axlen_cnt[3]),
+ .I5(axlen_cnt[5]),
+ .O(next_pending_r_i_6_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair118" *)
+ LUT2 #(
+ .INIT(4'hB))
+ next_pending_r_i_7
+ (.I0(axlen_cnt[1]),
+ .I1(axlen_cnt[0]),
+ .O(next_pending_r_i_7_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair119" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ next_pending_r_i_8
+ (.I0(axlen_cnt[6]),
+ .I1(axlen_cnt[5]),
+ .I2(axlen_cnt[8]),
+ .I3(axlen_cnt[7]),
+ .O(next_pending_r_i_8_n_0));
+ FDRE next_pending_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(incr_next_pending),
+ .Q(next_pending_r_reg_n_0),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hBA8A))
+ s_axburst_eq0_i_1
+ (.I0(incr_next_pending),
+ .I1(sel_first_i),
+ .I2(\axlen_cnt_reg[2]_1 [14]),
+ .I3(wrap_next_pending),
+ .O(\m_payload_i_reg[39] ));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_reg_2),
+ .Q(sel_first_reg_0),
+ .R(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_incr_cmd" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2
+ (incr_next_pending,
+ sel_first_reg_0,
+ \axaddr_incr_reg[11]_0 ,
+ \m_payload_i_reg[39] ,
+ \axlen_cnt_reg[2]_0 ,
+ m_axi_araddr,
+ sel_first_reg_1,
+ S,
+ aclk,
+ sel_first_reg_2,
+ sel_first_i,
+ \axlen_cnt_reg[2]_1 ,
+ wrap_next_pending,
+ E,
+ next_pending_r_reg_0,
+ r_push,
+ \axlen_cnt_reg[3]_0 ,
+ \axaddr_incr_reg[11]_1 ,
+ \axaddr_incr_reg[7]_0 ,
+ \axaddr_incr_reg[3]_0 ,
+ Q,
+ m_axi_araddr_0_sp_1,
+ \m_axi_araddr[0]_0 ,
+ \m_axi_araddr[0]_1 ,
+ \axlen_cnt_reg[0]_0 ,
+ si_rs_arvalid,
+ \axlen_cnt_reg[4]_0 ,
+ \axlen_cnt_reg[8]_0 ,
+ \axaddr_incr_reg[0]_0 ,
+ m_axi_arready);
+ output incr_next_pending;
+ output sel_first_reg_0;
+ output [0:0]\axaddr_incr_reg[11]_0 ;
+ output \m_payload_i_reg[39] ;
+ output \axlen_cnt_reg[2]_0 ;
+ output [10:0]m_axi_araddr;
+ output sel_first_reg_1;
+ output [3:0]S;
+ input aclk;
+ input sel_first_reg_2;
+ input sel_first_i;
+ input [17:0]\axlen_cnt_reg[2]_1 ;
+ input wrap_next_pending;
+ input [0:0]E;
+ input next_pending_r_reg_0;
+ input r_push;
+ input \axlen_cnt_reg[3]_0 ;
+ input [3:0]\axaddr_incr_reg[11]_1 ;
+ input [3:0]\axaddr_incr_reg[7]_0 ;
+ input [3:0]\axaddr_incr_reg[3]_0 ;
+ input [10:0]Q;
+ input m_axi_araddr_0_sp_1;
+ input \m_axi_araddr[0]_0 ;
+ input \m_axi_araddr[0]_1 ;
+ input [1:0]\axlen_cnt_reg[0]_0 ;
+ input si_rs_arvalid;
+ input \axlen_cnt_reg[4]_0 ;
+ input \axlen_cnt_reg[8]_0 ;
+ input [0:0]\axaddr_incr_reg[0]_0 ;
+ input m_axi_arready;
+
+ wire [0:0]E;
+ wire [10:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire \axaddr_incr[0]_i_1__0_n_0 ;
+ wire \axaddr_incr[10]_i_1__0_n_0 ;
+ wire \axaddr_incr[11]_i_2__0_n_0 ;
+ wire \axaddr_incr[1]_i_1__0_n_0 ;
+ wire \axaddr_incr[2]_i_1__0_n_0 ;
+ wire \axaddr_incr[3]_i_12_n_0 ;
+ wire \axaddr_incr[3]_i_13_n_0 ;
+ wire \axaddr_incr[3]_i_14_n_0 ;
+ wire \axaddr_incr[3]_i_15_n_0 ;
+ wire \axaddr_incr[3]_i_1__0_n_0 ;
+ wire \axaddr_incr[4]_i_1__0_n_0 ;
+ wire \axaddr_incr[5]_i_1__0_n_0 ;
+ wire \axaddr_incr[6]_i_1__0_n_0 ;
+ wire \axaddr_incr[7]_i_1__0_n_0 ;
+ wire \axaddr_incr[8]_i_1__0_n_0 ;
+ wire \axaddr_incr[9]_i_1__0_n_0 ;
+ wire [0:0]\axaddr_incr_reg[0]_0 ;
+ wire [0:0]\axaddr_incr_reg[11]_0 ;
+ wire [3:0]\axaddr_incr_reg[11]_1 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
+ wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
+ wire [3:0]\axaddr_incr_reg[3]_0 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
+ wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
+ wire [3:0]\axaddr_incr_reg[7]_0 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
+ wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
+ wire \axaddr_incr_reg_n_0_[0] ;
+ wire \axaddr_incr_reg_n_0_[10] ;
+ wire \axaddr_incr_reg_n_0_[1] ;
+ wire \axaddr_incr_reg_n_0_[2] ;
+ wire \axaddr_incr_reg_n_0_[3] ;
+ wire \axaddr_incr_reg_n_0_[4] ;
+ wire \axaddr_incr_reg_n_0_[5] ;
+ wire \axaddr_incr_reg_n_0_[6] ;
+ wire \axaddr_incr_reg_n_0_[7] ;
+ wire \axaddr_incr_reg_n_0_[8] ;
+ wire \axaddr_incr_reg_n_0_[9] ;
+ wire \axlen_cnt[0]_i_1__1_n_0 ;
+ wire \axlen_cnt[1]_i_1__2_n_0 ;
+ wire \axlen_cnt[2]_i_1__2_n_0 ;
+ wire \axlen_cnt[3]_i_2__1_n_0 ;
+ wire \axlen_cnt[4]_i_1__2_n_0 ;
+ wire \axlen_cnt[5]_i_1__0_n_0 ;
+ wire \axlen_cnt[6]_i_1__0_n_0 ;
+ wire \axlen_cnt[7]_i_1__0_n_0 ;
+ wire \axlen_cnt[8]_i_2__0_n_0 ;
+ wire \axlen_cnt[8]_i_3__0_n_0 ;
+ wire [1:0]\axlen_cnt_reg[0]_0 ;
+ wire \axlen_cnt_reg[2]_0 ;
+ wire [17:0]\axlen_cnt_reg[2]_1 ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire \axlen_cnt_reg[4]_0 ;
+ wire \axlen_cnt_reg[8]_0 ;
+ wire \axlen_cnt_reg_n_0_[0] ;
+ wire \axlen_cnt_reg_n_0_[1] ;
+ wire \axlen_cnt_reg_n_0_[2] ;
+ wire \axlen_cnt_reg_n_0_[3] ;
+ wire \axlen_cnt_reg_n_0_[4] ;
+ wire \axlen_cnt_reg_n_0_[5] ;
+ wire \axlen_cnt_reg_n_0_[6] ;
+ wire \axlen_cnt_reg_n_0_[7] ;
+ wire \axlen_cnt_reg_n_0_[8] ;
+ wire incr_next_pending;
+ wire [10:0]m_axi_araddr;
+ wire \m_axi_araddr[0]_0 ;
+ wire \m_axi_araddr[0]_1 ;
+ wire m_axi_araddr_0_sn_1;
+ wire m_axi_arready;
+ wire \m_payload_i_reg[39] ;
+ wire next_pending_r_i_3__0_n_0;
+ wire next_pending_r_i_5__0_n_0;
+ wire next_pending_r_i_6__0_n_0;
+ wire next_pending_r_i_7__0_n_0;
+ wire next_pending_r_reg_0;
+ wire next_pending_r_reg_n_0;
+ wire r_push;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire sel_first_reg_2;
+ wire si_rs_arvalid;
+ wire wrap_next_pending;
+ wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
+
+ assign m_axi_araddr_0_sn_1 = m_axi_araddr_0_sp_1;
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[0]_i_1__0
+ (.I0(\axaddr_incr_reg[3]_0 [0]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
+ .O(\axaddr_incr[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[10]_i_1__0
+ (.I0(\axaddr_incr_reg[11]_1 [2]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
+ .O(\axaddr_incr[10]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[11]_i_2__0
+ (.I0(\axaddr_incr_reg[11]_1 [3]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
+ .O(\axaddr_incr[11]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[1]_i_1__0
+ (.I0(\axaddr_incr_reg[3]_0 [1]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
+ .O(\axaddr_incr[1]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[2]_i_1__0
+ (.I0(\axaddr_incr_reg[3]_0 [2]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
+ .O(\axaddr_incr[2]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h060A0A0A0A0A0A0A))
+ \axaddr_incr[3]_i_10
+ (.I0(\axlen_cnt_reg[2]_1 [1]),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .I3(m_axi_arready),
+ .I4(\axlen_cnt_reg[0]_0 [1]),
+ .I5(\axlen_cnt_reg[0]_0 [0]),
+ .O(S[1]));
+ LUT6 #(
+ .INIT(64'h0102020202020202))
+ \axaddr_incr[3]_i_11
+ (.I0(\axlen_cnt_reg[2]_1 [0]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .I3(m_axi_arready),
+ .I4(\axlen_cnt_reg[0]_0 [1]),
+ .I5(\axlen_cnt_reg[0]_0 [0]),
+ .O(S[0]));
+ LUT3 #(
+ .INIT(8'h6A))
+ \axaddr_incr[3]_i_12
+ (.I0(\axaddr_incr_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .O(\axaddr_incr[3]_i_12_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_incr[3]_i_13
+ (.I0(\axaddr_incr_reg_n_0_[2] ),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_incr[3]_i_13_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_incr[3]_i_14
+ (.I0(\axaddr_incr_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .O(\axaddr_incr[3]_i_14_n_0 ));
+ LUT3 #(
+ .INIT(8'hA9))
+ \axaddr_incr[3]_i_15
+ (.I0(\axaddr_incr_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_incr[3]_i_15_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[3]_i_1__0
+ (.I0(\axaddr_incr_reg[3]_0 [3]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
+ .O(\axaddr_incr[3]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h6AAAAAAAAAAAAAAA))
+ \axaddr_incr[3]_i_8
+ (.I0(\axlen_cnt_reg[2]_1 [3]),
+ .I1(\axlen_cnt_reg[2]_1 [11]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .I3(m_axi_arready),
+ .I4(\axlen_cnt_reg[0]_0 [1]),
+ .I5(\axlen_cnt_reg[0]_0 [0]),
+ .O(S[3]));
+ LUT6 #(
+ .INIT(64'h262A2A2A2A2A2A2A))
+ \axaddr_incr[3]_i_9
+ (.I0(\axlen_cnt_reg[2]_1 [2]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [11]),
+ .I3(m_axi_arready),
+ .I4(\axlen_cnt_reg[0]_0 [1]),
+ .I5(\axlen_cnt_reg[0]_0 [0]),
+ .O(S[2]));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[4]_i_1__0
+ (.I0(\axaddr_incr_reg[7]_0 [0]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
+ .O(\axaddr_incr[4]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[5]_i_1__0
+ (.I0(\axaddr_incr_reg[7]_0 [1]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
+ .O(\axaddr_incr[5]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[6]_i_1__0
+ (.I0(\axaddr_incr_reg[7]_0 [2]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
+ .O(\axaddr_incr[6]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[7]_i_1__0
+ (.I0(\axaddr_incr_reg[7]_0 [3]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
+ .O(\axaddr_incr[7]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[8]_i_1__0
+ (.I0(\axaddr_incr_reg[11]_1 [0]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
+ .O(\axaddr_incr[8]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_incr[9]_i_1__0
+ (.I0(\axaddr_incr_reg[11]_1 [1]),
+ .I1(sel_first_reg_0),
+ .I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
+ .O(\axaddr_incr[9]_i_1__0_n_0 ));
+ FDRE \axaddr_incr_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[0]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[10]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[10]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[11]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[11]_i_2__0_n_0 ),
+ .Q(\axaddr_incr_reg[11]_0 ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[11]_i_4__0
+ (.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
+ .CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
+ .S({\axaddr_incr_reg[11]_0 ,\axaddr_incr_reg_n_0_[10] ,\axaddr_incr_reg_n_0_[9] ,\axaddr_incr_reg_n_0_[8] }));
+ FDRE \axaddr_incr_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[1]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[2]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[3]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[3] ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[3]_i_3__0
+ (.CI(1'b0),
+ .CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg_n_0_[1] ,\axaddr_incr_reg_n_0_[0] }),
+ .O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
+ .S({\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 ,\axaddr_incr[3]_i_15_n_0 }));
+ FDRE \axaddr_incr_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[4]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[5]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[5]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[6]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[6]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[7]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[7]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[7] ),
+ .R(1'b0));
+ CARRY4 \axaddr_incr_reg[7]_i_3__0
+ (.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
+ .CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
+ .S({\axaddr_incr_reg_n_0_[7] ,\axaddr_incr_reg_n_0_[6] ,\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg_n_0_[4] }));
+ FDRE \axaddr_incr_reg[8]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[8]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \axaddr_incr_reg[9]
+ (.C(aclk),
+ .CE(\axaddr_incr_reg[0]_0 ),
+ .D(\axaddr_incr[9]_i_1__0_n_0 ),
+ .Q(\axaddr_incr_reg_n_0_[9] ),
+ .R(1'b0));
+ LUT5 #(
+ .INIT(32'h4F444444))
+ \axlen_cnt[0]_i_1__1
+ (.I0(\axlen_cnt_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg[2]_0 ),
+ .I2(\axlen_cnt_reg[0]_0 [1]),
+ .I3(si_rs_arvalid),
+ .I4(\axlen_cnt_reg[2]_1 [15]),
+ .O(\axlen_cnt[0]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT5 #(
+ .INIT(32'hFF909090))
+ \axlen_cnt[1]_i_1__2
+ (.I0(\axlen_cnt_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg_n_0_[1] ),
+ .I2(\axlen_cnt_reg[2]_0 ),
+ .I3(E),
+ .I4(\axlen_cnt_reg[2]_1 [16]),
+ .O(\axlen_cnt[1]_i_1__2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFE100E100E100))
+ \axlen_cnt[2]_i_1__2
+ (.I0(\axlen_cnt_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg_n_0_[0] ),
+ .I2(\axlen_cnt_reg_n_0_[2] ),
+ .I3(\axlen_cnt_reg[2]_0 ),
+ .I4(E),
+ .I5(\axlen_cnt_reg[2]_1 [17]),
+ .O(\axlen_cnt[2]_i_1__2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFE010000))
+ \axlen_cnt[3]_i_2__1
+ (.I0(\axlen_cnt_reg_n_0_[2] ),
+ .I1(\axlen_cnt_reg_n_0_[0] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[3] ),
+ .I4(\axlen_cnt_reg[2]_0 ),
+ .I5(\axlen_cnt_reg[3]_0 ),
+ .O(\axlen_cnt[3]_i_2__1_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFE0001))
+ \axlen_cnt[4]_i_1__2
+ (.I0(\axlen_cnt_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg_n_0_[1] ),
+ .I2(\axlen_cnt_reg_n_0_[0] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(\axlen_cnt_reg_n_0_[4] ),
+ .O(\axlen_cnt[4]_i_1__2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFE00000001))
+ \axlen_cnt[5]_i_1__0
+ (.I0(\axlen_cnt_reg_n_0_[4] ),
+ .I1(\axlen_cnt_reg_n_0_[2] ),
+ .I2(\axlen_cnt_reg_n_0_[0] ),
+ .I3(\axlen_cnt_reg_n_0_[1] ),
+ .I4(\axlen_cnt_reg_n_0_[3] ),
+ .I5(\axlen_cnt_reg_n_0_[5] ),
+ .O(\axlen_cnt[5]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT2 #(
+ .INIT(4'h9))
+ \axlen_cnt[6]_i_1__0
+ (.I0(\axlen_cnt[8]_i_3__0_n_0 ),
+ .I1(\axlen_cnt_reg_n_0_[6] ),
+ .O(\axlen_cnt[6]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT3 #(
+ .INIT(8'hE1))
+ \axlen_cnt[7]_i_1__0
+ (.I0(\axlen_cnt_reg_n_0_[6] ),
+ .I1(\axlen_cnt[8]_i_3__0_n_0 ),
+ .I2(\axlen_cnt_reg_n_0_[7] ),
+ .O(\axlen_cnt[7]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT4 #(
+ .INIT(16'hFE01))
+ \axlen_cnt[8]_i_2__0
+ (.I0(\axlen_cnt_reg_n_0_[7] ),
+ .I1(\axlen_cnt[8]_i_3__0_n_0 ),
+ .I2(\axlen_cnt_reg_n_0_[6] ),
+ .I3(\axlen_cnt_reg_n_0_[8] ),
+ .O(\axlen_cnt[8]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFFE))
+ \axlen_cnt[8]_i_3__0
+ (.I0(\axlen_cnt_reg_n_0_[4] ),
+ .I1(\axlen_cnt_reg_n_0_[2] ),
+ .I2(\axlen_cnt_reg_n_0_[0] ),
+ .I3(\axlen_cnt_reg_n_0_[1] ),
+ .I4(\axlen_cnt_reg_n_0_[3] ),
+ .I5(\axlen_cnt_reg_n_0_[5] ),
+ .O(\axlen_cnt[8]_i_3__0_n_0 ));
+ FDRE \axlen_cnt_reg[0]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[0]_i_1__1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[1]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[1]_i_1__2_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[2]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[2]_i_1__2_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[3]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[3]_i_2__1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[4]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[4]_i_1__2_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[4] ),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[5]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[5]_i_1__0_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[5] ),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[6]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[6]_i_1__0_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[6] ),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[7]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[7]_i_1__0_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[7] ),
+ .R(\axlen_cnt_reg[8]_0 ));
+ FDRE \axlen_cnt_reg[8]
+ (.C(aclk),
+ .CE(\axlen_cnt_reg[4]_0 ),
+ .D(\axlen_cnt[8]_i_2__0_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[8] ),
+ .R(\axlen_cnt_reg[8]_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[0]_INST_0
+ (.I0(Q[0]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[0] ),
+ .I4(\axlen_cnt_reg[2]_1 [0]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[0]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[10]_INST_0
+ (.I0(Q[10]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[10] ),
+ .I4(\axlen_cnt_reg[2]_1 [10]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[10]));
+ LUT4 #(
+ .INIT(16'hFB0B))
+ \m_axi_araddr[11]_INST_0_i_3
+ (.I0(sel_first_reg_0),
+ .I1(\axlen_cnt_reg[2]_1 [13]),
+ .I2(\axlen_cnt_reg[2]_1 [14]),
+ .I3(\m_axi_araddr[0]_1 ),
+ .O(sel_first_reg_1));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[1]_INST_0
+ (.I0(Q[1]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[1] ),
+ .I4(\axlen_cnt_reg[2]_1 [1]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[1]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[2]_INST_0
+ (.I0(Q[2]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[2] ),
+ .I4(\axlen_cnt_reg[2]_1 [2]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[2]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[3] ),
+ .I4(\axlen_cnt_reg[2]_1 [3]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[3]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[4] ),
+ .I4(\axlen_cnt_reg[2]_1 [4]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[4]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[5]_INST_0
+ (.I0(Q[5]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[5] ),
+ .I4(\axlen_cnt_reg[2]_1 [5]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[5]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[6]_INST_0
+ (.I0(Q[6]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[6] ),
+ .I4(\axlen_cnt_reg[2]_1 [6]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[6]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[7]_INST_0
+ (.I0(Q[7]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[7] ),
+ .I4(\axlen_cnt_reg[2]_1 [7]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[7]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[8]_INST_0
+ (.I0(Q[8]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[8] ),
+ .I4(\axlen_cnt_reg[2]_1 [8]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[8]));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[9]_INST_0
+ (.I0(Q[9]),
+ .I1(m_axi_araddr_0_sn_1),
+ .I2(\m_axi_araddr[0]_0 ),
+ .I3(\axaddr_incr_reg_n_0_[9] ),
+ .I4(\axlen_cnt_reg[2]_1 [9]),
+ .I5(sel_first_reg_1),
+ .O(m_axi_araddr[9]));
+ LUT6 #(
+ .INIT(64'hFFF0F0F0F2F2F2F2))
+ next_pending_r_i_1__2
+ (.I0(next_pending_r_reg_n_0),
+ .I1(E),
+ .I2(next_pending_r_reg_0),
+ .I3(next_pending_r_i_3__0_n_0),
+ .I4(\axlen_cnt_reg[2]_0 ),
+ .I5(r_push),
+ .O(incr_next_pending));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFEEF))
+ next_pending_r_i_3__0
+ (.I0(next_pending_r_i_5__0_n_0),
+ .I1(\axlen_cnt_reg_n_0_[7] ),
+ .I2(\axlen_cnt[8]_i_3__0_n_0 ),
+ .I3(\axlen_cnt_reg_n_0_[6] ),
+ .I4(\axlen_cnt_reg_n_0_[8] ),
+ .I5(next_pending_r_i_6__0_n_0),
+ .O(next_pending_r_i_3__0_n_0));
+ LUT6 #(
+ .INIT(64'h00000000FFFFFFFE))
+ next_pending_r_i_4
+ (.I0(next_pending_r_i_7__0_n_0),
+ .I1(\axlen_cnt_reg_n_0_[2] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[4] ),
+ .I4(\axlen_cnt_reg_n_0_[3] ),
+ .I5(E),
+ .O(\axlen_cnt_reg[2]_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFEEEB))
+ next_pending_r_i_5__0
+ (.I0(\axlen_cnt_reg_n_0_[4] ),
+ .I1(\axlen_cnt_reg_n_0_[2] ),
+ .I2(\axlen_cnt_reg_n_0_[0] ),
+ .I3(\axlen_cnt_reg_n_0_[1] ),
+ .I4(\axlen_cnt_reg_n_0_[3] ),
+ .I5(\axlen_cnt_reg_n_0_[5] ),
+ .O(next_pending_r_i_5__0_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT2 #(
+ .INIT(4'hB))
+ next_pending_r_i_6__0
+ (.I0(\axlen_cnt_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg_n_0_[0] ),
+ .O(next_pending_r_i_6__0_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ next_pending_r_i_7__0
+ (.I0(\axlen_cnt_reg_n_0_[6] ),
+ .I1(\axlen_cnt_reg_n_0_[5] ),
+ .I2(\axlen_cnt_reg_n_0_[8] ),
+ .I3(\axlen_cnt_reg_n_0_[7] ),
+ .O(next_pending_r_i_7__0_n_0));
+ FDRE next_pending_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(incr_next_pending),
+ .Q(next_pending_r_reg_n_0),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hBA8A))
+ s_axburst_eq0_i_1__0
+ (.I0(incr_next_pending),
+ .I1(sel_first_i),
+ .I2(\axlen_cnt_reg[2]_1 [14]),
+ .I3(wrap_next_pending),
+ .O(\m_payload_i_reg[39] ));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_reg_2),
+ .Q(sel_first_reg_0),
+ .R(1'b0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel
+ (r_full,
+ m_axi_rready,
+ si_rs_rvalid,
+ out,
+ r_push_r_reg_0,
+ r_push,
+ aclk,
+ r_rlast,
+ m_axi_rvalid,
+ si_rs_rready,
+ in,
+ D,
+ areset_d1);
+ output r_full;
+ output m_axi_rready;
+ output si_rs_rvalid;
+ output [33:0]out;
+ output [12:0]r_push_r_reg_0;
+ input r_push;
+ input aclk;
+ input r_rlast;
+ input m_axi_rvalid;
+ input si_rs_rready;
+ input [33:0]in;
+ input [11:0]D;
+ input areset_d1;
+
+ wire [11:0]D;
+ wire a_full0;
+ wire aclk;
+ wire areset_d1;
+ wire [33:0]in;
+ wire m_axi_rready;
+ wire m_axi_rvalid;
+ wire [33:0]out;
+ wire r_full;
+ wire r_push;
+ wire r_push_r;
+ wire [12:0]r_push_r_reg_0;
+ wire r_rlast;
+ wire rd_a_full;
+ wire rd_en__1;
+ wire si_rs_rready;
+ wire si_rs_rvalid;
+ wire [12:0]trans_in;
+ wire transaction_fifo_0_n_1;
+ wire wr_en0;
+
+ FDRE \r_arid_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[0]),
+ .Q(trans_in[1]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[10]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[10]),
+ .Q(trans_in[11]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[11]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[11]),
+ .Q(trans_in[12]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[1]),
+ .Q(trans_in[2]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[2]),
+ .Q(trans_in[3]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[3]),
+ .Q(trans_in[4]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[4]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[4]),
+ .Q(trans_in[5]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[5]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[5]),
+ .Q(trans_in[6]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[6]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[6]),
+ .Q(trans_in[7]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[7]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[7]),
+ .Q(trans_in[8]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[8]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[8]),
+ .Q(trans_in[9]),
+ .R(1'b0));
+ FDRE \r_arid_r_reg[9]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[9]),
+ .Q(trans_in[10]),
+ .R(1'b0));
+ FDRE r_push_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(r_push),
+ .Q(r_push_r),
+ .R(1'b0));
+ FDRE r_rlast_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(r_rlast),
+ .Q(trans_in[0]),
+ .R(1'b0));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1 rd_data_fifo_0
+ (.E(transaction_fifo_0_n_1),
+ .a_full0(a_full0),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .in(in),
+ .m_axi_rready(m_axi_rready),
+ .m_axi_rvalid(m_axi_rvalid),
+ .out(out),
+ .rd_a_full(rd_a_full),
+ .rd_en__1(rd_en__1),
+ .wr_en0(wr_en0));
+ TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2 transaction_fifo_0
+ (.E(transaction_fifo_0_n_1),
+ .a_full0(a_full0),
+ .aclk(aclk),
+ .areset_d1(areset_d1),
+ .in(trans_in),
+ .r_full(r_full),
+ .r_push_r(r_push_r),
+ .r_push_r_reg(r_push_r_reg_0),
+ .rd_a_full(rd_a_full),
+ .rd_en__1(rd_en__1),
+ .si_rs_rready(si_rs_rready),
+ .si_rs_rvalid(si_rs_rvalid),
+ .wr_en0(wr_en0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm
+ (\FSM_sequential_state_reg[1]_0 ,
+ Q,
+ s_ready_i0,
+ m_valid_i0,
+ m_axi_arready_0,
+ m_axi_arready_1,
+ m_axi_arready_2,
+ sel_first_i,
+ E,
+ sel_first_reg,
+ D,
+ m_axi_arready_3,
+ m_axi_arvalid,
+ \FSM_sequential_state_reg[1]_1 ,
+ si_rs_arvalid,
+ m_axi_arready,
+ \axlen_cnt_reg[8] ,
+ s_axi_arvalid,
+ s_ready_i_reg,
+ sel_first_reg_0,
+ areset_d1,
+ \axaddr_incr_reg[0] ,
+ sel_first_reg_1,
+ O,
+ \axaddr_wrap_reg[11] ,
+ \axaddr_wrap_reg[11]_0 ,
+ \axaddr_wrap_reg[7] ,
+ \axaddr_wrap_reg[11]_1 ,
+ \axaddr_wrap_reg[11]_2 ,
+ next_pending,
+ r_full,
+ aclk);
+ output \FSM_sequential_state_reg[1]_0 ;
+ output [1:0]Q;
+ output s_ready_i0;
+ output m_valid_i0;
+ output m_axi_arready_0;
+ output m_axi_arready_1;
+ output m_axi_arready_2;
+ output sel_first_i;
+ output [0:0]E;
+ output [0:0]sel_first_reg;
+ output [11:0]D;
+ output m_axi_arready_3;
+ output m_axi_arvalid;
+ output [0:0]\FSM_sequential_state_reg[1]_1 ;
+ input si_rs_arvalid;
+ input m_axi_arready;
+ input \axlen_cnt_reg[8] ;
+ input s_axi_arvalid;
+ input s_ready_i_reg;
+ input sel_first_reg_0;
+ input areset_d1;
+ input \axaddr_incr_reg[0] ;
+ input sel_first_reg_1;
+ input [3:0]O;
+ input [11:0]\axaddr_wrap_reg[11] ;
+ input [11:0]\axaddr_wrap_reg[11]_0 ;
+ input [3:0]\axaddr_wrap_reg[7] ;
+ input [3:0]\axaddr_wrap_reg[11]_1 ;
+ input \axaddr_wrap_reg[11]_2 ;
+ input next_pending;
+ input r_full;
+ input aclk;
+
+ wire [11:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_state_reg[1]_0 ;
+ wire [0:0]\FSM_sequential_state_reg[1]_1 ;
+ wire [3:0]O;
+ wire [1:0]Q;
+ wire aclk;
+ wire areset_d1;
+ wire \axaddr_incr_reg[0] ;
+ wire \axaddr_wrap[11]_i_2_n_0 ;
+ wire \axaddr_wrap[11]_i_4_n_0 ;
+ wire [11:0]\axaddr_wrap_reg[11] ;
+ wire [11:0]\axaddr_wrap_reg[11]_0 ;
+ wire [3:0]\axaddr_wrap_reg[11]_1 ;
+ wire \axaddr_wrap_reg[11]_2 ;
+ wire [3:0]\axaddr_wrap_reg[7] ;
+ wire \axlen_cnt_reg[8] ;
+ wire m_axi_arready;
+ wire m_axi_arready_0;
+ wire m_axi_arready_1;
+ wire m_axi_arready_2;
+ wire m_axi_arready_3;
+ wire m_axi_arvalid;
+ wire m_valid_i0;
+ wire next_pending;
+ wire [1:0]next_state__0;
+ wire r_full;
+ wire s_axi_arvalid;
+ wire s_ready_i0;
+ wire s_ready_i_reg;
+ wire sel_first_i;
+ wire [0:0]sel_first_reg;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire si_rs_arvalid;
+
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'h77F755FF))
+ \FSM_sequential_state[0]_i_1
+ (.I0(Q[1]),
+ .I1(m_axi_arready),
+ .I2(next_pending),
+ .I3(r_full),
+ .I4(Q[0]),
+ .O(next_state__0[0]));
+ LUT6 #(
+ .INIT(64'hDDFFDDFF0F000000))
+ \FSM_sequential_state[1]_i_1
+ (.I0(m_axi_arready),
+ .I1(next_pending),
+ .I2(r_full),
+ .I3(Q[0]),
+ .I4(si_rs_arvalid),
+ .I5(Q[1]),
+ .O(next_state__0[1]));
+ (* FSM_ENCODED_STATES = "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11" *)
+ FDSE #(
+ .INIT(1'b1))
+ \FSM_sequential_state_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(next_state__0[0]),
+ .Q(Q[0]),
+ .S(areset_d1));
+ (* FSM_ENCODED_STATES = "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_state_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(next_state__0[1]),
+ .Q(Q[1]),
+ .R(areset_d1));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'hEAAA))
+ \axaddr_incr[11]_i_1__0
+ (.I0(\axaddr_incr_reg[0] ),
+ .I1(Q[0]),
+ .I2(Q[1]),
+ .I3(m_axi_arready),
+ .O(sel_first_reg));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[0]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(O[0]),
+ .I2(\axaddr_wrap_reg[11] [0]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [0]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[0]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[10]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[11]_1 [2]),
+ .I2(\axaddr_wrap_reg[11] [10]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [10]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[10]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[11]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[11]_1 [3]),
+ .I2(\axaddr_wrap_reg[11] [11]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [11]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[11]));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h0080))
+ \axaddr_wrap[11]_i_2
+ (.I0(Q[0]),
+ .I1(Q[1]),
+ .I2(m_axi_arready),
+ .I3(\axaddr_wrap_reg[11]_2 ),
+ .O(\axaddr_wrap[11]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \axaddr_wrap[11]_i_4
+ (.I0(\axaddr_wrap_reg[11]_2 ),
+ .I1(Q[0]),
+ .I2(Q[1]),
+ .I3(m_axi_arready),
+ .O(\axaddr_wrap[11]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[1]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(O[1]),
+ .I2(\axaddr_wrap_reg[11] [1]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [1]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[1]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[2]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(O[2]),
+ .I2(\axaddr_wrap_reg[11] [2]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [2]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[2]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[3]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(O[3]),
+ .I2(\axaddr_wrap_reg[11] [3]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [3]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[4]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[7] [0]),
+ .I2(\axaddr_wrap_reg[11] [4]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [4]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[4]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[5]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[7] [1]),
+ .I2(\axaddr_wrap_reg[11] [5]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [5]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[5]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[6]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[7] [2]),
+ .I2(\axaddr_wrap_reg[11] [6]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [6]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[6]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[7]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[7] [3]),
+ .I2(\axaddr_wrap_reg[11] [7]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [7]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[7]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[8]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[11]_1 [0]),
+ .I2(\axaddr_wrap_reg[11] [8]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [8]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[8]));
+ LUT6 #(
+ .INIT(64'hFFFF88F888F888F8))
+ \axaddr_wrap[9]_i_1
+ (.I0(\axaddr_wrap[11]_i_2_n_0 ),
+ .I1(\axaddr_wrap_reg[11]_1 [1]),
+ .I2(\axaddr_wrap_reg[11] [9]),
+ .I3(m_axi_arready_3),
+ .I4(\axaddr_wrap_reg[11]_0 [9]),
+ .I5(\axaddr_wrap[11]_i_4_n_0 ),
+ .O(D[9]));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'hA0C0))
+ \axlen_cnt[3]_i_1__1
+ (.I0(m_axi_arready),
+ .I1(si_rs_arvalid),
+ .I2(Q[0]),
+ .I3(Q[1]),
+ .O(m_axi_arready_0));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h0000C840))
+ \axlen_cnt[8]_i_1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_arvalid),
+ .I3(m_axi_arready),
+ .I4(\axlen_cnt_reg[8] ),
+ .O(\FSM_sequential_state_reg[1]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT2 #(
+ .INIT(4'h8))
+ m_axi_arvalid_INST_0
+ (.I0(Q[0]),
+ .I1(Q[1]),
+ .O(m_axi_arvalid));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT3 #(
+ .INIT(8'h1F))
+ \m_payload_i[31]_i_1__1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_arvalid),
+ .O(\FSM_sequential_state_reg[1]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'hFFFFE0FF))
+ m_valid_i_i_1__2
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_arvalid),
+ .I3(s_ready_i_reg),
+ .I4(s_axi_arvalid),
+ .O(m_valid_i0));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT3 #(
+ .INIT(8'h80))
+ r_push_r_i_1
+ (.I0(m_axi_arready),
+ .I1(Q[1]),
+ .I2(Q[0]),
+ .O(m_axi_arready_3));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h1FFF1F1F))
+ s_ready_i_i_1__2
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_arvalid),
+ .I3(s_axi_arvalid),
+ .I4(s_ready_i_reg),
+ .O(s_ready_i0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF4FCC4CCC))
+ sel_first_i_1__2
+ (.I0(m_axi_arready),
+ .I1(sel_first_reg_0),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_arvalid),
+ .I5(areset_d1),
+ .O(m_axi_arready_1));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF4FCC4CCC))
+ sel_first_i_1__3
+ (.I0(m_axi_arready),
+ .I1(\axaddr_incr_reg[0] ),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_arvalid),
+ .I5(areset_d1),
+ .O(m_axi_arready_2));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF4FCC4CCC))
+ sel_first_i_1__4
+ (.I0(m_axi_arready),
+ .I1(sel_first_reg_1),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_arvalid),
+ .I5(areset_d1),
+ .O(sel_first_i));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT3 #(
+ .INIT(8'h40))
+ \wrap_boundary_axaddr_r[11]_i_1__0
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_arvalid),
+ .O(E));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo
+ (b_full,
+ addr,
+ SR,
+ bresp_push,
+ shandshake_r_reg,
+ out,
+ areset_d1,
+ Q,
+ shandshake_r,
+ bresp_empty,
+ si_rs_bvalid,
+ si_rs_bready,
+ mhandshake_r,
+ b_push,
+ in,
+ aclk);
+ output b_full;
+ output [1:0]addr;
+ output [0:0]SR;
+ output bresp_push;
+ output shandshake_r_reg;
+ output [11:0]out;
+ input areset_d1;
+ input [7:0]Q;
+ input shandshake_r;
+ input bresp_empty;
+ input si_rs_bvalid;
+ input si_rs_bready;
+ input mhandshake_r;
+ input b_push;
+ input [15:0]in;
+ input aclk;
+
+ wire [7:0]Q;
+ wire [0:0]SR;
+ wire aclk;
+ wire [1:0]addr;
+ wire areset_d1;
+ wire b_full;
+ wire b_push;
+ wire bresp_empty;
+ wire bresp_push;
+ wire bvalid_i21_in;
+ wire \cnt_read[0]_i_1_n_0 ;
+ wire \cnt_read[1]_i_1_n_0 ;
+ wire [15:0]in;
+ wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
+ wire \memory_reg[3][0]_srl4_i_3__0_n_0 ;
+ wire \memory_reg[3][0]_srl4_n_0 ;
+ wire \memory_reg[3][1]_srl4_n_0 ;
+ wire \memory_reg[3][2]_srl4_n_0 ;
+ wire \memory_reg[3][3]_srl4_n_0 ;
+ wire mhandshake_r;
+ wire [11:0]out;
+ wire shandshake_r;
+ wire shandshake_r_reg;
+ wire si_rs_bready;
+ wire si_rs_bvalid;
+
+ LUT2 #(
+ .INIT(4'hE))
+ \bresp_cnt[7]_i_1
+ (.I0(areset_d1),
+ .I1(bresp_push),
+ .O(SR));
+ LUT6 #(
+ .INIT(64'h0000000400FF0004))
+ bvalid_i_i_1
+ (.I0(shandshake_r),
+ .I1(bvalid_i21_in),
+ .I2(bresp_empty),
+ .I3(areset_d1),
+ .I4(si_rs_bvalid),
+ .I5(si_rs_bready),
+ .O(shandshake_r_reg));
+ LUT2 #(
+ .INIT(4'h7))
+ bvalid_i_i_2
+ (.I0(addr[0]),
+ .I1(addr[1]),
+ .O(bvalid_i21_in));
+ (* SOFT_HLUTNM = "soft_lutpair129" *)
+ LUT3 #(
+ .INIT(8'h96))
+ \cnt_read[0]_i_1
+ (.I0(shandshake_r),
+ .I1(b_push),
+ .I2(addr[0]),
+ .O(\cnt_read[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair129" *)
+ LUT4 #(
+ .INIT(16'hE718))
+ \cnt_read[1]_i_1
+ (.I0(addr[0]),
+ .I1(b_push),
+ .I2(shandshake_r),
+ .I3(addr[1]),
+ .O(\cnt_read[1]_i_1_n_0 ));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\cnt_read[0]_i_1_n_0 ),
+ .Q(addr[0]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\cnt_read[1]_i_1_n_0 ),
+ .Q(addr[1]),
+ .S(areset_d1));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][0]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[0]),
+ .Q(\memory_reg[3][0]_srl4_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000082000082))
+ \memory_reg[3][0]_srl4_i_1
+ (.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
+ .I1(Q[2]),
+ .I2(\memory_reg[3][2]_srl4_n_0 ),
+ .I3(Q[3]),
+ .I4(\memory_reg[3][3]_srl4_n_0 ),
+ .I5(\memory_reg[3][0]_srl4_i_3__0_n_0 ),
+ .O(bresp_push));
+ (* SOFT_HLUTNM = "soft_lutpair128" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \memory_reg[3][0]_srl4_i_2
+ (.I0(addr[1]),
+ .I1(addr[0]),
+ .O(b_full));
+ (* SOFT_HLUTNM = "soft_lutpair128" *)
+ LUT5 #(
+ .INIT(32'h00020202))
+ \memory_reg[3][0]_srl4_i_2__0
+ (.I0(mhandshake_r),
+ .I1(Q[6]),
+ .I2(Q[7]),
+ .I3(addr[1]),
+ .I4(addr[0]),
+ .O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFF6FF6))
+ \memory_reg[3][0]_srl4_i_3__0
+ (.I0(\memory_reg[3][1]_srl4_n_0 ),
+ .I1(Q[1]),
+ .I2(\memory_reg[3][0]_srl4_n_0 ),
+ .I3(Q[0]),
+ .I4(Q[4]),
+ .I5(Q[5]),
+ .O(\memory_reg[3][0]_srl4_i_3__0_n_0 ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][10]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[6]),
+ .Q(out[2]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][11]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[7]),
+ .Q(out[3]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][12]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[8]),
+ .Q(out[4]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][13]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[9]),
+ .Q(out[5]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][14]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[10]),
+ .Q(out[6]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][15]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[11]),
+ .Q(out[7]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][16]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[12]),
+ .Q(out[8]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][17]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[13]),
+ .Q(out[9]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][18]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[14]),
+ .Q(out[10]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][19]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[15]),
+ .Q(out[11]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][1]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[1]),
+ .Q(\memory_reg[3][1]_srl4_n_0 ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][2]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[2]),
+ .Q(\memory_reg[3][2]_srl4_n_0 ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][3]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[3]),
+ .Q(\memory_reg[3][3]_srl4_n_0 ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][8]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[4]),
+ .Q(out[0]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][9]_srl4
+ (.A0(addr[0]),
+ .A1(addr[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(b_push),
+ .CLK(aclk),
+ .D(in[5]),
+ .Q(out[1]));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_simple_fifo" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0
+ (m_axi_bready,
+ mhandshake,
+ bresp_empty,
+ \s_bresp_acc_reg[1] ,
+ mhandshake_r,
+ m_axi_bvalid,
+ bresp_push,
+ in,
+ aclk,
+ shandshake_r,
+ areset_d1);
+ output m_axi_bready;
+ output mhandshake;
+ output bresp_empty;
+ output [1:0]\s_bresp_acc_reg[1] ;
+ input mhandshake_r;
+ input m_axi_bvalid;
+ input bresp_push;
+ input [1:0]in;
+ input aclk;
+ input shandshake_r;
+ input areset_d1;
+
+ wire aclk;
+ wire areset_d1;
+ wire bresp_empty;
+ wire bresp_push;
+ wire [1:0]cnt_read;
+ wire \cnt_read[0]_i_1_n_0 ;
+ wire \cnt_read[1]_i_1_n_0 ;
+ wire [1:0]in;
+ wire m_axi_bready;
+ wire m_axi_bvalid;
+ wire mhandshake;
+ wire mhandshake_r;
+ wire [1:0]\s_bresp_acc_reg[1] ;
+ wire shandshake_r;
+
+ LUT2 #(
+ .INIT(4'h8))
+ bvalid_i_i_3
+ (.I0(cnt_read[0]),
+ .I1(cnt_read[1]),
+ .O(bresp_empty));
+ (* SOFT_HLUTNM = "soft_lutpair130" *)
+ LUT3 #(
+ .INIT(8'h96))
+ \cnt_read[0]_i_1
+ (.I0(shandshake_r),
+ .I1(bresp_push),
+ .I2(cnt_read[0]),
+ .O(\cnt_read[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair130" *)
+ LUT4 #(
+ .INIT(16'hE718))
+ \cnt_read[1]_i_1
+ (.I0(cnt_read[0]),
+ .I1(bresp_push),
+ .I2(shandshake_r),
+ .I3(cnt_read[1]),
+ .O(\cnt_read[1]_i_1_n_0 ));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\cnt_read[0]_i_1_n_0 ),
+ .Q(cnt_read[0]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\cnt_read[1]_i_1_n_0 ),
+ .Q(cnt_read[1]),
+ .S(areset_d1));
+ (* SOFT_HLUTNM = "soft_lutpair131" *)
+ LUT3 #(
+ .INIT(8'h08))
+ m_axi_bready_INST_0
+ (.I0(cnt_read[1]),
+ .I1(cnt_read[0]),
+ .I2(mhandshake_r),
+ .O(m_axi_bready));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][0]_srl4
+ (.A0(cnt_read[0]),
+ .A1(cnt_read[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(bresp_push),
+ .CLK(aclk),
+ .D(in[0]),
+ .Q(\s_bresp_acc_reg[1] [0]));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \memory_reg[3][1]_srl4
+ (.A0(cnt_read[0]),
+ .A1(cnt_read[1]),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(bresp_push),
+ .CLK(aclk),
+ .D(in[1]),
+ .Q(\s_bresp_acc_reg[1] [1]));
+ (* SOFT_HLUTNM = "soft_lutpair131" *)
+ LUT4 #(
+ .INIT(16'h4000))
+ mhandshake_r_i_1
+ (.I0(mhandshake_r),
+ .I1(m_axi_bvalid),
+ .I2(cnt_read[1]),
+ .I3(cnt_read[0]),
+ .O(mhandshake));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_simple_fifo" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1
+ (m_axi_rready,
+ wr_en0,
+ rd_a_full,
+ a_full0,
+ out,
+ rd_en__1,
+ m_axi_rvalid,
+ in,
+ aclk,
+ areset_d1,
+ E);
+ output m_axi_rready;
+ output wr_en0;
+ output rd_a_full;
+ output a_full0;
+ output [33:0]out;
+ input rd_en__1;
+ input m_axi_rvalid;
+ input [33:0]in;
+ input aclk;
+ input areset_d1;
+ input [0:0]E;
+
+ wire [0:0]E;
+ wire a_full0;
+ wire aclk;
+ wire areset_d1;
+ wire \cnt_read[0]_i_1_n_0 ;
+ wire \cnt_read[1]_i_1_n_0 ;
+ wire \cnt_read[2]_i_1_n_0 ;
+ wire \cnt_read[3]_i_1_n_0 ;
+ wire \cnt_read[4]_i_2_n_0 ;
+ wire \cnt_read[4]_i_4_n_0 ;
+ wire [4:0]cnt_read_reg;
+ wire [33:0]in;
+ wire m_axi_rready;
+ wire m_axi_rvalid;
+ wire [33:0]out;
+ wire rd_a_full;
+ wire rd_en__1;
+ wire wr_en0;
+ wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT5 #(
+ .INIT(32'h08888080))
+ \FSM_sequential_state[1]_i_4
+ (.I0(cnt_read_reg[4]),
+ .I1(cnt_read_reg[3]),
+ .I2(cnt_read_reg[1]),
+ .I3(cnt_read_reg[0]),
+ .I4(cnt_read_reg[2]),
+ .O(rd_a_full));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \cnt_read[0]_i_1
+ (.I0(cnt_read_reg[0]),
+ .O(\cnt_read[0]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h9A65))
+ \cnt_read[1]_i_1
+ (.I0(cnt_read_reg[0]),
+ .I1(rd_en__1),
+ .I2(wr_en0),
+ .I3(cnt_read_reg[1]),
+ .O(\cnt_read[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT5 #(
+ .INIT(32'hBFF4400B))
+ \cnt_read[2]_i_1
+ (.I0(rd_en__1),
+ .I1(wr_en0),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[1]),
+ .I4(cnt_read_reg[2]),
+ .O(\cnt_read[2]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hBFFF4000FFF4000B))
+ \cnt_read[3]_i_1
+ (.I0(rd_en__1),
+ .I1(wr_en0),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[1]),
+ .I4(cnt_read_reg[3]),
+ .I5(cnt_read_reg[2]),
+ .O(\cnt_read[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h7E81))
+ \cnt_read[4]_i_2
+ (.I0(\cnt_read[4]_i_4_n_0 ),
+ .I1(cnt_read_reg[2]),
+ .I2(cnt_read_reg[3]),
+ .I3(cnt_read_reg[4]),
+ .O(\cnt_read[4]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT5 #(
+ .INIT(32'h5454D554))
+ \cnt_read[4]_i_4
+ (.I0(cnt_read_reg[2]),
+ .I1(cnt_read_reg[1]),
+ .I2(cnt_read_reg[0]),
+ .I3(wr_en0),
+ .I4(rd_en__1),
+ .O(\cnt_read[4]_i_4_n_0 ));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[0]
+ (.C(aclk),
+ .CE(E),
+ .D(\cnt_read[0]_i_1_n_0 ),
+ .Q(cnt_read_reg[0]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[1]
+ (.C(aclk),
+ .CE(E),
+ .D(\cnt_read[1]_i_1_n_0 ),
+ .Q(cnt_read_reg[1]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[2]
+ (.C(aclk),
+ .CE(E),
+ .D(\cnt_read[2]_i_1_n_0 ),
+ .Q(cnt_read_reg[2]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[3]
+ (.C(aclk),
+ .CE(E),
+ .D(\cnt_read[3]_i_1_n_0 ),
+ .Q(cnt_read_reg[3]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[4]
+ (.C(aclk),
+ .CE(E),
+ .D(\cnt_read[4]_i_2_n_0 ),
+ .Q(cnt_read_reg[4]),
+ .S(areset_d1));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT5 #(
+ .INIT(32'h85FFFFFF))
+ m_axi_rready_INST_0
+ (.I0(cnt_read_reg[2]),
+ .I1(cnt_read_reg[0]),
+ .I2(cnt_read_reg[1]),
+ .I3(cnt_read_reg[3]),
+ .I4(cnt_read_reg[4]),
+ .O(m_axi_rready));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT5 #(
+ .INIT(32'h7FFFFFFF))
+ m_valid_i_i_3
+ (.I0(cnt_read_reg[2]),
+ .I1(cnt_read_reg[0]),
+ .I2(cnt_read_reg[1]),
+ .I3(cnt_read_reg[3]),
+ .I4(cnt_read_reg[4]),
+ .O(a_full0));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][0]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[0]),
+ .Q(out[0]),
+ .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+ LUT6 #(
+ .INIT(64'h8022AAAAAAAAAAAA))
+ \memory_reg[31][0]_srl32_i_1
+ (.I0(m_axi_rvalid),
+ .I1(cnt_read_reg[2]),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[1]),
+ .I4(cnt_read_reg[3]),
+ .I5(cnt_read_reg[4]),
+ .O(wr_en0));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][10]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[10]),
+ .Q(out[10]),
+ .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][11]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[11]),
+ .Q(out[11]),
+ .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][12]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[12]),
+ .Q(out[12]),
+ .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][13]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[13]),
+ .Q(out[13]),
+ .Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][14]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[14]),
+ .Q(out[14]),
+ .Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][15]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[15]),
+ .Q(out[15]),
+ .Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][16]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[16]),
+ .Q(out[16]),
+ .Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][17]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[17]),
+ .Q(out[17]),
+ .Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][18]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[18]),
+ .Q(out[18]),
+ .Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][19]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[19]),
+ .Q(out[19]),
+ .Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][1]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[1]),
+ .Q(out[1]),
+ .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][20]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[20]),
+ .Q(out[20]),
+ .Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][21]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[21]),
+ .Q(out[21]),
+ .Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][22]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[22]),
+ .Q(out[22]),
+ .Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][23]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[23]),
+ .Q(out[23]),
+ .Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][24]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[24]),
+ .Q(out[24]),
+ .Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][25]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[25]),
+ .Q(out[25]),
+ .Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][26]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[26]),
+ .Q(out[26]),
+ .Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][27]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[27]),
+ .Q(out[27]),
+ .Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][28]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[28]),
+ .Q(out[28]),
+ .Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][29]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[29]),
+ .Q(out[29]),
+ .Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][2]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[2]),
+ .Q(out[2]),
+ .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][30]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[30]),
+ .Q(out[30]),
+ .Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][31]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[31]),
+ .Q(out[31]),
+ .Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][32]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[32]),
+ .Q(out[32]),
+ .Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][33]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[33]),
+ .Q(out[33]),
+ .Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][3]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[3]),
+ .Q(out[3]),
+ .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][4]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[4]),
+ .Q(out[4]),
+ .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][5]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[5]),
+ .Q(out[5]),
+ .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][6]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[6]),
+ .Q(out[6]),
+ .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][7]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[7]),
+ .Q(out[7]),
+ .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][8]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[8]),
+ .Q(out[8]),
+ .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][9]_srl32
+ (.A(cnt_read_reg),
+ .CE(wr_en0),
+ .CLK(aclk),
+ .D(in[9]),
+ .Q(out[9]),
+ .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_simple_fifo" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2
+ (r_full,
+ E,
+ rd_en__1,
+ si_rs_rvalid,
+ r_push_r_reg,
+ rd_a_full,
+ wr_en0,
+ r_push_r,
+ si_rs_rready,
+ a_full0,
+ in,
+ aclk,
+ areset_d1);
+ output r_full;
+ output [0:0]E;
+ output rd_en__1;
+ output si_rs_rvalid;
+ output [12:0]r_push_r_reg;
+ input rd_a_full;
+ input wr_en0;
+ input r_push_r;
+ input si_rs_rready;
+ input a_full0;
+ input [12:0]in;
+ input aclk;
+ input areset_d1;
+
+ wire [0:0]E;
+ wire a_full0;
+ wire aclk;
+ wire areset_d1;
+ wire \cnt_read[0]_i_1__0_n_0 ;
+ wire \cnt_read[1]_i_1__0_n_0 ;
+ wire \cnt_read[2]_i_1__0_n_0 ;
+ wire \cnt_read[3]_i_1__0_n_0 ;
+ wire \cnt_read[4]_i_1__0_n_0 ;
+ wire \cnt_read[4]_i_2__0_n_0 ;
+ wire \cnt_read[4]_i_3_n_0 ;
+ wire \cnt_read[4]_i_5_n_0 ;
+ wire [4:0]cnt_read_reg;
+ wire [12:0]in;
+ wire r_full;
+ wire r_push_r;
+ wire [12:0]r_push_r_reg;
+ wire rd_a_full;
+ wire rd_en__1;
+ wire si_rs_rready;
+ wire si_rs_rvalid;
+ wire wr_en0;
+ wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+ wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+ LUT6 #(
+ .INIT(64'hFFFFFFFF6000E000))
+ \FSM_sequential_state[1]_i_3
+ (.I0(cnt_read_reg[2]),
+ .I1(cnt_read_reg[1]),
+ .I2(cnt_read_reg[4]),
+ .I3(cnt_read_reg[3]),
+ .I4(cnt_read_reg[0]),
+ .I5(rd_a_full),
+ .O(r_full));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \cnt_read[0]_i_1__0
+ (.I0(cnt_read_reg[0]),
+ .O(\cnt_read[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'h9A65))
+ \cnt_read[1]_i_1__0
+ (.I0(cnt_read_reg[0]),
+ .I1(rd_en__1),
+ .I2(r_push_r),
+ .I3(cnt_read_reg[1]),
+ .O(\cnt_read[1]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT5 #(
+ .INIT(32'hBF40F40B))
+ \cnt_read[2]_i_1__0
+ (.I0(rd_en__1),
+ .I1(r_push_r),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[2]),
+ .I4(cnt_read_reg[1]),
+ .O(\cnt_read[2]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hBFFF4000FFF4000B))
+ \cnt_read[3]_i_1__0
+ (.I0(rd_en__1),
+ .I1(r_push_r),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[1]),
+ .I4(cnt_read_reg[3]),
+ .I5(cnt_read_reg[2]),
+ .O(\cnt_read[3]_i_1__0_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \cnt_read[4]_i_1
+ (.I0(rd_en__1),
+ .I1(wr_en0),
+ .O(E));
+ LUT2 #(
+ .INIT(4'h6))
+ \cnt_read[4]_i_1__0
+ (.I0(rd_en__1),
+ .I1(r_push_r),
+ .O(\cnt_read[4]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT4 #(
+ .INIT(16'h78E1))
+ \cnt_read[4]_i_2__0
+ (.I0(\cnt_read[4]_i_3_n_0 ),
+ .I1(cnt_read_reg[2]),
+ .I2(cnt_read_reg[4]),
+ .I3(cnt_read_reg[3]),
+ .O(\cnt_read[4]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT5 #(
+ .INIT(32'h5454D554))
+ \cnt_read[4]_i_3
+ (.I0(cnt_read_reg[2]),
+ .I1(cnt_read_reg[1]),
+ .I2(cnt_read_reg[0]),
+ .I3(r_push_r),
+ .I4(rd_en__1),
+ .O(\cnt_read[4]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h8AAAAAAA00000000))
+ \cnt_read[4]_i_3__0
+ (.I0(si_rs_rready),
+ .I1(\cnt_read[4]_i_5_n_0 ),
+ .I2(cnt_read_reg[0]),
+ .I3(cnt_read_reg[1]),
+ .I4(cnt_read_reg[2]),
+ .I5(a_full0),
+ .O(rd_en__1));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \cnt_read[4]_i_5
+ (.I0(cnt_read_reg[4]),
+ .I1(cnt_read_reg[3]),
+ .O(\cnt_read[4]_i_5_n_0 ));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[0]
+ (.C(aclk),
+ .CE(\cnt_read[4]_i_1__0_n_0 ),
+ .D(\cnt_read[0]_i_1__0_n_0 ),
+ .Q(cnt_read_reg[0]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[1]
+ (.C(aclk),
+ .CE(\cnt_read[4]_i_1__0_n_0 ),
+ .D(\cnt_read[1]_i_1__0_n_0 ),
+ .Q(cnt_read_reg[1]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[2]
+ (.C(aclk),
+ .CE(\cnt_read[4]_i_1__0_n_0 ),
+ .D(\cnt_read[2]_i_1__0_n_0 ),
+ .Q(cnt_read_reg[2]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[3]
+ (.C(aclk),
+ .CE(\cnt_read[4]_i_1__0_n_0 ),
+ .D(\cnt_read[3]_i_1__0_n_0 ),
+ .Q(cnt_read_reg[3]),
+ .S(areset_d1));
+ FDSE #(
+ .INIT(1'b1))
+ \cnt_read_reg[4]
+ (.C(aclk),
+ .CE(\cnt_read[4]_i_1__0_n_0 ),
+ .D(\cnt_read[4]_i_2__0_n_0 ),
+ .Q(cnt_read_reg[4]),
+ .S(areset_d1));
+ LUT6 #(
+ .INIT(64'h2AAAAAAAAAAAAAAA))
+ m_valid_i_i_2
+ (.I0(a_full0),
+ .I1(cnt_read_reg[2]),
+ .I2(cnt_read_reg[1]),
+ .I3(cnt_read_reg[0]),
+ .I4(cnt_read_reg[3]),
+ .I5(cnt_read_reg[4]),
+ .O(si_rs_rvalid));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][0]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[0]),
+ .Q(r_push_r_reg[0]),
+ .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][10]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[10]),
+ .Q(r_push_r_reg[10]),
+ .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][11]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[11]),
+ .Q(r_push_r_reg[11]),
+ .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][12]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[12]),
+ .Q(r_push_r_reg[12]),
+ .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][1]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[1]),
+ .Q(r_push_r_reg[1]),
+ .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][2]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[2]),
+ .Q(r_push_r_reg[2]),
+ .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][3]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[3]),
+ .Q(r_push_r_reg[3]),
+ .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][4]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[4]),
+ .Q(r_push_r_reg[4]),
+ .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][5]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[5]),
+ .Q(r_push_r_reg[5]),
+ .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][6]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[6]),
+ .Q(r_push_r_reg[6]),
+ .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][7]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[7]),
+ .Q(r_push_r_reg[7]),
+ .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][8]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[8]),
+ .Q(r_push_r_reg[8]),
+ .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+ (* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
+ (* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \memory_reg[31][9]_srl32
+ (.A(cnt_read_reg),
+ .CE(r_push_r),
+ .CLK(aclk),
+ .D(in[9]),
+ .Q(r_push_r_reg[9]),
+ .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm
+ (m_valid_i_reg,
+ next,
+ Q,
+ m_valid_i_reg_0,
+ sel_first_reg,
+ sel_first_reg_0,
+ sel_first_i,
+ D,
+ E,
+ m_valid_i_reg_1,
+ b_push,
+ m_axi_awvalid,
+ si_rs_awvalid,
+ \axlen_cnt_reg[8] ,
+ sel_first,
+ areset_d1,
+ sel_first_reg_1,
+ sel_first_reg_2,
+ \axlen_cnt_reg[3] ,
+ \axlen_cnt_reg[0] ,
+ \axlen_cnt_reg[0]_0 ,
+ \axlen_cnt_reg[3]_0 ,
+ next_pending,
+ m_axi_awready,
+ b_full,
+ cnt_read,
+ aclk);
+ output m_valid_i_reg;
+ output next;
+ output [1:0]Q;
+ output m_valid_i_reg_0;
+ output sel_first_reg;
+ output sel_first_reg_0;
+ output sel_first_i;
+ output [1:0]D;
+ output [0:0]E;
+ output [0:0]m_valid_i_reg_1;
+ output b_push;
+ output m_axi_awvalid;
+ input si_rs_awvalid;
+ input \axlen_cnt_reg[8] ;
+ input sel_first;
+ input areset_d1;
+ input sel_first_reg_1;
+ input sel_first_reg_2;
+ input [1:0]\axlen_cnt_reg[3] ;
+ input [0:0]\axlen_cnt_reg[0] ;
+ input \axlen_cnt_reg[0]_0 ;
+ input \axlen_cnt_reg[3]_0 ;
+ input next_pending;
+ input m_axi_awready;
+ input b_full;
+ input [1:0]cnt_read;
+ input aclk;
+
+ wire [1:0]D;
+ wire [0:0]E;
+ wire [1:0]Q;
+ wire aclk;
+ wire areset_d1;
+ wire [0:0]\axlen_cnt_reg[0] ;
+ wire \axlen_cnt_reg[0]_0 ;
+ wire [1:0]\axlen_cnt_reg[3] ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire \axlen_cnt_reg[8] ;
+ wire b_full;
+ wire b_push;
+ wire [1:0]cnt_read;
+ wire m_axi_awready;
+ wire m_axi_awvalid;
+ wire m_valid_i_reg;
+ wire m_valid_i_reg_0;
+ wire [0:0]m_valid_i_reg_1;
+ wire next;
+ wire next_pending;
+ wire sel_first;
+ wire sel_first_i;
+ wire sel_first_reg;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire sel_first_reg_2;
+ wire si_rs_awvalid;
+ wire \state[0]_i_1_n_0 ;
+ wire \state[1]_i_1_n_0 ;
+
+ LUT6 #(
+ .INIT(64'h1000FFFF10001000))
+ \axlen_cnt[0]_i_1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_awvalid),
+ .I3(\axlen_cnt_reg[3] [0]),
+ .I4(\axlen_cnt_reg[0] ),
+ .I5(\axlen_cnt_reg[0]_0 ),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair116" *)
+ LUT4 #(
+ .INIT(16'hAAAE))
+ \axlen_cnt[3]_i_1
+ (.I0(next),
+ .I1(si_rs_awvalid),
+ .I2(Q[0]),
+ .I3(Q[1]),
+ .O(m_valid_i_reg_0));
+ LUT6 #(
+ .INIT(64'hFFFF100010001000))
+ \axlen_cnt[3]_i_1__0
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_awvalid),
+ .I3(\axlen_cnt_reg[3] [1]),
+ .I4(\axlen_cnt_reg[3]_0 ),
+ .I5(\axlen_cnt_reg[0]_0 ),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair116" *)
+ LUT5 #(
+ .INIT(32'h0000AAAE))
+ \axlen_cnt[8]_i_1__0
+ (.I0(next),
+ .I1(si_rs_awvalid),
+ .I2(Q[0]),
+ .I3(Q[1]),
+ .I4(\axlen_cnt_reg[8] ),
+ .O(m_valid_i_reg));
+ (* SOFT_HLUTNM = "soft_lutpair117" *)
+ LUT2 #(
+ .INIT(4'h2))
+ m_axi_awvalid_INST_0
+ (.I0(Q[0]),
+ .I1(Q[1]),
+ .O(m_axi_awvalid));
+ LUT2 #(
+ .INIT(4'hB))
+ \m_payload_i[31]_i_1
+ (.I0(b_push),
+ .I1(si_rs_awvalid),
+ .O(m_valid_i_reg_1));
+ (* SOFT_HLUTNM = "soft_lutpair115" *)
+ LUT5 #(
+ .INIT(32'h08080C08))
+ \memory_reg[3][0]_srl4_i_1__0
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(b_full),
+ .I3(m_axi_awready),
+ .I4(next_pending),
+ .O(b_push));
+ (* SOFT_HLUTNM = "soft_lutpair115" *)
+ LUT5 #(
+ .INIT(32'h0FFF0400))
+ next_pending_r_i_4__0
+ (.I0(next_pending),
+ .I1(m_axi_awready),
+ .I2(b_full),
+ .I3(Q[0]),
+ .I4(Q[1]),
+ .O(next));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF444F4444))
+ sel_first_i_1
+ (.I0(next),
+ .I1(sel_first),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_awvalid),
+ .I5(areset_d1),
+ .O(sel_first_reg));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF444F4444))
+ sel_first_i_1__0
+ (.I0(next),
+ .I1(sel_first_reg_1),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_awvalid),
+ .I5(areset_d1),
+ .O(sel_first_reg_0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF444F4444))
+ sel_first_i_1__1
+ (.I0(next),
+ .I1(sel_first_reg_2),
+ .I2(Q[1]),
+ .I3(Q[0]),
+ .I4(si_rs_awvalid),
+ .I5(areset_d1),
+ .O(sel_first_i));
+ LUT6 #(
+ .INIT(64'hF0F0FFFF7373FF00))
+ \state[0]_i_1
+ (.I0(next_pending),
+ .I1(m_axi_awready),
+ .I2(b_full),
+ .I3(si_rs_awvalid),
+ .I4(Q[0]),
+ .I5(Q[1]),
+ .O(\state[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h08080808AA000800))
+ \state[1]_i_1
+ (.I0(Q[0]),
+ .I1(cnt_read[1]),
+ .I2(cnt_read[0]),
+ .I3(m_axi_awready),
+ .I4(next_pending),
+ .I5(Q[1]),
+ .O(\state[1]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \state_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\state[0]_i_1_n_0 ),
+ .Q(Q[0]),
+ .R(areset_d1));
+ FDRE #(
+ .INIT(1'b0))
+ \state_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\state[1]_i_1_n_0 ),
+ .Q(Q[1]),
+ .R(areset_d1));
+ (* SOFT_HLUTNM = "soft_lutpair117" *)
+ LUT3 #(
+ .INIT(8'h10))
+ \wrap_boundary_axaddr_r[11]_i_1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(si_rs_awvalid),
+ .O(E));
+endmodule
+
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd
+ (wrap_next_pending,
+ sel_first,
+ Q,
+ \m_payload_i_reg[39] ,
+ \axlen_cnt_reg[0]_0 ,
+ \axlen_cnt_reg[3]_0 ,
+ \axlen_cnt_reg[2]_0 ,
+ \axaddr_offset_r_reg[3]_0 ,
+ \wrap_second_len_r_reg[3]_0 ,
+ aclk,
+ sel_first_reg_0,
+ next,
+ \axlen_cnt_reg[2]_1 ,
+ sel_first_i,
+ incr_next_pending,
+ next_pending_r_reg_0,
+ E,
+ D,
+ \wrap_second_len_r_reg[3]_1 ,
+ \axaddr_wrap_reg[0]_0 ,
+ \axlen_cnt_reg[3]_1 ,
+ \wrap_cnt_r_reg[3]_0 ,
+ \wrap_boundary_axaddr_r_reg[6]_0 );
+ output wrap_next_pending;
+ output sel_first;
+ output [11:0]Q;
+ output \m_payload_i_reg[39] ;
+ output [0:0]\axlen_cnt_reg[0]_0 ;
+ output \axlen_cnt_reg[3]_0 ;
+ output \axlen_cnt_reg[2]_0 ;
+ output [3:0]\axaddr_offset_r_reg[3]_0 ;
+ output [3:0]\wrap_second_len_r_reg[3]_0 ;
+ input aclk;
+ input sel_first_reg_0;
+ input next;
+ input [16:0]\axlen_cnt_reg[2]_1 ;
+ input sel_first_i;
+ input incr_next_pending;
+ input next_pending_r_reg_0;
+ input [0:0]E;
+ input [3:0]D;
+ input [3:0]\wrap_second_len_r_reg[3]_1 ;
+ input \axaddr_wrap_reg[0]_0 ;
+ input [1:0]\axlen_cnt_reg[3]_1 ;
+ input [3:0]\wrap_cnt_r_reg[3]_0 ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [11:0]Q;
+ wire aclk;
+ wire [3:0]\axaddr_offset_r_reg[3]_0 ;
+ wire [11:0]axaddr_wrap0;
+ wire axaddr_wrap1;
+ wire \axaddr_wrap[0]_i_1__0_n_0 ;
+ wire \axaddr_wrap[10]_i_1__0_n_0 ;
+ wire \axaddr_wrap[11]_i_1__0_n_0 ;
+ wire \axaddr_wrap[11]_i_4__0_n_0 ;
+ wire \axaddr_wrap[1]_i_1__0_n_0 ;
+ wire \axaddr_wrap[2]_i_1__0_n_0 ;
+ wire \axaddr_wrap[3]_i_1__0_n_0 ;
+ wire \axaddr_wrap[3]_i_3_n_0 ;
+ wire \axaddr_wrap[3]_i_4_n_0 ;
+ wire \axaddr_wrap[3]_i_5_n_0 ;
+ wire \axaddr_wrap[3]_i_6_n_0 ;
+ wire \axaddr_wrap[4]_i_1__0_n_0 ;
+ wire \axaddr_wrap[5]_i_1__0_n_0 ;
+ wire \axaddr_wrap[6]_i_1__0_n_0 ;
+ wire \axaddr_wrap[7]_i_1__0_n_0 ;
+ wire \axaddr_wrap[8]_i_1__0_n_0 ;
+ wire \axaddr_wrap[9]_i_1__0_n_0 ;
+ wire \axaddr_wrap_reg[0]_0 ;
+ wire \axaddr_wrap_reg[11]_i_3_n_1 ;
+ wire \axaddr_wrap_reg[11]_i_3_n_2 ;
+ wire \axaddr_wrap_reg[11]_i_3_n_3 ;
+ wire \axaddr_wrap_reg[3]_i_2_n_0 ;
+ wire \axaddr_wrap_reg[3]_i_2_n_1 ;
+ wire \axaddr_wrap_reg[3]_i_2_n_2 ;
+ wire \axaddr_wrap_reg[3]_i_2_n_3 ;
+ wire \axaddr_wrap_reg[7]_i_2_n_0 ;
+ wire \axaddr_wrap_reg[7]_i_2_n_1 ;
+ wire \axaddr_wrap_reg[7]_i_2_n_2 ;
+ wire \axaddr_wrap_reg[7]_i_2_n_3 ;
+ wire \axlen_cnt[1]_i_1_n_0 ;
+ wire \axlen_cnt[2]_i_1_n_0 ;
+ wire \axlen_cnt[4]_i_1_n_0 ;
+ wire [0:0]\axlen_cnt_reg[0]_0 ;
+ wire \axlen_cnt_reg[2]_0 ;
+ wire [16:0]\axlen_cnt_reg[2]_1 ;
+ wire \axlen_cnt_reg[3]_0 ;
+ wire [1:0]\axlen_cnt_reg[3]_1 ;
+ wire \axlen_cnt_reg_n_0_[1] ;
+ wire \axlen_cnt_reg_n_0_[2] ;
+ wire \axlen_cnt_reg_n_0_[3] ;
+ wire \axlen_cnt_reg_n_0_[4] ;
+ wire incr_next_pending;
+ wire \m_payload_i_reg[39] ;
+ wire next;
+ wire next_pending_r_i_2__2_n_0;
+ wire next_pending_r_reg_0;
+ wire next_pending_r_reg_n_0;
+ wire sel_first;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire [11:0]wrap_boundary_axaddr_r;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
+ wire [3:0]wrap_cnt_r;
+ wire [3:0]\wrap_cnt_r_reg[3]_0 ;
+ wire wrap_next_pending;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+ wire [3:0]\wrap_second_len_r_reg[3]_1 ;
+ wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
+
+ FDRE \axaddr_offset_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[0]),
+ .Q(\axaddr_offset_r_reg[3]_0 [0]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[1]),
+ .Q(\axaddr_offset_r_reg[3]_0 [1]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[2]),
+ .Q(\axaddr_offset_r_reg[3]_0 [2]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[3]),
+ .Q(\axaddr_offset_r_reg[3]_0 [3]),
+ .R(1'b0));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[0]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[0]),
+ .I3(wrap_boundary_axaddr_r[0]),
+ .I4(\axlen_cnt_reg[2]_1 [0]),
+ .O(\axaddr_wrap[0]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[10]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[10]),
+ .I3(wrap_boundary_axaddr_r[10]),
+ .I4(\axlen_cnt_reg[2]_1 [10]),
+ .O(\axaddr_wrap[10]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[11]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[11]),
+ .I3(wrap_boundary_axaddr_r[11]),
+ .I4(\axlen_cnt_reg[2]_1 [11]),
+ .O(\axaddr_wrap[11]_i_1__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h4100004100000000))
+ \axaddr_wrap[11]_i_2__0
+ (.I0(\axlen_cnt_reg_n_0_[4] ),
+ .I1(wrap_cnt_r[1]),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(wrap_cnt_r[2]),
+ .I5(\axaddr_wrap[11]_i_4__0_n_0 ),
+ .O(axaddr_wrap1));
+ LUT4 #(
+ .INIT(16'h9009))
+ \axaddr_wrap[11]_i_4__0
+ (.I0(wrap_cnt_r[3]),
+ .I1(\axlen_cnt_reg_n_0_[3] ),
+ .I2(wrap_cnt_r[0]),
+ .I3(\axlen_cnt_reg[0]_0 ),
+ .O(\axaddr_wrap[11]_i_4__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[1]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[1]),
+ .I3(wrap_boundary_axaddr_r[1]),
+ .I4(\axlen_cnt_reg[2]_1 [1]),
+ .O(\axaddr_wrap[1]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[2]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[2]),
+ .I3(wrap_boundary_axaddr_r[2]),
+ .I4(\axlen_cnt_reg[2]_1 [2]),
+ .O(\axaddr_wrap[2]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[3]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[3]),
+ .I3(wrap_boundary_axaddr_r[3]),
+ .I4(\axlen_cnt_reg[2]_1 [3]),
+ .O(\axaddr_wrap[3]_i_1__0_n_0 ));
+ LUT3 #(
+ .INIT(8'h6A))
+ \axaddr_wrap[3]_i_3
+ (.I0(Q[3]),
+ .I1(\axlen_cnt_reg[2]_1 [13]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_wrap[3]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_wrap[3]_i_4
+ (.I0(Q[2]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [13]),
+ .O(\axaddr_wrap[3]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_wrap[3]_i_5
+ (.I0(Q[1]),
+ .I1(\axlen_cnt_reg[2]_1 [13]),
+ .I2(\axlen_cnt_reg[2]_1 [12]),
+ .O(\axaddr_wrap[3]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hA9))
+ \axaddr_wrap[3]_i_6
+ (.I0(Q[0]),
+ .I1(\axlen_cnt_reg[2]_1 [12]),
+ .I2(\axlen_cnt_reg[2]_1 [13]),
+ .O(\axaddr_wrap[3]_i_6_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[4]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[4]),
+ .I3(wrap_boundary_axaddr_r[4]),
+ .I4(\axlen_cnt_reg[2]_1 [4]),
+ .O(\axaddr_wrap[4]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[5]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[5]),
+ .I3(wrap_boundary_axaddr_r[5]),
+ .I4(\axlen_cnt_reg[2]_1 [5]),
+ .O(\axaddr_wrap[5]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[6]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[6]),
+ .I3(wrap_boundary_axaddr_r[6]),
+ .I4(\axlen_cnt_reg[2]_1 [6]),
+ .O(\axaddr_wrap[6]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[7]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[7]),
+ .I3(wrap_boundary_axaddr_r[7]),
+ .I4(\axlen_cnt_reg[2]_1 [7]),
+ .O(\axaddr_wrap[7]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[8]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[8]),
+ .I3(wrap_boundary_axaddr_r[8]),
+ .I4(\axlen_cnt_reg[2]_1 [8]),
+ .O(\axaddr_wrap[8]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'hFB73C840))
+ \axaddr_wrap[9]_i_1__0
+ (.I0(axaddr_wrap1),
+ .I1(next),
+ .I2(axaddr_wrap0[9]),
+ .I3(wrap_boundary_axaddr_r[9]),
+ .I4(\axlen_cnt_reg[2]_1 [9]),
+ .O(\axaddr_wrap[9]_i_1__0_n_0 ));
+ FDRE \axaddr_wrap_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[0]_i_1__0_n_0 ),
+ .Q(Q[0]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[10]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[10]_i_1__0_n_0 ),
+ .Q(Q[10]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[11]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[11]_i_1__0_n_0 ),
+ .Q(Q[11]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[11]_i_3
+ (.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
+ .CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(axaddr_wrap0[11:8]),
+ .S(Q[11:8]));
+ FDRE \axaddr_wrap_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[1]_i_1__0_n_0 ),
+ .Q(Q[1]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[2]_i_1__0_n_0 ),
+ .Q(Q[2]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[3]_i_1__0_n_0 ),
+ .Q(Q[3]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[3]_i_2
+ (.CI(1'b0),
+ .CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI(Q[3:0]),
+ .O(axaddr_wrap0[3:0]),
+ .S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
+ FDRE \axaddr_wrap_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[4]_i_1__0_n_0 ),
+ .Q(Q[4]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[5]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[5]_i_1__0_n_0 ),
+ .Q(Q[5]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[6]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[6]_i_1__0_n_0 ),
+ .Q(Q[6]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[7]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[7]_i_1__0_n_0 ),
+ .Q(Q[7]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[7]_i_2
+ (.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
+ .CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(axaddr_wrap0[7:4]),
+ .S(Q[7:4]));
+ FDRE \axaddr_wrap_reg[8]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[8]_i_1__0_n_0 ),
+ .Q(Q[8]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[9]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap[9]_i_1__0_n_0 ),
+ .Q(Q[9]),
+ .R(1'b0));
+ LUT5 #(
+ .INIT(32'hFF909090))
+ \axlen_cnt[1]_i_1
+ (.I0(\axlen_cnt_reg[0]_0 ),
+ .I1(\axlen_cnt_reg_n_0_[1] ),
+ .I2(\axlen_cnt_reg[3]_0 ),
+ .I3(E),
+ .I4(\axlen_cnt_reg[2]_1 [15]),
+ .O(\axlen_cnt[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFE100E100E100))
+ \axlen_cnt[2]_i_1
+ (.I0(\axlen_cnt_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg[0]_0 ),
+ .I2(\axlen_cnt_reg_n_0_[2] ),
+ .I3(\axlen_cnt_reg[3]_0 ),
+ .I4(E),
+ .I5(\axlen_cnt_reg[2]_1 [16]),
+ .O(\axlen_cnt[2]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hFE01))
+ \axlen_cnt[3]_i_2__0
+ (.I0(\axlen_cnt_reg_n_0_[2] ),
+ .I1(\axlen_cnt_reg[0]_0 ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[3] ),
+ .O(\axlen_cnt_reg[2]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair127" *)
+ LUT5 #(
+ .INIT(32'h0000FFFE))
+ \axlen_cnt[3]_i_3
+ (.I0(\axlen_cnt_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg_n_0_[4] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(E),
+ .O(\axlen_cnt_reg[3]_0 ));
+ LUT6 #(
+ .INIT(64'h4444444444444440))
+ \axlen_cnt[4]_i_1
+ (.I0(E),
+ .I1(\axlen_cnt_reg_n_0_[4] ),
+ .I2(\axlen_cnt_reg_n_0_[2] ),
+ .I3(\axlen_cnt_reg[0]_0 ),
+ .I4(\axlen_cnt_reg_n_0_[1] ),
+ .I5(\axlen_cnt_reg_n_0_[3] ),
+ .O(\axlen_cnt[4]_i_1_n_0 ));
+ FDRE \axlen_cnt_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt_reg[3]_1 [0]),
+ .Q(\axlen_cnt_reg[0]_0 ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[1]_i_1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[2]_i_1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt_reg[3]_1 [1]),
+ .Q(\axlen_cnt_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[4]_i_1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[4] ),
+ .R(1'b0));
+ LUT5 #(
+ .INIT(32'hFFAEAAAE))
+ next_pending_r_i_1
+ (.I0(next_pending_r_reg_0),
+ .I1(next_pending_r_reg_n_0),
+ .I2(E),
+ .I3(next),
+ .I4(next_pending_r_i_2__2_n_0),
+ .O(wrap_next_pending));
+ (* SOFT_HLUTNM = "soft_lutpair127" *)
+ LUT5 #(
+ .INIT(32'h55555554))
+ next_pending_r_i_2__2
+ (.I0(E),
+ .I1(\axlen_cnt_reg_n_0_[2] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[4] ),
+ .I4(\axlen_cnt_reg_n_0_[3] ),
+ .O(next_pending_r_i_2__2_n_0));
+ FDRE next_pending_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(wrap_next_pending),
+ .Q(next_pending_r_reg_n_0),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hABA8))
+ s_axburst_eq1_i_1
+ (.I0(wrap_next_pending),
+ .I1(sel_first_i),
+ .I2(\axlen_cnt_reg[2]_1 [14]),
+ .I3(incr_next_pending),
+ .O(\m_payload_i_reg[39] ));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_reg_0),
+ .Q(sel_first),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[0]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [0]),
+ .Q(wrap_boundary_axaddr_r[0]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[10]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[2]_1 [10]),
+ .Q(wrap_boundary_axaddr_r[10]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[11]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[2]_1 [11]),
+ .Q(wrap_boundary_axaddr_r[11]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[1]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [1]),
+ .Q(wrap_boundary_axaddr_r[1]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[2]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [2]),
+ .Q(wrap_boundary_axaddr_r[2]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[3]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [3]),
+ .Q(wrap_boundary_axaddr_r[3]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[4]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [4]),
+ .Q(wrap_boundary_axaddr_r[4]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[5]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [5]),
+ .Q(wrap_boundary_axaddr_r[5]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[6]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [6]),
+ .Q(wrap_boundary_axaddr_r[6]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[7]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[2]_1 [7]),
+ .Q(wrap_boundary_axaddr_r[7]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[8]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[2]_1 [8]),
+ .Q(wrap_boundary_axaddr_r[8]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[9]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[2]_1 [9]),
+ .Q(wrap_boundary_axaddr_r[9]),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [0]),
+ .Q(wrap_cnt_r[0]),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [1]),
+ .Q(wrap_cnt_r[1]),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [2]),
+ .Q(wrap_cnt_r[2]),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [3]),
+ .Q(wrap_cnt_r[3]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_second_len_r_reg[3]_1 [0]),
+ .Q(\wrap_second_len_r_reg[3]_0 [0]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_second_len_r_reg[3]_1 [1]),
+ .Q(\wrap_second_len_r_reg[3]_0 [1]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_second_len_r_reg[3]_1 [2]),
+ .Q(\wrap_second_len_r_reg[3]_0 [2]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_second_len_r_reg[3]_1 [3]),
+ .Q(\wrap_second_len_r_reg[3]_0 [3]),
+ .R(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_19_b2s_wrap_cmd" *)
+module TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3
+ (wrap_next_pending,
+ sel_first_reg_0,
+ O,
+ Q,
+ \axaddr_wrap_reg[7]_0 ,
+ \axaddr_wrap_reg[11]_0 ,
+ \m_payload_i_reg[39] ,
+ \axlen_cnt_reg[4]_0 ,
+ \axaddr_offset_r_reg[3]_0 ,
+ \wrap_second_len_r_reg[3]_0 ,
+ \wrap_boundary_axaddr_r_reg[11]_0 ,
+ aclk,
+ sel_first_reg_1,
+ sel_first_i,
+ \axlen_cnt_reg[3]_0 ,
+ incr_next_pending,
+ next_pending_r_reg_0,
+ E,
+ r_push,
+ \axlen_cnt_reg[3]_1 ,
+ si_rs_arvalid,
+ axaddr_offset,
+ D,
+ \axaddr_wrap_reg[0]_0 ,
+ \wrap_cnt_r_reg[3]_0 ,
+ \wrap_boundary_axaddr_r_reg[6]_0 ,
+ \axaddr_wrap_reg[11]_1 );
+ output wrap_next_pending;
+ output sel_first_reg_0;
+ output [3:0]O;
+ output [11:0]Q;
+ output [3:0]\axaddr_wrap_reg[7]_0 ;
+ output [3:0]\axaddr_wrap_reg[11]_0 ;
+ output \m_payload_i_reg[39] ;
+ output \axlen_cnt_reg[4]_0 ;
+ output [3:0]\axaddr_offset_r_reg[3]_0 ;
+ output [3:0]\wrap_second_len_r_reg[3]_0 ;
+ output [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ;
+ input aclk;
+ input sel_first_reg_1;
+ input sel_first_i;
+ input [11:0]\axlen_cnt_reg[3]_0 ;
+ input incr_next_pending;
+ input next_pending_r_reg_0;
+ input [0:0]E;
+ input r_push;
+ input [0:0]\axlen_cnt_reg[3]_1 ;
+ input si_rs_arvalid;
+ input [3:0]axaddr_offset;
+ input [3:0]D;
+ input \axaddr_wrap_reg[0]_0 ;
+ input [3:0]\wrap_cnt_r_reg[3]_0 ;
+ input [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
+ input [11:0]\axaddr_wrap_reg[11]_1 ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [3:0]O;
+ wire [11:0]Q;
+ wire aclk;
+ wire [3:0]axaddr_offset;
+ wire [3:0]\axaddr_offset_r_reg[3]_0 ;
+ wire \axaddr_wrap[11]_i_6_n_0 ;
+ wire \axaddr_wrap[3]_i_3_n_0 ;
+ wire \axaddr_wrap[3]_i_4_n_0 ;
+ wire \axaddr_wrap[3]_i_5_n_0 ;
+ wire \axaddr_wrap[3]_i_6_n_0 ;
+ wire \axaddr_wrap_reg[0]_0 ;
+ wire [3:0]\axaddr_wrap_reg[11]_0 ;
+ wire [11:0]\axaddr_wrap_reg[11]_1 ;
+ wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
+ wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
+ wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
+ wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
+ wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
+ wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
+ wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
+ wire [3:0]\axaddr_wrap_reg[7]_0 ;
+ wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
+ wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
+ wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
+ wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
+ wire \axlen_cnt[0]_i_1__2_n_0 ;
+ wire \axlen_cnt[1]_i_1__1_n_0 ;
+ wire \axlen_cnt[2]_i_1__1_n_0 ;
+ wire \axlen_cnt[3]_i_1__2_n_0 ;
+ wire \axlen_cnt[3]_i_2__2_n_0 ;
+ wire \axlen_cnt[3]_i_3__1_n_0 ;
+ wire \axlen_cnt[4]_i_1__1_n_0 ;
+ wire [11:0]\axlen_cnt_reg[3]_0 ;
+ wire [0:0]\axlen_cnt_reg[3]_1 ;
+ wire \axlen_cnt_reg[4]_0 ;
+ wire \axlen_cnt_reg_n_0_[0] ;
+ wire \axlen_cnt_reg_n_0_[1] ;
+ wire \axlen_cnt_reg_n_0_[2] ;
+ wire \axlen_cnt_reg_n_0_[3] ;
+ wire \axlen_cnt_reg_n_0_[4] ;
+ wire incr_next_pending;
+ wire \m_payload_i_reg[39] ;
+ wire next_pending_r_i_2__1_n_0;
+ wire next_pending_r_reg_0;
+ wire next_pending_r_reg_n_0;
+ wire r_push;
+ wire sel_first_i;
+ wire sel_first_reg_0;
+ wire sel_first_reg_1;
+ wire si_rs_arvalid;
+ wire [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ;
+ wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
+ wire [3:0]\wrap_cnt_r_reg[3]_0 ;
+ wire \wrap_cnt_r_reg_n_0_[0] ;
+ wire \wrap_cnt_r_reg_n_0_[1] ;
+ wire \wrap_cnt_r_reg_n_0_[2] ;
+ wire \wrap_cnt_r_reg_n_0_[3] ;
+ wire wrap_next_pending;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+ wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
+
+ FDRE \axaddr_offset_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(axaddr_offset[0]),
+ .Q(\axaddr_offset_r_reg[3]_0 [0]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(axaddr_offset[1]),
+ .Q(\axaddr_offset_r_reg[3]_0 [1]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(axaddr_offset[2]),
+ .Q(\axaddr_offset_r_reg[3]_0 [2]),
+ .R(1'b0));
+ FDRE \axaddr_offset_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(axaddr_offset[3]),
+ .Q(\axaddr_offset_r_reg[3]_0 [3]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h4100004100000000))
+ \axaddr_wrap[11]_i_5
+ (.I0(\axlen_cnt_reg_n_0_[4] ),
+ .I1(\wrap_cnt_r_reg_n_0_[1] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(\wrap_cnt_r_reg_n_0_[2] ),
+ .I5(\axaddr_wrap[11]_i_6_n_0 ),
+ .O(\axlen_cnt_reg[4]_0 ));
+ LUT4 #(
+ .INIT(16'h9009))
+ \axaddr_wrap[11]_i_6
+ (.I0(\wrap_cnt_r_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg_n_0_[3] ),
+ .I2(\wrap_cnt_r_reg_n_0_[0] ),
+ .I3(\axlen_cnt_reg_n_0_[0] ),
+ .O(\axaddr_wrap[11]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'h6A))
+ \axaddr_wrap[3]_i_3
+ (.I0(Q[3]),
+ .I1(\axlen_cnt_reg[3]_0 [6]),
+ .I2(\axlen_cnt_reg[3]_0 [5]),
+ .O(\axaddr_wrap[3]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_wrap[3]_i_4
+ (.I0(Q[2]),
+ .I1(\axlen_cnt_reg[3]_0 [5]),
+ .I2(\axlen_cnt_reg[3]_0 [6]),
+ .O(\axaddr_wrap[3]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'h9A))
+ \axaddr_wrap[3]_i_5
+ (.I0(Q[1]),
+ .I1(\axlen_cnt_reg[3]_0 [6]),
+ .I2(\axlen_cnt_reg[3]_0 [5]),
+ .O(\axaddr_wrap[3]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hA9))
+ \axaddr_wrap[3]_i_6
+ (.I0(Q[0]),
+ .I1(\axlen_cnt_reg[3]_0 [5]),
+ .I2(\axlen_cnt_reg[3]_0 [6]),
+ .O(\axaddr_wrap[3]_i_6_n_0 ));
+ FDRE \axaddr_wrap_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [0]),
+ .Q(Q[0]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[10]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [10]),
+ .Q(Q[10]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[11]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [11]),
+ .Q(Q[11]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[11]_i_3__0
+ (.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
+ .CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\axaddr_wrap_reg[11]_0 ),
+ .S(Q[11:8]));
+ FDRE \axaddr_wrap_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [1]),
+ .Q(Q[1]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [2]),
+ .Q(Q[2]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [3]),
+ .Q(Q[3]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[3]_i_2__0
+ (.CI(1'b0),
+ .CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI(Q[3:0]),
+ .O(O),
+ .S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
+ FDRE \axaddr_wrap_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [4]),
+ .Q(Q[4]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[5]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [5]),
+ .Q(Q[5]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[6]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [6]),
+ .Q(Q[6]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[7]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [7]),
+ .Q(Q[7]),
+ .R(1'b0));
+ CARRY4 \axaddr_wrap_reg[7]_i_2__0
+ (.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
+ .CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\axaddr_wrap_reg[7]_0 ),
+ .S(Q[7:4]));
+ FDRE \axaddr_wrap_reg[8]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [8]),
+ .Q(Q[8]),
+ .R(1'b0));
+ FDRE \axaddr_wrap_reg[9]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axaddr_wrap_reg[11]_1 [9]),
+ .Q(Q[9]),
+ .R(1'b0));
+ LUT5 #(
+ .INIT(32'h40FF4040))
+ \axlen_cnt[0]_i_1__2
+ (.I0(\axlen_cnt_reg[3]_1 ),
+ .I1(si_rs_arvalid),
+ .I2(\axlen_cnt_reg[3]_0 [8]),
+ .I3(\axlen_cnt_reg_n_0_[0] ),
+ .I4(\axlen_cnt[3]_i_3__1_n_0 ),
+ .O(\axlen_cnt[0]_i_1__2_n_0 ));
+ LUT5 #(
+ .INIT(32'hFF909090))
+ \axlen_cnt[1]_i_1__1
+ (.I0(\axlen_cnt_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg_n_0_[1] ),
+ .I2(\axlen_cnt[3]_i_3__1_n_0 ),
+ .I3(E),
+ .I4(\axlen_cnt_reg[3]_0 [9]),
+ .O(\axlen_cnt[1]_i_1__1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFE100E100E100))
+ \axlen_cnt[2]_i_1__1
+ (.I0(\axlen_cnt_reg_n_0_[1] ),
+ .I1(\axlen_cnt_reg_n_0_[0] ),
+ .I2(\axlen_cnt_reg_n_0_[2] ),
+ .I3(\axlen_cnt[3]_i_3__1_n_0 ),
+ .I4(E),
+ .I5(\axlen_cnt_reg[3]_0 [10]),
+ .O(\axlen_cnt[2]_i_1__1_n_0 ));
+ LUT5 #(
+ .INIT(32'hFF404040))
+ \axlen_cnt[3]_i_1__2
+ (.I0(\axlen_cnt_reg[3]_1 ),
+ .I1(si_rs_arvalid),
+ .I2(\axlen_cnt_reg[3]_0 [11]),
+ .I3(\axlen_cnt[3]_i_2__2_n_0 ),
+ .I4(\axlen_cnt[3]_i_3__1_n_0 ),
+ .O(\axlen_cnt[3]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT4 #(
+ .INIT(16'hFE01))
+ \axlen_cnt[3]_i_2__2
+ (.I0(\axlen_cnt_reg_n_0_[2] ),
+ .I1(\axlen_cnt_reg_n_0_[0] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[3] ),
+ .O(\axlen_cnt[3]_i_2__2_n_0 ));
+ LUT5 #(
+ .INIT(32'h0000FFFE))
+ \axlen_cnt[3]_i_3__1
+ (.I0(\axlen_cnt_reg_n_0_[3] ),
+ .I1(\axlen_cnt_reg_n_0_[4] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(E),
+ .O(\axlen_cnt[3]_i_3__1_n_0 ));
+ LUT6 #(
+ .INIT(64'h4444444444444440))
+ \axlen_cnt[4]_i_1__1
+ (.I0(E),
+ .I1(\axlen_cnt_reg_n_0_[4] ),
+ .I2(\axlen_cnt_reg_n_0_[2] ),
+ .I3(\axlen_cnt_reg_n_0_[0] ),
+ .I4(\axlen_cnt_reg_n_0_[1] ),
+ .I5(\axlen_cnt_reg_n_0_[3] ),
+ .O(\axlen_cnt[4]_i_1__1_n_0 ));
+ FDRE \axlen_cnt_reg[0]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[0]_i_1__2_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[1]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[1]_i_1__1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[2]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[2]_i_1__1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[3]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[3]_i_1__2_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \axlen_cnt_reg[4]
+ (.C(aclk),
+ .CE(\axaddr_wrap_reg[0]_0 ),
+ .D(\axlen_cnt[4]_i_1__1_n_0 ),
+ .Q(\axlen_cnt_reg_n_0_[4] ),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'hFFAAAAAAAEAEAEAE))
+ next_pending_r_i_1__1
+ (.I0(next_pending_r_reg_0),
+ .I1(next_pending_r_reg_n_0),
+ .I2(E),
+ .I3(next_pending_r_i_2__1_n_0),
+ .I4(\axlen_cnt[3]_i_3__1_n_0 ),
+ .I5(r_push),
+ .O(wrap_next_pending));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT5 #(
+ .INIT(32'hFFFFFFFD))
+ next_pending_r_i_2__1
+ (.I0(\axlen_cnt_reg_n_0_[0] ),
+ .I1(\axlen_cnt_reg_n_0_[3] ),
+ .I2(\axlen_cnt_reg_n_0_[1] ),
+ .I3(\axlen_cnt_reg_n_0_[2] ),
+ .I4(\axlen_cnt_reg_n_0_[4] ),
+ .O(next_pending_r_i_2__1_n_0));
+ FDRE next_pending_r_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(wrap_next_pending),
+ .Q(next_pending_r_reg_n_0),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hABA8))
+ s_axburst_eq1_i_1__0
+ (.I0(wrap_next_pending),
+ .I1(sel_first_i),
+ .I2(\axlen_cnt_reg[3]_0 [7]),
+ .I3(incr_next_pending),
+ .O(\m_payload_i_reg[39] ));
+ FDRE sel_first_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(sel_first_reg_1),
+ .Q(sel_first_reg_0),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[0]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [0]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [0]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[10]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[3]_0 [3]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [10]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[11]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[3]_0 [4]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [11]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[1]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [1]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [1]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[2]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [2]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [2]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[3]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [3]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [3]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[4]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [4]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [4]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[5]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [5]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [5]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[6]
+ (.C(aclk),
+ .CE(E),
+ .D(\wrap_boundary_axaddr_r_reg[6]_0 [6]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [6]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[7]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[3]_0 [0]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [7]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[8]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[3]_0 [1]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [8]),
+ .R(1'b0));
+ FDRE \wrap_boundary_axaddr_r_reg[9]
+ (.C(aclk),
+ .CE(E),
+ .D(\axlen_cnt_reg[3]_0 [2]),
+ .Q(\wrap_boundary_axaddr_r_reg[11]_0 [9]),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [0]),
+ .Q(\wrap_cnt_r_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [1]),
+ .Q(\wrap_cnt_r_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [2]),
+ .Q(\wrap_cnt_r_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \wrap_cnt_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\wrap_cnt_r_reg[3]_0 [3]),
+ .Q(\wrap_cnt_r_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[0]),
+ .Q(\wrap_second_len_r_reg[3]_0 [0]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[1]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[1]),
+ .Q(\wrap_second_len_r_reg[3]_0 [1]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[2]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[2]),
+ .Q(\wrap_second_len_r_reg[3]_0 [2]),
+ .R(1'b0));
+ FDRE \wrap_second_len_r_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(D[3]),
+ .Q(\wrap_second_len_r_reg[3]_0 [3]),
+ .R(1'b0));
+endmodule
+
+module TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice
+ (s_ready_i_reg,
+ s_ready_i_reg_0,
+ si_rs_awvalid,
+ m_valid_i_reg,
+ si_rs_bready,
+ si_rs_arvalid,
+ m_valid_i_reg_0,
+ si_rs_rready,
+ D,
+ axaddr_offset,
+ \wrap_second_len_r_reg[1] ,
+ axaddr_offset_0,
+ axaddr_incr,
+ \m_payload_i_reg[3] ,
+ \m_payload_i_reg[7] ,
+ O,
+ \m_payload_i_reg[47] ,
+ \m_payload_i_reg[61] ,
+ wrap_second_len,
+ \m_payload_i_reg[47]_0 ,
+ \m_payload_i_reg[47]_1 ,
+ \m_payload_i_reg[61]_0 ,
+ \wrap_second_len_r_reg[3] ,
+ \m_payload_i_reg[47]_2 ,
+ \m_payload_i_reg[6] ,
+ \m_payload_i_reg[6]_0 ,
+ m_axi_awaddr,
+ \m_payload_i_reg[39] ,
+ \m_payload_i_reg[38] ,
+ m_axi_araddr,
+ \m_payload_i_reg[39]_0 ,
+ \m_payload_i_reg[38]_0 ,
+ \m_payload_i_reg[13] ,
+ \m_payload_i_reg[46] ,
+ aclk,
+ s_ready_i0,
+ m_valid_i0,
+ aresetn,
+ \wrap_cnt_r_reg[0] ,
+ Q,
+ b_push,
+ s_axi_awvalid,
+ \wrap_cnt_r_reg[0]_0 ,
+ \wrap_second_len_r_reg[3]_0 ,
+ S,
+ \axaddr_incr_reg[3] ,
+ \axaddr_offset_r_reg[0] ,
+ \axaddr_offset_r_reg[3] ,
+ \axaddr_offset_r_reg[0]_0 ,
+ \axaddr_offset_r_reg[3]_0 ,
+ si_rs_rvalid,
+ s_axi_rready,
+ s_axi_bready,
+ si_rs_bvalid,
+ s_axi_awid,
+ s_axi_awlen,
+ s_axi_awburst,
+ s_axi_awsize,
+ s_axi_awprot,
+ s_axi_awaddr,
+ \m_axi_awaddr[11] ,
+ \m_axi_awaddr[11]_0 ,
+ \m_axi_awaddr[11]_1 ,
+ sel_first_1,
+ sel_first,
+ s_axi_arid,
+ s_axi_arlen,
+ s_axi_arburst,
+ s_axi_arsize,
+ s_axi_arprot,
+ s_axi_araddr,
+ \m_axi_araddr[11] ,
+ \m_axi_araddr[11]_0 ,
+ \m_axi_araddr[11]_1 ,
+ sel_first_2,
+ \m_axi_araddr[11]_2 ,
+ out,
+ \skid_buffer_reg[1] ,
+ \skid_buffer_reg[46] ,
+ \skid_buffer_reg[33] ,
+ E,
+ \m_payload_i_reg[0] );
+ output s_ready_i_reg;
+ output s_ready_i_reg_0;
+ output si_rs_awvalid;
+ output m_valid_i_reg;
+ output si_rs_bready;
+ output si_rs_arvalid;
+ output m_valid_i_reg_0;
+ output si_rs_rready;
+ output [3:0]D;
+ output [3:0]axaddr_offset;
+ output [3:0]\wrap_second_len_r_reg[1] ;
+ output [3:0]axaddr_offset_0;
+ output [11:0]axaddr_incr;
+ output [3:0]\m_payload_i_reg[3] ;
+ output [3:0]\m_payload_i_reg[7] ;
+ output [3:0]O;
+ output \m_payload_i_reg[47] ;
+ output [54:0]\m_payload_i_reg[61] ;
+ output [3:0]wrap_second_len;
+ output \m_payload_i_reg[47]_0 ;
+ output \m_payload_i_reg[47]_1 ;
+ output [54:0]\m_payload_i_reg[61]_0 ;
+ output [3:0]\wrap_second_len_r_reg[3] ;
+ output \m_payload_i_reg[47]_2 ;
+ output [6:0]\m_payload_i_reg[6] ;
+ output [6:0]\m_payload_i_reg[6]_0 ;
+ output [0:0]m_axi_awaddr;
+ output \m_payload_i_reg[39] ;
+ output \m_payload_i_reg[38] ;
+ output [0:0]m_axi_araddr;
+ output \m_payload_i_reg[39]_0 ;
+ output \m_payload_i_reg[38]_0 ;
+ output [13:0]\m_payload_i_reg[13] ;
+ output [46:0]\m_payload_i_reg[46] ;
+ input aclk;
+ input s_ready_i0;
+ input m_valid_i0;
+ input aresetn;
+ input \wrap_cnt_r_reg[0] ;
+ input [3:0]Q;
+ input b_push;
+ input s_axi_awvalid;
+ input \wrap_cnt_r_reg[0]_0 ;
+ input [3:0]\wrap_second_len_r_reg[3]_0 ;
+ input [3:0]S;
+ input [3:0]\axaddr_incr_reg[3] ;
+ input [1:0]\axaddr_offset_r_reg[0] ;
+ input [3:0]\axaddr_offset_r_reg[3] ;
+ input [1:0]\axaddr_offset_r_reg[0]_0 ;
+ input [3:0]\axaddr_offset_r_reg[3]_0 ;
+ input si_rs_rvalid;
+ input s_axi_rready;
+ input s_axi_bready;
+ input si_rs_bvalid;
+ input [11:0]s_axi_awid;
+ input [3:0]s_axi_awlen;
+ input [1:0]s_axi_awburst;
+ input [1:0]s_axi_awsize;
+ input [2:0]s_axi_awprot;
+ input [31:0]s_axi_awaddr;
+ input [0:0]\m_axi_awaddr[11] ;
+ input [0:0]\m_axi_awaddr[11]_0 ;
+ input \m_axi_awaddr[11]_1 ;
+ input sel_first_1;
+ input sel_first;
+ input [11:0]s_axi_arid;
+ input [3:0]s_axi_arlen;
+ input [1:0]s_axi_arburst;
+ input [1:0]s_axi_arsize;
+ input [2:0]s_axi_arprot;
+ input [31:0]s_axi_araddr;
+ input [0:0]\m_axi_araddr[11] ;
+ input [0:0]\m_axi_araddr[11]_0 ;
+ input \m_axi_araddr[11]_1 ;
+ input sel_first_2;
+ input \m_axi_araddr[11]_2 ;
+ input [11:0]out;
+ input [1:0]\skid_buffer_reg[1] ;
+ input [12:0]\skid_buffer_reg[46] ;
+ input [33:0]\skid_buffer_reg[33] ;
+ input [0:0]E;
+ input [0:0]\m_payload_i_reg[0] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [3:0]O;
+ wire [3:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire \ar.ar_pipe_n_2 ;
+ wire aresetn;
+ wire \aw.aw_pipe_n_1 ;
+ wire \aw.aw_pipe_n_94 ;
+ wire [11:0]axaddr_incr;
+ wire [3:0]\axaddr_incr_reg[3] ;
+ wire [3:0]axaddr_offset;
+ wire [3:0]axaddr_offset_0;
+ wire [1:0]\axaddr_offset_r_reg[0] ;
+ wire [1:0]\axaddr_offset_r_reg[0]_0 ;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire [3:0]\axaddr_offset_r_reg[3]_0 ;
+ wire b_push;
+ wire [0:0]m_axi_araddr;
+ wire [0:0]\m_axi_araddr[11] ;
+ wire [0:0]\m_axi_araddr[11]_0 ;
+ wire \m_axi_araddr[11]_1 ;
+ wire \m_axi_araddr[11]_2 ;
+ wire [0:0]m_axi_awaddr;
+ wire [0:0]\m_axi_awaddr[11] ;
+ wire [0:0]\m_axi_awaddr[11]_0 ;
+ wire \m_axi_awaddr[11]_1 ;
+ wire [0:0]\m_payload_i_reg[0] ;
+ wire [13:0]\m_payload_i_reg[13] ;
+ wire \m_payload_i_reg[38] ;
+ wire \m_payload_i_reg[38]_0 ;
+ wire \m_payload_i_reg[39] ;
+ wire \m_payload_i_reg[39]_0 ;
+ wire [3:0]\m_payload_i_reg[3] ;
+ wire [46:0]\m_payload_i_reg[46] ;
+ wire \m_payload_i_reg[47] ;
+ wire \m_payload_i_reg[47]_0 ;
+ wire \m_payload_i_reg[47]_1 ;
+ wire \m_payload_i_reg[47]_2 ;
+ wire [54:0]\m_payload_i_reg[61] ;
+ wire [54:0]\m_payload_i_reg[61]_0 ;
+ wire [6:0]\m_payload_i_reg[6] ;
+ wire [6:0]\m_payload_i_reg[6]_0 ;
+ wire [3:0]\m_payload_i_reg[7] ;
+ wire m_valid_i0;
+ wire m_valid_i_reg;
+ wire m_valid_i_reg_0;
+ wire [11:0]out;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [11:0]s_axi_arid;
+ wire [3:0]s_axi_arlen;
+ wire [2:0]s_axi_arprot;
+ wire [1:0]s_axi_arsize;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [11:0]s_axi_awid;
+ wire [3:0]s_axi_awlen;
+ wire [2:0]s_axi_awprot;
+ wire [1:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_rready;
+ wire s_ready_i0;
+ wire s_ready_i_reg;
+ wire s_ready_i_reg_0;
+ wire sel_first;
+ wire sel_first_1;
+ wire sel_first_2;
+ wire si_rs_arvalid;
+ wire si_rs_awvalid;
+ wire si_rs_bready;
+ wire si_rs_bvalid;
+ wire si_rs_rready;
+ wire si_rs_rvalid;
+ wire [1:0]\skid_buffer_reg[1] ;
+ wire [33:0]\skid_buffer_reg[33] ;
+ wire [12:0]\skid_buffer_reg[46] ;
+ wire \wrap_cnt_r_reg[0] ;
+ wire \wrap_cnt_r_reg[0]_0 ;
+ wire [3:0]wrap_second_len;
+ wire [3:0]\wrap_second_len_r_reg[1] ;
+ wire [3:0]\wrap_second_len_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+
+ TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice \ar.ar_pipe
+ (.O(O),
+ .Q(\m_payload_i_reg[61]_0 ),
+ .aclk(aclk),
+ .\aresetn_d_reg[1]_inv_0 (\ar.ar_pipe_n_2 ),
+ .\aresetn_d_reg[1]_inv_1 (\aw.aw_pipe_n_94 ),
+ .\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
+ .\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0]_0 ),
+ .\axaddr_offset_r_reg[1] (axaddr_offset_0[1]),
+ .\axaddr_offset_r_reg[2] (axaddr_offset_0[2]),
+ .\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
+ .m_axi_araddr(m_axi_araddr),
+ .\m_axi_araddr[11] (\m_axi_araddr[11] ),
+ .\m_axi_araddr[11]_0 (\m_axi_araddr[11]_0 ),
+ .\m_axi_araddr[11]_1 (\m_axi_araddr[11]_1 ),
+ .\m_axi_araddr[11]_2 (\m_axi_araddr[11]_2 ),
+ .\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ),
+ .\m_payload_i_reg[38]_0 (\m_payload_i_reg[38]_0 ),
+ .\m_payload_i_reg[39]_0 (\m_payload_i_reg[39]_0 ),
+ .\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
+ .\m_payload_i_reg[44]_0 (axaddr_offset_0[0]),
+ .\m_payload_i_reg[47]_0 (axaddr_offset_0[3]),
+ .\m_payload_i_reg[47]_1 (\m_payload_i_reg[47]_1 ),
+ .\m_payload_i_reg[47]_2 (\m_payload_i_reg[47]_2 ),
+ .\m_payload_i_reg[6]_0 (\m_payload_i_reg[6]_0 ),
+ .\m_payload_i_reg[7]_0 (\m_payload_i_reg[7] ),
+ .m_valid_i0(m_valid_i0),
+ .m_valid_i_reg_0(si_rs_arvalid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arsize(s_axi_arsize),
+ .s_ready_i0(s_ready_i0),
+ .s_ready_i_reg_0(s_ready_i_reg_0),
+ .s_ready_i_reg_1(\aw.aw_pipe_n_1 ),
+ .sel_first_2(sel_first_2),
+ .\wrap_cnt_r_reg[0] (\wrap_cnt_r_reg[0]_0 ),
+ .\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1] ),
+ .\wrap_second_len_r_reg[1]_0 (\wrap_second_len_r_reg[3] [1]),
+ .\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [3:2],\wrap_second_len_r_reg[3] [0]}),
+ .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_0 ));
+ TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0 \aw.aw_pipe
+ (.D(D),
+ .E(E),
+ .Q(Q),
+ .S(S),
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .\aresetn_d_reg[0]_0 (\aw.aw_pipe_n_1 ),
+ .\aresetn_d_reg[0]_1 (\aw.aw_pipe_n_94 ),
+ .axaddr_incr(axaddr_incr),
+ .\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
+ .\axaddr_offset_r_reg[1] (axaddr_offset[1]),
+ .\axaddr_offset_r_reg[2] (axaddr_offset[2]),
+ .\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
+ .b_push(b_push),
+ .m_axi_awaddr(m_axi_awaddr),
+ .\m_axi_awaddr[11] (\m_axi_awaddr[11] ),
+ .\m_axi_awaddr[11]_0 (\m_axi_awaddr[11]_0 ),
+ .\m_axi_awaddr[11]_1 (\m_axi_awaddr[11]_1 ),
+ .\m_payload_i_reg[38]_0 (\m_payload_i_reg[38] ),
+ .\m_payload_i_reg[39]_0 (\m_payload_i_reg[39] ),
+ .\m_payload_i_reg[44]_0 (axaddr_offset[0]),
+ .\m_payload_i_reg[47]_0 (axaddr_offset[3]),
+ .\m_payload_i_reg[47]_1 (\m_payload_i_reg[47] ),
+ .\m_payload_i_reg[47]_2 (\m_payload_i_reg[47]_0 ),
+ .\m_payload_i_reg[61]_0 (\m_payload_i_reg[61] ),
+ .\m_payload_i_reg[6]_0 (\m_payload_i_reg[6] ),
+ .m_valid_i_reg_0(si_rs_awvalid),
+ .m_valid_i_reg_1(\ar.ar_pipe_n_2 ),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awsize(s_axi_awsize),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_ready_i_reg_0(s_ready_i_reg),
+ .sel_first(sel_first),
+ .sel_first_1(sel_first_1),
+ .\wrap_cnt_r_reg[0] (\wrap_cnt_r_reg[0] ),
+ .wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
+ .\wrap_second_len_r_reg[1] (wrap_second_len[1]));
+ TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1 \b.b_pipe
+ (.aclk(aclk),
+ .\m_payload_i_reg[13]_0 (\m_payload_i_reg[13] ),
+ .m_valid_i_reg_0(m_valid_i_reg),
+ .m_valid_i_reg_1(\ar.ar_pipe_n_2 ),
+ .out(out),
+ .s_axi_bready(s_axi_bready),
+ .s_ready_i_reg_0(si_rs_bready),
+ .s_ready_i_reg_1(\aw.aw_pipe_n_1 ),
+ .si_rs_bvalid(si_rs_bvalid),
+ .\skid_buffer_reg[1]_0 (\skid_buffer_reg[1] ));
+ TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2 \r.r_pipe
+ (.aclk(aclk),
+ .\m_payload_i_reg[46]_0 (\m_payload_i_reg[46] ),
+ .m_valid_i_reg_0(m_valid_i_reg_0),
+ .m_valid_i_reg_1(\ar.ar_pipe_n_2 ),
+ .s_axi_rready(s_axi_rready),
+ .s_ready_i_reg_0(si_rs_rready),
+ .s_ready_i_reg_1(\aw.aw_pipe_n_1 ),
+ .si_rs_rvalid(si_rs_rvalid),
+ .\skid_buffer_reg[33]_0 (\skid_buffer_reg[33] ),
+ .\skid_buffer_reg[46]_0 (\skid_buffer_reg[46] ));
+endmodule
+
+module TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice
+ (s_ready_i_reg_0,
+ m_valid_i_reg_0,
+ \aresetn_d_reg[1]_inv_0 ,
+ \wrap_second_len_r_reg[1] ,
+ \m_payload_i_reg[44]_0 ,
+ \axaddr_offset_r_reg[1] ,
+ \m_payload_i_reg[47]_0 ,
+ \axaddr_offset_r_reg[2] ,
+ \m_payload_i_reg[3]_0 ,
+ \m_payload_i_reg[7]_0 ,
+ O,
+ \m_payload_i_reg[47]_1 ,
+ Q,
+ \wrap_second_len_r_reg[1]_0 ,
+ \wrap_second_len_r_reg[3] ,
+ \m_payload_i_reg[47]_2 ,
+ \m_payload_i_reg[6]_0 ,
+ m_axi_araddr,
+ \m_payload_i_reg[39]_0 ,
+ \m_payload_i_reg[38]_0 ,
+ s_ready_i_reg_1,
+ s_ready_i0,
+ aclk,
+ m_valid_i0,
+ \aresetn_d_reg[1]_inv_1 ,
+ \wrap_cnt_r_reg[0] ,
+ \wrap_second_len_r_reg[3]_0 ,
+ \axaddr_incr_reg[3] ,
+ \axaddr_offset_r_reg[0] ,
+ \axaddr_offset_r_reg[3] ,
+ s_axi_arid,
+ s_axi_arlen,
+ s_axi_arburst,
+ s_axi_arsize,
+ s_axi_arprot,
+ s_axi_araddr,
+ \m_axi_araddr[11] ,
+ \m_axi_araddr[11]_0 ,
+ \m_axi_araddr[11]_1 ,
+ sel_first_2,
+ \m_axi_araddr[11]_2 ,
+ \m_payload_i_reg[0]_0 );
+ output s_ready_i_reg_0;
+ output m_valid_i_reg_0;
+ output \aresetn_d_reg[1]_inv_0 ;
+ output [3:0]\wrap_second_len_r_reg[1] ;
+ output \m_payload_i_reg[44]_0 ;
+ output \axaddr_offset_r_reg[1] ;
+ output \m_payload_i_reg[47]_0 ;
+ output \axaddr_offset_r_reg[2] ;
+ output [3:0]\m_payload_i_reg[3]_0 ;
+ output [3:0]\m_payload_i_reg[7]_0 ;
+ output [3:0]O;
+ output \m_payload_i_reg[47]_1 ;
+ output [54:0]Q;
+ output \wrap_second_len_r_reg[1]_0 ;
+ output [2:0]\wrap_second_len_r_reg[3] ;
+ output \m_payload_i_reg[47]_2 ;
+ output [6:0]\m_payload_i_reg[6]_0 ;
+ output [0:0]m_axi_araddr;
+ output \m_payload_i_reg[39]_0 ;
+ output \m_payload_i_reg[38]_0 ;
+ input s_ready_i_reg_1;
+ input s_ready_i0;
+ input aclk;
+ input m_valid_i0;
+ input \aresetn_d_reg[1]_inv_1 ;
+ input \wrap_cnt_r_reg[0] ;
+ input [3:0]\wrap_second_len_r_reg[3]_0 ;
+ input [3:0]\axaddr_incr_reg[3] ;
+ input [1:0]\axaddr_offset_r_reg[0] ;
+ input [3:0]\axaddr_offset_r_reg[3] ;
+ input [11:0]s_axi_arid;
+ input [3:0]s_axi_arlen;
+ input [1:0]s_axi_arburst;
+ input [1:0]s_axi_arsize;
+ input [2:0]s_axi_arprot;
+ input [31:0]s_axi_araddr;
+ input [0:0]\m_axi_araddr[11] ;
+ input [0:0]\m_axi_araddr[11]_0 ;
+ input \m_axi_araddr[11]_1 ;
+ input sel_first_2;
+ input \m_axi_araddr[11]_2 ;
+ input [0:0]\m_payload_i_reg[0]_0 ;
+
+ wire [3:0]O;
+ wire [54:0]Q;
+ wire aclk;
+ wire \aresetn_d_reg[1]_inv_0 ;
+ wire \aresetn_d_reg[1]_inv_1 ;
+ wire \axaddr_incr[11]_i_5__0_n_0 ;
+ wire \axaddr_incr[11]_i_6__0_n_0 ;
+ wire \axaddr_incr[11]_i_7__0_n_0 ;
+ wire \axaddr_incr[11]_i_8__0_n_0 ;
+ wire \axaddr_incr[3]_i_4__0_n_0 ;
+ wire \axaddr_incr[3]_i_5__0_n_0 ;
+ wire \axaddr_incr[3]_i_6__0_n_0 ;
+ wire \axaddr_incr[3]_i_7__0_n_0 ;
+ wire \axaddr_incr[7]_i_4__0_n_0 ;
+ wire \axaddr_incr[7]_i_5__0_n_0 ;
+ wire \axaddr_incr[7]_i_6__0_n_0 ;
+ wire \axaddr_incr[7]_i_7__0_n_0 ;
+ wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
+ wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
+ wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
+ wire [3:0]\axaddr_incr_reg[3] ;
+ wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
+ wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
+ wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
+ wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
+ wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
+ wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
+ wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
+ wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
+ wire \axaddr_offset_r[0]_i_2__0_n_0 ;
+ wire \axaddr_offset_r[1]_i_2__0_n_0 ;
+ wire \axaddr_offset_r[2]_i_2__0_n_0 ;
+ wire \axaddr_offset_r[2]_i_3__0_n_0 ;
+ wire \axaddr_offset_r[3]_i_2__0_n_0 ;
+ wire [1:0]\axaddr_offset_r_reg[0] ;
+ wire \axaddr_offset_r_reg[1] ;
+ wire \axaddr_offset_r_reg[2] ;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire [0:0]m_axi_araddr;
+ wire [0:0]\m_axi_araddr[11] ;
+ wire [0:0]\m_axi_araddr[11]_0 ;
+ wire \m_axi_araddr[11]_1 ;
+ wire \m_axi_araddr[11]_2 ;
+ wire \m_payload_i[0]_i_1__0_n_0 ;
+ wire \m_payload_i[10]_i_1__0_n_0 ;
+ wire \m_payload_i[11]_i_1__0_n_0 ;
+ wire \m_payload_i[12]_i_1__0_n_0 ;
+ wire \m_payload_i[13]_i_1__1_n_0 ;
+ wire \m_payload_i[14]_i_1__0_n_0 ;
+ wire \m_payload_i[15]_i_1__0_n_0 ;
+ wire \m_payload_i[16]_i_1__0_n_0 ;
+ wire \m_payload_i[17]_i_1__0_n_0 ;
+ wire \m_payload_i[18]_i_1__0_n_0 ;
+ wire \m_payload_i[19]_i_1__0_n_0 ;
+ wire \m_payload_i[1]_i_1__0_n_0 ;
+ wire \m_payload_i[20]_i_1__0_n_0 ;
+ wire \m_payload_i[21]_i_1__0_n_0 ;
+ wire \m_payload_i[22]_i_1__0_n_0 ;
+ wire \m_payload_i[23]_i_1__0_n_0 ;
+ wire \m_payload_i[24]_i_1__0_n_0 ;
+ wire \m_payload_i[25]_i_1__0_n_0 ;
+ wire \m_payload_i[26]_i_1__0_n_0 ;
+ wire \m_payload_i[27]_i_1__0_n_0 ;
+ wire \m_payload_i[28]_i_1__0_n_0 ;
+ wire \m_payload_i[29]_i_1__0_n_0 ;
+ wire \m_payload_i[2]_i_1__0_n_0 ;
+ wire \m_payload_i[30]_i_1__0_n_0 ;
+ wire \m_payload_i[31]_i_2__0_n_0 ;
+ wire \m_payload_i[32]_i_1__0_n_0 ;
+ wire \m_payload_i[33]_i_1__0_n_0 ;
+ wire \m_payload_i[34]_i_1__0_n_0 ;
+ wire \m_payload_i[35]_i_1__0_n_0 ;
+ wire \m_payload_i[36]_i_1__0_n_0 ;
+ wire \m_payload_i[38]_i_1__0_n_0 ;
+ wire \m_payload_i[39]_i_1__0_n_0 ;
+ wire \m_payload_i[3]_i_1__0_n_0 ;
+ wire \m_payload_i[44]_i_1__0_n_0 ;
+ wire \m_payload_i[45]_i_1__0_n_0 ;
+ wire \m_payload_i[46]_i_1__1_n_0 ;
+ wire \m_payload_i[47]_i_1__0_n_0 ;
+ wire \m_payload_i[4]_i_1__0_n_0 ;
+ wire \m_payload_i[50]_i_1__0_n_0 ;
+ wire \m_payload_i[51]_i_1__0_n_0 ;
+ wire \m_payload_i[52]_i_1__0_n_0 ;
+ wire \m_payload_i[53]_i_1__0_n_0 ;
+ wire \m_payload_i[54]_i_1__0_n_0 ;
+ wire \m_payload_i[55]_i_1__0_n_0 ;
+ wire \m_payload_i[56]_i_1__0_n_0 ;
+ wire \m_payload_i[57]_i_1__0_n_0 ;
+ wire \m_payload_i[58]_i_1__0_n_0 ;
+ wire \m_payload_i[59]_i_1__0_n_0 ;
+ wire \m_payload_i[5]_i_1__0_n_0 ;
+ wire \m_payload_i[60]_i_1__0_n_0 ;
+ wire \m_payload_i[61]_i_1__0_n_0 ;
+ wire \m_payload_i[6]_i_1__0_n_0 ;
+ wire \m_payload_i[7]_i_1__0_n_0 ;
+ wire \m_payload_i[8]_i_1__0_n_0 ;
+ wire \m_payload_i[9]_i_1__0_n_0 ;
+ wire [0:0]\m_payload_i_reg[0]_0 ;
+ wire \m_payload_i_reg[38]_0 ;
+ wire \m_payload_i_reg[39]_0 ;
+ wire [3:0]\m_payload_i_reg[3]_0 ;
+ wire \m_payload_i_reg[44]_0 ;
+ wire \m_payload_i_reg[47]_0 ;
+ wire \m_payload_i_reg[47]_1 ;
+ wire \m_payload_i_reg[47]_2 ;
+ wire [6:0]\m_payload_i_reg[6]_0 ;
+ wire [3:0]\m_payload_i_reg[7]_0 ;
+ wire m_valid_i0;
+ wire m_valid_i_reg_0;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [11:0]s_axi_arid;
+ wire [3:0]s_axi_arlen;
+ wire [2:0]s_axi_arprot;
+ wire [1:0]s_axi_arsize;
+ wire s_ready_i0;
+ wire s_ready_i_reg_0;
+ wire s_ready_i_reg_1;
+ wire sel_first_2;
+ wire \skid_buffer_reg_n_0_[0] ;
+ wire \skid_buffer_reg_n_0_[10] ;
+ wire \skid_buffer_reg_n_0_[11] ;
+ wire \skid_buffer_reg_n_0_[12] ;
+ wire \skid_buffer_reg_n_0_[13] ;
+ wire \skid_buffer_reg_n_0_[14] ;
+ wire \skid_buffer_reg_n_0_[15] ;
+ wire \skid_buffer_reg_n_0_[16] ;
+ wire \skid_buffer_reg_n_0_[17] ;
+ wire \skid_buffer_reg_n_0_[18] ;
+ wire \skid_buffer_reg_n_0_[19] ;
+ wire \skid_buffer_reg_n_0_[1] ;
+ wire \skid_buffer_reg_n_0_[20] ;
+ wire \skid_buffer_reg_n_0_[21] ;
+ wire \skid_buffer_reg_n_0_[22] ;
+ wire \skid_buffer_reg_n_0_[23] ;
+ wire \skid_buffer_reg_n_0_[24] ;
+ wire \skid_buffer_reg_n_0_[25] ;
+ wire \skid_buffer_reg_n_0_[26] ;
+ wire \skid_buffer_reg_n_0_[27] ;
+ wire \skid_buffer_reg_n_0_[28] ;
+ wire \skid_buffer_reg_n_0_[29] ;
+ wire \skid_buffer_reg_n_0_[2] ;
+ wire \skid_buffer_reg_n_0_[30] ;
+ wire \skid_buffer_reg_n_0_[31] ;
+ wire \skid_buffer_reg_n_0_[32] ;
+ wire \skid_buffer_reg_n_0_[33] ;
+ wire \skid_buffer_reg_n_0_[34] ;
+ wire \skid_buffer_reg_n_0_[35] ;
+ wire \skid_buffer_reg_n_0_[36] ;
+ wire \skid_buffer_reg_n_0_[38] ;
+ wire \skid_buffer_reg_n_0_[39] ;
+ wire \skid_buffer_reg_n_0_[3] ;
+ wire \skid_buffer_reg_n_0_[44] ;
+ wire \skid_buffer_reg_n_0_[45] ;
+ wire \skid_buffer_reg_n_0_[46] ;
+ wire \skid_buffer_reg_n_0_[47] ;
+ wire \skid_buffer_reg_n_0_[4] ;
+ wire \skid_buffer_reg_n_0_[50] ;
+ wire \skid_buffer_reg_n_0_[51] ;
+ wire \skid_buffer_reg_n_0_[52] ;
+ wire \skid_buffer_reg_n_0_[53] ;
+ wire \skid_buffer_reg_n_0_[54] ;
+ wire \skid_buffer_reg_n_0_[55] ;
+ wire \skid_buffer_reg_n_0_[56] ;
+ wire \skid_buffer_reg_n_0_[57] ;
+ wire \skid_buffer_reg_n_0_[58] ;
+ wire \skid_buffer_reg_n_0_[59] ;
+ wire \skid_buffer_reg_n_0_[5] ;
+ wire \skid_buffer_reg_n_0_[60] ;
+ wire \skid_buffer_reg_n_0_[61] ;
+ wire \skid_buffer_reg_n_0_[6] ;
+ wire \skid_buffer_reg_n_0_[7] ;
+ wire \skid_buffer_reg_n_0_[8] ;
+ wire \skid_buffer_reg_n_0_[9] ;
+ wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
+ wire \wrap_cnt_r[3]_i_2__0_n_0 ;
+ wire \wrap_cnt_r_reg[0] ;
+ wire [3:0]\wrap_second_len_r_reg[1] ;
+ wire \wrap_second_len_r_reg[1]_0 ;
+ wire [2:0]\wrap_second_len_r_reg[3] ;
+ wire [3:0]\wrap_second_len_r_reg[3]_0 ;
+ wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
+
+ FDRE #(
+ .INIT(1'b1))
+ \aresetn_d_reg[1]_inv
+ (.C(aclk),
+ .CE(1'b1),
+ .D(\aresetn_d_reg[1]_inv_1 ),
+ .Q(\aresetn_d_reg[1]_inv_0 ),
+ .R(1'b0));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_5__0
+ (.I0(Q[11]),
+ .O(\axaddr_incr[11]_i_5__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_6__0
+ (.I0(Q[10]),
+ .O(\axaddr_incr[11]_i_6__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_7__0
+ (.I0(Q[9]),
+ .O(\axaddr_incr[11]_i_7__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_8__0
+ (.I0(Q[8]),
+ .O(\axaddr_incr[11]_i_8__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[3]_i_4__0
+ (.I0(Q[3]),
+ .O(\axaddr_incr[3]_i_4__0_n_0 ));
+ LUT3 #(
+ .INIT(8'h70))
+ \axaddr_incr[3]_i_5__0
+ (.I0(Q[36]),
+ .I1(Q[35]),
+ .I2(Q[2]),
+ .O(\axaddr_incr[3]_i_5__0_n_0 ));
+ LUT2 #(
+ .INIT(4'h4))
+ \axaddr_incr[3]_i_6__0
+ (.I0(Q[36]),
+ .I1(Q[1]),
+ .O(\axaddr_incr[3]_i_6__0_n_0 ));
+ LUT3 #(
+ .INIT(8'h02))
+ \axaddr_incr[3]_i_7__0
+ (.I0(Q[0]),
+ .I1(Q[35]),
+ .I2(Q[36]),
+ .O(\axaddr_incr[3]_i_7__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_4__0
+ (.I0(Q[7]),
+ .O(\axaddr_incr[7]_i_4__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_5__0
+ (.I0(Q[6]),
+ .O(\axaddr_incr[7]_i_5__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_6__0
+ (.I0(Q[5]),
+ .O(\axaddr_incr[7]_i_6__0_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_7__0
+ (.I0(Q[4]),
+ .O(\axaddr_incr[7]_i_7__0_n_0 ));
+ CARRY4 \axaddr_incr_reg[11]_i_3__0
+ (.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
+ .CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(O),
+ .S({\axaddr_incr[11]_i_5__0_n_0 ,\axaddr_incr[11]_i_6__0_n_0 ,\axaddr_incr[11]_i_7__0_n_0 ,\axaddr_incr[11]_i_8__0_n_0 }));
+ CARRY4 \axaddr_incr_reg[3]_i_2__0
+ (.CI(1'b0),
+ .CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 ,\axaddr_incr[3]_i_7__0_n_0 }),
+ .O(\m_payload_i_reg[3]_0 ),
+ .S(\axaddr_incr_reg[3] ));
+ CARRY4 \axaddr_incr_reg[7]_i_2__0
+ (.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
+ .CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\m_payload_i_reg[7]_0 ),
+ .S({\axaddr_incr[7]_i_4__0_n_0 ,\axaddr_incr[7]_i_5__0_n_0 ,\axaddr_incr[7]_i_6__0_n_0 ,\axaddr_incr[7]_i_7__0_n_0 }));
+ LUT6 #(
+ .INIT(64'hF8FFFFFF08000000))
+ \axaddr_offset_r[0]_i_1__0
+ (.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
+ .I1(Q[39]),
+ .I2(\axaddr_offset_r_reg[0] [1]),
+ .I3(\axaddr_offset_r_reg[0] [0]),
+ .I4(m_valid_i_reg_0),
+ .I5(\axaddr_offset_r_reg[3] [0]),
+ .O(\m_payload_i_reg[44]_0 ));
+ LUT6 #(
+ .INIT(64'hFC0CFAFAFC0C0A0A))
+ \axaddr_offset_r[0]_i_2__0
+ (.I0(Q[0]),
+ .I1(Q[2]),
+ .I2(Q[35]),
+ .I3(Q[3]),
+ .I4(Q[36]),
+ .I5(Q[1]),
+ .O(\axaddr_offset_r[0]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hF0AA00AAC0AAC0AA))
+ \axaddr_offset_r[1]_i_1__0
+ (.I0(\axaddr_offset_r_reg[3] [1]),
+ .I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
+ .I2(Q[40]),
+ .I3(\wrap_cnt_r_reg[0] ),
+ .I4(\axaddr_offset_r[2]_i_2__0_n_0 ),
+ .I5(Q[35]),
+ .O(\axaddr_offset_r_reg[1] ));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[1]_i_2__0
+ (.I0(Q[3]),
+ .I1(Q[36]),
+ .I2(Q[1]),
+ .O(\axaddr_offset_r[1]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hF0AA00AAC0AAC0AA))
+ \axaddr_offset_r[2]_i_1__0
+ (.I0(\axaddr_offset_r_reg[3] [2]),
+ .I1(\axaddr_offset_r[2]_i_2__0_n_0 ),
+ .I2(Q[41]),
+ .I3(\wrap_cnt_r_reg[0] ),
+ .I4(\axaddr_offset_r[2]_i_3__0_n_0 ),
+ .I5(Q[35]),
+ .O(\axaddr_offset_r_reg[2] ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[2]_i_2__0
+ (.I0(Q[4]),
+ .I1(Q[36]),
+ .I2(Q[2]),
+ .O(\axaddr_offset_r[2]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[2]_i_3__0
+ (.I0(Q[5]),
+ .I1(Q[36]),
+ .I2(Q[3]),
+ .O(\axaddr_offset_r[2]_i_3__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hF8FFFFFF08000000))
+ \axaddr_offset_r[3]_i_1__0
+ (.I0(\axaddr_offset_r[3]_i_2__0_n_0 ),
+ .I1(Q[42]),
+ .I2(\axaddr_offset_r_reg[0] [1]),
+ .I3(\axaddr_offset_r_reg[0] [0]),
+ .I4(m_valid_i_reg_0),
+ .I5(\axaddr_offset_r_reg[3] [3]),
+ .O(\m_payload_i_reg[47]_0 ));
+ LUT6 #(
+ .INIT(64'hFFCCF0AA00CCF0AA))
+ \axaddr_offset_r[3]_i_2__0
+ (.I0(Q[3]),
+ .I1(Q[5]),
+ .I2(Q[4]),
+ .I3(Q[35]),
+ .I4(Q[36]),
+ .I5(Q[6]),
+ .O(\axaddr_offset_r[3]_i_2__0_n_0 ));
+ LUT4 #(
+ .INIT(16'h0080))
+ \axlen_cnt[3]_i_3__2
+ (.I0(Q[42]),
+ .I1(m_valid_i_reg_0),
+ .I2(\axaddr_offset_r_reg[0] [0]),
+ .I3(\axaddr_offset_r_reg[0] [1]),
+ .O(\m_payload_i_reg[47]_2 ));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_araddr[11]_INST_0
+ (.I0(\m_payload_i_reg[39]_0 ),
+ .I1(\m_axi_araddr[11] ),
+ .I2(\m_payload_i_reg[38]_0 ),
+ .I3(\m_axi_araddr[11]_0 ),
+ .I4(Q[11]),
+ .I5(\m_axi_araddr[11]_1 ),
+ .O(m_axi_araddr));
+ (* SOFT_HLUTNM = "soft_lutpair53" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \m_axi_araddr[11]_INST_0_i_1
+ (.I0(Q[38]),
+ .I1(\m_axi_araddr[11]_2 ),
+ .O(\m_payload_i_reg[39]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair53" *)
+ LUT3 #(
+ .INIT(8'h02))
+ \m_axi_araddr[11]_INST_0_i_2
+ (.I0(Q[37]),
+ .I1(sel_first_2),
+ .I2(Q[38]),
+ .O(\m_payload_i_reg[38]_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[0]_i_1__0
+ (.I0(s_axi_araddr[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[0] ),
+ .O(\m_payload_i[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair48" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[10]_i_1__0
+ (.I0(s_axi_araddr[10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[10] ),
+ .O(\m_payload_i[10]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair47" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[11]_i_1__0
+ (.I0(s_axi_araddr[11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[11] ),
+ .O(\m_payload_i[11]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair47" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[12]_i_1__0
+ (.I0(s_axi_araddr[12]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[12] ),
+ .O(\m_payload_i[12]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair46" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[13]_i_1__1
+ (.I0(s_axi_araddr[13]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[13] ),
+ .O(\m_payload_i[13]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair46" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[14]_i_1__0
+ (.I0(s_axi_araddr[14]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[14] ),
+ .O(\m_payload_i[14]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair45" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[15]_i_1__0
+ (.I0(s_axi_araddr[15]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[15] ),
+ .O(\m_payload_i[15]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair45" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[16]_i_1__0
+ (.I0(s_axi_araddr[16]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[16] ),
+ .O(\m_payload_i[16]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair44" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[17]_i_1__0
+ (.I0(s_axi_araddr[17]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[17] ),
+ .O(\m_payload_i[17]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair44" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[18]_i_1__0
+ (.I0(s_axi_araddr[18]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[18] ),
+ .O(\m_payload_i[18]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair43" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[19]_i_1__0
+ (.I0(s_axi_araddr[19]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[19] ),
+ .O(\m_payload_i[19]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair52" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[1]_i_1__0
+ (.I0(s_axi_araddr[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[1] ),
+ .O(\m_payload_i[1]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair43" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[20]_i_1__0
+ (.I0(s_axi_araddr[20]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[20] ),
+ .O(\m_payload_i[20]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair42" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[21]_i_1__0
+ (.I0(s_axi_araddr[21]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[21] ),
+ .O(\m_payload_i[21]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair42" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[22]_i_1__0
+ (.I0(s_axi_araddr[22]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[22] ),
+ .O(\m_payload_i[22]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair41" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[23]_i_1__0
+ (.I0(s_axi_araddr[23]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[23] ),
+ .O(\m_payload_i[23]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair41" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[24]_i_1__0
+ (.I0(s_axi_araddr[24]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[24] ),
+ .O(\m_payload_i[24]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair40" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[25]_i_1__0
+ (.I0(s_axi_araddr[25]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[25] ),
+ .O(\m_payload_i[25]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair40" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[26]_i_1__0
+ (.I0(s_axi_araddr[26]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[26] ),
+ .O(\m_payload_i[26]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair39" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[27]_i_1__0
+ (.I0(s_axi_araddr[27]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[27] ),
+ .O(\m_payload_i[27]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair39" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[28]_i_1__0
+ (.I0(s_axi_araddr[28]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[28] ),
+ .O(\m_payload_i[28]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair38" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[29]_i_1__0
+ (.I0(s_axi_araddr[29]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[29] ),
+ .O(\m_payload_i[29]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair52" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[2]_i_1__0
+ (.I0(s_axi_araddr[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[2] ),
+ .O(\m_payload_i[2]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair38" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[30]_i_1__0
+ (.I0(s_axi_araddr[30]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[30] ),
+ .O(\m_payload_i[30]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair37" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[31]_i_2__0
+ (.I0(s_axi_araddr[31]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[31] ),
+ .O(\m_payload_i[31]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair37" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[32]_i_1__0
+ (.I0(s_axi_arprot[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[32] ),
+ .O(\m_payload_i[32]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair36" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[33]_i_1__0
+ (.I0(s_axi_arprot[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[33] ),
+ .O(\m_payload_i[33]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair36" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[34]_i_1__0
+ (.I0(s_axi_arprot[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[34] ),
+ .O(\m_payload_i[34]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair35" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[35]_i_1__0
+ (.I0(s_axi_arsize[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[35] ),
+ .O(\m_payload_i[35]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair35" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[36]_i_1__0
+ (.I0(s_axi_arsize[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[36] ),
+ .O(\m_payload_i[36]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair34" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[38]_i_1__0
+ (.I0(s_axi_arburst[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[38] ),
+ .O(\m_payload_i[38]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair34" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[39]_i_1__0
+ (.I0(s_axi_arburst[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[39] ),
+ .O(\m_payload_i[39]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair51" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[3]_i_1__0
+ (.I0(s_axi_araddr[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[3] ),
+ .O(\m_payload_i[3]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair33" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[44]_i_1__0
+ (.I0(s_axi_arlen[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[44] ),
+ .O(\m_payload_i[44]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair33" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[45]_i_1__0
+ (.I0(s_axi_arlen[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[45] ),
+ .O(\m_payload_i[45]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[46]_i_1__1
+ (.I0(s_axi_arlen[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[46] ),
+ .O(\m_payload_i[46]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[47]_i_1__0
+ (.I0(s_axi_arlen[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[47] ),
+ .O(\m_payload_i[47]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair51" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[4]_i_1__0
+ (.I0(s_axi_araddr[4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[4] ),
+ .O(\m_payload_i[4]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[50]_i_1__0
+ (.I0(s_axi_arid[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[50] ),
+ .O(\m_payload_i[50]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[51]_i_1__0
+ (.I0(s_axi_arid[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[51] ),
+ .O(\m_payload_i[51]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[52]_i_1__0
+ (.I0(s_axi_arid[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[52] ),
+ .O(\m_payload_i[52]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[53]_i_1__0
+ (.I0(s_axi_arid[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[53] ),
+ .O(\m_payload_i[53]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[54]_i_1__0
+ (.I0(s_axi_arid[4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[54] ),
+ .O(\m_payload_i[54]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[55]_i_1__0
+ (.I0(s_axi_arid[5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[55] ),
+ .O(\m_payload_i[55]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[56]_i_1__0
+ (.I0(s_axi_arid[6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[56] ),
+ .O(\m_payload_i[56]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[57]_i_1__0
+ (.I0(s_axi_arid[7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[57] ),
+ .O(\m_payload_i[57]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[58]_i_1__0
+ (.I0(s_axi_arid[8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[58] ),
+ .O(\m_payload_i[58]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[59]_i_1__0
+ (.I0(s_axi_arid[9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[59] ),
+ .O(\m_payload_i[59]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair50" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[5]_i_1__0
+ (.I0(s_axi_araddr[5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[5] ),
+ .O(\m_payload_i[5]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[60]_i_1__0
+ (.I0(s_axi_arid[10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[60] ),
+ .O(\m_payload_i[60]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[61]_i_1__0
+ (.I0(s_axi_arid[11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[61] ),
+ .O(\m_payload_i[61]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair50" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[6]_i_1__0
+ (.I0(s_axi_araddr[6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[6] ),
+ .O(\m_payload_i[6]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair49" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[7]_i_1__0
+ (.I0(s_axi_araddr[7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[7] ),
+ .O(\m_payload_i[7]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair49" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[8]_i_1__0
+ (.I0(s_axi_araddr[8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[8] ),
+ .O(\m_payload_i[8]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair48" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[9]_i_1__0
+ (.I0(s_axi_araddr[9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[9] ),
+ .O(\m_payload_i[9]_i_1__0_n_0 ));
+ FDRE \m_payload_i_reg[0]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[0]_i_1__0_n_0 ),
+ .Q(Q[0]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[10]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[10]_i_1__0_n_0 ),
+ .Q(Q[10]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[11]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[11]_i_1__0_n_0 ),
+ .Q(Q[11]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[12]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[12]_i_1__0_n_0 ),
+ .Q(Q[12]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[13]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[13]_i_1__1_n_0 ),
+ .Q(Q[13]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[14]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[14]_i_1__0_n_0 ),
+ .Q(Q[14]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[15]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[15]_i_1__0_n_0 ),
+ .Q(Q[15]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[16]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[16]_i_1__0_n_0 ),
+ .Q(Q[16]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[17]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[17]_i_1__0_n_0 ),
+ .Q(Q[17]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[18]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[18]_i_1__0_n_0 ),
+ .Q(Q[18]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[19]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[19]_i_1__0_n_0 ),
+ .Q(Q[19]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[1]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[1]_i_1__0_n_0 ),
+ .Q(Q[1]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[20]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[20]_i_1__0_n_0 ),
+ .Q(Q[20]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[21]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[21]_i_1__0_n_0 ),
+ .Q(Q[21]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[22]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[22]_i_1__0_n_0 ),
+ .Q(Q[22]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[23]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[23]_i_1__0_n_0 ),
+ .Q(Q[23]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[24]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[24]_i_1__0_n_0 ),
+ .Q(Q[24]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[25]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[25]_i_1__0_n_0 ),
+ .Q(Q[25]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[26]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[26]_i_1__0_n_0 ),
+ .Q(Q[26]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[27]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[27]_i_1__0_n_0 ),
+ .Q(Q[27]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[28]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[28]_i_1__0_n_0 ),
+ .Q(Q[28]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[29]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[29]_i_1__0_n_0 ),
+ .Q(Q[29]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[2]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[2]_i_1__0_n_0 ),
+ .Q(Q[2]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[30]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[30]_i_1__0_n_0 ),
+ .Q(Q[30]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[31]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[31]_i_2__0_n_0 ),
+ .Q(Q[31]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[32]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[32]_i_1__0_n_0 ),
+ .Q(Q[32]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[33]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[33]_i_1__0_n_0 ),
+ .Q(Q[33]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[34]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[34]_i_1__0_n_0 ),
+ .Q(Q[34]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[35]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[35]_i_1__0_n_0 ),
+ .Q(Q[35]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[36]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[36]_i_1__0_n_0 ),
+ .Q(Q[36]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[38]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[38]_i_1__0_n_0 ),
+ .Q(Q[37]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[39]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[39]_i_1__0_n_0 ),
+ .Q(Q[38]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[3]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[3]_i_1__0_n_0 ),
+ .Q(Q[3]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[44]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[44]_i_1__0_n_0 ),
+ .Q(Q[39]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[45]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[45]_i_1__0_n_0 ),
+ .Q(Q[40]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[46]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[46]_i_1__1_n_0 ),
+ .Q(Q[41]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[47]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[47]_i_1__0_n_0 ),
+ .Q(Q[42]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[4]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[4]_i_1__0_n_0 ),
+ .Q(Q[4]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[50]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[50]_i_1__0_n_0 ),
+ .Q(Q[43]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[51]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[51]_i_1__0_n_0 ),
+ .Q(Q[44]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[52]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[52]_i_1__0_n_0 ),
+ .Q(Q[45]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[53]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[53]_i_1__0_n_0 ),
+ .Q(Q[46]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[54]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[54]_i_1__0_n_0 ),
+ .Q(Q[47]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[55]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[55]_i_1__0_n_0 ),
+ .Q(Q[48]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[56]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[56]_i_1__0_n_0 ),
+ .Q(Q[49]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[57]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[57]_i_1__0_n_0 ),
+ .Q(Q[50]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[58]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[58]_i_1__0_n_0 ),
+ .Q(Q[51]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[59]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[59]_i_1__0_n_0 ),
+ .Q(Q[52]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[5]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[5]_i_1__0_n_0 ),
+ .Q(Q[5]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[60]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[60]_i_1__0_n_0 ),
+ .Q(Q[53]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[61]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[61]_i_1__0_n_0 ),
+ .Q(Q[54]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[6]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[6]_i_1__0_n_0 ),
+ .Q(Q[6]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[7]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[7]_i_1__0_n_0 ),
+ .Q(Q[7]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[8]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[8]_i_1__0_n_0 ),
+ .Q(Q[8]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[9]
+ (.C(aclk),
+ .CE(\m_payload_i_reg[0]_0 ),
+ .D(\m_payload_i[9]_i_1__0_n_0 ),
+ .Q(Q[9]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ m_valid_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_valid_i0),
+ .Q(m_valid_i_reg_0),
+ .R(\aresetn_d_reg[1]_inv_0 ));
+ LUT5 #(
+ .INIT(32'hFFFE0000))
+ next_pending_r_i_2__0
+ (.I0(Q[42]),
+ .I1(Q[39]),
+ .I2(Q[40]),
+ .I3(Q[41]),
+ .I4(\wrap_cnt_r_reg[0] ),
+ .O(\m_payload_i_reg[47]_1 ));
+ FDRE #(
+ .INIT(1'b0))
+ s_ready_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(s_ready_i0),
+ .Q(s_ready_i_reg_0),
+ .R(s_ready_i_reg_1));
+ FDRE \skid_buffer_reg[0]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[0]),
+ .Q(\skid_buffer_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[10]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[10]),
+ .Q(\skid_buffer_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[11]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[11]),
+ .Q(\skid_buffer_reg_n_0_[11] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[12]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[12]),
+ .Q(\skid_buffer_reg_n_0_[12] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[13]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[13]),
+ .Q(\skid_buffer_reg_n_0_[13] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[14]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[14]),
+ .Q(\skid_buffer_reg_n_0_[14] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[15]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[15]),
+ .Q(\skid_buffer_reg_n_0_[15] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[16]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[16]),
+ .Q(\skid_buffer_reg_n_0_[16] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[17]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[17]),
+ .Q(\skid_buffer_reg_n_0_[17] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[18]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[18]),
+ .Q(\skid_buffer_reg_n_0_[18] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[19]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[19]),
+ .Q(\skid_buffer_reg_n_0_[19] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[1]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[1]),
+ .Q(\skid_buffer_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[20]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[20]),
+ .Q(\skid_buffer_reg_n_0_[20] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[21]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[21]),
+ .Q(\skid_buffer_reg_n_0_[21] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[22]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[22]),
+ .Q(\skid_buffer_reg_n_0_[22] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[23]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[23]),
+ .Q(\skid_buffer_reg_n_0_[23] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[24]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[24]),
+ .Q(\skid_buffer_reg_n_0_[24] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[25]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[25]),
+ .Q(\skid_buffer_reg_n_0_[25] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[26]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[26]),
+ .Q(\skid_buffer_reg_n_0_[26] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[27]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[27]),
+ .Q(\skid_buffer_reg_n_0_[27] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[28]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[28]),
+ .Q(\skid_buffer_reg_n_0_[28] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[29]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[29]),
+ .Q(\skid_buffer_reg_n_0_[29] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[2]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[2]),
+ .Q(\skid_buffer_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[30]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[30]),
+ .Q(\skid_buffer_reg_n_0_[30] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[31]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[31]),
+ .Q(\skid_buffer_reg_n_0_[31] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[32]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arprot[0]),
+ .Q(\skid_buffer_reg_n_0_[32] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[33]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arprot[1]),
+ .Q(\skid_buffer_reg_n_0_[33] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[34]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arprot[2]),
+ .Q(\skid_buffer_reg_n_0_[34] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[35]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arsize[0]),
+ .Q(\skid_buffer_reg_n_0_[35] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[36]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arsize[1]),
+ .Q(\skid_buffer_reg_n_0_[36] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[38]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arburst[0]),
+ .Q(\skid_buffer_reg_n_0_[38] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[39]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arburst[1]),
+ .Q(\skid_buffer_reg_n_0_[39] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[3]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[3]),
+ .Q(\skid_buffer_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[44]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arlen[0]),
+ .Q(\skid_buffer_reg_n_0_[44] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[45]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arlen[1]),
+ .Q(\skid_buffer_reg_n_0_[45] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[46]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arlen[2]),
+ .Q(\skid_buffer_reg_n_0_[46] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[47]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arlen[3]),
+ .Q(\skid_buffer_reg_n_0_[47] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[4]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[4]),
+ .Q(\skid_buffer_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[50]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[0]),
+ .Q(\skid_buffer_reg_n_0_[50] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[51]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[1]),
+ .Q(\skid_buffer_reg_n_0_[51] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[52]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[2]),
+ .Q(\skid_buffer_reg_n_0_[52] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[53]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[3]),
+ .Q(\skid_buffer_reg_n_0_[53] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[54]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[4]),
+ .Q(\skid_buffer_reg_n_0_[54] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[55]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[5]),
+ .Q(\skid_buffer_reg_n_0_[55] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[56]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[6]),
+ .Q(\skid_buffer_reg_n_0_[56] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[57]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[7]),
+ .Q(\skid_buffer_reg_n_0_[57] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[58]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[8]),
+ .Q(\skid_buffer_reg_n_0_[58] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[59]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[9]),
+ .Q(\skid_buffer_reg_n_0_[59] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[5]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[5]),
+ .Q(\skid_buffer_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[60]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[10]),
+ .Q(\skid_buffer_reg_n_0_[60] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[61]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_arid[11]),
+ .Q(\skid_buffer_reg_n_0_[61] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[6]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[6]),
+ .Q(\skid_buffer_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[7]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[7]),
+ .Q(\skid_buffer_reg_n_0_[7] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[8]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[8]),
+ .Q(\skid_buffer_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[9]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_araddr[9]),
+ .Q(\skid_buffer_reg_n_0_[9] ),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hAA8A))
+ \wrap_boundary_axaddr_r[0]_i_1__0
+ (.I0(Q[0]),
+ .I1(Q[35]),
+ .I2(Q[39]),
+ .I3(Q[36]),
+ .O(\m_payload_i_reg[6]_0 [0]));
+ LUT5 #(
+ .INIT(32'hFF470000))
+ \wrap_boundary_axaddr_r[1]_i_1__0
+ (.I0(Q[39]),
+ .I1(Q[35]),
+ .I2(Q[40]),
+ .I3(Q[36]),
+ .I4(Q[1]),
+ .O(\m_payload_i_reg[6]_0 [1]));
+ LUT6 #(
+ .INIT(64'hA0A002A2AAAA02A2))
+ \wrap_boundary_axaddr_r[2]_i_1__0
+ (.I0(Q[2]),
+ .I1(Q[41]),
+ .I2(Q[35]),
+ .I3(Q[40]),
+ .I4(Q[36]),
+ .I5(Q[39]),
+ .O(\m_payload_i_reg[6]_0 [2]));
+ LUT6 #(
+ .INIT(64'h4747000000FF0000))
+ \wrap_boundary_axaddr_r[3]_i_1__0
+ (.I0(Q[39]),
+ .I1(Q[35]),
+ .I2(Q[40]),
+ .I3(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
+ .I4(Q[3]),
+ .I5(Q[36]),
+ .O(\m_payload_i_reg[6]_0 [3]));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \wrap_boundary_axaddr_r[3]_i_2__0
+ (.I0(Q[41]),
+ .I1(Q[35]),
+ .I2(Q[42]),
+ .O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h002A0A2AA02AAA2A))
+ \wrap_boundary_axaddr_r[4]_i_1__0
+ (.I0(Q[4]),
+ .I1(Q[42]),
+ .I2(Q[35]),
+ .I3(Q[36]),
+ .I4(Q[41]),
+ .I5(Q[40]),
+ .O(\m_payload_i_reg[6]_0 [4]));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT5 #(
+ .INIT(32'h47FF0000))
+ \wrap_boundary_axaddr_r[5]_i_1__0
+ (.I0(Q[41]),
+ .I1(Q[35]),
+ .I2(Q[42]),
+ .I3(Q[36]),
+ .I4(Q[5]),
+ .O(\m_payload_i_reg[6]_0 [5]));
+ LUT4 #(
+ .INIT(16'h2AAA))
+ \wrap_boundary_axaddr_r[6]_i_1__0
+ (.I0(Q[6]),
+ .I1(Q[35]),
+ .I2(Q[36]),
+ .I3(Q[42]),
+ .O(\m_payload_i_reg[6]_0 [6]));
+ LUT6 #(
+ .INIT(64'hA0AFA0AFA0AFA1AE))
+ \wrap_cnt_r[0]_i_1__0
+ (.I0(\m_payload_i_reg[44]_0 ),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\wrap_cnt_r_reg[0] ),
+ .I3(\wrap_second_len_r_reg[3]_0 [0]),
+ .I4(\m_payload_i_reg[47]_0 ),
+ .I5(\axaddr_offset_r_reg[2] ),
+ .O(\wrap_second_len_r_reg[1] [0]));
+ LUT2 #(
+ .INIT(4'h6))
+ \wrap_cnt_r[1]_i_1__0
+ (.I0(\wrap_cnt_r[3]_i_2__0_n_0 ),
+ .I1(\wrap_second_len_r_reg[1]_0 ),
+ .O(\wrap_second_len_r_reg[1] [1]));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \wrap_cnt_r[2]_i_1__0
+ (.I0(\wrap_cnt_r[3]_i_2__0_n_0 ),
+ .I1(\wrap_second_len_r_reg[1]_0 ),
+ .I2(\wrap_second_len_r_reg[3] [1]),
+ .O(\wrap_second_len_r_reg[1] [2]));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT4 #(
+ .INIT(16'h7F80))
+ \wrap_cnt_r[3]_i_1__0
+ (.I0(\wrap_second_len_r_reg[1]_0 ),
+ .I1(\wrap_cnt_r[3]_i_2__0_n_0 ),
+ .I2(\wrap_second_len_r_reg[3] [1]),
+ .I3(\wrap_second_len_r_reg[3] [2]),
+ .O(\wrap_second_len_r_reg[1] [3]));
+ LUT6 #(
+ .INIT(64'h5555FFFC0000AAA8))
+ \wrap_cnt_r[3]_i_2__0
+ (.I0(\wrap_cnt_r_reg[0] ),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\m_payload_i_reg[47]_0 ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(\wrap_second_len_r_reg[3]_0 [0]),
+ .O(\wrap_cnt_r[3]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h33333330AAAAAAAA))
+ \wrap_second_len_r[0]_i_1__0
+ (.I0(\wrap_second_len_r_reg[3]_0 [0]),
+ .I1(\m_payload_i_reg[44]_0 ),
+ .I2(\m_payload_i_reg[47]_0 ),
+ .I3(\axaddr_offset_r_reg[2] ),
+ .I4(\axaddr_offset_r_reg[1] ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(\wrap_second_len_r_reg[3] [0]));
+ LUT6 #(
+ .INIT(64'hFF0000FCAAAAAAAA))
+ \wrap_second_len_r[1]_i_1__0
+ (.I0(\wrap_second_len_r_reg[3]_0 [1]),
+ .I1(\m_payload_i_reg[47]_0 ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\axaddr_offset_r_reg[1] ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(\wrap_second_len_r_reg[1]_0 ));
+ LUT6 #(
+ .INIT(64'hF0F0F00CAAAAAAAA))
+ \wrap_second_len_r[2]_i_1__0
+ (.I0(\wrap_second_len_r_reg[3]_0 [2]),
+ .I1(\m_payload_i_reg[47]_0 ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\axaddr_offset_r_reg[1] ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(\wrap_second_len_r_reg[3] [1]));
+ LUT6 #(
+ .INIT(64'hFFFCAAAA0000AAAA))
+ \wrap_second_len_r[3]_i_1__0
+ (.I0(\wrap_second_len_r_reg[3]_0 [3]),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\m_payload_i_reg[44]_0 ),
+ .I3(\axaddr_offset_r_reg[2] ),
+ .I4(\wrap_cnt_r_reg[0] ),
+ .I5(\m_payload_i_reg[47]_0 ),
+ .O(\wrap_second_len_r_reg[3] [2]));
+endmodule
+
+(* ORIG_REF_NAME = "axi_register_slice_v2_1_19_axic_register_slice" *)
+module TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0
+ (s_ready_i_reg_0,
+ \aresetn_d_reg[0]_0 ,
+ m_valid_i_reg_0,
+ D,
+ \m_payload_i_reg[44]_0 ,
+ \axaddr_offset_r_reg[1] ,
+ \m_payload_i_reg[47]_0 ,
+ \axaddr_offset_r_reg[2] ,
+ axaddr_incr,
+ \m_payload_i_reg[47]_1 ,
+ \m_payload_i_reg[61]_0 ,
+ \wrap_second_len_r_reg[1] ,
+ wrap_second_len,
+ \m_payload_i_reg[47]_2 ,
+ \m_payload_i_reg[6]_0 ,
+ m_axi_awaddr,
+ \m_payload_i_reg[39]_0 ,
+ \m_payload_i_reg[38]_0 ,
+ \aresetn_d_reg[0]_1 ,
+ aclk,
+ m_valid_i_reg_1,
+ aresetn,
+ \wrap_cnt_r_reg[0] ,
+ Q,
+ b_push,
+ s_axi_awvalid,
+ S,
+ \axaddr_offset_r_reg[0] ,
+ \axaddr_offset_r_reg[3] ,
+ s_axi_awid,
+ s_axi_awlen,
+ s_axi_awburst,
+ s_axi_awsize,
+ s_axi_awprot,
+ s_axi_awaddr,
+ \m_axi_awaddr[11] ,
+ \m_axi_awaddr[11]_0 ,
+ \m_axi_awaddr[11]_1 ,
+ sel_first_1,
+ sel_first,
+ E);
+ output s_ready_i_reg_0;
+ output \aresetn_d_reg[0]_0 ;
+ output m_valid_i_reg_0;
+ output [3:0]D;
+ output \m_payload_i_reg[44]_0 ;
+ output \axaddr_offset_r_reg[1] ;
+ output \m_payload_i_reg[47]_0 ;
+ output \axaddr_offset_r_reg[2] ;
+ output [11:0]axaddr_incr;
+ output \m_payload_i_reg[47]_1 ;
+ output [54:0]\m_payload_i_reg[61]_0 ;
+ output \wrap_second_len_r_reg[1] ;
+ output [2:0]wrap_second_len;
+ output \m_payload_i_reg[47]_2 ;
+ output [6:0]\m_payload_i_reg[6]_0 ;
+ output [0:0]m_axi_awaddr;
+ output \m_payload_i_reg[39]_0 ;
+ output \m_payload_i_reg[38]_0 ;
+ output \aresetn_d_reg[0]_1 ;
+ input aclk;
+ input m_valid_i_reg_1;
+ input aresetn;
+ input \wrap_cnt_r_reg[0] ;
+ input [3:0]Q;
+ input b_push;
+ input s_axi_awvalid;
+ input [3:0]S;
+ input [1:0]\axaddr_offset_r_reg[0] ;
+ input [3:0]\axaddr_offset_r_reg[3] ;
+ input [11:0]s_axi_awid;
+ input [3:0]s_axi_awlen;
+ input [1:0]s_axi_awburst;
+ input [1:0]s_axi_awsize;
+ input [2:0]s_axi_awprot;
+ input [31:0]s_axi_awaddr;
+ input [0:0]\m_axi_awaddr[11] ;
+ input [0:0]\m_axi_awaddr[11]_0 ;
+ input \m_axi_awaddr[11]_1 ;
+ input sel_first_1;
+ input sel_first;
+ input [0:0]E;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [3:0]Q;
+ wire [3:0]S;
+ wire aclk;
+ wire aresetn;
+ wire \aresetn_d_reg[0]_0 ;
+ wire \aresetn_d_reg[0]_1 ;
+ wire \aresetn_d_reg_n_0_[0] ;
+ wire [11:0]axaddr_incr;
+ wire \axaddr_incr[11]_i_5_n_0 ;
+ wire \axaddr_incr[11]_i_6_n_0 ;
+ wire \axaddr_incr[11]_i_7_n_0 ;
+ wire \axaddr_incr[11]_i_8_n_0 ;
+ wire \axaddr_incr[3]_i_4_n_0 ;
+ wire \axaddr_incr[3]_i_5_n_0 ;
+ wire \axaddr_incr[3]_i_6_n_0 ;
+ wire \axaddr_incr[3]_i_7_n_0 ;
+ wire \axaddr_incr[7]_i_4_n_0 ;
+ wire \axaddr_incr[7]_i_5_n_0 ;
+ wire \axaddr_incr[7]_i_6_n_0 ;
+ wire \axaddr_incr[7]_i_7_n_0 ;
+ wire \axaddr_incr_reg[11]_i_3_n_1 ;
+ wire \axaddr_incr_reg[11]_i_3_n_2 ;
+ wire \axaddr_incr_reg[11]_i_3_n_3 ;
+ wire \axaddr_incr_reg[3]_i_2_n_0 ;
+ wire \axaddr_incr_reg[3]_i_2_n_1 ;
+ wire \axaddr_incr_reg[3]_i_2_n_2 ;
+ wire \axaddr_incr_reg[3]_i_2_n_3 ;
+ wire \axaddr_incr_reg[7]_i_2_n_0 ;
+ wire \axaddr_incr_reg[7]_i_2_n_1 ;
+ wire \axaddr_incr_reg[7]_i_2_n_2 ;
+ wire \axaddr_incr_reg[7]_i_2_n_3 ;
+ wire \axaddr_offset_r[0]_i_2_n_0 ;
+ wire \axaddr_offset_r[1]_i_2_n_0 ;
+ wire \axaddr_offset_r[2]_i_2_n_0 ;
+ wire \axaddr_offset_r[2]_i_3_n_0 ;
+ wire \axaddr_offset_r[3]_i_2_n_0 ;
+ wire [1:0]\axaddr_offset_r_reg[0] ;
+ wire \axaddr_offset_r_reg[1] ;
+ wire \axaddr_offset_r_reg[2] ;
+ wire [3:0]\axaddr_offset_r_reg[3] ;
+ wire b_push;
+ wire [0:0]m_axi_awaddr;
+ wire [0:0]\m_axi_awaddr[11] ;
+ wire [0:0]\m_axi_awaddr[11]_0 ;
+ wire \m_axi_awaddr[11]_1 ;
+ wire \m_payload_i_reg[38]_0 ;
+ wire \m_payload_i_reg[39]_0 ;
+ wire \m_payload_i_reg[44]_0 ;
+ wire \m_payload_i_reg[47]_0 ;
+ wire \m_payload_i_reg[47]_1 ;
+ wire \m_payload_i_reg[47]_2 ;
+ wire [54:0]\m_payload_i_reg[61]_0 ;
+ wire [6:0]\m_payload_i_reg[6]_0 ;
+ wire m_valid_i0;
+ wire m_valid_i_reg_0;
+ wire m_valid_i_reg_1;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [11:0]s_axi_awid;
+ wire [3:0]s_axi_awlen;
+ wire [2:0]s_axi_awprot;
+ wire [1:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire s_ready_i0;
+ wire s_ready_i_reg_0;
+ wire sel_first;
+ wire sel_first_1;
+ wire [61:0]skid_buffer;
+ wire \skid_buffer_reg_n_0_[0] ;
+ wire \skid_buffer_reg_n_0_[10] ;
+ wire \skid_buffer_reg_n_0_[11] ;
+ wire \skid_buffer_reg_n_0_[12] ;
+ wire \skid_buffer_reg_n_0_[13] ;
+ wire \skid_buffer_reg_n_0_[14] ;
+ wire \skid_buffer_reg_n_0_[15] ;
+ wire \skid_buffer_reg_n_0_[16] ;
+ wire \skid_buffer_reg_n_0_[17] ;
+ wire \skid_buffer_reg_n_0_[18] ;
+ wire \skid_buffer_reg_n_0_[19] ;
+ wire \skid_buffer_reg_n_0_[1] ;
+ wire \skid_buffer_reg_n_0_[20] ;
+ wire \skid_buffer_reg_n_0_[21] ;
+ wire \skid_buffer_reg_n_0_[22] ;
+ wire \skid_buffer_reg_n_0_[23] ;
+ wire \skid_buffer_reg_n_0_[24] ;
+ wire \skid_buffer_reg_n_0_[25] ;
+ wire \skid_buffer_reg_n_0_[26] ;
+ wire \skid_buffer_reg_n_0_[27] ;
+ wire \skid_buffer_reg_n_0_[28] ;
+ wire \skid_buffer_reg_n_0_[29] ;
+ wire \skid_buffer_reg_n_0_[2] ;
+ wire \skid_buffer_reg_n_0_[30] ;
+ wire \skid_buffer_reg_n_0_[31] ;
+ wire \skid_buffer_reg_n_0_[32] ;
+ wire \skid_buffer_reg_n_0_[33] ;
+ wire \skid_buffer_reg_n_0_[34] ;
+ wire \skid_buffer_reg_n_0_[35] ;
+ wire \skid_buffer_reg_n_0_[36] ;
+ wire \skid_buffer_reg_n_0_[38] ;
+ wire \skid_buffer_reg_n_0_[39] ;
+ wire \skid_buffer_reg_n_0_[3] ;
+ wire \skid_buffer_reg_n_0_[44] ;
+ wire \skid_buffer_reg_n_0_[45] ;
+ wire \skid_buffer_reg_n_0_[46] ;
+ wire \skid_buffer_reg_n_0_[47] ;
+ wire \skid_buffer_reg_n_0_[4] ;
+ wire \skid_buffer_reg_n_0_[50] ;
+ wire \skid_buffer_reg_n_0_[51] ;
+ wire \skid_buffer_reg_n_0_[52] ;
+ wire \skid_buffer_reg_n_0_[53] ;
+ wire \skid_buffer_reg_n_0_[54] ;
+ wire \skid_buffer_reg_n_0_[55] ;
+ wire \skid_buffer_reg_n_0_[56] ;
+ wire \skid_buffer_reg_n_0_[57] ;
+ wire \skid_buffer_reg_n_0_[58] ;
+ wire \skid_buffer_reg_n_0_[59] ;
+ wire \skid_buffer_reg_n_0_[5] ;
+ wire \skid_buffer_reg_n_0_[60] ;
+ wire \skid_buffer_reg_n_0_[61] ;
+ wire \skid_buffer_reg_n_0_[6] ;
+ wire \skid_buffer_reg_n_0_[7] ;
+ wire \skid_buffer_reg_n_0_[8] ;
+ wire \skid_buffer_reg_n_0_[9] ;
+ wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
+ wire \wrap_cnt_r[3]_i_2_n_0 ;
+ wire \wrap_cnt_r_reg[0] ;
+ wire [2:0]wrap_second_len;
+ wire \wrap_second_len_r_reg[1] ;
+ wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
+
+ LUT2 #(
+ .INIT(4'h7))
+ \aresetn_d[1]_inv_i_1
+ (.I0(\aresetn_d_reg_n_0_[0] ),
+ .I1(aresetn),
+ .O(\aresetn_d_reg[0]_1 ));
+ FDRE #(
+ .INIT(1'b0))
+ \aresetn_d_reg[0]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(aresetn),
+ .Q(\aresetn_d_reg_n_0_[0] ),
+ .R(1'b0));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_5
+ (.I0(\m_payload_i_reg[61]_0 [11]),
+ .O(\axaddr_incr[11]_i_5_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_6
+ (.I0(\m_payload_i_reg[61]_0 [10]),
+ .O(\axaddr_incr[11]_i_6_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_7
+ (.I0(\m_payload_i_reg[61]_0 [9]),
+ .O(\axaddr_incr[11]_i_7_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[11]_i_8
+ (.I0(\m_payload_i_reg[61]_0 [8]),
+ .O(\axaddr_incr[11]_i_8_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[3]_i_4
+ (.I0(\m_payload_i_reg[61]_0 [3]),
+ .O(\axaddr_incr[3]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'h70))
+ \axaddr_incr[3]_i_5
+ (.I0(\m_payload_i_reg[61]_0 [36]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [2]),
+ .O(\axaddr_incr[3]_i_5_n_0 ));
+ LUT2 #(
+ .INIT(4'h4))
+ \axaddr_incr[3]_i_6
+ (.I0(\m_payload_i_reg[61]_0 [36]),
+ .I1(\m_payload_i_reg[61]_0 [1]),
+ .O(\axaddr_incr[3]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'h02))
+ \axaddr_incr[3]_i_7
+ (.I0(\m_payload_i_reg[61]_0 [0]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [36]),
+ .O(\axaddr_incr[3]_i_7_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_4
+ (.I0(\m_payload_i_reg[61]_0 [7]),
+ .O(\axaddr_incr[7]_i_4_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_5
+ (.I0(\m_payload_i_reg[61]_0 [6]),
+ .O(\axaddr_incr[7]_i_5_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_6
+ (.I0(\m_payload_i_reg[61]_0 [5]),
+ .O(\axaddr_incr[7]_i_6_n_0 ));
+ LUT1 #(
+ .INIT(2'h2))
+ \axaddr_incr[7]_i_7
+ (.I0(\m_payload_i_reg[61]_0 [4]),
+ .O(\axaddr_incr[7]_i_7_n_0 ));
+ CARRY4 \axaddr_incr_reg[11]_i_3
+ (.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
+ .CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(axaddr_incr[11:8]),
+ .S({\axaddr_incr[11]_i_5_n_0 ,\axaddr_incr[11]_i_6_n_0 ,\axaddr_incr[11]_i_7_n_0 ,\axaddr_incr[11]_i_8_n_0 }));
+ CARRY4 \axaddr_incr_reg[3]_i_2
+ (.CI(1'b0),
+ .CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 ,\axaddr_incr[3]_i_7_n_0 }),
+ .O(axaddr_incr[3:0]),
+ .S(S));
+ CARRY4 \axaddr_incr_reg[7]_i_2
+ (.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
+ .CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(axaddr_incr[7:4]),
+ .S({\axaddr_incr[7]_i_4_n_0 ,\axaddr_incr[7]_i_5_n_0 ,\axaddr_incr[7]_i_6_n_0 ,\axaddr_incr[7]_i_7_n_0 }));
+ LUT6 #(
+ .INIT(64'hFFF8FFFF00080000))
+ \axaddr_offset_r[0]_i_1
+ (.I0(\axaddr_offset_r[0]_i_2_n_0 ),
+ .I1(\m_payload_i_reg[61]_0 [39]),
+ .I2(\axaddr_offset_r_reg[0] [1]),
+ .I3(\axaddr_offset_r_reg[0] [0]),
+ .I4(m_valid_i_reg_0),
+ .I5(\axaddr_offset_r_reg[3] [0]),
+ .O(\m_payload_i_reg[44]_0 ));
+ LUT6 #(
+ .INIT(64'hFC0CFAFAFC0C0A0A))
+ \axaddr_offset_r[0]_i_2
+ (.I0(\m_payload_i_reg[61]_0 [0]),
+ .I1(\m_payload_i_reg[61]_0 [2]),
+ .I2(\m_payload_i_reg[61]_0 [35]),
+ .I3(\m_payload_i_reg[61]_0 [3]),
+ .I4(\m_payload_i_reg[61]_0 [36]),
+ .I5(\m_payload_i_reg[61]_0 [1]),
+ .O(\axaddr_offset_r[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hF0AA00AAC0AAC0AA))
+ \axaddr_offset_r[1]_i_1
+ (.I0(\axaddr_offset_r_reg[3] [1]),
+ .I1(\axaddr_offset_r[1]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[61]_0 [40]),
+ .I3(\wrap_cnt_r_reg[0] ),
+ .I4(\axaddr_offset_r[2]_i_2_n_0 ),
+ .I5(\m_payload_i_reg[61]_0 [35]),
+ .O(\axaddr_offset_r_reg[1] ));
+ (* SOFT_HLUTNM = "soft_lutpair56" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[1]_i_2
+ (.I0(\m_payload_i_reg[61]_0 [3]),
+ .I1(\m_payload_i_reg[61]_0 [36]),
+ .I2(\m_payload_i_reg[61]_0 [1]),
+ .O(\axaddr_offset_r[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hF0AA00AAC0AAC0AA))
+ \axaddr_offset_r[2]_i_1
+ (.I0(\axaddr_offset_r_reg[3] [2]),
+ .I1(\axaddr_offset_r[2]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[61]_0 [41]),
+ .I3(\wrap_cnt_r_reg[0] ),
+ .I4(\axaddr_offset_r[2]_i_3_n_0 ),
+ .I5(\m_payload_i_reg[61]_0 [35]),
+ .O(\axaddr_offset_r_reg[2] ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[2]_i_2
+ (.I0(\m_payload_i_reg[61]_0 [4]),
+ .I1(\m_payload_i_reg[61]_0 [36]),
+ .I2(\m_payload_i_reg[61]_0 [2]),
+ .O(\axaddr_offset_r[2]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair56" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \axaddr_offset_r[2]_i_3
+ (.I0(\m_payload_i_reg[61]_0 [5]),
+ .I1(\m_payload_i_reg[61]_0 [36]),
+ .I2(\m_payload_i_reg[61]_0 [3]),
+ .O(\axaddr_offset_r[2]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFF8FFFF00080000))
+ \axaddr_offset_r[3]_i_1
+ (.I0(\axaddr_offset_r[3]_i_2_n_0 ),
+ .I1(\m_payload_i_reg[61]_0 [42]),
+ .I2(\axaddr_offset_r_reg[0] [1]),
+ .I3(\axaddr_offset_r_reg[0] [0]),
+ .I4(m_valid_i_reg_0),
+ .I5(\axaddr_offset_r_reg[3] [3]),
+ .O(\m_payload_i_reg[47]_0 ));
+ LUT6 #(
+ .INIT(64'hFFCCF0AA00CCF0AA))
+ \axaddr_offset_r[3]_i_2
+ (.I0(\m_payload_i_reg[61]_0 [3]),
+ .I1(\m_payload_i_reg[61]_0 [5]),
+ .I2(\m_payload_i_reg[61]_0 [4]),
+ .I3(\m_payload_i_reg[61]_0 [35]),
+ .I4(\m_payload_i_reg[61]_0 [36]),
+ .I5(\m_payload_i_reg[61]_0 [6]),
+ .O(\axaddr_offset_r[3]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'h0008))
+ \axlen_cnt[3]_i_3__0
+ (.I0(\m_payload_i_reg[61]_0 [42]),
+ .I1(m_valid_i_reg_0),
+ .I2(\axaddr_offset_r_reg[0] [0]),
+ .I3(\axaddr_offset_r_reg[0] [1]),
+ .O(\m_payload_i_reg[47]_2 ));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \m_axi_awaddr[11]_INST_0
+ (.I0(\m_payload_i_reg[39]_0 ),
+ .I1(\m_axi_awaddr[11] ),
+ .I2(\m_payload_i_reg[38]_0 ),
+ .I3(\m_axi_awaddr[11]_0 ),
+ .I4(\m_payload_i_reg[61]_0 [11]),
+ .I5(\m_axi_awaddr[11]_1 ),
+ .O(m_axi_awaddr));
+ (* SOFT_HLUTNM = "soft_lutpair84" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \m_axi_awaddr[11]_INST_0_i_1
+ (.I0(\m_payload_i_reg[61]_0 [38]),
+ .I1(sel_first),
+ .O(\m_payload_i_reg[39]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair84" *)
+ LUT3 #(
+ .INIT(8'h02))
+ \m_axi_awaddr[11]_INST_0_i_2
+ (.I0(\m_payload_i_reg[61]_0 [37]),
+ .I1(sel_first_1),
+ .I2(\m_payload_i_reg[61]_0 [38]),
+ .O(\m_payload_i_reg[38]_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[0]_i_1
+ (.I0(s_axi_awaddr[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[0] ),
+ .O(skid_buffer[0]));
+ (* SOFT_HLUTNM = "soft_lutpair79" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[10]_i_1
+ (.I0(s_axi_awaddr[10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[10] ),
+ .O(skid_buffer[10]));
+ (* SOFT_HLUTNM = "soft_lutpair78" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[11]_i_1
+ (.I0(s_axi_awaddr[11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[11] ),
+ .O(skid_buffer[11]));
+ (* SOFT_HLUTNM = "soft_lutpair78" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[12]_i_1
+ (.I0(s_axi_awaddr[12]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[12] ),
+ .O(skid_buffer[12]));
+ (* SOFT_HLUTNM = "soft_lutpair77" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[13]_i_1__0
+ (.I0(s_axi_awaddr[13]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[13] ),
+ .O(skid_buffer[13]));
+ (* SOFT_HLUTNM = "soft_lutpair77" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[14]_i_1
+ (.I0(s_axi_awaddr[14]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[14] ),
+ .O(skid_buffer[14]));
+ (* SOFT_HLUTNM = "soft_lutpair76" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[15]_i_1
+ (.I0(s_axi_awaddr[15]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[15] ),
+ .O(skid_buffer[15]));
+ (* SOFT_HLUTNM = "soft_lutpair76" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[16]_i_1
+ (.I0(s_axi_awaddr[16]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[16] ),
+ .O(skid_buffer[16]));
+ (* SOFT_HLUTNM = "soft_lutpair75" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[17]_i_1
+ (.I0(s_axi_awaddr[17]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[17] ),
+ .O(skid_buffer[17]));
+ (* SOFT_HLUTNM = "soft_lutpair75" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[18]_i_1
+ (.I0(s_axi_awaddr[18]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[18] ),
+ .O(skid_buffer[18]));
+ (* SOFT_HLUTNM = "soft_lutpair74" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[19]_i_1
+ (.I0(s_axi_awaddr[19]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[19] ),
+ .O(skid_buffer[19]));
+ (* SOFT_HLUTNM = "soft_lutpair83" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[1]_i_1
+ (.I0(s_axi_awaddr[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[1] ),
+ .O(skid_buffer[1]));
+ (* SOFT_HLUTNM = "soft_lutpair74" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[20]_i_1
+ (.I0(s_axi_awaddr[20]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[20] ),
+ .O(skid_buffer[20]));
+ (* SOFT_HLUTNM = "soft_lutpair73" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[21]_i_1
+ (.I0(s_axi_awaddr[21]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[21] ),
+ .O(skid_buffer[21]));
+ (* SOFT_HLUTNM = "soft_lutpair73" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[22]_i_1
+ (.I0(s_axi_awaddr[22]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[22] ),
+ .O(skid_buffer[22]));
+ (* SOFT_HLUTNM = "soft_lutpair72" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[23]_i_1
+ (.I0(s_axi_awaddr[23]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[23] ),
+ .O(skid_buffer[23]));
+ (* SOFT_HLUTNM = "soft_lutpair72" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[24]_i_1
+ (.I0(s_axi_awaddr[24]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[24] ),
+ .O(skid_buffer[24]));
+ (* SOFT_HLUTNM = "soft_lutpair71" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[25]_i_1
+ (.I0(s_axi_awaddr[25]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[25] ),
+ .O(skid_buffer[25]));
+ (* SOFT_HLUTNM = "soft_lutpair71" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[26]_i_1
+ (.I0(s_axi_awaddr[26]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[26] ),
+ .O(skid_buffer[26]));
+ (* SOFT_HLUTNM = "soft_lutpair70" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[27]_i_1
+ (.I0(s_axi_awaddr[27]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[27] ),
+ .O(skid_buffer[27]));
+ (* SOFT_HLUTNM = "soft_lutpair70" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[28]_i_1
+ (.I0(s_axi_awaddr[28]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[28] ),
+ .O(skid_buffer[28]));
+ (* SOFT_HLUTNM = "soft_lutpair69" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[29]_i_1
+ (.I0(s_axi_awaddr[29]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[29] ),
+ .O(skid_buffer[29]));
+ (* SOFT_HLUTNM = "soft_lutpair83" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[2]_i_1
+ (.I0(s_axi_awaddr[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[2] ),
+ .O(skid_buffer[2]));
+ (* SOFT_HLUTNM = "soft_lutpair69" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[30]_i_1
+ (.I0(s_axi_awaddr[30]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[30] ),
+ .O(skid_buffer[30]));
+ (* SOFT_HLUTNM = "soft_lutpair68" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[31]_i_2
+ (.I0(s_axi_awaddr[31]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[31] ),
+ .O(skid_buffer[31]));
+ (* SOFT_HLUTNM = "soft_lutpair68" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[32]_i_1
+ (.I0(s_axi_awprot[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[32] ),
+ .O(skid_buffer[32]));
+ (* SOFT_HLUTNM = "soft_lutpair67" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[33]_i_1
+ (.I0(s_axi_awprot[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[33] ),
+ .O(skid_buffer[33]));
+ (* SOFT_HLUTNM = "soft_lutpair67" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[34]_i_1
+ (.I0(s_axi_awprot[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[34] ),
+ .O(skid_buffer[34]));
+ (* SOFT_HLUTNM = "soft_lutpair66" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[35]_i_1
+ (.I0(s_axi_awsize[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[35] ),
+ .O(skid_buffer[35]));
+ (* SOFT_HLUTNM = "soft_lutpair66" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[36]_i_1
+ (.I0(s_axi_awsize[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[36] ),
+ .O(skid_buffer[36]));
+ (* SOFT_HLUTNM = "soft_lutpair65" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[38]_i_1
+ (.I0(s_axi_awburst[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[38] ),
+ .O(skid_buffer[38]));
+ (* SOFT_HLUTNM = "soft_lutpair65" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[39]_i_1
+ (.I0(s_axi_awburst[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[39] ),
+ .O(skid_buffer[39]));
+ (* SOFT_HLUTNM = "soft_lutpair82" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[3]_i_1
+ (.I0(s_axi_awaddr[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[3] ),
+ .O(skid_buffer[3]));
+ (* SOFT_HLUTNM = "soft_lutpair64" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[44]_i_1
+ (.I0(s_axi_awlen[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[44] ),
+ .O(skid_buffer[44]));
+ (* SOFT_HLUTNM = "soft_lutpair64" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[45]_i_1
+ (.I0(s_axi_awlen[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[45] ),
+ .O(skid_buffer[45]));
+ (* SOFT_HLUTNM = "soft_lutpair63" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[46]_i_1__0
+ (.I0(s_axi_awlen[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[46] ),
+ .O(skid_buffer[46]));
+ (* SOFT_HLUTNM = "soft_lutpair63" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[47]_i_1
+ (.I0(s_axi_awlen[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[47] ),
+ .O(skid_buffer[47]));
+ (* SOFT_HLUTNM = "soft_lutpair82" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[4]_i_1
+ (.I0(s_axi_awaddr[4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[4] ),
+ .O(skid_buffer[4]));
+ (* SOFT_HLUTNM = "soft_lutpair62" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[50]_i_1
+ (.I0(s_axi_awid[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[50] ),
+ .O(skid_buffer[50]));
+ (* SOFT_HLUTNM = "soft_lutpair62" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[51]_i_1
+ (.I0(s_axi_awid[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[51] ),
+ .O(skid_buffer[51]));
+ (* SOFT_HLUTNM = "soft_lutpair61" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[52]_i_1
+ (.I0(s_axi_awid[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[52] ),
+ .O(skid_buffer[52]));
+ (* SOFT_HLUTNM = "soft_lutpair61" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[53]_i_1
+ (.I0(s_axi_awid[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[53] ),
+ .O(skid_buffer[53]));
+ (* SOFT_HLUTNM = "soft_lutpair60" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[54]_i_1
+ (.I0(s_axi_awid[4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[54] ),
+ .O(skid_buffer[54]));
+ (* SOFT_HLUTNM = "soft_lutpair60" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[55]_i_1
+ (.I0(s_axi_awid[5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[55] ),
+ .O(skid_buffer[55]));
+ (* SOFT_HLUTNM = "soft_lutpair59" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[56]_i_1
+ (.I0(s_axi_awid[6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[56] ),
+ .O(skid_buffer[56]));
+ (* SOFT_HLUTNM = "soft_lutpair59" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[57]_i_1
+ (.I0(s_axi_awid[7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[57] ),
+ .O(skid_buffer[57]));
+ (* SOFT_HLUTNM = "soft_lutpair58" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[58]_i_1
+ (.I0(s_axi_awid[8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[58] ),
+ .O(skid_buffer[58]));
+ (* SOFT_HLUTNM = "soft_lutpair58" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[59]_i_1
+ (.I0(s_axi_awid[9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[59] ),
+ .O(skid_buffer[59]));
+ (* SOFT_HLUTNM = "soft_lutpair81" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[5]_i_1
+ (.I0(s_axi_awaddr[5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[5] ),
+ .O(skid_buffer[5]));
+ (* SOFT_HLUTNM = "soft_lutpair57" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[60]_i_1
+ (.I0(s_axi_awid[10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[60] ),
+ .O(skid_buffer[60]));
+ (* SOFT_HLUTNM = "soft_lutpair57" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[61]_i_1
+ (.I0(s_axi_awid[11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[61] ),
+ .O(skid_buffer[61]));
+ (* SOFT_HLUTNM = "soft_lutpair81" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[6]_i_1
+ (.I0(s_axi_awaddr[6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[6] ),
+ .O(skid_buffer[6]));
+ (* SOFT_HLUTNM = "soft_lutpair80" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[7]_i_1
+ (.I0(s_axi_awaddr[7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[7] ),
+ .O(skid_buffer[7]));
+ (* SOFT_HLUTNM = "soft_lutpair80" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[8]_i_1
+ (.I0(s_axi_awaddr[8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[8] ),
+ .O(skid_buffer[8]));
+ (* SOFT_HLUTNM = "soft_lutpair79" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[9]_i_1
+ (.I0(s_axi_awaddr[9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[9] ),
+ .O(skid_buffer[9]));
+ FDRE \m_payload_i_reg[0]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[0]),
+ .Q(\m_payload_i_reg[61]_0 [0]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[10]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[10]),
+ .Q(\m_payload_i_reg[61]_0 [10]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[11]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[11]),
+ .Q(\m_payload_i_reg[61]_0 [11]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[12]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[12]),
+ .Q(\m_payload_i_reg[61]_0 [12]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[13]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[13]),
+ .Q(\m_payload_i_reg[61]_0 [13]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[14]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[14]),
+ .Q(\m_payload_i_reg[61]_0 [14]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[15]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[15]),
+ .Q(\m_payload_i_reg[61]_0 [15]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[16]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[16]),
+ .Q(\m_payload_i_reg[61]_0 [16]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[17]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[17]),
+ .Q(\m_payload_i_reg[61]_0 [17]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[18]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[18]),
+ .Q(\m_payload_i_reg[61]_0 [18]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[19]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[19]),
+ .Q(\m_payload_i_reg[61]_0 [19]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[1]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[1]),
+ .Q(\m_payload_i_reg[61]_0 [1]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[20]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[20]),
+ .Q(\m_payload_i_reg[61]_0 [20]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[21]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[21]),
+ .Q(\m_payload_i_reg[61]_0 [21]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[22]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[22]),
+ .Q(\m_payload_i_reg[61]_0 [22]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[23]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[23]),
+ .Q(\m_payload_i_reg[61]_0 [23]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[24]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[24]),
+ .Q(\m_payload_i_reg[61]_0 [24]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[25]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[25]),
+ .Q(\m_payload_i_reg[61]_0 [25]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[26]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[26]),
+ .Q(\m_payload_i_reg[61]_0 [26]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[27]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[27]),
+ .Q(\m_payload_i_reg[61]_0 [27]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[28]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[28]),
+ .Q(\m_payload_i_reg[61]_0 [28]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[29]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[29]),
+ .Q(\m_payload_i_reg[61]_0 [29]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[2]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[2]),
+ .Q(\m_payload_i_reg[61]_0 [2]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[30]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[30]),
+ .Q(\m_payload_i_reg[61]_0 [30]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[31]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[31]),
+ .Q(\m_payload_i_reg[61]_0 [31]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[32]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[32]),
+ .Q(\m_payload_i_reg[61]_0 [32]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[33]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[33]),
+ .Q(\m_payload_i_reg[61]_0 [33]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[34]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[34]),
+ .Q(\m_payload_i_reg[61]_0 [34]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[35]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[35]),
+ .Q(\m_payload_i_reg[61]_0 [35]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[36]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[36]),
+ .Q(\m_payload_i_reg[61]_0 [36]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[38]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[38]),
+ .Q(\m_payload_i_reg[61]_0 [37]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[39]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[39]),
+ .Q(\m_payload_i_reg[61]_0 [38]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[3]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[3]),
+ .Q(\m_payload_i_reg[61]_0 [3]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[44]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[44]),
+ .Q(\m_payload_i_reg[61]_0 [39]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[45]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[45]),
+ .Q(\m_payload_i_reg[61]_0 [40]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[46]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[46]),
+ .Q(\m_payload_i_reg[61]_0 [41]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[47]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[47]),
+ .Q(\m_payload_i_reg[61]_0 [42]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[4]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[4]),
+ .Q(\m_payload_i_reg[61]_0 [4]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[50]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[50]),
+ .Q(\m_payload_i_reg[61]_0 [43]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[51]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[51]),
+ .Q(\m_payload_i_reg[61]_0 [44]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[52]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[52]),
+ .Q(\m_payload_i_reg[61]_0 [45]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[53]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[53]),
+ .Q(\m_payload_i_reg[61]_0 [46]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[54]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[54]),
+ .Q(\m_payload_i_reg[61]_0 [47]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[55]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[55]),
+ .Q(\m_payload_i_reg[61]_0 [48]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[56]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[56]),
+ .Q(\m_payload_i_reg[61]_0 [49]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[57]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[57]),
+ .Q(\m_payload_i_reg[61]_0 [50]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[58]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[58]),
+ .Q(\m_payload_i_reg[61]_0 [51]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[59]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[59]),
+ .Q(\m_payload_i_reg[61]_0 [52]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[5]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[5]),
+ .Q(\m_payload_i_reg[61]_0 [5]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[60]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[60]),
+ .Q(\m_payload_i_reg[61]_0 [53]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[61]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[61]),
+ .Q(\m_payload_i_reg[61]_0 [54]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[6]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[6]),
+ .Q(\m_payload_i_reg[61]_0 [6]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[7]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[7]),
+ .Q(\m_payload_i_reg[61]_0 [7]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[8]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[8]),
+ .Q(\m_payload_i_reg[61]_0 [8]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[9]
+ (.C(aclk),
+ .CE(E),
+ .D(skid_buffer[9]),
+ .Q(\m_payload_i_reg[61]_0 [9]),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hFF4F))
+ m_valid_i_i_1__1
+ (.I0(b_push),
+ .I1(m_valid_i_reg_0),
+ .I2(s_ready_i_reg_0),
+ .I3(s_axi_awvalid),
+ .O(m_valid_i0));
+ FDRE #(
+ .INIT(1'b0))
+ m_valid_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_valid_i0),
+ .Q(m_valid_i_reg_0),
+ .R(m_valid_i_reg_1));
+ LUT5 #(
+ .INIT(32'hFFFE0000))
+ next_pending_r_i_2
+ (.I0(\m_payload_i_reg[61]_0 [42]),
+ .I1(\m_payload_i_reg[61]_0 [39]),
+ .I2(\m_payload_i_reg[61]_0 [40]),
+ .I3(\m_payload_i_reg[61]_0 [41]),
+ .I4(\wrap_cnt_r_reg[0] ),
+ .O(\m_payload_i_reg[47]_1 ));
+ LUT1 #(
+ .INIT(2'h1))
+ s_ready_i_i_1__1
+ (.I0(\aresetn_d_reg_n_0_[0] ),
+ .O(\aresetn_d_reg[0]_0 ));
+ LUT4 #(
+ .INIT(16'hBFBB))
+ s_ready_i_i_2
+ (.I0(b_push),
+ .I1(m_valid_i_reg_0),
+ .I2(s_axi_awvalid),
+ .I3(s_ready_i_reg_0),
+ .O(s_ready_i0));
+ FDRE #(
+ .INIT(1'b0))
+ s_ready_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(s_ready_i0),
+ .Q(s_ready_i_reg_0),
+ .R(\aresetn_d_reg[0]_0 ));
+ FDRE \skid_buffer_reg[0]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[0]),
+ .Q(\skid_buffer_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[10]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[10]),
+ .Q(\skid_buffer_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[11]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[11]),
+ .Q(\skid_buffer_reg_n_0_[11] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[12]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[12]),
+ .Q(\skid_buffer_reg_n_0_[12] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[13]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[13]),
+ .Q(\skid_buffer_reg_n_0_[13] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[14]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[14]),
+ .Q(\skid_buffer_reg_n_0_[14] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[15]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[15]),
+ .Q(\skid_buffer_reg_n_0_[15] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[16]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[16]),
+ .Q(\skid_buffer_reg_n_0_[16] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[17]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[17]),
+ .Q(\skid_buffer_reg_n_0_[17] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[18]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[18]),
+ .Q(\skid_buffer_reg_n_0_[18] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[19]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[19]),
+ .Q(\skid_buffer_reg_n_0_[19] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[1]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[1]),
+ .Q(\skid_buffer_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[20]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[20]),
+ .Q(\skid_buffer_reg_n_0_[20] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[21]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[21]),
+ .Q(\skid_buffer_reg_n_0_[21] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[22]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[22]),
+ .Q(\skid_buffer_reg_n_0_[22] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[23]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[23]),
+ .Q(\skid_buffer_reg_n_0_[23] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[24]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[24]),
+ .Q(\skid_buffer_reg_n_0_[24] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[25]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[25]),
+ .Q(\skid_buffer_reg_n_0_[25] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[26]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[26]),
+ .Q(\skid_buffer_reg_n_0_[26] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[27]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[27]),
+ .Q(\skid_buffer_reg_n_0_[27] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[28]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[28]),
+ .Q(\skid_buffer_reg_n_0_[28] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[29]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[29]),
+ .Q(\skid_buffer_reg_n_0_[29] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[2]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[2]),
+ .Q(\skid_buffer_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[30]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[30]),
+ .Q(\skid_buffer_reg_n_0_[30] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[31]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[31]),
+ .Q(\skid_buffer_reg_n_0_[31] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[32]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awprot[0]),
+ .Q(\skid_buffer_reg_n_0_[32] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[33]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awprot[1]),
+ .Q(\skid_buffer_reg_n_0_[33] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[34]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awprot[2]),
+ .Q(\skid_buffer_reg_n_0_[34] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[35]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awsize[0]),
+ .Q(\skid_buffer_reg_n_0_[35] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[36]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awsize[1]),
+ .Q(\skid_buffer_reg_n_0_[36] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[38]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awburst[0]),
+ .Q(\skid_buffer_reg_n_0_[38] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[39]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awburst[1]),
+ .Q(\skid_buffer_reg_n_0_[39] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[3]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[3]),
+ .Q(\skid_buffer_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[44]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awlen[0]),
+ .Q(\skid_buffer_reg_n_0_[44] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[45]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awlen[1]),
+ .Q(\skid_buffer_reg_n_0_[45] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[46]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awlen[2]),
+ .Q(\skid_buffer_reg_n_0_[46] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[47]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awlen[3]),
+ .Q(\skid_buffer_reg_n_0_[47] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[4]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[4]),
+ .Q(\skid_buffer_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[50]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[0]),
+ .Q(\skid_buffer_reg_n_0_[50] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[51]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[1]),
+ .Q(\skid_buffer_reg_n_0_[51] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[52]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[2]),
+ .Q(\skid_buffer_reg_n_0_[52] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[53]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[3]),
+ .Q(\skid_buffer_reg_n_0_[53] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[54]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[4]),
+ .Q(\skid_buffer_reg_n_0_[54] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[55]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[5]),
+ .Q(\skid_buffer_reg_n_0_[55] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[56]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[6]),
+ .Q(\skid_buffer_reg_n_0_[56] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[57]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[7]),
+ .Q(\skid_buffer_reg_n_0_[57] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[58]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[8]),
+ .Q(\skid_buffer_reg_n_0_[58] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[59]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[9]),
+ .Q(\skid_buffer_reg_n_0_[59] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[5]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[5]),
+ .Q(\skid_buffer_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[60]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[10]),
+ .Q(\skid_buffer_reg_n_0_[60] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[61]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awid[11]),
+ .Q(\skid_buffer_reg_n_0_[61] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[6]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[6]),
+ .Q(\skid_buffer_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[7]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[7]),
+ .Q(\skid_buffer_reg_n_0_[7] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[8]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[8]),
+ .Q(\skid_buffer_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[9]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(s_axi_awaddr[9]),
+ .Q(\skid_buffer_reg_n_0_[9] ),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hAA8A))
+ \wrap_boundary_axaddr_r[0]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [0]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [39]),
+ .I3(\m_payload_i_reg[61]_0 [36]),
+ .O(\m_payload_i_reg[6]_0 [0]));
+ LUT5 #(
+ .INIT(32'hFF470000))
+ \wrap_boundary_axaddr_r[1]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [39]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [40]),
+ .I3(\m_payload_i_reg[61]_0 [36]),
+ .I4(\m_payload_i_reg[61]_0 [1]),
+ .O(\m_payload_i_reg[6]_0 [1]));
+ LUT6 #(
+ .INIT(64'hA0A002A2AAAA02A2))
+ \wrap_boundary_axaddr_r[2]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [2]),
+ .I1(\m_payload_i_reg[61]_0 [41]),
+ .I2(\m_payload_i_reg[61]_0 [35]),
+ .I3(\m_payload_i_reg[61]_0 [40]),
+ .I4(\m_payload_i_reg[61]_0 [36]),
+ .I5(\m_payload_i_reg[61]_0 [39]),
+ .O(\m_payload_i_reg[6]_0 [2]));
+ LUT6 #(
+ .INIT(64'h4747000000FF0000))
+ \wrap_boundary_axaddr_r[3]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [39]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [40]),
+ .I3(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
+ .I4(\m_payload_i_reg[61]_0 [3]),
+ .I5(\m_payload_i_reg[61]_0 [36]),
+ .O(\m_payload_i_reg[6]_0 [3]));
+ (* SOFT_HLUTNM = "soft_lutpair54" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \wrap_boundary_axaddr_r[3]_i_2
+ (.I0(\m_payload_i_reg[61]_0 [41]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [42]),
+ .O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h002A0A2AA02AAA2A))
+ \wrap_boundary_axaddr_r[4]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [4]),
+ .I1(\m_payload_i_reg[61]_0 [42]),
+ .I2(\m_payload_i_reg[61]_0 [35]),
+ .I3(\m_payload_i_reg[61]_0 [36]),
+ .I4(\m_payload_i_reg[61]_0 [41]),
+ .I5(\m_payload_i_reg[61]_0 [40]),
+ .O(\m_payload_i_reg[6]_0 [4]));
+ (* SOFT_HLUTNM = "soft_lutpair54" *)
+ LUT5 #(
+ .INIT(32'h47FF0000))
+ \wrap_boundary_axaddr_r[5]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [41]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [42]),
+ .I3(\m_payload_i_reg[61]_0 [36]),
+ .I4(\m_payload_i_reg[61]_0 [5]),
+ .O(\m_payload_i_reg[6]_0 [5]));
+ LUT4 #(
+ .INIT(16'h2AAA))
+ \wrap_boundary_axaddr_r[6]_i_1
+ (.I0(\m_payload_i_reg[61]_0 [6]),
+ .I1(\m_payload_i_reg[61]_0 [35]),
+ .I2(\m_payload_i_reg[61]_0 [36]),
+ .I3(\m_payload_i_reg[61]_0 [42]),
+ .O(\m_payload_i_reg[6]_0 [6]));
+ LUT6 #(
+ .INIT(64'hA0AFA0AFA0AFA1AE))
+ \wrap_cnt_r[0]_i_1
+ (.I0(\m_payload_i_reg[44]_0 ),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\wrap_cnt_r_reg[0] ),
+ .I3(Q[0]),
+ .I4(\m_payload_i_reg[47]_0 ),
+ .I5(\axaddr_offset_r_reg[2] ),
+ .O(D[0]));
+ LUT2 #(
+ .INIT(4'h6))
+ \wrap_cnt_r[1]_i_1
+ (.I0(\wrap_cnt_r[3]_i_2_n_0 ),
+ .I1(\wrap_second_len_r_reg[1] ),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair55" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \wrap_cnt_r[2]_i_1
+ (.I0(\wrap_cnt_r[3]_i_2_n_0 ),
+ .I1(\wrap_second_len_r_reg[1] ),
+ .I2(wrap_second_len[1]),
+ .O(D[2]));
+ (* SOFT_HLUTNM = "soft_lutpair55" *)
+ LUT4 #(
+ .INIT(16'h7F80))
+ \wrap_cnt_r[3]_i_1
+ (.I0(\wrap_second_len_r_reg[1] ),
+ .I1(\wrap_cnt_r[3]_i_2_n_0 ),
+ .I2(wrap_second_len[1]),
+ .I3(wrap_second_len[2]),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'h5555FFFC0000AAA8))
+ \wrap_cnt_r[3]_i_2
+ (.I0(\wrap_cnt_r_reg[0] ),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\m_payload_i_reg[47]_0 ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(Q[0]),
+ .O(\wrap_cnt_r[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h33333330AAAAAAAA))
+ \wrap_second_len_r[0]_i_1
+ (.I0(Q[0]),
+ .I1(\m_payload_i_reg[44]_0 ),
+ .I2(\m_payload_i_reg[47]_0 ),
+ .I3(\axaddr_offset_r_reg[2] ),
+ .I4(\axaddr_offset_r_reg[1] ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(wrap_second_len[0]));
+ LUT6 #(
+ .INIT(64'hFF0000FCAAAAAAAA))
+ \wrap_second_len_r[1]_i_1
+ (.I0(Q[1]),
+ .I1(\m_payload_i_reg[47]_0 ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\axaddr_offset_r_reg[1] ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(\wrap_second_len_r_reg[1] ));
+ LUT6 #(
+ .INIT(64'hF0F0F00CAAAAAAAA))
+ \wrap_second_len_r[2]_i_1
+ (.I0(Q[2]),
+ .I1(\m_payload_i_reg[47]_0 ),
+ .I2(\axaddr_offset_r_reg[2] ),
+ .I3(\axaddr_offset_r_reg[1] ),
+ .I4(\m_payload_i_reg[44]_0 ),
+ .I5(\wrap_cnt_r_reg[0] ),
+ .O(wrap_second_len[1]));
+ LUT6 #(
+ .INIT(64'hFFFCAAAA0000AAAA))
+ \wrap_second_len_r[3]_i_1
+ (.I0(Q[3]),
+ .I1(\axaddr_offset_r_reg[1] ),
+ .I2(\m_payload_i_reg[44]_0 ),
+ .I3(\axaddr_offset_r_reg[2] ),
+ .I4(\wrap_cnt_r_reg[0] ),
+ .I5(\m_payload_i_reg[47]_0 ),
+ .O(wrap_second_len[2]));
+endmodule
+
+(* ORIG_REF_NAME = "axi_register_slice_v2_1_19_axic_register_slice" *)
+module TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1
+ (m_valid_i_reg_0,
+ s_ready_i_reg_0,
+ \m_payload_i_reg[13]_0 ,
+ m_valid_i_reg_1,
+ aclk,
+ s_ready_i_reg_1,
+ s_axi_bready,
+ si_rs_bvalid,
+ out,
+ \skid_buffer_reg[1]_0 );
+ output m_valid_i_reg_0;
+ output s_ready_i_reg_0;
+ output [13:0]\m_payload_i_reg[13]_0 ;
+ input m_valid_i_reg_1;
+ input aclk;
+ input s_ready_i_reg_1;
+ input s_axi_bready;
+ input si_rs_bvalid;
+ input [11:0]out;
+ input [1:0]\skid_buffer_reg[1]_0 ;
+
+ wire aclk;
+ wire \m_payload_i[0]_i_1__1_n_0 ;
+ wire \m_payload_i[10]_i_1__1_n_0 ;
+ wire \m_payload_i[11]_i_1__1_n_0 ;
+ wire \m_payload_i[12]_i_1__1_n_0 ;
+ wire \m_payload_i[13]_i_2_n_0 ;
+ wire \m_payload_i[1]_i_1__1_n_0 ;
+ wire \m_payload_i[2]_i_1__1_n_0 ;
+ wire \m_payload_i[3]_i_1__1_n_0 ;
+ wire \m_payload_i[4]_i_1__1_n_0 ;
+ wire \m_payload_i[5]_i_1__1_n_0 ;
+ wire \m_payload_i[6]_i_1__1_n_0 ;
+ wire \m_payload_i[7]_i_1__1_n_0 ;
+ wire \m_payload_i[8]_i_1__1_n_0 ;
+ wire \m_payload_i[9]_i_1__1_n_0 ;
+ wire [13:0]\m_payload_i_reg[13]_0 ;
+ wire m_valid_i0;
+ wire m_valid_i_reg_0;
+ wire m_valid_i_reg_1;
+ wire [11:0]out;
+ wire p_1_in;
+ wire s_axi_bready;
+ wire s_ready_i0;
+ wire s_ready_i_reg_0;
+ wire s_ready_i_reg_1;
+ wire si_rs_bvalid;
+ wire [1:0]\skid_buffer_reg[1]_0 ;
+ wire \skid_buffer_reg_n_0_[0] ;
+ wire \skid_buffer_reg_n_0_[10] ;
+ wire \skid_buffer_reg_n_0_[11] ;
+ wire \skid_buffer_reg_n_0_[12] ;
+ wire \skid_buffer_reg_n_0_[13] ;
+ wire \skid_buffer_reg_n_0_[1] ;
+ wire \skid_buffer_reg_n_0_[2] ;
+ wire \skid_buffer_reg_n_0_[3] ;
+ wire \skid_buffer_reg_n_0_[4] ;
+ wire \skid_buffer_reg_n_0_[5] ;
+ wire \skid_buffer_reg_n_0_[6] ;
+ wire \skid_buffer_reg_n_0_[7] ;
+ wire \skid_buffer_reg_n_0_[8] ;
+ wire \skid_buffer_reg_n_0_[9] ;
+
+ (* SOFT_HLUTNM = "soft_lutpair91" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[0]_i_1__1
+ (.I0(\skid_buffer_reg[1]_0 [0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[0] ),
+ .O(\m_payload_i[0]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair86" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[10]_i_1__1
+ (.I0(out[8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[10] ),
+ .O(\m_payload_i[10]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair85" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[11]_i_1__1
+ (.I0(out[9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[11] ),
+ .O(\m_payload_i[11]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair86" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[12]_i_1__1
+ (.I0(out[10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[12] ),
+ .O(\m_payload_i[12]_i_1__1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \m_payload_i[13]_i_1
+ (.I0(s_axi_bready),
+ .I1(m_valid_i_reg_0),
+ .O(p_1_in));
+ (* SOFT_HLUTNM = "soft_lutpair85" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[13]_i_2
+ (.I0(out[11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[13] ),
+ .O(\m_payload_i[13]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair91" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[1]_i_1__1
+ (.I0(\skid_buffer_reg[1]_0 [1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[1] ),
+ .O(\m_payload_i[1]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair90" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[2]_i_1__1
+ (.I0(out[0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[2] ),
+ .O(\m_payload_i[2]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair90" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[3]_i_1__1
+ (.I0(out[1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[3] ),
+ .O(\m_payload_i[3]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair89" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[4]_i_1__1
+ (.I0(out[2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[4] ),
+ .O(\m_payload_i[4]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair89" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[5]_i_1__1
+ (.I0(out[3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[5] ),
+ .O(\m_payload_i[5]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair88" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[6]_i_1__1
+ (.I0(out[4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[6] ),
+ .O(\m_payload_i[6]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair88" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[7]_i_1__1
+ (.I0(out[5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[7] ),
+ .O(\m_payload_i[7]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair87" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[8]_i_1__1
+ (.I0(out[6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[8] ),
+ .O(\m_payload_i[8]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair87" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[9]_i_1__1
+ (.I0(out[7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[9] ),
+ .O(\m_payload_i[9]_i_1__1_n_0 ));
+ FDRE \m_payload_i_reg[0]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[0]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [0]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[10]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[10]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [10]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[11]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[11]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [11]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[12]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[12]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [12]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[13]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[13]_i_2_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [13]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[1]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[1]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [1]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[2]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[2]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [2]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[3]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[3]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [3]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[4]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[4]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [4]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[5]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[5]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [5]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[6]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[6]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [6]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[7]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[7]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [7]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[8]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[8]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [8]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[9]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[9]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[13]_0 [9]),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hFF4F))
+ m_valid_i_i_1__0
+ (.I0(s_axi_bready),
+ .I1(m_valid_i_reg_0),
+ .I2(s_ready_i_reg_0),
+ .I3(si_rs_bvalid),
+ .O(m_valid_i0));
+ FDRE #(
+ .INIT(1'b0))
+ m_valid_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_valid_i0),
+ .Q(m_valid_i_reg_0),
+ .R(m_valid_i_reg_1));
+ LUT4 #(
+ .INIT(16'hFF4F))
+ s_ready_i_i_1__0
+ (.I0(si_rs_bvalid),
+ .I1(s_ready_i_reg_0),
+ .I2(m_valid_i_reg_0),
+ .I3(s_axi_bready),
+ .O(s_ready_i0));
+ FDRE #(
+ .INIT(1'b0))
+ s_ready_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(s_ready_i0),
+ .Q(s_ready_i_reg_0),
+ .R(s_ready_i_reg_1));
+ FDRE \skid_buffer_reg[0]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[1]_0 [0]),
+ .Q(\skid_buffer_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[10]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[8]),
+ .Q(\skid_buffer_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[11]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[9]),
+ .Q(\skid_buffer_reg_n_0_[11] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[12]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[10]),
+ .Q(\skid_buffer_reg_n_0_[12] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[13]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[11]),
+ .Q(\skid_buffer_reg_n_0_[13] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[1]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[1]_0 [1]),
+ .Q(\skid_buffer_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[2]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[0]),
+ .Q(\skid_buffer_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[3]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[1]),
+ .Q(\skid_buffer_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[4]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[2]),
+ .Q(\skid_buffer_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[5]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[3]),
+ .Q(\skid_buffer_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[6]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[4]),
+ .Q(\skid_buffer_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[7]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[5]),
+ .Q(\skid_buffer_reg_n_0_[7] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[8]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[6]),
+ .Q(\skid_buffer_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[9]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(out[7]),
+ .Q(\skid_buffer_reg_n_0_[9] ),
+ .R(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "axi_register_slice_v2_1_19_axic_register_slice" *)
+module TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2
+ (m_valid_i_reg_0,
+ s_ready_i_reg_0,
+ \m_payload_i_reg[46]_0 ,
+ m_valid_i_reg_1,
+ aclk,
+ s_ready_i_reg_1,
+ si_rs_rvalid,
+ s_axi_rready,
+ \skid_buffer_reg[46]_0 ,
+ \skid_buffer_reg[33]_0 );
+ output m_valid_i_reg_0;
+ output s_ready_i_reg_0;
+ output [46:0]\m_payload_i_reg[46]_0 ;
+ input m_valid_i_reg_1;
+ input aclk;
+ input s_ready_i_reg_1;
+ input si_rs_rvalid;
+ input s_axi_rready;
+ input [12:0]\skid_buffer_reg[46]_0 ;
+ input [33:0]\skid_buffer_reg[33]_0 ;
+
+ wire aclk;
+ wire \m_payload_i[0]_i_1__2_n_0 ;
+ wire \m_payload_i[10]_i_1__2_n_0 ;
+ wire \m_payload_i[11]_i_1__2_n_0 ;
+ wire \m_payload_i[12]_i_1__2_n_0 ;
+ wire \m_payload_i[13]_i_1__2_n_0 ;
+ wire \m_payload_i[14]_i_1__1_n_0 ;
+ wire \m_payload_i[15]_i_1__1_n_0 ;
+ wire \m_payload_i[16]_i_1__1_n_0 ;
+ wire \m_payload_i[17]_i_1__1_n_0 ;
+ wire \m_payload_i[18]_i_1__1_n_0 ;
+ wire \m_payload_i[19]_i_1__1_n_0 ;
+ wire \m_payload_i[1]_i_1__2_n_0 ;
+ wire \m_payload_i[20]_i_1__1_n_0 ;
+ wire \m_payload_i[21]_i_1__1_n_0 ;
+ wire \m_payload_i[22]_i_1__1_n_0 ;
+ wire \m_payload_i[23]_i_1__1_n_0 ;
+ wire \m_payload_i[24]_i_1__1_n_0 ;
+ wire \m_payload_i[25]_i_1__1_n_0 ;
+ wire \m_payload_i[26]_i_1__1_n_0 ;
+ wire \m_payload_i[27]_i_1__1_n_0 ;
+ wire \m_payload_i[28]_i_1__1_n_0 ;
+ wire \m_payload_i[29]_i_1__1_n_0 ;
+ wire \m_payload_i[2]_i_1__2_n_0 ;
+ wire \m_payload_i[30]_i_1__1_n_0 ;
+ wire \m_payload_i[31]_i_1__0_n_0 ;
+ wire \m_payload_i[32]_i_1__1_n_0 ;
+ wire \m_payload_i[33]_i_1__1_n_0 ;
+ wire \m_payload_i[34]_i_1__1_n_0 ;
+ wire \m_payload_i[35]_i_1__1_n_0 ;
+ wire \m_payload_i[36]_i_1__1_n_0 ;
+ wire \m_payload_i[37]_i_1_n_0 ;
+ wire \m_payload_i[38]_i_1__1_n_0 ;
+ wire \m_payload_i[39]_i_1__1_n_0 ;
+ wire \m_payload_i[3]_i_1__2_n_0 ;
+ wire \m_payload_i[40]_i_1_n_0 ;
+ wire \m_payload_i[41]_i_1_n_0 ;
+ wire \m_payload_i[42]_i_1_n_0 ;
+ wire \m_payload_i[43]_i_1_n_0 ;
+ wire \m_payload_i[44]_i_1__1_n_0 ;
+ wire \m_payload_i[45]_i_1__1_n_0 ;
+ wire \m_payload_i[46]_i_2_n_0 ;
+ wire \m_payload_i[4]_i_1__2_n_0 ;
+ wire \m_payload_i[5]_i_1__2_n_0 ;
+ wire \m_payload_i[6]_i_1__2_n_0 ;
+ wire \m_payload_i[7]_i_1__2_n_0 ;
+ wire \m_payload_i[8]_i_1__2_n_0 ;
+ wire \m_payload_i[9]_i_1__2_n_0 ;
+ wire [46:0]\m_payload_i_reg[46]_0 ;
+ wire m_valid_i0;
+ wire m_valid_i_reg_0;
+ wire m_valid_i_reg_1;
+ wire p_1_in;
+ wire s_axi_rready;
+ wire s_ready_i0;
+ wire s_ready_i_reg_0;
+ wire s_ready_i_reg_1;
+ wire si_rs_rvalid;
+ wire [33:0]\skid_buffer_reg[33]_0 ;
+ wire [12:0]\skid_buffer_reg[46]_0 ;
+ wire \skid_buffer_reg_n_0_[0] ;
+ wire \skid_buffer_reg_n_0_[10] ;
+ wire \skid_buffer_reg_n_0_[11] ;
+ wire \skid_buffer_reg_n_0_[12] ;
+ wire \skid_buffer_reg_n_0_[13] ;
+ wire \skid_buffer_reg_n_0_[14] ;
+ wire \skid_buffer_reg_n_0_[15] ;
+ wire \skid_buffer_reg_n_0_[16] ;
+ wire \skid_buffer_reg_n_0_[17] ;
+ wire \skid_buffer_reg_n_0_[18] ;
+ wire \skid_buffer_reg_n_0_[19] ;
+ wire \skid_buffer_reg_n_0_[1] ;
+ wire \skid_buffer_reg_n_0_[20] ;
+ wire \skid_buffer_reg_n_0_[21] ;
+ wire \skid_buffer_reg_n_0_[22] ;
+ wire \skid_buffer_reg_n_0_[23] ;
+ wire \skid_buffer_reg_n_0_[24] ;
+ wire \skid_buffer_reg_n_0_[25] ;
+ wire \skid_buffer_reg_n_0_[26] ;
+ wire \skid_buffer_reg_n_0_[27] ;
+ wire \skid_buffer_reg_n_0_[28] ;
+ wire \skid_buffer_reg_n_0_[29] ;
+ wire \skid_buffer_reg_n_0_[2] ;
+ wire \skid_buffer_reg_n_0_[30] ;
+ wire \skid_buffer_reg_n_0_[31] ;
+ wire \skid_buffer_reg_n_0_[32] ;
+ wire \skid_buffer_reg_n_0_[33] ;
+ wire \skid_buffer_reg_n_0_[34] ;
+ wire \skid_buffer_reg_n_0_[35] ;
+ wire \skid_buffer_reg_n_0_[36] ;
+ wire \skid_buffer_reg_n_0_[37] ;
+ wire \skid_buffer_reg_n_0_[38] ;
+ wire \skid_buffer_reg_n_0_[39] ;
+ wire \skid_buffer_reg_n_0_[3] ;
+ wire \skid_buffer_reg_n_0_[40] ;
+ wire \skid_buffer_reg_n_0_[41] ;
+ wire \skid_buffer_reg_n_0_[42] ;
+ wire \skid_buffer_reg_n_0_[43] ;
+ wire \skid_buffer_reg_n_0_[44] ;
+ wire \skid_buffer_reg_n_0_[45] ;
+ wire \skid_buffer_reg_n_0_[46] ;
+ wire \skid_buffer_reg_n_0_[4] ;
+ wire \skid_buffer_reg_n_0_[5] ;
+ wire \skid_buffer_reg_n_0_[6] ;
+ wire \skid_buffer_reg_n_0_[7] ;
+ wire \skid_buffer_reg_n_0_[8] ;
+ wire \skid_buffer_reg_n_0_[9] ;
+
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[0]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[0] ),
+ .O(\m_payload_i[0]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair110" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[10]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[10] ),
+ .O(\m_payload_i[10]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair109" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[11]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[11] ),
+ .O(\m_payload_i[11]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair109" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[12]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [12]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[12] ),
+ .O(\m_payload_i[12]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair108" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[13]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [13]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[13] ),
+ .O(\m_payload_i[13]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair108" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[14]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [14]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[14] ),
+ .O(\m_payload_i[14]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair107" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[15]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [15]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[15] ),
+ .O(\m_payload_i[15]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair107" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[16]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [16]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[16] ),
+ .O(\m_payload_i[16]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair106" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[17]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [17]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[17] ),
+ .O(\m_payload_i[17]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair106" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[18]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [18]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[18] ),
+ .O(\m_payload_i[18]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair105" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[19]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [19]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[19] ),
+ .O(\m_payload_i[19]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair114" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[1]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[1] ),
+ .O(\m_payload_i[1]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair105" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[20]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [20]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[20] ),
+ .O(\m_payload_i[20]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair104" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[21]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [21]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[21] ),
+ .O(\m_payload_i[21]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair104" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[22]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [22]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[22] ),
+ .O(\m_payload_i[22]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair103" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[23]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [23]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[23] ),
+ .O(\m_payload_i[23]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair103" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[24]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [24]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[24] ),
+ .O(\m_payload_i[24]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair102" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[25]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [25]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[25] ),
+ .O(\m_payload_i[25]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair102" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[26]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [26]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[26] ),
+ .O(\m_payload_i[26]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair101" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[27]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [27]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[27] ),
+ .O(\m_payload_i[27]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair101" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[28]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [28]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[28] ),
+ .O(\m_payload_i[28]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair100" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[29]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [29]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[29] ),
+ .O(\m_payload_i[29]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair114" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[2]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[2] ),
+ .O(\m_payload_i[2]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair100" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[30]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [30]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[30] ),
+ .O(\m_payload_i[30]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair99" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[31]_i_1__0
+ (.I0(\skid_buffer_reg[33]_0 [31]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[31] ),
+ .O(\m_payload_i[31]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair99" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[32]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [32]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[32] ),
+ .O(\m_payload_i[32]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair98" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[33]_i_1__1
+ (.I0(\skid_buffer_reg[33]_0 [33]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[33] ),
+ .O(\m_payload_i[33]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair98" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[34]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [0]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[34] ),
+ .O(\m_payload_i[34]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair97" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[35]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [1]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[35] ),
+ .O(\m_payload_i[35]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair97" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[36]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [2]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[36] ),
+ .O(\m_payload_i[36]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair96" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[37]_i_1
+ (.I0(\skid_buffer_reg[46]_0 [3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[37] ),
+ .O(\m_payload_i[37]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair96" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[38]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[38] ),
+ .O(\m_payload_i[38]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair95" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[39]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[39] ),
+ .O(\m_payload_i[39]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair113" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[3]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [3]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[3] ),
+ .O(\m_payload_i[3]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair95" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[40]_i_1
+ (.I0(\skid_buffer_reg[46]_0 [6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[40] ),
+ .O(\m_payload_i[40]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair94" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[41]_i_1
+ (.I0(\skid_buffer_reg[46]_0 [7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[41] ),
+ .O(\m_payload_i[41]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair94" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[42]_i_1
+ (.I0(\skid_buffer_reg[46]_0 [8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[42] ),
+ .O(\m_payload_i[42]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair93" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[43]_i_1
+ (.I0(\skid_buffer_reg[46]_0 [9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[43] ),
+ .O(\m_payload_i[43]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair92" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[44]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [10]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[44] ),
+ .O(\m_payload_i[44]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair93" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[45]_i_1__1
+ (.I0(\skid_buffer_reg[46]_0 [11]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[45] ),
+ .O(\m_payload_i[45]_i_1__1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \m_payload_i[46]_i_1
+ (.I0(s_axi_rready),
+ .I1(m_valid_i_reg_0),
+ .O(p_1_in));
+ (* SOFT_HLUTNM = "soft_lutpair92" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[46]_i_2
+ (.I0(\skid_buffer_reg[46]_0 [12]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[46] ),
+ .O(\m_payload_i[46]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair113" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[4]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [4]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[4] ),
+ .O(\m_payload_i[4]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair112" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[5]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [5]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[5] ),
+ .O(\m_payload_i[5]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair112" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[6]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [6]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[6] ),
+ .O(\m_payload_i[6]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair111" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[7]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [7]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[7] ),
+ .O(\m_payload_i[7]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair111" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[8]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [8]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[8] ),
+ .O(\m_payload_i[8]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair110" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_payload_i[9]_i_1__2
+ (.I0(\skid_buffer_reg[33]_0 [9]),
+ .I1(s_ready_i_reg_0),
+ .I2(\skid_buffer_reg_n_0_[9] ),
+ .O(\m_payload_i[9]_i_1__2_n_0 ));
+ FDRE \m_payload_i_reg[0]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[0]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [0]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[10]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[10]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [10]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[11]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[11]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [11]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[12]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[12]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [12]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[13]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[13]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [13]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[14]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[14]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [14]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[15]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[15]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [15]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[16]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[16]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [16]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[17]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[17]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [17]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[18]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[18]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [18]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[19]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[19]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [19]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[1]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[1]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [1]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[20]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[20]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [20]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[21]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[21]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [21]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[22]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[22]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [22]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[23]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[23]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [23]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[24]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[24]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [24]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[25]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[25]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [25]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[26]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[26]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [26]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[27]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[27]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [27]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[28]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[28]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [28]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[29]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[29]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [29]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[2]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[2]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [2]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[30]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[30]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [30]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[31]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[31]_i_1__0_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [31]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[32]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[32]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [32]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[33]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[33]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [33]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[34]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[34]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [34]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[35]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[35]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [35]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[36]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[36]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [36]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[37]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[37]_i_1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [37]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[38]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[38]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [38]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[39]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[39]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [39]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[3]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[3]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [3]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[40]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[40]_i_1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [40]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[41]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[41]_i_1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [41]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[42]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[42]_i_1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [42]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[43]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[43]_i_1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [43]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[44]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[44]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [44]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[45]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[45]_i_1__1_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [45]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[46]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[46]_i_2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [46]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[4]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[4]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [4]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[5]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[5]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [5]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[6]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[6]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [6]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[7]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[7]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [7]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[8]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[8]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [8]),
+ .R(1'b0));
+ FDRE \m_payload_i_reg[9]
+ (.C(aclk),
+ .CE(p_1_in),
+ .D(\m_payload_i[9]_i_1__2_n_0 ),
+ .Q(\m_payload_i_reg[46]_0 [9]),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hFF4F))
+ m_valid_i_i_1
+ (.I0(s_axi_rready),
+ .I1(m_valid_i_reg_0),
+ .I2(s_ready_i_reg_0),
+ .I3(si_rs_rvalid),
+ .O(m_valid_i0));
+ FDRE #(
+ .INIT(1'b0))
+ m_valid_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_valid_i0),
+ .Q(m_valid_i_reg_0),
+ .R(m_valid_i_reg_1));
+ LUT4 #(
+ .INIT(16'hFF4F))
+ s_ready_i_i_1
+ (.I0(si_rs_rvalid),
+ .I1(s_ready_i_reg_0),
+ .I2(m_valid_i_reg_0),
+ .I3(s_axi_rready),
+ .O(s_ready_i0));
+ FDRE #(
+ .INIT(1'b0))
+ s_ready_i_reg
+ (.C(aclk),
+ .CE(1'b1),
+ .D(s_ready_i0),
+ .Q(s_ready_i_reg_0),
+ .R(s_ready_i_reg_1));
+ FDRE \skid_buffer_reg[0]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [0]),
+ .Q(\skid_buffer_reg_n_0_[0] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[10]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [10]),
+ .Q(\skid_buffer_reg_n_0_[10] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[11]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [11]),
+ .Q(\skid_buffer_reg_n_0_[11] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[12]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [12]),
+ .Q(\skid_buffer_reg_n_0_[12] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[13]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [13]),
+ .Q(\skid_buffer_reg_n_0_[13] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[14]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [14]),
+ .Q(\skid_buffer_reg_n_0_[14] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[15]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [15]),
+ .Q(\skid_buffer_reg_n_0_[15] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[16]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [16]),
+ .Q(\skid_buffer_reg_n_0_[16] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[17]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [17]),
+ .Q(\skid_buffer_reg_n_0_[17] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[18]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [18]),
+ .Q(\skid_buffer_reg_n_0_[18] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[19]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [19]),
+ .Q(\skid_buffer_reg_n_0_[19] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[1]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [1]),
+ .Q(\skid_buffer_reg_n_0_[1] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[20]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [20]),
+ .Q(\skid_buffer_reg_n_0_[20] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[21]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [21]),
+ .Q(\skid_buffer_reg_n_0_[21] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[22]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [22]),
+ .Q(\skid_buffer_reg_n_0_[22] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[23]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [23]),
+ .Q(\skid_buffer_reg_n_0_[23] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[24]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [24]),
+ .Q(\skid_buffer_reg_n_0_[24] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[25]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [25]),
+ .Q(\skid_buffer_reg_n_0_[25] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[26]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [26]),
+ .Q(\skid_buffer_reg_n_0_[26] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[27]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [27]),
+ .Q(\skid_buffer_reg_n_0_[27] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[28]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [28]),
+ .Q(\skid_buffer_reg_n_0_[28] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[29]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [29]),
+ .Q(\skid_buffer_reg_n_0_[29] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[2]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [2]),
+ .Q(\skid_buffer_reg_n_0_[2] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[30]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [30]),
+ .Q(\skid_buffer_reg_n_0_[30] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[31]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [31]),
+ .Q(\skid_buffer_reg_n_0_[31] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[32]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [32]),
+ .Q(\skid_buffer_reg_n_0_[32] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[33]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [33]),
+ .Q(\skid_buffer_reg_n_0_[33] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[34]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [0]),
+ .Q(\skid_buffer_reg_n_0_[34] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[35]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [1]),
+ .Q(\skid_buffer_reg_n_0_[35] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[36]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [2]),
+ .Q(\skid_buffer_reg_n_0_[36] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[37]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [3]),
+ .Q(\skid_buffer_reg_n_0_[37] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[38]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [4]),
+ .Q(\skid_buffer_reg_n_0_[38] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[39]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [5]),
+ .Q(\skid_buffer_reg_n_0_[39] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[3]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [3]),
+ .Q(\skid_buffer_reg_n_0_[3] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[40]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [6]),
+ .Q(\skid_buffer_reg_n_0_[40] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[41]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [7]),
+ .Q(\skid_buffer_reg_n_0_[41] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[42]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [8]),
+ .Q(\skid_buffer_reg_n_0_[42] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[43]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [9]),
+ .Q(\skid_buffer_reg_n_0_[43] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[44]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [10]),
+ .Q(\skid_buffer_reg_n_0_[44] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[45]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [11]),
+ .Q(\skid_buffer_reg_n_0_[45] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[46]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[46]_0 [12]),
+ .Q(\skid_buffer_reg_n_0_[46] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[4]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [4]),
+ .Q(\skid_buffer_reg_n_0_[4] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[5]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [5]),
+ .Q(\skid_buffer_reg_n_0_[5] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[6]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [6]),
+ .Q(\skid_buffer_reg_n_0_[6] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[7]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [7]),
+ .Q(\skid_buffer_reg_n_0_[7] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[8]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [8]),
+ .Q(\skid_buffer_reg_n_0_[8] ),
+ .R(1'b0));
+ FDRE \skid_buffer_reg[9]
+ (.C(aclk),
+ .CE(s_ready_i_reg_0),
+ .D(\skid_buffer_reg[33]_0 [9]),
+ .Q(\skid_buffer_reg_n_0_[9] ),
+ .R(1'b0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.vhdl
new file mode 100644
index 0000000..143af30
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_sim_netlist.vhdl
@@ -0,0 +1,14945 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Mon Oct 14 17:17:37 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim -rename_top TopLevel_auto_pc_0 -prefix
+-- TopLevel_auto_pc_0_ TopLevel_auto_pc_0_sim_netlist.vhdl
+-- Design : TopLevel_auto_pc_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd is
+ port (
+ incr_next_pending : out STD_LOGIC;
+ sel_first_reg_0 : out STD_LOGIC;
+ \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]\ : out STD_LOGIC;
+ \axlen_cnt_reg[2]_0\ : out STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg_1 : out STD_LOGIC;
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_reg_2 : in STD_LOGIC;
+ sel_first_i : in STD_LOGIC;
+ \axlen_cnt_reg[2]_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
+ wrap_next_pending : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ next_pending_r_reg_0 : in STD_LOGIC;
+ \next\ : in STD_LOGIC;
+ \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ si_rs_awvalid : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC;
+ axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ m_axi_awaddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_awaddr[0]_0\ : in STD_LOGIC;
+ sel_first : in STD_LOGIC;
+ \axlen_cnt_reg[4]_0\ : in STD_LOGIC;
+ \axlen_cnt_reg[8]_0\ : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd is
+ signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_15_n_0\ : STD_LOGIC;
+ signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[10]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[6]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[7]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[8]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[9]\ : STD_LOGIC;
+ signal axlen_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
+ signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[7]_i_1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[8]_i_2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[8]_i_3_n_0\ : STD_LOGIC;
+ signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC;
+ signal \^incr_next_pending\ : STD_LOGIC;
+ signal m_axi_awaddr_0_sn_1 : STD_LOGIC;
+ signal next_pending_r_i_3_n_0 : STD_LOGIC;
+ signal next_pending_r_i_6_n_0 : STD_LOGIC;
+ signal next_pending_r_i_7_n_0 : STD_LOGIC;
+ signal next_pending_r_i_8_n_0 : STD_LOGIC;
+ signal next_pending_r_reg_n_0 : STD_LOGIC;
+ signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal \^sel_first_reg_0\ : STD_LOGIC;
+ signal \^sel_first_reg_1\ : STD_LOGIC;
+ signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair123";
+ attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair123";
+ attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair122";
+ attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair124";
+ attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair125";
+ attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair126";
+ attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair121";
+ attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair125";
+ attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair122";
+ attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair126";
+ attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair124";
+ attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair121";
+ attribute SOFT_HLUTNM of \axlen_cnt[1]_i_1__0\ : label is "soft_lutpair118";
+ attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair120";
+ attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair120";
+ attribute SOFT_HLUTNM of \axlen_cnt[8]_i_2\ : label is "soft_lutpair119";
+ attribute SOFT_HLUTNM of next_pending_r_i_7 : label is "soft_lutpair118";
+ attribute SOFT_HLUTNM of next_pending_r_i_8 : label is "soft_lutpair119";
+begin
+ \axaddr_incr_reg[11]_0\(0) <= \^axaddr_incr_reg[11]_0\(0);
+ \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\;
+ incr_next_pending <= \^incr_next_pending\;
+ m_axi_awaddr_0_sn_1 <= m_axi_awaddr_0_sp_1;
+ sel_first_reg_0 <= \^sel_first_reg_0\;
+ sel_first_reg_1 <= \^sel_first_reg_1\;
+\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(0),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3_n_7\,
+ O => p_1_in(0)
+ );
+\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(10),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4_n_5\,
+ O => p_1_in(10)
+ );
+\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^sel_first_reg_0\,
+ I1 => \next\,
+ O => \axaddr_incr[11]_i_1_n_0\
+ );
+\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(11),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4_n_4\,
+ O => p_1_in(11)
+ );
+\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(1),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3_n_6\,
+ O => p_1_in(1)
+ );
+\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(2),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3_n_5\,
+ O => p_1_in(2)
+ );
+\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(3),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3_n_4\,
+ O => p_1_in(3)
+ );
+\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"060A"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(1),
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ I3 => \next\,
+ O => S(1)
+ );
+\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0102"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(0),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ I3 => \next\,
+ O => S(0)
+ );
+\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ O => \axaddr_incr[3]_i_12_n_0\
+ );
+\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[2]\,
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_incr[3]_i_13_n_0\
+ );
+\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[1]\,
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ O => \axaddr_incr[3]_i_14_n_0\
+ );
+\axaddr_incr[3]_i_15\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A9"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[0]\,
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_incr[3]_i_15_n_0\
+ );
+\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6AAA"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(3),
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ I3 => \next\,
+ O => S(3)
+ );
+\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"262A"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(2),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ I3 => \next\,
+ O => S(2)
+ );
+\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(4),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3_n_7\,
+ O => p_1_in(4)
+ );
+\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(5),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3_n_6\,
+ O => p_1_in(5)
+ );
+\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(6),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3_n_5\,
+ O => p_1_in(6)
+ );
+\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(7),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3_n_4\,
+ O => p_1_in(7)
+ );
+\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(8),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4_n_7\,
+ O => p_1_in(8)
+ );
+\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => axaddr_incr(9),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4_n_6\,
+ O => p_1_in(9)
+ );
+\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(0),
+ Q => \axaddr_incr_reg_n_0_[0]\,
+ R => '0'
+ );
+\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(10),
+ Q => \axaddr_incr_reg_n_0_[10]\,
+ R => '0'
+ );
+\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(11),
+ Q => \^axaddr_incr_reg[11]_0\(0),
+ R => '0'
+ );
+\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[7]_i_3_n_0\,
+ CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
+ CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
+ CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
+ O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
+ O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
+ O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
+ S(3) => \^axaddr_incr_reg[11]_0\(0),
+ S(2) => \axaddr_incr_reg_n_0_[10]\,
+ S(1) => \axaddr_incr_reg_n_0_[9]\,
+ S(0) => \axaddr_incr_reg_n_0_[8]\
+ );
+\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(1),
+ Q => \axaddr_incr_reg_n_0_[1]\,
+ R => '0'
+ );
+\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(2),
+ Q => \axaddr_incr_reg_n_0_[2]\,
+ R => '0'
+ );
+\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(3),
+ Q => \axaddr_incr_reg_n_0_[3]\,
+ R => '0'
+ );
+\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
+ CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
+ CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
+ CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
+ CYINIT => '0',
+ DI(3) => \axaddr_incr_reg_n_0_[3]\,
+ DI(2) => \axaddr_incr_reg_n_0_[2]\,
+ DI(1) => \axaddr_incr_reg_n_0_[1]\,
+ DI(0) => \axaddr_incr_reg_n_0_[0]\,
+ O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
+ O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
+ O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
+ O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
+ S(3) => \axaddr_incr[3]_i_12_n_0\,
+ S(2) => \axaddr_incr[3]_i_13_n_0\,
+ S(1) => \axaddr_incr[3]_i_14_n_0\,
+ S(0) => \axaddr_incr[3]_i_15_n_0\
+ );
+\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(4),
+ Q => \axaddr_incr_reg_n_0_[4]\,
+ R => '0'
+ );
+\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(5),
+ Q => \axaddr_incr_reg_n_0_[5]\,
+ R => '0'
+ );
+\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(6),
+ Q => \axaddr_incr_reg_n_0_[6]\,
+ R => '0'
+ );
+\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(7),
+ Q => \axaddr_incr_reg_n_0_[7]\,
+ R => '0'
+ );
+\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[3]_i_3_n_0\,
+ CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
+ CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
+ CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
+ CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
+ O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
+ O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
+ O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
+ S(3) => \axaddr_incr_reg_n_0_[7]\,
+ S(2) => \axaddr_incr_reg_n_0_[6]\,
+ S(1) => \axaddr_incr_reg_n_0_[5]\,
+ S(0) => \axaddr_incr_reg_n_0_[4]\
+ );
+\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(8),
+ Q => \axaddr_incr_reg_n_0_[8]\,
+ R => '0'
+ );
+\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr[11]_i_1_n_0\,
+ D => p_1_in(9),
+ Q => \axaddr_incr_reg_n_0_[9]\,
+ R => '0'
+ );
+\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"444F444444444444"
+ )
+ port map (
+ I0 => axlen_cnt(0),
+ I1 => \^axlen_cnt_reg[2]_0\,
+ I2 => \axlen_cnt_reg[0]_0\(1),
+ I3 => \axlen_cnt_reg[0]_0\(0),
+ I4 => si_rs_awvalid,
+ I5 => \axlen_cnt_reg[2]_1\(15),
+ O => \axlen_cnt[0]_i_1__0_n_0\
+ );
+\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF909090"
+ )
+ port map (
+ I0 => axlen_cnt(0),
+ I1 => axlen_cnt(1),
+ I2 => \^axlen_cnt_reg[2]_0\,
+ I3 => E(0),
+ I4 => \axlen_cnt_reg[2]_1\(16),
+ O => \axlen_cnt[1]_i_1__0_n_0\
+ );
+\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFE100E100E100"
+ )
+ port map (
+ I0 => axlen_cnt(1),
+ I1 => axlen_cnt(0),
+ I2 => axlen_cnt(2),
+ I3 => \^axlen_cnt_reg[2]_0\,
+ I4 => E(0),
+ I5 => \axlen_cnt_reg[2]_1\(17),
+ O => \axlen_cnt[2]_i_1__0_n_0\
+ );
+\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFE010000"
+ )
+ port map (
+ I0 => axlen_cnt(2),
+ I1 => axlen_cnt(0),
+ I2 => axlen_cnt(1),
+ I3 => axlen_cnt(3),
+ I4 => \^axlen_cnt_reg[2]_0\,
+ I5 => \axlen_cnt_reg[3]_0\,
+ O => \axlen_cnt[3]_i_2_n_0\
+ );
+\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFE0001"
+ )
+ port map (
+ I0 => axlen_cnt(3),
+ I1 => axlen_cnt(1),
+ I2 => axlen_cnt(0),
+ I3 => axlen_cnt(2),
+ I4 => axlen_cnt(4),
+ O => \axlen_cnt[4]_i_1__0_n_0\
+ );
+\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFE00000001"
+ )
+ port map (
+ I0 => axlen_cnt(4),
+ I1 => axlen_cnt(2),
+ I2 => axlen_cnt(0),
+ I3 => axlen_cnt(1),
+ I4 => axlen_cnt(3),
+ I5 => axlen_cnt(5),
+ O => \axlen_cnt[5]_i_1_n_0\
+ );
+\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => \axlen_cnt[8]_i_3_n_0\,
+ I1 => axlen_cnt(6),
+ O => \axlen_cnt[6]_i_1_n_0\
+ );
+\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"E1"
+ )
+ port map (
+ I0 => axlen_cnt(6),
+ I1 => \axlen_cnt[8]_i_3_n_0\,
+ I2 => axlen_cnt(7),
+ O => \axlen_cnt[7]_i_1_n_0\
+ );
+\axlen_cnt[8]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE01"
+ )
+ port map (
+ I0 => axlen_cnt(7),
+ I1 => \axlen_cnt[8]_i_3_n_0\,
+ I2 => axlen_cnt(6),
+ I3 => axlen_cnt(8),
+ O => \axlen_cnt[8]_i_2_n_0\
+ );
+\axlen_cnt[8]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFFE"
+ )
+ port map (
+ I0 => axlen_cnt(4),
+ I1 => axlen_cnt(2),
+ I2 => axlen_cnt(0),
+ I3 => axlen_cnt(1),
+ I4 => axlen_cnt(3),
+ I5 => axlen_cnt(5),
+ O => \axlen_cnt[8]_i_3_n_0\
+ );
+\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[0]_i_1__0_n_0\,
+ Q => axlen_cnt(0),
+ R => '0'
+ );
+\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[1]_i_1__0_n_0\,
+ Q => axlen_cnt(1),
+ R => '0'
+ );
+\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[2]_i_1__0_n_0\,
+ Q => axlen_cnt(2),
+ R => '0'
+ );
+\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[3]_i_2_n_0\,
+ Q => axlen_cnt(3),
+ R => '0'
+ );
+\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[4]_i_1__0_n_0\,
+ Q => axlen_cnt(4),
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[5]_i_1_n_0\,
+ Q => axlen_cnt(5),
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[6]_i_1_n_0\,
+ Q => axlen_cnt(6),
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[7]_i_1_n_0\,
+ Q => axlen_cnt(7),
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[8]_i_2_n_0\,
+ Q => axlen_cnt(8),
+ R => \axlen_cnt_reg[8]_0\
+ );
+\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[0]\,
+ I4 => \axlen_cnt_reg[2]_1\(0),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(0)
+ );
+\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(10),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[10]\,
+ I4 => \axlen_cnt_reg[2]_1\(10),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(10)
+ );
+\m_axi_awaddr[11]_INST_0_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB0B"
+ )
+ port map (
+ I0 => \^sel_first_reg_0\,
+ I1 => \axlen_cnt_reg[2]_1\(13),
+ I2 => \axlen_cnt_reg[2]_1\(14),
+ I3 => sel_first,
+ O => \^sel_first_reg_1\
+ );
+\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[1]\,
+ I4 => \axlen_cnt_reg[2]_1\(1),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(1)
+ );
+\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[2]\,
+ I4 => \axlen_cnt_reg[2]_1\(2),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(2)
+ );
+\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[3]\,
+ I4 => \axlen_cnt_reg[2]_1\(3),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(3)
+ );
+\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[4]\,
+ I4 => \axlen_cnt_reg[2]_1\(4),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(4)
+ );
+\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(5),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[5]\,
+ I4 => \axlen_cnt_reg[2]_1\(5),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(5)
+ );
+\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(6),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[6]\,
+ I4 => \axlen_cnt_reg[2]_1\(6),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(6)
+ );
+\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(7),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[7]\,
+ I4 => \axlen_cnt_reg[2]_1\(7),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(7)
+ );
+\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(8),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[8]\,
+ I4 => \axlen_cnt_reg[2]_1\(8),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(8)
+ );
+\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(9),
+ I1 => m_axi_awaddr_0_sn_1,
+ I2 => \m_axi_awaddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[9]\,
+ I4 => \axlen_cnt_reg[2]_1\(9),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_awaddr(9)
+ );
+\next_pending_r_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFF0F2F2F0F0F2F2"
+ )
+ port map (
+ I0 => next_pending_r_reg_n_0,
+ I1 => E(0),
+ I2 => next_pending_r_reg_0,
+ I3 => next_pending_r_i_3_n_0,
+ I4 => \next\,
+ I5 => \^axlen_cnt_reg[2]_0\,
+ O => \^incr_next_pending\
+ );
+next_pending_r_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFEEF"
+ )
+ port map (
+ I0 => next_pending_r_i_6_n_0,
+ I1 => axlen_cnt(7),
+ I2 => \axlen_cnt[8]_i_3_n_0\,
+ I3 => axlen_cnt(6),
+ I4 => axlen_cnt(8),
+ I5 => next_pending_r_i_7_n_0,
+ O => next_pending_r_i_3_n_0
+ );
+next_pending_r_i_5: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000FFFFFFFE"
+ )
+ port map (
+ I0 => next_pending_r_i_8_n_0,
+ I1 => axlen_cnt(2),
+ I2 => axlen_cnt(1),
+ I3 => axlen_cnt(4),
+ I4 => axlen_cnt(3),
+ I5 => E(0),
+ O => \^axlen_cnt_reg[2]_0\
+ );
+next_pending_r_i_6: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFEEEB"
+ )
+ port map (
+ I0 => axlen_cnt(4),
+ I1 => axlen_cnt(2),
+ I2 => axlen_cnt(0),
+ I3 => axlen_cnt(1),
+ I4 => axlen_cnt(3),
+ I5 => axlen_cnt(5),
+ O => next_pending_r_i_6_n_0
+ );
+next_pending_r_i_7: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => axlen_cnt(1),
+ I1 => axlen_cnt(0),
+ O => next_pending_r_i_7_n_0
+ );
+next_pending_r_i_8: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => axlen_cnt(6),
+ I1 => axlen_cnt(5),
+ I2 => axlen_cnt(8),
+ I3 => axlen_cnt(7),
+ O => next_pending_r_i_8_n_0
+ );
+next_pending_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \^incr_next_pending\,
+ Q => next_pending_r_reg_n_0,
+ R => '0'
+ );
+s_axburst_eq0_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BA8A"
+ )
+ port map (
+ I0 => \^incr_next_pending\,
+ I1 => sel_first_i,
+ I2 => \axlen_cnt_reg[2]_1\(14),
+ I3 => wrap_next_pending,
+ O => \m_payload_i_reg[39]\
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_reg_2,
+ Q => \^sel_first_reg_0\,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2 is
+ port (
+ incr_next_pending : out STD_LOGIC;
+ sel_first_reg_0 : out STD_LOGIC;
+ \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]\ : out STD_LOGIC;
+ \axlen_cnt_reg[2]_0\ : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg_1 : out STD_LOGIC;
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_reg_2 : in STD_LOGIC;
+ sel_first_i : in STD_LOGIC;
+ \axlen_cnt_reg[2]_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
+ wrap_next_pending : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ next_pending_r_reg_0 : in STD_LOGIC;
+ r_push : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC;
+ \axaddr_incr_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ m_axi_araddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_araddr[0]_0\ : in STD_LOGIC;
+ \m_axi_araddr[0]_1\ : in STD_LOGIC;
+ \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ si_rs_arvalid : in STD_LOGIC;
+ \axlen_cnt_reg[4]_0\ : in STD_LOGIC;
+ \axlen_cnt_reg[8]_0\ : in STD_LOGIC;
+ \axaddr_incr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_arready : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_19_b2s_incr_cmd";
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2 is
+ signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_15_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
+ signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[10]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[6]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[7]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[8]\ : STD_LOGIC;
+ signal \axaddr_incr_reg_n_0_[9]\ : STD_LOGIC;
+ signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[7]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[8]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[8]_i_3__0_n_0\ : STD_LOGIC;
+ signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[8]\ : STD_LOGIC;
+ signal \^incr_next_pending\ : STD_LOGIC;
+ signal m_axi_araddr_0_sn_1 : STD_LOGIC;
+ signal \next_pending_r_i_3__0_n_0\ : STD_LOGIC;
+ signal \next_pending_r_i_5__0_n_0\ : STD_LOGIC;
+ signal \next_pending_r_i_6__0_n_0\ : STD_LOGIC;
+ signal \next_pending_r_i_7__0_n_0\ : STD_LOGIC;
+ signal next_pending_r_reg_n_0 : STD_LOGIC;
+ signal \^sel_first_reg_0\ : STD_LOGIC;
+ signal \^sel_first_reg_1\ : STD_LOGIC;
+ signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \axlen_cnt[1]_i_1__2\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \axlen_cnt[8]_i_2__0\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \next_pending_r_i_6__0\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \next_pending_r_i_7__0\ : label is "soft_lutpair7";
+begin
+ \axaddr_incr_reg[11]_0\(0) <= \^axaddr_incr_reg[11]_0\(0);
+ \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\;
+ incr_next_pending <= \^incr_next_pending\;
+ m_axi_araddr_0_sn_1 <= m_axi_araddr_0_sp_1;
+ sel_first_reg_0 <= \^sel_first_reg_0\;
+ sel_first_reg_1 <= \^sel_first_reg_1\;
+\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[3]_0\(0),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
+ O => \axaddr_incr[0]_i_1__0_n_0\
+ );
+\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[11]_1\(2),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
+ O => \axaddr_incr[10]_i_1__0_n_0\
+ );
+\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[11]_1\(3),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
+ O => \axaddr_incr[11]_i_2__0_n_0\
+ );
+\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[3]_0\(1),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
+ O => \axaddr_incr[1]_i_1__0_n_0\
+ );
+\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[3]_0\(2),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
+ O => \axaddr_incr[2]_i_1__0_n_0\
+ );
+\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"060A0A0A0A0A0A0A"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(1),
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ I3 => m_axi_arready,
+ I4 => \axlen_cnt_reg[0]_0\(1),
+ I5 => \axlen_cnt_reg[0]_0\(0),
+ O => S(1)
+ );
+\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0102020202020202"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(0),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ I3 => m_axi_arready,
+ I4 => \axlen_cnt_reg[0]_0\(1),
+ I5 => \axlen_cnt_reg[0]_0\(0),
+ O => S(0)
+ );
+\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ O => \axaddr_incr[3]_i_12_n_0\
+ );
+\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[2]\,
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_incr[3]_i_13_n_0\
+ );
+\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[1]\,
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ O => \axaddr_incr[3]_i_14_n_0\
+ );
+\axaddr_incr[3]_i_15\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A9"
+ )
+ port map (
+ I0 => \axaddr_incr_reg_n_0_[0]\,
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_incr[3]_i_15_n_0\
+ );
+\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[3]_0\(3),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
+ O => \axaddr_incr[3]_i_1__0_n_0\
+ );
+\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6AAAAAAAAAAAAAAA"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(3),
+ I1 => \axlen_cnt_reg[2]_1\(11),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ I3 => m_axi_arready,
+ I4 => \axlen_cnt_reg[0]_0\(1),
+ I5 => \axlen_cnt_reg[0]_0\(0),
+ O => S(3)
+ );
+\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"262A2A2A2A2A2A2A"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[2]_1\(2),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(11),
+ I3 => m_axi_arready,
+ I4 => \axlen_cnt_reg[0]_0\(1),
+ I5 => \axlen_cnt_reg[0]_0\(0),
+ O => S(2)
+ );
+\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[7]_0\(0),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
+ O => \axaddr_incr[4]_i_1__0_n_0\
+ );
+\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[7]_0\(1),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
+ O => \axaddr_incr[5]_i_1__0_n_0\
+ );
+\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[7]_0\(2),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
+ O => \axaddr_incr[6]_i_1__0_n_0\
+ );
+\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[7]_0\(3),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
+ O => \axaddr_incr[7]_i_1__0_n_0\
+ );
+\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[11]_1\(0),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
+ O => \axaddr_incr[8]_i_1__0_n_0\
+ );
+\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[11]_1\(1),
+ I1 => \^sel_first_reg_0\,
+ I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
+ O => \axaddr_incr[9]_i_1__0_n_0\
+ );
+\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[0]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[0]\,
+ R => '0'
+ );
+\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[10]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[10]\,
+ R => '0'
+ );
+\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[11]_i_2__0_n_0\,
+ Q => \^axaddr_incr_reg[11]_0\(0),
+ R => '0'
+ );
+\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
+ CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
+ CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
+ CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
+ O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
+ O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
+ O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
+ S(3) => \^axaddr_incr_reg[11]_0\(0),
+ S(2) => \axaddr_incr_reg_n_0_[10]\,
+ S(1) => \axaddr_incr_reg_n_0_[9]\,
+ S(0) => \axaddr_incr_reg_n_0_[8]\
+ );
+\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[1]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[1]\,
+ R => '0'
+ );
+\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[2]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[2]\,
+ R => '0'
+ );
+\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[3]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[3]\,
+ R => '0'
+ );
+\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
+ CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
+ CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
+ CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
+ CYINIT => '0',
+ DI(3) => \axaddr_incr_reg_n_0_[3]\,
+ DI(2) => \axaddr_incr_reg_n_0_[2]\,
+ DI(1) => \axaddr_incr_reg_n_0_[1]\,
+ DI(0) => \axaddr_incr_reg_n_0_[0]\,
+ O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
+ O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
+ O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
+ O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
+ S(3) => \axaddr_incr[3]_i_12_n_0\,
+ S(2) => \axaddr_incr[3]_i_13_n_0\,
+ S(1) => \axaddr_incr[3]_i_14_n_0\,
+ S(0) => \axaddr_incr[3]_i_15_n_0\
+ );
+\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[4]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[4]\,
+ R => '0'
+ );
+\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[5]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[5]\,
+ R => '0'
+ );
+\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[6]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[6]\,
+ R => '0'
+ );
+\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[7]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[7]\,
+ R => '0'
+ );
+\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
+ CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
+ CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
+ CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
+ CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
+ O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
+ O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
+ O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
+ S(3) => \axaddr_incr_reg_n_0_[7]\,
+ S(2) => \axaddr_incr_reg_n_0_[6]\,
+ S(1) => \axaddr_incr_reg_n_0_[5]\,
+ S(0) => \axaddr_incr_reg_n_0_[4]\
+ );
+\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[8]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[8]\,
+ R => '0'
+ );
+\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_incr_reg[0]_0\(0),
+ D => \axaddr_incr[9]_i_1__0_n_0\,
+ Q => \axaddr_incr_reg_n_0_[9]\,
+ R => '0'
+ );
+\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"4F444444"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[0]\,
+ I1 => \^axlen_cnt_reg[2]_0\,
+ I2 => \axlen_cnt_reg[0]_0\(1),
+ I3 => si_rs_arvalid,
+ I4 => \axlen_cnt_reg[2]_1\(15),
+ O => \axlen_cnt[0]_i_1__1_n_0\
+ );
+\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF909090"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[0]\,
+ I1 => \axlen_cnt_reg_n_0_[1]\,
+ I2 => \^axlen_cnt_reg[2]_0\,
+ I3 => E(0),
+ I4 => \axlen_cnt_reg[2]_1\(16),
+ O => \axlen_cnt[1]_i_1__2_n_0\
+ );
+\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFE100E100E100"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[1]\,
+ I1 => \axlen_cnt_reg_n_0_[0]\,
+ I2 => \axlen_cnt_reg_n_0_[2]\,
+ I3 => \^axlen_cnt_reg[2]_0\,
+ I4 => E(0),
+ I5 => \axlen_cnt_reg[2]_1\(17),
+ O => \axlen_cnt[2]_i_1__2_n_0\
+ );
+\axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFE010000"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[2]\,
+ I1 => \axlen_cnt_reg_n_0_[0]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[3]\,
+ I4 => \^axlen_cnt_reg[2]_0\,
+ I5 => \axlen_cnt_reg[3]_0\,
+ O => \axlen_cnt[3]_i_2__1_n_0\
+ );
+\axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFE0001"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg_n_0_[1]\,
+ I2 => \axlen_cnt_reg_n_0_[0]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => \axlen_cnt_reg_n_0_[4]\,
+ O => \axlen_cnt[4]_i_1__2_n_0\
+ );
+\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFE00000001"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[4]\,
+ I1 => \axlen_cnt_reg_n_0_[2]\,
+ I2 => \axlen_cnt_reg_n_0_[0]\,
+ I3 => \axlen_cnt_reg_n_0_[1]\,
+ I4 => \axlen_cnt_reg_n_0_[3]\,
+ I5 => \axlen_cnt_reg_n_0_[5]\,
+ O => \axlen_cnt[5]_i_1__0_n_0\
+ );
+\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => \axlen_cnt[8]_i_3__0_n_0\,
+ I1 => \axlen_cnt_reg_n_0_[6]\,
+ O => \axlen_cnt[6]_i_1__0_n_0\
+ );
+\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"E1"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[6]\,
+ I1 => \axlen_cnt[8]_i_3__0_n_0\,
+ I2 => \axlen_cnt_reg_n_0_[7]\,
+ O => \axlen_cnt[7]_i_1__0_n_0\
+ );
+\axlen_cnt[8]_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE01"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[7]\,
+ I1 => \axlen_cnt[8]_i_3__0_n_0\,
+ I2 => \axlen_cnt_reg_n_0_[6]\,
+ I3 => \axlen_cnt_reg_n_0_[8]\,
+ O => \axlen_cnt[8]_i_2__0_n_0\
+ );
+\axlen_cnt[8]_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFFE"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[4]\,
+ I1 => \axlen_cnt_reg_n_0_[2]\,
+ I2 => \axlen_cnt_reg_n_0_[0]\,
+ I3 => \axlen_cnt_reg_n_0_[1]\,
+ I4 => \axlen_cnt_reg_n_0_[3]\,
+ I5 => \axlen_cnt_reg_n_0_[5]\,
+ O => \axlen_cnt[8]_i_3__0_n_0\
+ );
+\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[0]_i_1__1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[0]\,
+ R => '0'
+ );
+\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[1]_i_1__2_n_0\,
+ Q => \axlen_cnt_reg_n_0_[1]\,
+ R => '0'
+ );
+\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[2]_i_1__2_n_0\,
+ Q => \axlen_cnt_reg_n_0_[2]\,
+ R => '0'
+ );
+\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[3]_i_2__1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[3]\,
+ R => '0'
+ );
+\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[4]_i_1__2_n_0\,
+ Q => \axlen_cnt_reg_n_0_[4]\,
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[5]_i_1__0_n_0\,
+ Q => \axlen_cnt_reg_n_0_[5]\,
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[6]_i_1__0_n_0\,
+ Q => \axlen_cnt_reg_n_0_[6]\,
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[7]_i_1__0_n_0\,
+ Q => \axlen_cnt_reg_n_0_[7]\,
+ R => \axlen_cnt_reg[8]_0\
+ );
+\axlen_cnt_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axlen_cnt_reg[4]_0\,
+ D => \axlen_cnt[8]_i_2__0_n_0\,
+ Q => \axlen_cnt_reg_n_0_[8]\,
+ R => \axlen_cnt_reg[8]_0\
+ );
+\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[0]\,
+ I4 => \axlen_cnt_reg[2]_1\(0),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(0)
+ );
+\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(10),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[10]\,
+ I4 => \axlen_cnt_reg[2]_1\(10),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(10)
+ );
+\m_axi_araddr[11]_INST_0_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB0B"
+ )
+ port map (
+ I0 => \^sel_first_reg_0\,
+ I1 => \axlen_cnt_reg[2]_1\(13),
+ I2 => \axlen_cnt_reg[2]_1\(14),
+ I3 => \m_axi_araddr[0]_1\,
+ O => \^sel_first_reg_1\
+ );
+\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[1]\,
+ I4 => \axlen_cnt_reg[2]_1\(1),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(1)
+ );
+\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[2]\,
+ I4 => \axlen_cnt_reg[2]_1\(2),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(2)
+ );
+\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[3]\,
+ I4 => \axlen_cnt_reg[2]_1\(3),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(3)
+ );
+\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[4]\,
+ I4 => \axlen_cnt_reg[2]_1\(4),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(4)
+ );
+\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(5),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[5]\,
+ I4 => \axlen_cnt_reg[2]_1\(5),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(5)
+ );
+\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(6),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[6]\,
+ I4 => \axlen_cnt_reg[2]_1\(6),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(6)
+ );
+\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(7),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[7]\,
+ I4 => \axlen_cnt_reg[2]_1\(7),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(7)
+ );
+\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(8),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[8]\,
+ I4 => \axlen_cnt_reg[2]_1\(8),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(8)
+ );
+\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => Q(9),
+ I1 => m_axi_araddr_0_sn_1,
+ I2 => \m_axi_araddr[0]_0\,
+ I3 => \axaddr_incr_reg_n_0_[9]\,
+ I4 => \axlen_cnt_reg[2]_1\(9),
+ I5 => \^sel_first_reg_1\,
+ O => m_axi_araddr(9)
+ );
+\next_pending_r_i_1__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFF0F0F0F2F2F2F2"
+ )
+ port map (
+ I0 => next_pending_r_reg_n_0,
+ I1 => E(0),
+ I2 => next_pending_r_reg_0,
+ I3 => \next_pending_r_i_3__0_n_0\,
+ I4 => \^axlen_cnt_reg[2]_0\,
+ I5 => r_push,
+ O => \^incr_next_pending\
+ );
+\next_pending_r_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFEEF"
+ )
+ port map (
+ I0 => \next_pending_r_i_5__0_n_0\,
+ I1 => \axlen_cnt_reg_n_0_[7]\,
+ I2 => \axlen_cnt[8]_i_3__0_n_0\,
+ I3 => \axlen_cnt_reg_n_0_[6]\,
+ I4 => \axlen_cnt_reg_n_0_[8]\,
+ I5 => \next_pending_r_i_6__0_n_0\,
+ O => \next_pending_r_i_3__0_n_0\
+ );
+next_pending_r_i_4: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000FFFFFFFE"
+ )
+ port map (
+ I0 => \next_pending_r_i_7__0_n_0\,
+ I1 => \axlen_cnt_reg_n_0_[2]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[4]\,
+ I4 => \axlen_cnt_reg_n_0_[3]\,
+ I5 => E(0),
+ O => \^axlen_cnt_reg[2]_0\
+ );
+\next_pending_r_i_5__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFEEEB"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[4]\,
+ I1 => \axlen_cnt_reg_n_0_[2]\,
+ I2 => \axlen_cnt_reg_n_0_[0]\,
+ I3 => \axlen_cnt_reg_n_0_[1]\,
+ I4 => \axlen_cnt_reg_n_0_[3]\,
+ I5 => \axlen_cnt_reg_n_0_[5]\,
+ O => \next_pending_r_i_5__0_n_0\
+ );
+\next_pending_r_i_6__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[1]\,
+ I1 => \axlen_cnt_reg_n_0_[0]\,
+ O => \next_pending_r_i_6__0_n_0\
+ );
+\next_pending_r_i_7__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[6]\,
+ I1 => \axlen_cnt_reg_n_0_[5]\,
+ I2 => \axlen_cnt_reg_n_0_[8]\,
+ I3 => \axlen_cnt_reg_n_0_[7]\,
+ O => \next_pending_r_i_7__0_n_0\
+ );
+next_pending_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \^incr_next_pending\,
+ Q => next_pending_r_reg_n_0,
+ R => '0'
+ );
+\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BA8A"
+ )
+ port map (
+ I0 => \^incr_next_pending\,
+ I1 => sel_first_i,
+ I2 => \axlen_cnt_reg[2]_1\(14),
+ I3 => wrap_next_pending,
+ O => \m_payload_i_reg[39]\
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_reg_2,
+ Q => \^sel_first_reg_0\,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm is
+ port (
+ \FSM_sequential_state_reg[1]_0\ : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_ready_i0 : out STD_LOGIC;
+ m_valid_i0 : out STD_LOGIC;
+ m_axi_arready_0 : out STD_LOGIC;
+ m_axi_arready_1 : out STD_LOGIC;
+ m_axi_arready_2 : out STD_LOGIC;
+ sel_first_i : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sel_first_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
+ D : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_arready_3 : out STD_LOGIC;
+ m_axi_arvalid : out STD_LOGIC;
+ \FSM_sequential_state_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ si_rs_arvalid : in STD_LOGIC;
+ m_axi_arready : in STD_LOGIC;
+ \axlen_cnt_reg[8]\ : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_ready_i_reg : in STD_LOGIC;
+ sel_first_reg_0 : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC;
+ \axaddr_incr_reg[0]\ : in STD_LOGIC;
+ sel_first_reg_1 : in STD_LOGIC;
+ O : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \axaddr_wrap_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \axaddr_wrap_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]_2\ : in STD_LOGIC;
+ next_pending : in STD_LOGIC;
+ r_full : in STD_LOGIC;
+ aclk : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm is
+ signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
+ signal \^m_axi_arready_3\ : STD_LOGIC;
+ signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_1\ : label is "soft_lutpair2";
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11";
+ attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_4\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \axlen_cnt[8]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair4";
+begin
+ Q(1 downto 0) <= \^q\(1 downto 0);
+ m_axi_arready_3 <= \^m_axi_arready_3\;
+\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"77F755FF"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => m_axi_arready,
+ I2 => next_pending,
+ I3 => r_full,
+ I4 => \^q\(0),
+ O => \next_state__0\(0)
+ );
+\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"DDFFDDFF0F000000"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => next_pending,
+ I2 => r_full,
+ I3 => \^q\(0),
+ I4 => si_rs_arvalid,
+ I5 => \^q\(1),
+ O => \next_state__0\(1)
+ );
+\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \next_state__0\(0),
+ Q => \^q\(0),
+ S => areset_d1
+ );
+\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \next_state__0\(1),
+ Q => \^q\(1),
+ R => areset_d1
+ );
+\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EAAA"
+ )
+ port map (
+ I0 => \axaddr_incr_reg[0]\,
+ I1 => \^q\(0),
+ I2 => \^q\(1),
+ I3 => m_axi_arready,
+ O => sel_first_reg(0)
+ );
+\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => O(0),
+ I2 => \axaddr_wrap_reg[11]\(0),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(0),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(0)
+ );
+\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[11]_1\(2),
+ I2 => \axaddr_wrap_reg[11]\(10),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(10),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(10)
+ );
+\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[11]_1\(3),
+ I2 => \axaddr_wrap_reg[11]\(11),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(11),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(11)
+ );
+\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0080"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(1),
+ I2 => m_axi_arready,
+ I3 => \axaddr_wrap_reg[11]_2\,
+ O => \axaddr_wrap[11]_i_2_n_0\
+ );
+\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \axaddr_wrap_reg[11]_2\,
+ I1 => \^q\(0),
+ I2 => \^q\(1),
+ I3 => m_axi_arready,
+ O => \axaddr_wrap[11]_i_4_n_0\
+ );
+\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => O(1),
+ I2 => \axaddr_wrap_reg[11]\(1),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(1),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(1)
+ );
+\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => O(2),
+ I2 => \axaddr_wrap_reg[11]\(2),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(2),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(2)
+ );
+\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => O(3),
+ I2 => \axaddr_wrap_reg[11]\(3),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(3),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(3)
+ );
+\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[7]\(0),
+ I2 => \axaddr_wrap_reg[11]\(4),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(4),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(4)
+ );
+\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[7]\(1),
+ I2 => \axaddr_wrap_reg[11]\(5),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(5),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(5)
+ );
+\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[7]\(2),
+ I2 => \axaddr_wrap_reg[11]\(6),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(6),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(6)
+ );
+\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[7]\(3),
+ I2 => \axaddr_wrap_reg[11]\(7),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(7),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(7)
+ );
+\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[11]_1\(0),
+ I2 => \axaddr_wrap_reg[11]\(8),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(8),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(8)
+ );
+\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF88F888F888F8"
+ )
+ port map (
+ I0 => \axaddr_wrap[11]_i_2_n_0\,
+ I1 => \axaddr_wrap_reg[11]_1\(1),
+ I2 => \axaddr_wrap_reg[11]\(9),
+ I3 => \^m_axi_arready_3\,
+ I4 => \axaddr_wrap_reg[11]_0\(9),
+ I5 => \axaddr_wrap[11]_i_4_n_0\,
+ O => D(9)
+ );
+\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A0C0"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => si_rs_arvalid,
+ I2 => \^q\(0),
+ I3 => \^q\(1),
+ O => m_axi_arready_0
+ );
+\axlen_cnt[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000C840"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_arvalid,
+ I3 => m_axi_arready,
+ I4 => \axlen_cnt_reg[8]\,
+ O => \FSM_sequential_state_reg[1]_0\
+ );
+m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(1),
+ O => m_axi_arvalid
+ );
+\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"1F"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_arvalid,
+ O => \FSM_sequential_state_reg[1]_1\(0)
+ );
+\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFE0FF"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_arvalid,
+ I3 => s_ready_i_reg,
+ I4 => s_axi_arvalid,
+ O => m_valid_i0
+ );
+r_push_r_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => \^q\(1),
+ I2 => \^q\(0),
+ O => \^m_axi_arready_3\
+ );
+\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"1FFF1F1F"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_arvalid,
+ I3 => s_axi_arvalid,
+ I4 => s_ready_i_reg,
+ O => s_ready_i0
+ );
+\sel_first_i_1__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF4FCC4CCC"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => sel_first_reg_0,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_arvalid,
+ I5 => areset_d1,
+ O => m_axi_arready_1
+ );
+\sel_first_i_1__3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF4FCC4CCC"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => \axaddr_incr_reg[0]\,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_arvalid,
+ I5 => areset_d1,
+ O => m_axi_arready_2
+ );
+\sel_first_i_1__4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF4FCC4CCC"
+ )
+ port map (
+ I0 => m_axi_arready,
+ I1 => sel_first_reg_1,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_arvalid,
+ I5 => areset_d1,
+ O => sel_first_i
+ );
+\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_arvalid,
+ O => E(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo is
+ port (
+ b_full : out STD_LOGIC;
+ addr : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ SR : out STD_LOGIC_VECTOR ( 0 to 0 );
+ bresp_push : out STD_LOGIC;
+ shandshake_r_reg : out STD_LOGIC;
+ \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ areset_d1 : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ shandshake_r : in STD_LOGIC;
+ bresp_empty : in STD_LOGIC;
+ si_rs_bvalid : in STD_LOGIC;
+ si_rs_bready : in STD_LOGIC;
+ mhandshake_r : in STD_LOGIC;
+ b_push : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ aclk : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo is
+ signal \^addr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \^bresp_push\ : STD_LOGIC;
+ signal bvalid_i21_in : STD_LOGIC;
+ signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][0]_srl4_i_3__0_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
+ signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair129";
+ attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair129";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name : string;
+ attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
+ attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_2\ : label is "soft_lutpair128";
+ attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_2__0\ : label is "soft_lutpair128";
+ attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
+begin
+ addr(1 downto 0) <= \^addr\(1 downto 0);
+ bresp_push <= \^bresp_push\;
+\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => areset_d1,
+ I1 => \^bresp_push\,
+ O => SR(0)
+ );
+bvalid_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000400FF0004"
+ )
+ port map (
+ I0 => shandshake_r,
+ I1 => bvalid_i21_in,
+ I2 => bresp_empty,
+ I3 => areset_d1,
+ I4 => si_rs_bvalid,
+ I5 => si_rs_bready,
+ O => shandshake_r_reg
+ );
+bvalid_i_i_2: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \^addr\(0),
+ I1 => \^addr\(1),
+ O => bvalid_i21_in
+ );
+\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"96"
+ )
+ port map (
+ I0 => shandshake_r,
+ I1 => b_push,
+ I2 => \^addr\(0),
+ O => \cnt_read[0]_i_1_n_0\
+ );
+\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E718"
+ )
+ port map (
+ I0 => \^addr\(0),
+ I1 => b_push,
+ I2 => shandshake_r,
+ I3 => \^addr\(1),
+ O => \cnt_read[1]_i_1_n_0\
+ );
+\cnt_read_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \cnt_read[0]_i_1_n_0\,
+ Q => \^addr\(0),
+ S => areset_d1
+ );
+\cnt_read_reg[1]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \cnt_read[1]_i_1_n_0\,
+ Q => \^addr\(1),
+ S => areset_d1
+ );
+\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(0),
+ Q => \memory_reg[3][0]_srl4_n_0\
+ );
+\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000082000082"
+ )
+ port map (
+ I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
+ I1 => Q(2),
+ I2 => \memory_reg[3][2]_srl4_n_0\,
+ I3 => Q(3),
+ I4 => \memory_reg[3][3]_srl4_n_0\,
+ I5 => \memory_reg[3][0]_srl4_i_3__0_n_0\,
+ O => \^bresp_push\
+ );
+\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^addr\(1),
+ I1 => \^addr\(0),
+ O => b_full
+ );
+\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00020202"
+ )
+ port map (
+ I0 => mhandshake_r,
+ I1 => Q(6),
+ I2 => Q(7),
+ I3 => \^addr\(1),
+ I4 => \^addr\(0),
+ O => \memory_reg[3][0]_srl4_i_2__0_n_0\
+ );
+\memory_reg[3][0]_srl4_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFF6FF6"
+ )
+ port map (
+ I0 => \memory_reg[3][1]_srl4_n_0\,
+ I1 => Q(1),
+ I2 => \memory_reg[3][0]_srl4_n_0\,
+ I3 => Q(0),
+ I4 => Q(4),
+ I5 => Q(5),
+ O => \memory_reg[3][0]_srl4_i_3__0_n_0\
+ );
+\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(6),
+ Q => \out\(2)
+ );
+\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(7),
+ Q => \out\(3)
+ );
+\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(8),
+ Q => \out\(4)
+ );
+\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(9),
+ Q => \out\(5)
+ );
+\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(10),
+ Q => \out\(6)
+ );
+\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(11),
+ Q => \out\(7)
+ );
+\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(12),
+ Q => \out\(8)
+ );
+\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(13),
+ Q => \out\(9)
+ );
+\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(14),
+ Q => \out\(10)
+ );
+\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(15),
+ Q => \out\(11)
+ );
+\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(1),
+ Q => \memory_reg[3][1]_srl4_n_0\
+ );
+\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(2),
+ Q => \memory_reg[3][2]_srl4_n_0\
+ );
+\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(3),
+ Q => \memory_reg[3][3]_srl4_n_0\
+ );
+\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(4),
+ Q => \out\(0)
+ );
+\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => \^addr\(0),
+ A1 => \^addr\(1),
+ A2 => '0',
+ A3 => '0',
+ CE => b_push,
+ CLK => aclk,
+ D => \in\(5),
+ Q => \out\(1)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0\ is
+ port (
+ m_axi_bready : out STD_LOGIC;
+ mhandshake : out STD_LOGIC;
+ bresp_empty : out STD_LOGIC;
+ \s_bresp_acc_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ mhandshake_r : in STD_LOGIC;
+ m_axi_bvalid : in STD_LOGIC;
+ bresp_push : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ aclk : in STD_LOGIC;
+ shandshake_r : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_19_b2s_simple_fifo";
+end \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0\;
+
+architecture STRUCTURE of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0\ is
+ signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair130";
+ attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair130";
+ attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair131";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
+ attribute srl_name : string;
+ attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
+ attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
+ attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
+ attribute SOFT_HLUTNM of mhandshake_r_i_1 : label is "soft_lutpair131";
+begin
+bvalid_i_i_3: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => cnt_read(0),
+ I1 => cnt_read(1),
+ O => bresp_empty
+ );
+\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"96"
+ )
+ port map (
+ I0 => shandshake_r,
+ I1 => bresp_push,
+ I2 => cnt_read(0),
+ O => \cnt_read[0]_i_1_n_0\
+ );
+\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E718"
+ )
+ port map (
+ I0 => cnt_read(0),
+ I1 => bresp_push,
+ I2 => shandshake_r,
+ I3 => cnt_read(1),
+ O => \cnt_read[1]_i_1_n_0\
+ );
+\cnt_read_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \cnt_read[0]_i_1_n_0\,
+ Q => cnt_read(0),
+ S => areset_d1
+ );
+\cnt_read_reg[1]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \cnt_read[1]_i_1_n_0\,
+ Q => cnt_read(1),
+ S => areset_d1
+ );
+m_axi_bready_INST_0: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => cnt_read(1),
+ I1 => cnt_read(0),
+ I2 => mhandshake_r,
+ O => m_axi_bready
+ );
+\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => cnt_read(0),
+ A1 => cnt_read(1),
+ A2 => '0',
+ A3 => '0',
+ CE => bresp_push,
+ CLK => aclk,
+ D => \in\(0),
+ Q => \s_bresp_acc_reg[1]\(0)
+ );
+\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000"
+ )
+ port map (
+ A0 => cnt_read(0),
+ A1 => cnt_read(1),
+ A2 => '0',
+ A3 => '0',
+ CE => bresp_push,
+ CLK => aclk,
+ D => \in\(1),
+ Q => \s_bresp_acc_reg[1]\(1)
+ );
+mhandshake_r_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4000"
+ )
+ port map (
+ I0 => mhandshake_r,
+ I1 => m_axi_bvalid,
+ I2 => cnt_read(1),
+ I3 => cnt_read(0),
+ O => mhandshake
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1\ is
+ port (
+ m_axi_rready : out STD_LOGIC;
+ wr_en0 : out STD_LOGIC;
+ rd_a_full : out STD_LOGIC;
+ a_full0 : out STD_LOGIC;
+ \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
+ \rd_en__1\ : in STD_LOGIC;
+ m_axi_rvalid : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
+ aclk : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_19_b2s_simple_fifo";
+end \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1\;
+
+architecture STRUCTURE of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1\ is
+ signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_4_n_0\ : STD_LOGIC;
+ signal cnt_read_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \^wr_en0\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_4\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair17";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name : string;
+ attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
+begin
+ wr_en0 <= \^wr_en0\;
+\FSM_sequential_state[1]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"08888080"
+ )
+ port map (
+ I0 => cnt_read_reg(4),
+ I1 => cnt_read_reg(3),
+ I2 => cnt_read_reg(1),
+ I3 => cnt_read_reg(0),
+ I4 => cnt_read_reg(2),
+ O => rd_a_full
+ );
+\cnt_read[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => cnt_read_reg(0),
+ O => \cnt_read[0]_i_1_n_0\
+ );
+\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9A65"
+ )
+ port map (
+ I0 => cnt_read_reg(0),
+ I1 => \rd_en__1\,
+ I2 => \^wr_en0\,
+ I3 => cnt_read_reg(1),
+ O => \cnt_read[1]_i_1_n_0\
+ );
+\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"BFF4400B"
+ )
+ port map (
+ I0 => \rd_en__1\,
+ I1 => \^wr_en0\,
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(1),
+ I4 => cnt_read_reg(2),
+ O => \cnt_read[2]_i_1_n_0\
+ );
+\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BFFF4000FFF4000B"
+ )
+ port map (
+ I0 => \rd_en__1\,
+ I1 => \^wr_en0\,
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(1),
+ I4 => cnt_read_reg(3),
+ I5 => cnt_read_reg(2),
+ O => \cnt_read[3]_i_1_n_0\
+ );
+\cnt_read[4]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7E81"
+ )
+ port map (
+ I0 => \cnt_read[4]_i_4_n_0\,
+ I1 => cnt_read_reg(2),
+ I2 => cnt_read_reg(3),
+ I3 => cnt_read_reg(4),
+ O => \cnt_read[4]_i_2_n_0\
+ );
+\cnt_read[4]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"5454D554"
+ )
+ port map (
+ I0 => cnt_read_reg(2),
+ I1 => cnt_read_reg(1),
+ I2 => cnt_read_reg(0),
+ I3 => \^wr_en0\,
+ I4 => \rd_en__1\,
+ O => \cnt_read[4]_i_4_n_0\
+ );
+\cnt_read_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \cnt_read[0]_i_1_n_0\,
+ Q => cnt_read_reg(0),
+ S => areset_d1
+ );
+\cnt_read_reg[1]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \cnt_read[1]_i_1_n_0\,
+ Q => cnt_read_reg(1),
+ S => areset_d1
+ );
+\cnt_read_reg[2]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \cnt_read[2]_i_1_n_0\,
+ Q => cnt_read_reg(2),
+ S => areset_d1
+ );
+\cnt_read_reg[3]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \cnt_read[3]_i_1_n_0\,
+ Q => cnt_read_reg(3),
+ S => areset_d1
+ );
+\cnt_read_reg[4]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \cnt_read[4]_i_2_n_0\,
+ Q => cnt_read_reg(4),
+ S => areset_d1
+ );
+m_axi_rready_INST_0: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"85FFFFFF"
+ )
+ port map (
+ I0 => cnt_read_reg(2),
+ I1 => cnt_read_reg(0),
+ I2 => cnt_read_reg(1),
+ I3 => cnt_read_reg(3),
+ I4 => cnt_read_reg(4),
+ O => m_axi_rready
+ );
+m_valid_i_i_3: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFFFFFF"
+ )
+ port map (
+ I0 => cnt_read_reg(2),
+ I1 => cnt_read_reg(0),
+ I2 => cnt_read_reg(1),
+ I3 => cnt_read_reg(3),
+ I4 => cnt_read_reg(4),
+ O => a_full0
+ );
+\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(0),
+ Q => \out\(0),
+ Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8022AAAAAAAAAAAA"
+ )
+ port map (
+ I0 => m_axi_rvalid,
+ I1 => cnt_read_reg(2),
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(1),
+ I4 => cnt_read_reg(3),
+ I5 => cnt_read_reg(4),
+ O => \^wr_en0\
+ );
+\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(10),
+ Q => \out\(10),
+ Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(11),
+ Q => \out\(11),
+ Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(12),
+ Q => \out\(12),
+ Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(13),
+ Q => \out\(13),
+ Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(14),
+ Q => \out\(14),
+ Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(15),
+ Q => \out\(15),
+ Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(16),
+ Q => \out\(16),
+ Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(17),
+ Q => \out\(17),
+ Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(18),
+ Q => \out\(18),
+ Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(19),
+ Q => \out\(19),
+ Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(1),
+ Q => \out\(1),
+ Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(20),
+ Q => \out\(20),
+ Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(21),
+ Q => \out\(21),
+ Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(22),
+ Q => \out\(22),
+ Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(23),
+ Q => \out\(23),
+ Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(24),
+ Q => \out\(24),
+ Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(25),
+ Q => \out\(25),
+ Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(26),
+ Q => \out\(26),
+ Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(27),
+ Q => \out\(27),
+ Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(28),
+ Q => \out\(28),
+ Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(29),
+ Q => \out\(29),
+ Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(2),
+ Q => \out\(2),
+ Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(30),
+ Q => \out\(30),
+ Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(31),
+ Q => \out\(31),
+ Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(32),
+ Q => \out\(32),
+ Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(33),
+ Q => \out\(33),
+ Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(3),
+ Q => \out\(3),
+ Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(4),
+ Q => \out\(4),
+ Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(5),
+ Q => \out\(5),
+ Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(6),
+ Q => \out\(6),
+ Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(7),
+ Q => \out\(7),
+ Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(8),
+ Q => \out\(8),
+ Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => \^wr_en0\,
+ CLK => aclk,
+ D => \in\(9),
+ Q => \out\(9),
+ Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2\ is
+ port (
+ r_full : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \rd_en__1\ : out STD_LOGIC;
+ si_rs_rvalid : out STD_LOGIC;
+ r_push_r_reg : out STD_LOGIC_VECTOR ( 12 downto 0 );
+ rd_a_full : in STD_LOGIC;
+ wr_en0 : in STD_LOGIC;
+ r_push_r : in STD_LOGIC;
+ si_rs_rready : in STD_LOGIC;
+ a_full0 : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
+ aclk : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_19_b2s_simple_fifo";
+end \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2\;
+
+architecture STRUCTURE of \TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2\ is
+ signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC;
+ signal cnt_read_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \^rd_en__1\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair21";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name : string;
+ attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
+ attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
+ attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
+begin
+ \rd_en__1\ <= \^rd_en__1\;
+\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF6000E000"
+ )
+ port map (
+ I0 => cnt_read_reg(2),
+ I1 => cnt_read_reg(1),
+ I2 => cnt_read_reg(4),
+ I3 => cnt_read_reg(3),
+ I4 => cnt_read_reg(0),
+ I5 => rd_a_full,
+ O => r_full
+ );
+\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => cnt_read_reg(0),
+ O => \cnt_read[0]_i_1__0_n_0\
+ );
+\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9A65"
+ )
+ port map (
+ I0 => cnt_read_reg(0),
+ I1 => \^rd_en__1\,
+ I2 => r_push_r,
+ I3 => cnt_read_reg(1),
+ O => \cnt_read[1]_i_1__0_n_0\
+ );
+\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"BF40F40B"
+ )
+ port map (
+ I0 => \^rd_en__1\,
+ I1 => r_push_r,
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(2),
+ I4 => cnt_read_reg(1),
+ O => \cnt_read[2]_i_1__0_n_0\
+ );
+\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BFFF4000FFF4000B"
+ )
+ port map (
+ I0 => \^rd_en__1\,
+ I1 => r_push_r,
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(1),
+ I4 => cnt_read_reg(3),
+ I5 => cnt_read_reg(2),
+ O => \cnt_read[3]_i_1__0_n_0\
+ );
+\cnt_read[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \^rd_en__1\,
+ I1 => wr_en0,
+ O => E(0)
+ );
+\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \^rd_en__1\,
+ I1 => r_push_r,
+ O => \cnt_read[4]_i_1__0_n_0\
+ );
+\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"78E1"
+ )
+ port map (
+ I0 => \cnt_read[4]_i_3_n_0\,
+ I1 => cnt_read_reg(2),
+ I2 => cnt_read_reg(4),
+ I3 => cnt_read_reg(3),
+ O => \cnt_read[4]_i_2__0_n_0\
+ );
+\cnt_read[4]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"5454D554"
+ )
+ port map (
+ I0 => cnt_read_reg(2),
+ I1 => cnt_read_reg(1),
+ I2 => cnt_read_reg(0),
+ I3 => r_push_r,
+ I4 => \^rd_en__1\,
+ O => \cnt_read[4]_i_3_n_0\
+ );
+\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8AAAAAAA00000000"
+ )
+ port map (
+ I0 => si_rs_rready,
+ I1 => \cnt_read[4]_i_5_n_0\,
+ I2 => cnt_read_reg(0),
+ I3 => cnt_read_reg(1),
+ I4 => cnt_read_reg(2),
+ I5 => a_full0,
+ O => \^rd_en__1\
+ );
+\cnt_read[4]_i_5\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => cnt_read_reg(4),
+ I1 => cnt_read_reg(3),
+ O => \cnt_read[4]_i_5_n_0\
+ );
+\cnt_read_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => \cnt_read[4]_i_1__0_n_0\,
+ D => \cnt_read[0]_i_1__0_n_0\,
+ Q => cnt_read_reg(0),
+ S => areset_d1
+ );
+\cnt_read_reg[1]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => \cnt_read[4]_i_1__0_n_0\,
+ D => \cnt_read[1]_i_1__0_n_0\,
+ Q => cnt_read_reg(1),
+ S => areset_d1
+ );
+\cnt_read_reg[2]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => \cnt_read[4]_i_1__0_n_0\,
+ D => \cnt_read[2]_i_1__0_n_0\,
+ Q => cnt_read_reg(2),
+ S => areset_d1
+ );
+\cnt_read_reg[3]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => \cnt_read[4]_i_1__0_n_0\,
+ D => \cnt_read[3]_i_1__0_n_0\,
+ Q => cnt_read_reg(3),
+ S => areset_d1
+ );
+\cnt_read_reg[4]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => \cnt_read[4]_i_1__0_n_0\,
+ D => \cnt_read[4]_i_2__0_n_0\,
+ Q => cnt_read_reg(4),
+ S => areset_d1
+ );
+m_valid_i_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2AAAAAAAAAAAAAAA"
+ )
+ port map (
+ I0 => a_full0,
+ I1 => cnt_read_reg(2),
+ I2 => cnt_read_reg(1),
+ I3 => cnt_read_reg(0),
+ I4 => cnt_read_reg(3),
+ I5 => cnt_read_reg(4),
+ O => si_rs_rvalid
+ );
+\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(0),
+ Q => r_push_r_reg(0),
+ Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(10),
+ Q => r_push_r_reg(10),
+ Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(11),
+ Q => r_push_r_reg(11),
+ Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(12),
+ Q => r_push_r_reg(12),
+ Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(1),
+ Q => r_push_r_reg(1),
+ Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(2),
+ Q => r_push_r_reg(2),
+ Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(3),
+ Q => r_push_r_reg(3),
+ Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(4),
+ Q => r_push_r_reg(4),
+ Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(5),
+ Q => r_push_r_reg(5),
+ Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(6),
+ Q => r_push_r_reg(6),
+ Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(7),
+ Q => r_push_r_reg(7),
+ Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(8),
+ Q => r_push_r_reg(8),
+ Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
+ );
+\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
+ generic map(
+ INIT => X"00000000"
+ )
+ port map (
+ A(4 downto 0) => cnt_read_reg(4 downto 0),
+ CE => r_push_r,
+ CLK => aclk,
+ D => \in\(9),
+ Q => r_push_r_reg(9),
+ Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm is
+ port (
+ m_valid_i_reg : out STD_LOGIC;
+ \next\ : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_valid_i_reg_0 : out STD_LOGIC;
+ sel_first_reg : out STD_LOGIC;
+ sel_first_reg_0 : out STD_LOGIC;
+ sel_first_i : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+ b_push : out STD_LOGIC;
+ m_axi_awvalid : out STD_LOGIC;
+ si_rs_awvalid : in STD_LOGIC;
+ \axlen_cnt_reg[8]\ : in STD_LOGIC;
+ sel_first : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC;
+ sel_first_reg_1 : in STD_LOGIC;
+ sel_first_reg_2 : in STD_LOGIC;
+ \axlen_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axlen_cnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[0]_0\ : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC;
+ next_pending : in STD_LOGIC;
+ m_axi_awready : in STD_LOGIC;
+ b_full : in STD_LOGIC;
+ cnt_read : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ aclk : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm is
+ signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \^b_push\ : STD_LOGIC;
+ signal \^next\ : STD_LOGIC;
+ signal \state[0]_i_1_n_0\ : STD_LOGIC;
+ signal \state[1]_i_1_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair116";
+ attribute SOFT_HLUTNM of \axlen_cnt[8]_i_1__0\ : label is "soft_lutpair116";
+ attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair117";
+ attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair115";
+ attribute SOFT_HLUTNM of \next_pending_r_i_4__0\ : label is "soft_lutpair115";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair117";
+begin
+ Q(1 downto 0) <= \^q\(1 downto 0);
+ b_push <= \^b_push\;
+ \next\ <= \^next\;
+\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"1000FFFF10001000"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_awvalid,
+ I3 => \axlen_cnt_reg[3]\(0),
+ I4 => \axlen_cnt_reg[0]\(0),
+ I5 => \axlen_cnt_reg[0]_0\,
+ O => D(0)
+ );
+\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AAAE"
+ )
+ port map (
+ I0 => \^next\,
+ I1 => si_rs_awvalid,
+ I2 => \^q\(0),
+ I3 => \^q\(1),
+ O => m_valid_i_reg_0
+ );
+\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF100010001000"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_awvalid,
+ I3 => \axlen_cnt_reg[3]\(1),
+ I4 => \axlen_cnt_reg[3]_0\,
+ I5 => \axlen_cnt_reg[0]_0\,
+ O => D(1)
+ );
+\axlen_cnt[8]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000AAAE"
+ )
+ port map (
+ I0 => \^next\,
+ I1 => si_rs_awvalid,
+ I2 => \^q\(0),
+ I3 => \^q\(1),
+ I4 => \axlen_cnt_reg[8]\,
+ O => m_valid_i_reg
+ );
+m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(1),
+ O => m_axi_awvalid
+ );
+\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \^b_push\,
+ I1 => si_rs_awvalid,
+ O => m_valid_i_reg_1(0)
+ );
+\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"08080C08"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => b_full,
+ I3 => m_axi_awready,
+ I4 => next_pending,
+ O => \^b_push\
+ );
+\next_pending_r_i_4__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0FFF0400"
+ )
+ port map (
+ I0 => next_pending,
+ I1 => m_axi_awready,
+ I2 => b_full,
+ I3 => \^q\(0),
+ I4 => \^q\(1),
+ O => \^next\
+ );
+sel_first_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF444F4444"
+ )
+ port map (
+ I0 => \^next\,
+ I1 => sel_first,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_awvalid,
+ I5 => areset_d1,
+ O => sel_first_reg
+ );
+\sel_first_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF444F4444"
+ )
+ port map (
+ I0 => \^next\,
+ I1 => sel_first_reg_1,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_awvalid,
+ I5 => areset_d1,
+ O => sel_first_reg_0
+ );
+\sel_first_i_1__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF444F4444"
+ )
+ port map (
+ I0 => \^next\,
+ I1 => sel_first_reg_2,
+ I2 => \^q\(1),
+ I3 => \^q\(0),
+ I4 => si_rs_awvalid,
+ I5 => areset_d1,
+ O => sel_first_i
+ );
+\state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0F0FFFF7373FF00"
+ )
+ port map (
+ I0 => next_pending,
+ I1 => m_axi_awready,
+ I2 => b_full,
+ I3 => si_rs_awvalid,
+ I4 => \^q\(0),
+ I5 => \^q\(1),
+ O => \state[0]_i_1_n_0\
+ );
+\state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"08080808AA000800"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => cnt_read(1),
+ I2 => cnt_read(0),
+ I3 => m_axi_awready,
+ I4 => next_pending,
+ I5 => \^q\(1),
+ O => \state[1]_i_1_n_0\
+ );
+\state_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \state[0]_i_1_n_0\,
+ Q => \^q\(0),
+ R => areset_d1
+ );
+\state_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \state[1]_i_1_n_0\,
+ Q => \^q\(1),
+ R => areset_d1
+ );
+\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"10"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => si_rs_awvalid,
+ O => E(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd is
+ port (
+ wrap_next_pending : out STD_LOGIC;
+ sel_first : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \m_payload_i_reg[39]\ : out STD_LOGIC;
+ \axlen_cnt_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[3]_0\ : out STD_LOGIC;
+ \axlen_cnt_reg[2]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_reg_0 : in STD_LOGIC;
+ \next\ : in STD_LOGIC;
+ \axlen_cnt_reg[2]_1\ : in STD_LOGIC_VECTOR ( 16 downto 0 );
+ sel_first_i : in STD_LOGIC;
+ incr_next_pending : in STD_LOGIC;
+ next_pending_r_reg_0 : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[0]_0\ : in STD_LOGIC;
+ \axlen_cnt_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \wrap_cnt_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd is
+ signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal axaddr_wrap1 : STD_LOGIC;
+ signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
+ signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
+ signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^axlen_cnt_reg[3]_0\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
+ signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC;
+ signal next_pending_r_reg_n_0 : STD_LOGIC;
+ signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^wrap_next_pending\ : STD_LOGIC;
+ signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair127";
+ attribute SOFT_HLUTNM of \next_pending_r_i_2__2\ : label is "soft_lutpair127";
+begin
+ Q(11 downto 0) <= \^q\(11 downto 0);
+ \axlen_cnt_reg[0]_0\(0) <= \^axlen_cnt_reg[0]_0\(0);
+ \axlen_cnt_reg[3]_0\ <= \^axlen_cnt_reg[3]_0\;
+ wrap_next_pending <= \^wrap_next_pending\;
+\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(0),
+ Q => \axaddr_offset_r_reg[3]_0\(0),
+ R => '0'
+ );
+\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(1),
+ Q => \axaddr_offset_r_reg[3]_0\(1),
+ R => '0'
+ );
+\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(2),
+ Q => \axaddr_offset_r_reg[3]_0\(2),
+ R => '0'
+ );
+\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(3),
+ Q => \axaddr_offset_r_reg[3]_0\(3),
+ R => '0'
+ );
+\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(0),
+ I3 => wrap_boundary_axaddr_r(0),
+ I4 => \axlen_cnt_reg[2]_1\(0),
+ O => \axaddr_wrap[0]_i_1__0_n_0\
+ );
+\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(10),
+ I3 => wrap_boundary_axaddr_r(10),
+ I4 => \axlen_cnt_reg[2]_1\(10),
+ O => \axaddr_wrap[10]_i_1__0_n_0\
+ );
+\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(11),
+ I3 => wrap_boundary_axaddr_r(11),
+ I4 => \axlen_cnt_reg[2]_1\(11),
+ O => \axaddr_wrap[11]_i_1__0_n_0\
+ );
+\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4100004100000000"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[4]\,
+ I1 => wrap_cnt_r(1),
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => wrap_cnt_r(2),
+ I5 => \axaddr_wrap[11]_i_4__0_n_0\,
+ O => axaddr_wrap1
+ );
+\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => wrap_cnt_r(3),
+ I1 => \axlen_cnt_reg_n_0_[3]\,
+ I2 => wrap_cnt_r(0),
+ I3 => \^axlen_cnt_reg[0]_0\(0),
+ O => \axaddr_wrap[11]_i_4__0_n_0\
+ );
+\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(1),
+ I3 => wrap_boundary_axaddr_r(1),
+ I4 => \axlen_cnt_reg[2]_1\(1),
+ O => \axaddr_wrap[1]_i_1__0_n_0\
+ );
+\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(2),
+ I3 => wrap_boundary_axaddr_r(2),
+ I4 => \axlen_cnt_reg[2]_1\(2),
+ O => \axaddr_wrap[2]_i_1__0_n_0\
+ );
+\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(3),
+ I3 => wrap_boundary_axaddr_r(3),
+ I4 => \axlen_cnt_reg[2]_1\(3),
+ O => \axaddr_wrap[3]_i_1__0_n_0\
+ );
+\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \axlen_cnt_reg[2]_1\(13),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_wrap[3]_i_3_n_0\
+ );
+\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(13),
+ O => \axaddr_wrap[3]_i_4_n_0\
+ );
+\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \axlen_cnt_reg[2]_1\(13),
+ I2 => \axlen_cnt_reg[2]_1\(12),
+ O => \axaddr_wrap[3]_i_5_n_0\
+ );
+\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A9"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \axlen_cnt_reg[2]_1\(12),
+ I2 => \axlen_cnt_reg[2]_1\(13),
+ O => \axaddr_wrap[3]_i_6_n_0\
+ );
+\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(4),
+ I3 => wrap_boundary_axaddr_r(4),
+ I4 => \axlen_cnt_reg[2]_1\(4),
+ O => \axaddr_wrap[4]_i_1__0_n_0\
+ );
+\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(5),
+ I3 => wrap_boundary_axaddr_r(5),
+ I4 => \axlen_cnt_reg[2]_1\(5),
+ O => \axaddr_wrap[5]_i_1__0_n_0\
+ );
+\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(6),
+ I3 => wrap_boundary_axaddr_r(6),
+ I4 => \axlen_cnt_reg[2]_1\(6),
+ O => \axaddr_wrap[6]_i_1__0_n_0\
+ );
+\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(7),
+ I3 => wrap_boundary_axaddr_r(7),
+ I4 => \axlen_cnt_reg[2]_1\(7),
+ O => \axaddr_wrap[7]_i_1__0_n_0\
+ );
+\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(8),
+ I3 => wrap_boundary_axaddr_r(8),
+ I4 => \axlen_cnt_reg[2]_1\(8),
+ O => \axaddr_wrap[8]_i_1__0_n_0\
+ );
+\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FB73C840"
+ )
+ port map (
+ I0 => axaddr_wrap1,
+ I1 => \next\,
+ I2 => axaddr_wrap0(9),
+ I3 => wrap_boundary_axaddr_r(9),
+ I4 => \axlen_cnt_reg[2]_1\(9),
+ O => \axaddr_wrap[9]_i_1__0_n_0\
+ );
+\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[0]_i_1__0_n_0\,
+ Q => \^q\(0),
+ R => '0'
+ );
+\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[10]_i_1__0_n_0\,
+ Q => \^q\(10),
+ R => '0'
+ );
+\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[11]_i_1__0_n_0\,
+ Q => \^q\(11),
+ R => '0'
+ );
+\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_wrap_reg[7]_i_2_n_0\,
+ CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
+ CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
+ CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => axaddr_wrap0(11 downto 8),
+ S(3 downto 0) => \^q\(11 downto 8)
+ );
+\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[1]_i_1__0_n_0\,
+ Q => \^q\(1),
+ R => '0'
+ );
+\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[2]_i_1__0_n_0\,
+ Q => \^q\(2),
+ R => '0'
+ );
+\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[3]_i_1__0_n_0\,
+ Q => \^q\(3),
+ R => '0'
+ );
+\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
+ CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
+ CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
+ CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => \^q\(3 downto 0),
+ O(3 downto 0) => axaddr_wrap0(3 downto 0),
+ S(3) => \axaddr_wrap[3]_i_3_n_0\,
+ S(2) => \axaddr_wrap[3]_i_4_n_0\,
+ S(1) => \axaddr_wrap[3]_i_5_n_0\,
+ S(0) => \axaddr_wrap[3]_i_6_n_0\
+ );
+\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[4]_i_1__0_n_0\,
+ Q => \^q\(4),
+ R => '0'
+ );
+\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[5]_i_1__0_n_0\,
+ Q => \^q\(5),
+ R => '0'
+ );
+\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[6]_i_1__0_n_0\,
+ Q => \^q\(6),
+ R => '0'
+ );
+\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[7]_i_1__0_n_0\,
+ Q => \^q\(7),
+ R => '0'
+ );
+\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_wrap_reg[3]_i_2_n_0\,
+ CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
+ CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
+ CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
+ CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => axaddr_wrap0(7 downto 4),
+ S(3 downto 0) => \^q\(7 downto 4)
+ );
+\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[8]_i_1__0_n_0\,
+ Q => \^q\(8),
+ R => '0'
+ );
+\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap[9]_i_1__0_n_0\,
+ Q => \^q\(9),
+ R => '0'
+ );
+\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF909090"
+ )
+ port map (
+ I0 => \^axlen_cnt_reg[0]_0\(0),
+ I1 => \axlen_cnt_reg_n_0_[1]\,
+ I2 => \^axlen_cnt_reg[3]_0\,
+ I3 => E(0),
+ I4 => \axlen_cnt_reg[2]_1\(15),
+ O => \axlen_cnt[1]_i_1_n_0\
+ );
+\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFE100E100E100"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[1]\,
+ I1 => \^axlen_cnt_reg[0]_0\(0),
+ I2 => \axlen_cnt_reg_n_0_[2]\,
+ I3 => \^axlen_cnt_reg[3]_0\,
+ I4 => E(0),
+ I5 => \axlen_cnt_reg[2]_1\(16),
+ O => \axlen_cnt[2]_i_1_n_0\
+ );
+\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE01"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[2]\,
+ I1 => \^axlen_cnt_reg[0]_0\(0),
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[3]\,
+ O => \axlen_cnt_reg[2]_0\
+ );
+\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FFFE"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg_n_0_[4]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => E(0),
+ O => \^axlen_cnt_reg[3]_0\
+ );
+\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4444444444444440"
+ )
+ port map (
+ I0 => E(0),
+ I1 => \axlen_cnt_reg_n_0_[4]\,
+ I2 => \axlen_cnt_reg_n_0_[2]\,
+ I3 => \^axlen_cnt_reg[0]_0\(0),
+ I4 => \axlen_cnt_reg_n_0_[1]\,
+ I5 => \axlen_cnt_reg_n_0_[3]\,
+ O => \axlen_cnt[4]_i_1_n_0\
+ );
+\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt_reg[3]_1\(0),
+ Q => \^axlen_cnt_reg[0]_0\(0),
+ R => '0'
+ );
+\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[1]_i_1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[1]\,
+ R => '0'
+ );
+\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[2]_i_1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[2]\,
+ R => '0'
+ );
+\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt_reg[3]_1\(1),
+ Q => \axlen_cnt_reg_n_0_[3]\,
+ R => '0'
+ );
+\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[4]_i_1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[4]\,
+ R => '0'
+ );
+next_pending_r_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFAEAAAE"
+ )
+ port map (
+ I0 => next_pending_r_reg_0,
+ I1 => next_pending_r_reg_n_0,
+ I2 => E(0),
+ I3 => \next\,
+ I4 => \next_pending_r_i_2__2_n_0\,
+ O => \^wrap_next_pending\
+ );
+\next_pending_r_i_2__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55555554"
+ )
+ port map (
+ I0 => E(0),
+ I1 => \axlen_cnt_reg_n_0_[2]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[4]\,
+ I4 => \axlen_cnt_reg_n_0_[3]\,
+ O => \next_pending_r_i_2__2_n_0\
+ );
+next_pending_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \^wrap_next_pending\,
+ Q => next_pending_r_reg_n_0,
+ R => '0'
+ );
+s_axburst_eq1_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABA8"
+ )
+ port map (
+ I0 => \^wrap_next_pending\,
+ I1 => sel_first_i,
+ I2 => \axlen_cnt_reg[2]_1\(14),
+ I3 => incr_next_pending,
+ O => \m_payload_i_reg[39]\
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_reg_0,
+ Q => sel_first,
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(0),
+ Q => wrap_boundary_axaddr_r(0),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[2]_1\(10),
+ Q => wrap_boundary_axaddr_r(10),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[2]_1\(11),
+ Q => wrap_boundary_axaddr_r(11),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(1),
+ Q => wrap_boundary_axaddr_r(1),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(2),
+ Q => wrap_boundary_axaddr_r(2),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(3),
+ Q => wrap_boundary_axaddr_r(3),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(4),
+ Q => wrap_boundary_axaddr_r(4),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(5),
+ Q => wrap_boundary_axaddr_r(5),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(6),
+ Q => wrap_boundary_axaddr_r(6),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[2]_1\(7),
+ Q => wrap_boundary_axaddr_r(7),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[2]_1\(8),
+ Q => wrap_boundary_axaddr_r(8),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[2]_1\(9),
+ Q => wrap_boundary_axaddr_r(9),
+ R => '0'
+ );
+\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(0),
+ Q => wrap_cnt_r(0),
+ R => '0'
+ );
+\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(1),
+ Q => wrap_cnt_r(1),
+ R => '0'
+ );
+\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(2),
+ Q => wrap_cnt_r(2),
+ R => '0'
+ );
+\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(3),
+ Q => wrap_cnt_r(3),
+ R => '0'
+ );
+\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_second_len_r_reg[3]_1\(0),
+ Q => \wrap_second_len_r_reg[3]_0\(0),
+ R => '0'
+ );
+\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_second_len_r_reg[3]_1\(1),
+ Q => \wrap_second_len_r_reg[3]_0\(1),
+ R => '0'
+ );
+\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_second_len_r_reg[3]_1\(2),
+ Q => \wrap_second_len_r_reg[3]_0\(2),
+ R => '0'
+ );
+\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_second_len_r_reg[3]_1\(3),
+ Q => \wrap_second_len_r_reg[3]_0\(3),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3 is
+ port (
+ wrap_next_pending : out STD_LOGIC;
+ sel_first_reg_0 : out STD_LOGIC;
+ O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \axaddr_wrap_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[39]\ : out STD_LOGIC;
+ \axlen_cnt_reg[4]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_reg_1 : in STD_LOGIC;
+ sel_first_i : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ incr_next_pending : in STD_LOGIC;
+ next_pending_r_reg_0 : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ r_push : in STD_LOGIC;
+ \axlen_cnt_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ si_rs_arvalid : in STD_LOGIC;
+ axaddr_offset : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[0]_0\ : in STD_LOGIC;
+ \wrap_cnt_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ \axaddr_wrap_reg[11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_19_b2s_wrap_cmd";
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3 is
+ signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
+ signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
+ signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[3]_i_2__2_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[3]_i_3__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
+ signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
+ signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
+ signal next_pending_r_reg_n_0 : STD_LOGIC;
+ signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
+ signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
+ signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
+ signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
+ signal \^wrap_next_pending\ : STD_LOGIC;
+ signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2__2\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair15";
+begin
+ Q(11 downto 0) <= \^q\(11 downto 0);
+ wrap_next_pending <= \^wrap_next_pending\;
+\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => axaddr_offset(0),
+ Q => \axaddr_offset_r_reg[3]_0\(0),
+ R => '0'
+ );
+\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => axaddr_offset(1),
+ Q => \axaddr_offset_r_reg[3]_0\(1),
+ R => '0'
+ );
+\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => axaddr_offset(2),
+ Q => \axaddr_offset_r_reg[3]_0\(2),
+ R => '0'
+ );
+\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => axaddr_offset(3),
+ Q => \axaddr_offset_r_reg[3]_0\(3),
+ R => '0'
+ );
+\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4100004100000000"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[4]\,
+ I1 => \wrap_cnt_r_reg_n_0_[1]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => \wrap_cnt_r_reg_n_0_[2]\,
+ I5 => \axaddr_wrap[11]_i_6_n_0\,
+ O => \axlen_cnt_reg[4]_0\
+ );
+\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \wrap_cnt_r_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg_n_0_[3]\,
+ I2 => \wrap_cnt_r_reg_n_0_[0]\,
+ I3 => \axlen_cnt_reg_n_0_[0]\,
+ O => \axaddr_wrap[11]_i_6_n_0\
+ );
+\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \axlen_cnt_reg[3]_0\(6),
+ I2 => \axlen_cnt_reg[3]_0\(5),
+ O => \axaddr_wrap[3]_i_3_n_0\
+ );
+\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \axlen_cnt_reg[3]_0\(5),
+ I2 => \axlen_cnt_reg[3]_0\(6),
+ O => \axaddr_wrap[3]_i_4_n_0\
+ );
+\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"9A"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \axlen_cnt_reg[3]_0\(6),
+ I2 => \axlen_cnt_reg[3]_0\(5),
+ O => \axaddr_wrap[3]_i_5_n_0\
+ );
+\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A9"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \axlen_cnt_reg[3]_0\(5),
+ I2 => \axlen_cnt_reg[3]_0\(6),
+ O => \axaddr_wrap[3]_i_6_n_0\
+ );
+\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(0),
+ Q => \^q\(0),
+ R => '0'
+ );
+\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(10),
+ Q => \^q\(10),
+ R => '0'
+ );
+\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(11),
+ Q => \^q\(11),
+ R => '0'
+ );
+\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
+ CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
+ CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
+ CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \axaddr_wrap_reg[11]_0\(3 downto 0),
+ S(3 downto 0) => \^q\(11 downto 8)
+ );
+\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(1),
+ Q => \^q\(1),
+ R => '0'
+ );
+\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(2),
+ Q => \^q\(2),
+ R => '0'
+ );
+\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(3),
+ Q => \^q\(3),
+ R => '0'
+ );
+\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
+ CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
+ CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
+ CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => \^q\(3 downto 0),
+ O(3 downto 0) => O(3 downto 0),
+ S(3) => \axaddr_wrap[3]_i_3_n_0\,
+ S(2) => \axaddr_wrap[3]_i_4_n_0\,
+ S(1) => \axaddr_wrap[3]_i_5_n_0\,
+ S(0) => \axaddr_wrap[3]_i_6_n_0\
+ );
+\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(4),
+ Q => \^q\(4),
+ R => '0'
+ );
+\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(5),
+ Q => \^q\(5),
+ R => '0'
+ );
+\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(6),
+ Q => \^q\(6),
+ R => '0'
+ );
+\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(7),
+ Q => \^q\(7),
+ R => '0'
+ );
+\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
+ CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
+ CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
+ CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
+ CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \axaddr_wrap_reg[7]_0\(3 downto 0),
+ S(3 downto 0) => \^q\(7 downto 4)
+ );
+\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(8),
+ Q => \^q\(8),
+ R => '0'
+ );
+\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axaddr_wrap_reg[11]_1\(9),
+ Q => \^q\(9),
+ R => '0'
+ );
+\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"40FF4040"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[3]_1\(0),
+ I1 => si_rs_arvalid,
+ I2 => \axlen_cnt_reg[3]_0\(8),
+ I3 => \axlen_cnt_reg_n_0_[0]\,
+ I4 => \axlen_cnt[3]_i_3__1_n_0\,
+ O => \axlen_cnt[0]_i_1__2_n_0\
+ );
+\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF909090"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[0]\,
+ I1 => \axlen_cnt_reg_n_0_[1]\,
+ I2 => \axlen_cnt[3]_i_3__1_n_0\,
+ I3 => E(0),
+ I4 => \axlen_cnt_reg[3]_0\(9),
+ O => \axlen_cnt[1]_i_1__1_n_0\
+ );
+\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFE100E100E100"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[1]\,
+ I1 => \axlen_cnt_reg_n_0_[0]\,
+ I2 => \axlen_cnt_reg_n_0_[2]\,
+ I3 => \axlen_cnt[3]_i_3__1_n_0\,
+ I4 => E(0),
+ I5 => \axlen_cnt_reg[3]_0\(10),
+ O => \axlen_cnt[2]_i_1__1_n_0\
+ );
+\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF404040"
+ )
+ port map (
+ I0 => \axlen_cnt_reg[3]_1\(0),
+ I1 => si_rs_arvalid,
+ I2 => \axlen_cnt_reg[3]_0\(11),
+ I3 => \axlen_cnt[3]_i_2__2_n_0\,
+ I4 => \axlen_cnt[3]_i_3__1_n_0\,
+ O => \axlen_cnt[3]_i_1__2_n_0\
+ );
+\axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE01"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[2]\,
+ I1 => \axlen_cnt_reg_n_0_[0]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[3]\,
+ O => \axlen_cnt[3]_i_2__2_n_0\
+ );
+\axlen_cnt[3]_i_3__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FFFE"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[3]\,
+ I1 => \axlen_cnt_reg_n_0_[4]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => E(0),
+ O => \axlen_cnt[3]_i_3__1_n_0\
+ );
+\axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4444444444444440"
+ )
+ port map (
+ I0 => E(0),
+ I1 => \axlen_cnt_reg_n_0_[4]\,
+ I2 => \axlen_cnt_reg_n_0_[2]\,
+ I3 => \axlen_cnt_reg_n_0_[0]\,
+ I4 => \axlen_cnt_reg_n_0_[1]\,
+ I5 => \axlen_cnt_reg_n_0_[3]\,
+ O => \axlen_cnt[4]_i_1__1_n_0\
+ );
+\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[0]_i_1__2_n_0\,
+ Q => \axlen_cnt_reg_n_0_[0]\,
+ R => '0'
+ );
+\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[1]_i_1__1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[1]\,
+ R => '0'
+ );
+\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[2]_i_1__1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[2]\,
+ R => '0'
+ );
+\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[3]_i_1__2_n_0\,
+ Q => \axlen_cnt_reg_n_0_[3]\,
+ R => '0'
+ );
+\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \axaddr_wrap_reg[0]_0\,
+ D => \axlen_cnt[4]_i_1__1_n_0\,
+ Q => \axlen_cnt_reg_n_0_[4]\,
+ R => '0'
+ );
+\next_pending_r_i_1__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFAAAAAAAEAEAEAE"
+ )
+ port map (
+ I0 => next_pending_r_reg_0,
+ I1 => next_pending_r_reg_n_0,
+ I2 => E(0),
+ I3 => \next_pending_r_i_2__1_n_0\,
+ I4 => \axlen_cnt[3]_i_3__1_n_0\,
+ I5 => r_push,
+ O => \^wrap_next_pending\
+ );
+\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFFD"
+ )
+ port map (
+ I0 => \axlen_cnt_reg_n_0_[0]\,
+ I1 => \axlen_cnt_reg_n_0_[3]\,
+ I2 => \axlen_cnt_reg_n_0_[1]\,
+ I3 => \axlen_cnt_reg_n_0_[2]\,
+ I4 => \axlen_cnt_reg_n_0_[4]\,
+ O => \next_pending_r_i_2__1_n_0\
+ );
+next_pending_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \^wrap_next_pending\,
+ Q => next_pending_r_reg_n_0,
+ R => '0'
+ );
+\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABA8"
+ )
+ port map (
+ I0 => \^wrap_next_pending\,
+ I1 => sel_first_i,
+ I2 => \axlen_cnt_reg[3]_0\(7),
+ I3 => incr_next_pending,
+ O => \m_payload_i_reg[39]\
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_reg_1,
+ Q => sel_first_reg_0,
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(0),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(0),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[3]_0\(3),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(10),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[3]_0\(4),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(11),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(1),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(1),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(2),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(2),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(3),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(3),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(4),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(4),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(5),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(5),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \wrap_boundary_axaddr_r_reg[6]_0\(6),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(6),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[3]_0\(0),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(7),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[3]_0\(1),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(8),
+ R => '0'
+ );
+\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => \axlen_cnt_reg[3]_0\(2),
+ Q => \wrap_boundary_axaddr_r_reg[11]_0\(9),
+ R => '0'
+ );
+\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(0),
+ Q => \wrap_cnt_r_reg_n_0_[0]\,
+ R => '0'
+ );
+\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(1),
+ Q => \wrap_cnt_r_reg_n_0_[1]\,
+ R => '0'
+ );
+\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(2),
+ Q => \wrap_cnt_r_reg_n_0_[2]\,
+ R => '0'
+ );
+\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \wrap_cnt_r_reg[3]_0\(3),
+ Q => \wrap_cnt_r_reg_n_0_[3]\,
+ R => '0'
+ );
+\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(0),
+ Q => \wrap_second_len_r_reg[3]_0\(0),
+ R => '0'
+ );
+\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(1),
+ Q => \wrap_second_len_r_reg[3]_0\(1),
+ R => '0'
+ );
+\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(2),
+ Q => \wrap_second_len_r_reg[3]_0\(2),
+ R => '0'
+ );
+\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(3),
+ Q => \wrap_second_len_r_reg[3]_0\(3),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice is
+ port (
+ s_ready_i_reg_0 : out STD_LOGIC;
+ m_valid_i_reg_0 : out STD_LOGIC;
+ \aresetn_d_reg[1]_inv_0\ : out STD_LOGIC;
+ \wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[44]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[1]\ : out STD_LOGIC;
+ \m_payload_i_reg[47]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[2]\ : out STD_LOGIC;
+ \m_payload_i_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[47]_1\ : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
+ \wrap_second_len_r_reg[1]_0\ : out STD_LOGIC;
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ \m_payload_i_reg[47]_2\ : out STD_LOGIC;
+ \m_payload_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]_0\ : out STD_LOGIC;
+ \m_payload_i_reg[38]_0\ : out STD_LOGIC;
+ s_ready_i_reg_1 : in STD_LOGIC;
+ s_ready_i0 : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ m_valid_i0 : in STD_LOGIC;
+ \aresetn_d_reg[1]_inv_1\ : in STD_LOGIC;
+ \wrap_cnt_r_reg[0]\ : in STD_LOGIC;
+ \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_offset_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ \m_axi_araddr[11]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_araddr[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_araddr[11]_1\ : in STD_LOGIC;
+ sel_first_2 : in STD_LOGIC;
+ \m_axi_araddr[11]_2\ : in STD_LOGIC;
+ \m_payload_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice is
+ signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
+ signal \^aresetn_d_reg[1]_inv_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_5__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_6__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_7__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_8__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_7__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_4__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_5__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_6__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_7__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
+ signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
+ signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
+ signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
+ signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[38]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[39]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[44]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[47]_0\ : STD_LOGIC;
+ signal \^m_valid_i_reg_0\ : STD_LOGIC;
+ signal \^s_ready_i_reg_0\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
+ signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
+ signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
+ signal \^wrap_second_len_r_reg[1]_0\ : STD_LOGIC;
+ signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3__0\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair53";
+ attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_2\ : label is "soft_lutpair53";
+ attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair48";
+ attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair47";
+ attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair47";
+ attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair46";
+ attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair46";
+ attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair45";
+ attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair45";
+ attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair44";
+ attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair44";
+ attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair43";
+ attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair52";
+ attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair43";
+ attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair42";
+ attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair42";
+ attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair41";
+ attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair41";
+ attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair40";
+ attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair40";
+ attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair39";
+ attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair39";
+ attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair38";
+ attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair52";
+ attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair38";
+ attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair37";
+ attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair37";
+ attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair36";
+ attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair36";
+ attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair35";
+ attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair35";
+ attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair34";
+ attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair34";
+ attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair51";
+ attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair33";
+ attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair33";
+ attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair51";
+ attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair50";
+ attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair50";
+ attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair49";
+ attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair49";
+ attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair48";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair24";
+begin
+ Q(54 downto 0) <= \^q\(54 downto 0);
+ \aresetn_d_reg[1]_inv_0\ <= \^aresetn_d_reg[1]_inv_0\;
+ \axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
+ \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
+ \m_payload_i_reg[38]_0\ <= \^m_payload_i_reg[38]_0\;
+ \m_payload_i_reg[39]_0\ <= \^m_payload_i_reg[39]_0\;
+ \m_payload_i_reg[44]_0\ <= \^m_payload_i_reg[44]_0\;
+ \m_payload_i_reg[47]_0\ <= \^m_payload_i_reg[47]_0\;
+ m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
+ s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
+ \wrap_second_len_r_reg[1]_0\ <= \^wrap_second_len_r_reg[1]_0\;
+ \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
+\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \aresetn_d_reg[1]_inv_1\,
+ Q => \^aresetn_d_reg[1]_inv_0\,
+ R => '0'
+ );
+\axaddr_incr[11]_i_5__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(11),
+ O => \axaddr_incr[11]_i_5__0_n_0\
+ );
+\axaddr_incr[11]_i_6__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(10),
+ O => \axaddr_incr[11]_i_6__0_n_0\
+ );
+\axaddr_incr[11]_i_7__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(9),
+ O => \axaddr_incr[11]_i_7__0_n_0\
+ );
+\axaddr_incr[11]_i_8__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(8),
+ O => \axaddr_incr[11]_i_8__0_n_0\
+ );
+\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(3),
+ O => \axaddr_incr[3]_i_4__0_n_0\
+ );
+\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"70"
+ )
+ port map (
+ I0 => \^q\(36),
+ I1 => \^q\(35),
+ I2 => \^q\(2),
+ O => \axaddr_incr[3]_i_5__0_n_0\
+ );
+\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"4"
+ )
+ port map (
+ I0 => \^q\(36),
+ I1 => \^q\(1),
+ O => \axaddr_incr[3]_i_6__0_n_0\
+ );
+\axaddr_incr[3]_i_7__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(35),
+ I2 => \^q\(36),
+ O => \axaddr_incr[3]_i_7__0_n_0\
+ );
+\axaddr_incr[7]_i_4__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(7),
+ O => \axaddr_incr[7]_i_4__0_n_0\
+ );
+\axaddr_incr[7]_i_5__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(6),
+ O => \axaddr_incr[7]_i_5__0_n_0\
+ );
+\axaddr_incr[7]_i_6__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(5),
+ O => \axaddr_incr[7]_i_6__0_n_0\
+ );
+\axaddr_incr[7]_i_7__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(4),
+ O => \axaddr_incr[7]_i_7__0_n_0\
+ );
+\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
+ CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
+ CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
+ CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => O(3 downto 0),
+ S(3) => \axaddr_incr[11]_i_5__0_n_0\,
+ S(2) => \axaddr_incr[11]_i_6__0_n_0\,
+ S(1) => \axaddr_incr[11]_i_7__0_n_0\,
+ S(0) => \axaddr_incr[11]_i_8__0_n_0\
+ );
+\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
+ CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
+ CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
+ CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
+ CYINIT => '0',
+ DI(3) => \axaddr_incr[3]_i_4__0_n_0\,
+ DI(2) => \axaddr_incr[3]_i_5__0_n_0\,
+ DI(1) => \axaddr_incr[3]_i_6__0_n_0\,
+ DI(0) => \axaddr_incr[3]_i_7__0_n_0\,
+ O(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
+ S(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0)
+ );
+\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
+ CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
+ CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
+ CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
+ CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \m_payload_i_reg[7]_0\(3 downto 0),
+ S(3) => \axaddr_incr[7]_i_4__0_n_0\,
+ S(2) => \axaddr_incr[7]_i_5__0_n_0\,
+ S(1) => \axaddr_incr[7]_i_6__0_n_0\,
+ S(0) => \axaddr_incr[7]_i_7__0_n_0\
+ );
+\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F8FFFFFF08000000"
+ )
+ port map (
+ I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
+ I1 => \^q\(39),
+ I2 => \axaddr_offset_r_reg[0]\(1),
+ I3 => \axaddr_offset_r_reg[0]\(0),
+ I4 => \^m_valid_i_reg_0\,
+ I5 => \axaddr_offset_r_reg[3]\(0),
+ O => \^m_payload_i_reg[44]_0\
+ );
+\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FC0CFAFAFC0C0A0A"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(2),
+ I2 => \^q\(35),
+ I3 => \^q\(3),
+ I4 => \^q\(36),
+ I5 => \^q\(1),
+ O => \axaddr_offset_r[0]_i_2__0_n_0\
+ );
+\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0AA00AAC0AAC0AA"
+ )
+ port map (
+ I0 => \axaddr_offset_r_reg[3]\(1),
+ I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
+ I2 => \^q\(40),
+ I3 => \wrap_cnt_r_reg[0]\,
+ I4 => \axaddr_offset_r[2]_i_2__0_n_0\,
+ I5 => \^q\(35),
+ O => \^axaddr_offset_r_reg[1]\
+ );
+\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \^q\(36),
+ I2 => \^q\(1),
+ O => \axaddr_offset_r[1]_i_2__0_n_0\
+ );
+\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0AA00AAC0AAC0AA"
+ )
+ port map (
+ I0 => \axaddr_offset_r_reg[3]\(2),
+ I1 => \axaddr_offset_r[2]_i_2__0_n_0\,
+ I2 => \^q\(41),
+ I3 => \wrap_cnt_r_reg[0]\,
+ I4 => \axaddr_offset_r[2]_i_3__0_n_0\,
+ I5 => \^q\(35),
+ O => \^axaddr_offset_r_reg[2]\
+ );
+\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \^q\(36),
+ I2 => \^q\(2),
+ O => \axaddr_offset_r[2]_i_2__0_n_0\
+ );
+\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \^q\(36),
+ I2 => \^q\(3),
+ O => \axaddr_offset_r[2]_i_3__0_n_0\
+ );
+\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F8FFFFFF08000000"
+ )
+ port map (
+ I0 => \axaddr_offset_r[3]_i_2__0_n_0\,
+ I1 => \^q\(42),
+ I2 => \axaddr_offset_r_reg[0]\(1),
+ I3 => \axaddr_offset_r_reg[0]\(0),
+ I4 => \^m_valid_i_reg_0\,
+ I5 => \axaddr_offset_r_reg[3]\(3),
+ O => \^m_payload_i_reg[47]_0\
+ );
+\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFCCF0AA00CCF0AA"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \^q\(5),
+ I2 => \^q\(4),
+ I3 => \^q\(35),
+ I4 => \^q\(36),
+ I5 => \^q\(6),
+ O => \axaddr_offset_r[3]_i_2__0_n_0\
+ );
+\axlen_cnt[3]_i_3__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0080"
+ )
+ port map (
+ I0 => \^q\(42),
+ I1 => \^m_valid_i_reg_0\,
+ I2 => \axaddr_offset_r_reg[0]\(0),
+ I3 => \axaddr_offset_r_reg[0]\(1),
+ O => \m_payload_i_reg[47]_2\
+ );
+\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[39]_0\,
+ I1 => \m_axi_araddr[11]\(0),
+ I2 => \^m_payload_i_reg[38]_0\,
+ I3 => \m_axi_araddr[11]_0\(0),
+ I4 => \^q\(11),
+ I5 => \m_axi_araddr[11]_1\,
+ O => m_axi_araddr(0)
+ );
+\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^q\(38),
+ I1 => \m_axi_araddr[11]_2\,
+ O => \^m_payload_i_reg[39]_0\
+ );
+\m_axi_araddr[11]_INST_0_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => \^q\(37),
+ I1 => sel_first_2,
+ I2 => \^q\(38),
+ O => \^m_payload_i_reg[38]_0\
+ );
+\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[0]\,
+ O => \m_payload_i[0]_i_1__0_n_0\
+ );
+\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[10]\,
+ O => \m_payload_i[10]_i_1__0_n_0\
+ );
+\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[11]\,
+ O => \m_payload_i[11]_i_1__0_n_0\
+ );
+\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(12),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[12]\,
+ O => \m_payload_i[12]_i_1__0_n_0\
+ );
+\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(13),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[13]\,
+ O => \m_payload_i[13]_i_1__1_n_0\
+ );
+\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(14),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[14]\,
+ O => \m_payload_i[14]_i_1__0_n_0\
+ );
+\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(15),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[15]\,
+ O => \m_payload_i[15]_i_1__0_n_0\
+ );
+\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(16),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[16]\,
+ O => \m_payload_i[16]_i_1__0_n_0\
+ );
+\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(17),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[17]\,
+ O => \m_payload_i[17]_i_1__0_n_0\
+ );
+\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(18),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[18]\,
+ O => \m_payload_i[18]_i_1__0_n_0\
+ );
+\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(19),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[19]\,
+ O => \m_payload_i[19]_i_1__0_n_0\
+ );
+\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[1]\,
+ O => \m_payload_i[1]_i_1__0_n_0\
+ );
+\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(20),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[20]\,
+ O => \m_payload_i[20]_i_1__0_n_0\
+ );
+\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(21),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[21]\,
+ O => \m_payload_i[21]_i_1__0_n_0\
+ );
+\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(22),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[22]\,
+ O => \m_payload_i[22]_i_1__0_n_0\
+ );
+\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(23),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[23]\,
+ O => \m_payload_i[23]_i_1__0_n_0\
+ );
+\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(24),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[24]\,
+ O => \m_payload_i[24]_i_1__0_n_0\
+ );
+\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(25),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[25]\,
+ O => \m_payload_i[25]_i_1__0_n_0\
+ );
+\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(26),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[26]\,
+ O => \m_payload_i[26]_i_1__0_n_0\
+ );
+\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(27),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[27]\,
+ O => \m_payload_i[27]_i_1__0_n_0\
+ );
+\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(28),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[28]\,
+ O => \m_payload_i[28]_i_1__0_n_0\
+ );
+\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(29),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[29]\,
+ O => \m_payload_i[29]_i_1__0_n_0\
+ );
+\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[2]\,
+ O => \m_payload_i[2]_i_1__0_n_0\
+ );
+\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(30),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[30]\,
+ O => \m_payload_i[30]_i_1__0_n_0\
+ );
+\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(31),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[31]\,
+ O => \m_payload_i[31]_i_2__0_n_0\
+ );
+\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arprot(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[32]\,
+ O => \m_payload_i[32]_i_1__0_n_0\
+ );
+\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arprot(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[33]\,
+ O => \m_payload_i[33]_i_1__0_n_0\
+ );
+\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arprot(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[34]\,
+ O => \m_payload_i[34]_i_1__0_n_0\
+ );
+\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arsize(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[35]\,
+ O => \m_payload_i[35]_i_1__0_n_0\
+ );
+\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arsize(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[36]\,
+ O => \m_payload_i[36]_i_1__0_n_0\
+ );
+\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arburst(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[38]\,
+ O => \m_payload_i[38]_i_1__0_n_0\
+ );
+\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arburst(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[39]\,
+ O => \m_payload_i[39]_i_1__0_n_0\
+ );
+\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[3]\,
+ O => \m_payload_i[3]_i_1__0_n_0\
+ );
+\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arlen(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[44]\,
+ O => \m_payload_i[44]_i_1__0_n_0\
+ );
+\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arlen(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[45]\,
+ O => \m_payload_i[45]_i_1__0_n_0\
+ );
+\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arlen(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[46]\,
+ O => \m_payload_i[46]_i_1__1_n_0\
+ );
+\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arlen(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[47]\,
+ O => \m_payload_i[47]_i_1__0_n_0\
+ );
+\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[4]\,
+ O => \m_payload_i[4]_i_1__0_n_0\
+ );
+\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[50]\,
+ O => \m_payload_i[50]_i_1__0_n_0\
+ );
+\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[51]\,
+ O => \m_payload_i[51]_i_1__0_n_0\
+ );
+\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[52]\,
+ O => \m_payload_i[52]_i_1__0_n_0\
+ );
+\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[53]\,
+ O => \m_payload_i[53]_i_1__0_n_0\
+ );
+\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[54]\,
+ O => \m_payload_i[54]_i_1__0_n_0\
+ );
+\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[55]\,
+ O => \m_payload_i[55]_i_1__0_n_0\
+ );
+\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[56]\,
+ O => \m_payload_i[56]_i_1__0_n_0\
+ );
+\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[57]\,
+ O => \m_payload_i[57]_i_1__0_n_0\
+ );
+\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[58]\,
+ O => \m_payload_i[58]_i_1__0_n_0\
+ );
+\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[59]\,
+ O => \m_payload_i[59]_i_1__0_n_0\
+ );
+\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[5]\,
+ O => \m_payload_i[5]_i_1__0_n_0\
+ );
+\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[60]\,
+ O => \m_payload_i[60]_i_1__0_n_0\
+ );
+\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_arid(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[61]\,
+ O => \m_payload_i[61]_i_1__0_n_0\
+ );
+\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[6]\,
+ O => \m_payload_i[6]_i_1__0_n_0\
+ );
+\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[7]\,
+ O => \m_payload_i[7]_i_1__0_n_0\
+ );
+\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[8]\,
+ O => \m_payload_i[8]_i_1__0_n_0\
+ );
+\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[9]\,
+ O => \m_payload_i[9]_i_1__0_n_0\
+ );
+\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[0]_i_1__0_n_0\,
+ Q => \^q\(0),
+ R => '0'
+ );
+\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[10]_i_1__0_n_0\,
+ Q => \^q\(10),
+ R => '0'
+ );
+\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[11]_i_1__0_n_0\,
+ Q => \^q\(11),
+ R => '0'
+ );
+\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[12]_i_1__0_n_0\,
+ Q => \^q\(12),
+ R => '0'
+ );
+\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[13]_i_1__1_n_0\,
+ Q => \^q\(13),
+ R => '0'
+ );
+\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[14]_i_1__0_n_0\,
+ Q => \^q\(14),
+ R => '0'
+ );
+\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[15]_i_1__0_n_0\,
+ Q => \^q\(15),
+ R => '0'
+ );
+\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[16]_i_1__0_n_0\,
+ Q => \^q\(16),
+ R => '0'
+ );
+\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[17]_i_1__0_n_0\,
+ Q => \^q\(17),
+ R => '0'
+ );
+\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[18]_i_1__0_n_0\,
+ Q => \^q\(18),
+ R => '0'
+ );
+\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[19]_i_1__0_n_0\,
+ Q => \^q\(19),
+ R => '0'
+ );
+\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[1]_i_1__0_n_0\,
+ Q => \^q\(1),
+ R => '0'
+ );
+\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[20]_i_1__0_n_0\,
+ Q => \^q\(20),
+ R => '0'
+ );
+\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[21]_i_1__0_n_0\,
+ Q => \^q\(21),
+ R => '0'
+ );
+\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[22]_i_1__0_n_0\,
+ Q => \^q\(22),
+ R => '0'
+ );
+\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[23]_i_1__0_n_0\,
+ Q => \^q\(23),
+ R => '0'
+ );
+\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[24]_i_1__0_n_0\,
+ Q => \^q\(24),
+ R => '0'
+ );
+\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[25]_i_1__0_n_0\,
+ Q => \^q\(25),
+ R => '0'
+ );
+\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[26]_i_1__0_n_0\,
+ Q => \^q\(26),
+ R => '0'
+ );
+\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[27]_i_1__0_n_0\,
+ Q => \^q\(27),
+ R => '0'
+ );
+\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[28]_i_1__0_n_0\,
+ Q => \^q\(28),
+ R => '0'
+ );
+\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[29]_i_1__0_n_0\,
+ Q => \^q\(29),
+ R => '0'
+ );
+\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[2]_i_1__0_n_0\,
+ Q => \^q\(2),
+ R => '0'
+ );
+\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[30]_i_1__0_n_0\,
+ Q => \^q\(30),
+ R => '0'
+ );
+\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[31]_i_2__0_n_0\,
+ Q => \^q\(31),
+ R => '0'
+ );
+\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[32]_i_1__0_n_0\,
+ Q => \^q\(32),
+ R => '0'
+ );
+\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[33]_i_1__0_n_0\,
+ Q => \^q\(33),
+ R => '0'
+ );
+\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[34]_i_1__0_n_0\,
+ Q => \^q\(34),
+ R => '0'
+ );
+\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[35]_i_1__0_n_0\,
+ Q => \^q\(35),
+ R => '0'
+ );
+\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[36]_i_1__0_n_0\,
+ Q => \^q\(36),
+ R => '0'
+ );
+\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[38]_i_1__0_n_0\,
+ Q => \^q\(37),
+ R => '0'
+ );
+\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[39]_i_1__0_n_0\,
+ Q => \^q\(38),
+ R => '0'
+ );
+\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[3]_i_1__0_n_0\,
+ Q => \^q\(3),
+ R => '0'
+ );
+\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[44]_i_1__0_n_0\,
+ Q => \^q\(39),
+ R => '0'
+ );
+\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[45]_i_1__0_n_0\,
+ Q => \^q\(40),
+ R => '0'
+ );
+\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[46]_i_1__1_n_0\,
+ Q => \^q\(41),
+ R => '0'
+ );
+\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[47]_i_1__0_n_0\,
+ Q => \^q\(42),
+ R => '0'
+ );
+\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[4]_i_1__0_n_0\,
+ Q => \^q\(4),
+ R => '0'
+ );
+\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[50]_i_1__0_n_0\,
+ Q => \^q\(43),
+ R => '0'
+ );
+\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[51]_i_1__0_n_0\,
+ Q => \^q\(44),
+ R => '0'
+ );
+\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[52]_i_1__0_n_0\,
+ Q => \^q\(45),
+ R => '0'
+ );
+\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[53]_i_1__0_n_0\,
+ Q => \^q\(46),
+ R => '0'
+ );
+\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[54]_i_1__0_n_0\,
+ Q => \^q\(47),
+ R => '0'
+ );
+\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[55]_i_1__0_n_0\,
+ Q => \^q\(48),
+ R => '0'
+ );
+\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[56]_i_1__0_n_0\,
+ Q => \^q\(49),
+ R => '0'
+ );
+\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[57]_i_1__0_n_0\,
+ Q => \^q\(50),
+ R => '0'
+ );
+\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[58]_i_1__0_n_0\,
+ Q => \^q\(51),
+ R => '0'
+ );
+\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[59]_i_1__0_n_0\,
+ Q => \^q\(52),
+ R => '0'
+ );
+\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[5]_i_1__0_n_0\,
+ Q => \^q\(5),
+ R => '0'
+ );
+\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[60]_i_1__0_n_0\,
+ Q => \^q\(53),
+ R => '0'
+ );
+\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[61]_i_1__0_n_0\,
+ Q => \^q\(54),
+ R => '0'
+ );
+\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[6]_i_1__0_n_0\,
+ Q => \^q\(6),
+ R => '0'
+ );
+\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[7]_i_1__0_n_0\,
+ Q => \^q\(7),
+ R => '0'
+ );
+\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[8]_i_1__0_n_0\,
+ Q => \^q\(8),
+ R => '0'
+ );
+\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \m_payload_i_reg[0]_0\(0),
+ D => \m_payload_i[9]_i_1__0_n_0\,
+ Q => \^q\(9),
+ R => '0'
+ );
+m_valid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_valid_i0,
+ Q => \^m_valid_i_reg_0\,
+ R => \^aresetn_d_reg[1]_inv_0\
+ );
+\next_pending_r_i_2__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFE0000"
+ )
+ port map (
+ I0 => \^q\(42),
+ I1 => \^q\(39),
+ I2 => \^q\(40),
+ I3 => \^q\(41),
+ I4 => \wrap_cnt_r_reg[0]\,
+ O => \m_payload_i_reg[47]_1\
+ );
+s_ready_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => s_ready_i0,
+ Q => \^s_ready_i_reg_0\,
+ R => s_ready_i_reg_1
+ );
+\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(0),
+ Q => \skid_buffer_reg_n_0_[0]\,
+ R => '0'
+ );
+\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(10),
+ Q => \skid_buffer_reg_n_0_[10]\,
+ R => '0'
+ );
+\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(11),
+ Q => \skid_buffer_reg_n_0_[11]\,
+ R => '0'
+ );
+\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(12),
+ Q => \skid_buffer_reg_n_0_[12]\,
+ R => '0'
+ );
+\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(13),
+ Q => \skid_buffer_reg_n_0_[13]\,
+ R => '0'
+ );
+\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(14),
+ Q => \skid_buffer_reg_n_0_[14]\,
+ R => '0'
+ );
+\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(15),
+ Q => \skid_buffer_reg_n_0_[15]\,
+ R => '0'
+ );
+\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(16),
+ Q => \skid_buffer_reg_n_0_[16]\,
+ R => '0'
+ );
+\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(17),
+ Q => \skid_buffer_reg_n_0_[17]\,
+ R => '0'
+ );
+\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(18),
+ Q => \skid_buffer_reg_n_0_[18]\,
+ R => '0'
+ );
+\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(19),
+ Q => \skid_buffer_reg_n_0_[19]\,
+ R => '0'
+ );
+\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(1),
+ Q => \skid_buffer_reg_n_0_[1]\,
+ R => '0'
+ );
+\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(20),
+ Q => \skid_buffer_reg_n_0_[20]\,
+ R => '0'
+ );
+\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(21),
+ Q => \skid_buffer_reg_n_0_[21]\,
+ R => '0'
+ );
+\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(22),
+ Q => \skid_buffer_reg_n_0_[22]\,
+ R => '0'
+ );
+\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(23),
+ Q => \skid_buffer_reg_n_0_[23]\,
+ R => '0'
+ );
+\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(24),
+ Q => \skid_buffer_reg_n_0_[24]\,
+ R => '0'
+ );
+\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(25),
+ Q => \skid_buffer_reg_n_0_[25]\,
+ R => '0'
+ );
+\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(26),
+ Q => \skid_buffer_reg_n_0_[26]\,
+ R => '0'
+ );
+\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(27),
+ Q => \skid_buffer_reg_n_0_[27]\,
+ R => '0'
+ );
+\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(28),
+ Q => \skid_buffer_reg_n_0_[28]\,
+ R => '0'
+ );
+\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(29),
+ Q => \skid_buffer_reg_n_0_[29]\,
+ R => '0'
+ );
+\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(2),
+ Q => \skid_buffer_reg_n_0_[2]\,
+ R => '0'
+ );
+\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(30),
+ Q => \skid_buffer_reg_n_0_[30]\,
+ R => '0'
+ );
+\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(31),
+ Q => \skid_buffer_reg_n_0_[31]\,
+ R => '0'
+ );
+\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arprot(0),
+ Q => \skid_buffer_reg_n_0_[32]\,
+ R => '0'
+ );
+\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arprot(1),
+ Q => \skid_buffer_reg_n_0_[33]\,
+ R => '0'
+ );
+\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arprot(2),
+ Q => \skid_buffer_reg_n_0_[34]\,
+ R => '0'
+ );
+\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arsize(0),
+ Q => \skid_buffer_reg_n_0_[35]\,
+ R => '0'
+ );
+\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arsize(1),
+ Q => \skid_buffer_reg_n_0_[36]\,
+ R => '0'
+ );
+\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arburst(0),
+ Q => \skid_buffer_reg_n_0_[38]\,
+ R => '0'
+ );
+\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arburst(1),
+ Q => \skid_buffer_reg_n_0_[39]\,
+ R => '0'
+ );
+\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(3),
+ Q => \skid_buffer_reg_n_0_[3]\,
+ R => '0'
+ );
+\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arlen(0),
+ Q => \skid_buffer_reg_n_0_[44]\,
+ R => '0'
+ );
+\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arlen(1),
+ Q => \skid_buffer_reg_n_0_[45]\,
+ R => '0'
+ );
+\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arlen(2),
+ Q => \skid_buffer_reg_n_0_[46]\,
+ R => '0'
+ );
+\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arlen(3),
+ Q => \skid_buffer_reg_n_0_[47]\,
+ R => '0'
+ );
+\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(4),
+ Q => \skid_buffer_reg_n_0_[4]\,
+ R => '0'
+ );
+\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(0),
+ Q => \skid_buffer_reg_n_0_[50]\,
+ R => '0'
+ );
+\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(1),
+ Q => \skid_buffer_reg_n_0_[51]\,
+ R => '0'
+ );
+\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(2),
+ Q => \skid_buffer_reg_n_0_[52]\,
+ R => '0'
+ );
+\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(3),
+ Q => \skid_buffer_reg_n_0_[53]\,
+ R => '0'
+ );
+\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(4),
+ Q => \skid_buffer_reg_n_0_[54]\,
+ R => '0'
+ );
+\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(5),
+ Q => \skid_buffer_reg_n_0_[55]\,
+ R => '0'
+ );
+\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(6),
+ Q => \skid_buffer_reg_n_0_[56]\,
+ R => '0'
+ );
+\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(7),
+ Q => \skid_buffer_reg_n_0_[57]\,
+ R => '0'
+ );
+\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(8),
+ Q => \skid_buffer_reg_n_0_[58]\,
+ R => '0'
+ );
+\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(9),
+ Q => \skid_buffer_reg_n_0_[59]\,
+ R => '0'
+ );
+\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(5),
+ Q => \skid_buffer_reg_n_0_[5]\,
+ R => '0'
+ );
+\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(10),
+ Q => \skid_buffer_reg_n_0_[60]\,
+ R => '0'
+ );
+\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_arid(11),
+ Q => \skid_buffer_reg_n_0_[61]\,
+ R => '0'
+ );
+\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(6),
+ Q => \skid_buffer_reg_n_0_[6]\,
+ R => '0'
+ );
+\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(7),
+ Q => \skid_buffer_reg_n_0_[7]\,
+ R => '0'
+ );
+\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(8),
+ Q => \skid_buffer_reg_n_0_[8]\,
+ R => '0'
+ );
+\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_araddr(9),
+ Q => \skid_buffer_reg_n_0_[9]\,
+ R => '0'
+ );
+\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AA8A"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(35),
+ I2 => \^q\(39),
+ I3 => \^q\(36),
+ O => \m_payload_i_reg[6]_0\(0)
+ );
+\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF470000"
+ )
+ port map (
+ I0 => \^q\(39),
+ I1 => \^q\(35),
+ I2 => \^q\(40),
+ I3 => \^q\(36),
+ I4 => \^q\(1),
+ O => \m_payload_i_reg[6]_0\(1)
+ );
+\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"A0A002A2AAAA02A2"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(41),
+ I2 => \^q\(35),
+ I3 => \^q\(40),
+ I4 => \^q\(36),
+ I5 => \^q\(39),
+ O => \m_payload_i_reg[6]_0\(2)
+ );
+\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4747000000FF0000"
+ )
+ port map (
+ I0 => \^q\(39),
+ I1 => \^q\(35),
+ I2 => \^q\(40),
+ I3 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
+ I4 => \^q\(3),
+ I5 => \^q\(36),
+ O => \m_payload_i_reg[6]_0\(3)
+ );
+\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^q\(41),
+ I1 => \^q\(35),
+ I2 => \^q\(42),
+ O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
+ );
+\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002A0A2AA02AAA2A"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \^q\(42),
+ I2 => \^q\(35),
+ I3 => \^q\(36),
+ I4 => \^q\(41),
+ I5 => \^q\(40),
+ O => \m_payload_i_reg[6]_0\(4)
+ );
+\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"47FF0000"
+ )
+ port map (
+ I0 => \^q\(41),
+ I1 => \^q\(35),
+ I2 => \^q\(42),
+ I3 => \^q\(36),
+ I4 => \^q\(5),
+ O => \m_payload_i_reg[6]_0\(5)
+ );
+\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2AAA"
+ )
+ port map (
+ I0 => \^q\(6),
+ I1 => \^q\(35),
+ I2 => \^q\(36),
+ I3 => \^q\(42),
+ O => \m_payload_i_reg[6]_0\(6)
+ );
+\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"A0AFA0AFA0AFA1AE"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[44]_0\,
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \wrap_cnt_r_reg[0]\,
+ I3 => \wrap_second_len_r_reg[3]_0\(0),
+ I4 => \^m_payload_i_reg[47]_0\,
+ I5 => \^axaddr_offset_r_reg[2]\,
+ O => \wrap_second_len_r_reg[1]\(0)
+ );
+\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \wrap_cnt_r[3]_i_2__0_n_0\,
+ I1 => \^wrap_second_len_r_reg[1]_0\,
+ O => \wrap_second_len_r_reg[1]\(1)
+ );
+\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \wrap_cnt_r[3]_i_2__0_n_0\,
+ I1 => \^wrap_second_len_r_reg[1]_0\,
+ I2 => \^wrap_second_len_r_reg[3]\(1),
+ O => \wrap_second_len_r_reg[1]\(2)
+ );
+\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => \^wrap_second_len_r_reg[1]_0\,
+ I1 => \wrap_cnt_r[3]_i_2__0_n_0\,
+ I2 => \^wrap_second_len_r_reg[3]\(1),
+ I3 => \^wrap_second_len_r_reg[3]\(2),
+ O => \wrap_second_len_r_reg[1]\(3)
+ );
+\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5555FFFC0000AAA8"
+ )
+ port map (
+ I0 => \wrap_cnt_r_reg[0]\,
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^m_payload_i_reg[47]_0\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => \wrap_second_len_r_reg[3]_0\(0),
+ O => \wrap_cnt_r[3]_i_2__0_n_0\
+ );
+\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"33333330AAAAAAAA"
+ )
+ port map (
+ I0 => \wrap_second_len_r_reg[3]_0\(0),
+ I1 => \^m_payload_i_reg[44]_0\,
+ I2 => \^m_payload_i_reg[47]_0\,
+ I3 => \^axaddr_offset_r_reg[2]\,
+ I4 => \^axaddr_offset_r_reg[1]\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len_r_reg[3]\(0)
+ );
+\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FF0000FCAAAAAAAA"
+ )
+ port map (
+ I0 => \wrap_second_len_r_reg[3]_0\(1),
+ I1 => \^m_payload_i_reg[47]_0\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^axaddr_offset_r_reg[1]\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len_r_reg[1]_0\
+ );
+\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0F0F00CAAAAAAAA"
+ )
+ port map (
+ I0 => \wrap_second_len_r_reg[3]_0\(2),
+ I1 => \^m_payload_i_reg[47]_0\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^axaddr_offset_r_reg[1]\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len_r_reg[3]\(1)
+ );
+\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFCAAAA0000AAAA"
+ )
+ port map (
+ I0 => \wrap_second_len_r_reg[3]_0\(3),
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \^m_payload_i_reg[44]_0\,
+ I3 => \^axaddr_offset_r_reg[2]\,
+ I4 => \wrap_cnt_r_reg[0]\,
+ I5 => \^m_payload_i_reg[47]_0\,
+ O => \^wrap_second_len_r_reg[3]\(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0 is
+ port (
+ s_ready_i_reg_0 : out STD_LOGIC;
+ \aresetn_d_reg[0]_0\ : out STD_LOGIC;
+ m_valid_i_reg_0 : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[44]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[1]\ : out STD_LOGIC;
+ \m_payload_i_reg[47]_0\ : out STD_LOGIC;
+ \axaddr_offset_r_reg[2]\ : out STD_LOGIC;
+ axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \m_payload_i_reg[47]_1\ : out STD_LOGIC;
+ \m_payload_i_reg[61]_0\ : out STD_LOGIC_VECTOR ( 54 downto 0 );
+ \wrap_second_len_r_reg[1]\ : out STD_LOGIC;
+ wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ \m_payload_i_reg[47]_2\ : out STD_LOGIC;
+ \m_payload_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]_0\ : out STD_LOGIC;
+ \m_payload_i_reg[38]_0\ : out STD_LOGIC;
+ \aresetn_d_reg[0]_1\ : out STD_LOGIC;
+ aclk : in STD_LOGIC;
+ m_valid_i_reg_1 : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+ \wrap_cnt_r_reg[0]\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ b_push : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ S : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_offset_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ \m_axi_awaddr[11]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_awaddr[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_awaddr[11]_1\ : in STD_LOGIC;
+ sel_first_1 : in STD_LOGIC;
+ sel_first : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0 : entity is "axi_register_slice_v2_1_19_axic_register_slice";
+end TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0 is
+ signal \^aresetn_d_reg[0]_0\ : STD_LOGIC;
+ signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_5_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_7_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[11]_i_8_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[3]_i_7_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_4_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_5_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_6_n_0\ : STD_LOGIC;
+ signal \axaddr_incr[7]_i_7_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
+ signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
+ signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
+ signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
+ signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
+ signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
+ signal \^m_payload_i_reg[38]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[39]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[44]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[47]_0\ : STD_LOGIC;
+ signal \^m_payload_i_reg[61]_0\ : STD_LOGIC_VECTOR ( 54 downto 0 );
+ signal m_valid_i0 : STD_LOGIC;
+ signal \^m_valid_i_reg_0\ : STD_LOGIC;
+ signal s_ready_i0 : STD_LOGIC;
+ signal \^s_ready_i_reg_0\ : STD_LOGIC;
+ signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
+ signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
+ signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
+ signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
+ signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC;
+ signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2\ : label is "soft_lutpair56";
+ attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair56";
+ attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair84";
+ attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_2\ : label is "soft_lutpair84";
+ attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair79";
+ attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair78";
+ attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair78";
+ attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair77";
+ attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair77";
+ attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair76";
+ attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair76";
+ attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair75";
+ attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair75";
+ attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair74";
+ attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair83";
+ attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair74";
+ attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair73";
+ attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair73";
+ attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair72";
+ attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair72";
+ attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair71";
+ attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair71";
+ attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair70";
+ attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair70";
+ attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair69";
+ attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair83";
+ attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair69";
+ attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair68";
+ attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair68";
+ attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair67";
+ attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair67";
+ attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair66";
+ attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair66";
+ attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair65";
+ attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair65";
+ attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair82";
+ attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair64";
+ attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair64";
+ attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair63";
+ attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair63";
+ attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair82";
+ attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair62";
+ attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair62";
+ attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair61";
+ attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair61";
+ attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair60";
+ attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair60";
+ attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair59";
+ attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair59";
+ attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair58";
+ attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair58";
+ attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair81";
+ attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair57";
+ attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair57";
+ attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair81";
+ attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair80";
+ attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair80";
+ attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair79";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair54";
+ attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair54";
+ attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair55";
+ attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair55";
+begin
+ \aresetn_d_reg[0]_0\ <= \^aresetn_d_reg[0]_0\;
+ \axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
+ \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
+ \m_payload_i_reg[38]_0\ <= \^m_payload_i_reg[38]_0\;
+ \m_payload_i_reg[39]_0\ <= \^m_payload_i_reg[39]_0\;
+ \m_payload_i_reg[44]_0\ <= \^m_payload_i_reg[44]_0\;
+ \m_payload_i_reg[47]_0\ <= \^m_payload_i_reg[47]_0\;
+ \m_payload_i_reg[61]_0\(54 downto 0) <= \^m_payload_i_reg[61]_0\(54 downto 0);
+ m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
+ s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
+ wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0);
+ \wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\;
+\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \aresetn_d_reg_n_0_[0]\,
+ I1 => aresetn,
+ O => \aresetn_d_reg[0]_1\
+ );
+\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => aresetn,
+ Q => \aresetn_d_reg_n_0_[0]\,
+ R => '0'
+ );
+\axaddr_incr[11]_i_5\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(11),
+ O => \axaddr_incr[11]_i_5_n_0\
+ );
+\axaddr_incr[11]_i_6\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(10),
+ O => \axaddr_incr[11]_i_6_n_0\
+ );
+\axaddr_incr[11]_i_7\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(9),
+ O => \axaddr_incr[11]_i_7_n_0\
+ );
+\axaddr_incr[11]_i_8\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(8),
+ O => \axaddr_incr[11]_i_8_n_0\
+ );
+\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(3),
+ O => \axaddr_incr[3]_i_4_n_0\
+ );
+\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"70"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(36),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(2),
+ O => \axaddr_incr[3]_i_5_n_0\
+ );
+\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"4"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(36),
+ I1 => \^m_payload_i_reg[61]_0\(1),
+ O => \axaddr_incr[3]_i_6_n_0\
+ );
+\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(0),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(36),
+ O => \axaddr_incr[3]_i_7_n_0\
+ );
+\axaddr_incr[7]_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(7),
+ O => \axaddr_incr[7]_i_4_n_0\
+ );
+\axaddr_incr[7]_i_5\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(6),
+ O => \axaddr_incr[7]_i_5_n_0\
+ );
+\axaddr_incr[7]_i_6\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(5),
+ O => \axaddr_incr[7]_i_6_n_0\
+ );
+\axaddr_incr[7]_i_7\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(4),
+ O => \axaddr_incr[7]_i_7_n_0\
+ );
+\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[7]_i_2_n_0\,
+ CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
+ CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
+ CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
+ CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => axaddr_incr(11 downto 8),
+ S(3) => \axaddr_incr[11]_i_5_n_0\,
+ S(2) => \axaddr_incr[11]_i_6_n_0\,
+ S(1) => \axaddr_incr[11]_i_7_n_0\,
+ S(0) => \axaddr_incr[11]_i_8_n_0\
+ );
+\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
+ CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
+ CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
+ CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3) => \axaddr_incr[3]_i_4_n_0\,
+ DI(2) => \axaddr_incr[3]_i_5_n_0\,
+ DI(1) => \axaddr_incr[3]_i_6_n_0\,
+ DI(0) => \axaddr_incr[3]_i_7_n_0\,
+ O(3 downto 0) => axaddr_incr(3 downto 0),
+ S(3 downto 0) => S(3 downto 0)
+ );
+\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \axaddr_incr_reg[3]_i_2_n_0\,
+ CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
+ CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
+ CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
+ CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => axaddr_incr(7 downto 4),
+ S(3) => \axaddr_incr[7]_i_4_n_0\,
+ S(2) => \axaddr_incr[7]_i_5_n_0\,
+ S(1) => \axaddr_incr[7]_i_6_n_0\,
+ S(0) => \axaddr_incr[7]_i_7_n_0\
+ );
+\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFF8FFFF00080000"
+ )
+ port map (
+ I0 => \axaddr_offset_r[0]_i_2_n_0\,
+ I1 => \^m_payload_i_reg[61]_0\(39),
+ I2 => \axaddr_offset_r_reg[0]\(1),
+ I3 => \axaddr_offset_r_reg[0]\(0),
+ I4 => \^m_valid_i_reg_0\,
+ I5 => \axaddr_offset_r_reg[3]\(0),
+ O => \^m_payload_i_reg[44]_0\
+ );
+\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FC0CFAFAFC0C0A0A"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(0),
+ I1 => \^m_payload_i_reg[61]_0\(2),
+ I2 => \^m_payload_i_reg[61]_0\(35),
+ I3 => \^m_payload_i_reg[61]_0\(3),
+ I4 => \^m_payload_i_reg[61]_0\(36),
+ I5 => \^m_payload_i_reg[61]_0\(1),
+ O => \axaddr_offset_r[0]_i_2_n_0\
+ );
+\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0AA00AAC0AAC0AA"
+ )
+ port map (
+ I0 => \axaddr_offset_r_reg[3]\(1),
+ I1 => \axaddr_offset_r[1]_i_2_n_0\,
+ I2 => \^m_payload_i_reg[61]_0\(40),
+ I3 => \wrap_cnt_r_reg[0]\,
+ I4 => \axaddr_offset_r[2]_i_2_n_0\,
+ I5 => \^m_payload_i_reg[61]_0\(35),
+ O => \^axaddr_offset_r_reg[1]\
+ );
+\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(3),
+ I1 => \^m_payload_i_reg[61]_0\(36),
+ I2 => \^m_payload_i_reg[61]_0\(1),
+ O => \axaddr_offset_r[1]_i_2_n_0\
+ );
+\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0AA00AAC0AAC0AA"
+ )
+ port map (
+ I0 => \axaddr_offset_r_reg[3]\(2),
+ I1 => \axaddr_offset_r[2]_i_2_n_0\,
+ I2 => \^m_payload_i_reg[61]_0\(41),
+ I3 => \wrap_cnt_r_reg[0]\,
+ I4 => \axaddr_offset_r[2]_i_3_n_0\,
+ I5 => \^m_payload_i_reg[61]_0\(35),
+ O => \^axaddr_offset_r_reg[2]\
+ );
+\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(4),
+ I1 => \^m_payload_i_reg[61]_0\(36),
+ I2 => \^m_payload_i_reg[61]_0\(2),
+ O => \axaddr_offset_r[2]_i_2_n_0\
+ );
+\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(5),
+ I1 => \^m_payload_i_reg[61]_0\(36),
+ I2 => \^m_payload_i_reg[61]_0\(3),
+ O => \axaddr_offset_r[2]_i_3_n_0\
+ );
+\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFF8FFFF00080000"
+ )
+ port map (
+ I0 => \axaddr_offset_r[3]_i_2_n_0\,
+ I1 => \^m_payload_i_reg[61]_0\(42),
+ I2 => \axaddr_offset_r_reg[0]\(1),
+ I3 => \axaddr_offset_r_reg[0]\(0),
+ I4 => \^m_valid_i_reg_0\,
+ I5 => \axaddr_offset_r_reg[3]\(3),
+ O => \^m_payload_i_reg[47]_0\
+ );
+\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFCCF0AA00CCF0AA"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(3),
+ I1 => \^m_payload_i_reg[61]_0\(5),
+ I2 => \^m_payload_i_reg[61]_0\(4),
+ I3 => \^m_payload_i_reg[61]_0\(35),
+ I4 => \^m_payload_i_reg[61]_0\(36),
+ I5 => \^m_payload_i_reg[61]_0\(6),
+ O => \axaddr_offset_r[3]_i_2_n_0\
+ );
+\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0008"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(42),
+ I1 => \^m_valid_i_reg_0\,
+ I2 => \axaddr_offset_r_reg[0]\(0),
+ I3 => \axaddr_offset_r_reg[0]\(1),
+ O => \m_payload_i_reg[47]_2\
+ );
+\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[39]_0\,
+ I1 => \m_axi_awaddr[11]\(0),
+ I2 => \^m_payload_i_reg[38]_0\,
+ I3 => \m_axi_awaddr[11]_0\(0),
+ I4 => \^m_payload_i_reg[61]_0\(11),
+ I5 => \m_axi_awaddr[11]_1\,
+ O => m_axi_awaddr(0)
+ );
+\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(38),
+ I1 => sel_first,
+ O => \^m_payload_i_reg[39]_0\
+ );
+\m_axi_awaddr[11]_INST_0_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(37),
+ I1 => sel_first_1,
+ I2 => \^m_payload_i_reg[61]_0\(38),
+ O => \^m_payload_i_reg[38]_0\
+ );
+\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[0]\,
+ O => skid_buffer(0)
+ );
+\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[10]\,
+ O => skid_buffer(10)
+ );
+\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[11]\,
+ O => skid_buffer(11)
+ );
+\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(12),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[12]\,
+ O => skid_buffer(12)
+ );
+\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(13),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[13]\,
+ O => skid_buffer(13)
+ );
+\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(14),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[14]\,
+ O => skid_buffer(14)
+ );
+\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(15),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[15]\,
+ O => skid_buffer(15)
+ );
+\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(16),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[16]\,
+ O => skid_buffer(16)
+ );
+\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(17),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[17]\,
+ O => skid_buffer(17)
+ );
+\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(18),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[18]\,
+ O => skid_buffer(18)
+ );
+\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(19),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[19]\,
+ O => skid_buffer(19)
+ );
+\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[1]\,
+ O => skid_buffer(1)
+ );
+\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(20),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[20]\,
+ O => skid_buffer(20)
+ );
+\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(21),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[21]\,
+ O => skid_buffer(21)
+ );
+\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(22),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[22]\,
+ O => skid_buffer(22)
+ );
+\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(23),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[23]\,
+ O => skid_buffer(23)
+ );
+\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(24),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[24]\,
+ O => skid_buffer(24)
+ );
+\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(25),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[25]\,
+ O => skid_buffer(25)
+ );
+\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(26),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[26]\,
+ O => skid_buffer(26)
+ );
+\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(27),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[27]\,
+ O => skid_buffer(27)
+ );
+\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(28),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[28]\,
+ O => skid_buffer(28)
+ );
+\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(29),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[29]\,
+ O => skid_buffer(29)
+ );
+\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[2]\,
+ O => skid_buffer(2)
+ );
+\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(30),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[30]\,
+ O => skid_buffer(30)
+ );
+\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(31),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[31]\,
+ O => skid_buffer(31)
+ );
+\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awprot(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[32]\,
+ O => skid_buffer(32)
+ );
+\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awprot(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[33]\,
+ O => skid_buffer(33)
+ );
+\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awprot(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[34]\,
+ O => skid_buffer(34)
+ );
+\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awsize(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[35]\,
+ O => skid_buffer(35)
+ );
+\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awsize(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[36]\,
+ O => skid_buffer(36)
+ );
+\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awburst(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[38]\,
+ O => skid_buffer(38)
+ );
+\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awburst(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[39]\,
+ O => skid_buffer(39)
+ );
+\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[3]\,
+ O => skid_buffer(3)
+ );
+\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awlen(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[44]\,
+ O => skid_buffer(44)
+ );
+\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awlen(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[45]\,
+ O => skid_buffer(45)
+ );
+\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awlen(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[46]\,
+ O => skid_buffer(46)
+ );
+\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awlen(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[47]\,
+ O => skid_buffer(47)
+ );
+\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[4]\,
+ O => skid_buffer(4)
+ );
+\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[50]\,
+ O => skid_buffer(50)
+ );
+\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[51]\,
+ O => skid_buffer(51)
+ );
+\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[52]\,
+ O => skid_buffer(52)
+ );
+\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[53]\,
+ O => skid_buffer(53)
+ );
+\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[54]\,
+ O => skid_buffer(54)
+ );
+\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[55]\,
+ O => skid_buffer(55)
+ );
+\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[56]\,
+ O => skid_buffer(56)
+ );
+\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[57]\,
+ O => skid_buffer(57)
+ );
+\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[58]\,
+ O => skid_buffer(58)
+ );
+\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[59]\,
+ O => skid_buffer(59)
+ );
+\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[5]\,
+ O => skid_buffer(5)
+ );
+\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[60]\,
+ O => skid_buffer(60)
+ );
+\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awid(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[61]\,
+ O => skid_buffer(61)
+ );
+\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[6]\,
+ O => skid_buffer(6)
+ );
+\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[7]\,
+ O => skid_buffer(7)
+ );
+\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[8]\,
+ O => skid_buffer(8)
+ );
+\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_awaddr(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[9]\,
+ O => skid_buffer(9)
+ );
+\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(0),
+ Q => \^m_payload_i_reg[61]_0\(0),
+ R => '0'
+ );
+\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(10),
+ Q => \^m_payload_i_reg[61]_0\(10),
+ R => '0'
+ );
+\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(11),
+ Q => \^m_payload_i_reg[61]_0\(11),
+ R => '0'
+ );
+\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(12),
+ Q => \^m_payload_i_reg[61]_0\(12),
+ R => '0'
+ );
+\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(13),
+ Q => \^m_payload_i_reg[61]_0\(13),
+ R => '0'
+ );
+\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(14),
+ Q => \^m_payload_i_reg[61]_0\(14),
+ R => '0'
+ );
+\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(15),
+ Q => \^m_payload_i_reg[61]_0\(15),
+ R => '0'
+ );
+\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(16),
+ Q => \^m_payload_i_reg[61]_0\(16),
+ R => '0'
+ );
+\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(17),
+ Q => \^m_payload_i_reg[61]_0\(17),
+ R => '0'
+ );
+\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(18),
+ Q => \^m_payload_i_reg[61]_0\(18),
+ R => '0'
+ );
+\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(19),
+ Q => \^m_payload_i_reg[61]_0\(19),
+ R => '0'
+ );
+\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(1),
+ Q => \^m_payload_i_reg[61]_0\(1),
+ R => '0'
+ );
+\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(20),
+ Q => \^m_payload_i_reg[61]_0\(20),
+ R => '0'
+ );
+\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(21),
+ Q => \^m_payload_i_reg[61]_0\(21),
+ R => '0'
+ );
+\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(22),
+ Q => \^m_payload_i_reg[61]_0\(22),
+ R => '0'
+ );
+\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(23),
+ Q => \^m_payload_i_reg[61]_0\(23),
+ R => '0'
+ );
+\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(24),
+ Q => \^m_payload_i_reg[61]_0\(24),
+ R => '0'
+ );
+\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(25),
+ Q => \^m_payload_i_reg[61]_0\(25),
+ R => '0'
+ );
+\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(26),
+ Q => \^m_payload_i_reg[61]_0\(26),
+ R => '0'
+ );
+\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(27),
+ Q => \^m_payload_i_reg[61]_0\(27),
+ R => '0'
+ );
+\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(28),
+ Q => \^m_payload_i_reg[61]_0\(28),
+ R => '0'
+ );
+\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(29),
+ Q => \^m_payload_i_reg[61]_0\(29),
+ R => '0'
+ );
+\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(2),
+ Q => \^m_payload_i_reg[61]_0\(2),
+ R => '0'
+ );
+\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(30),
+ Q => \^m_payload_i_reg[61]_0\(30),
+ R => '0'
+ );
+\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(31),
+ Q => \^m_payload_i_reg[61]_0\(31),
+ R => '0'
+ );
+\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(32),
+ Q => \^m_payload_i_reg[61]_0\(32),
+ R => '0'
+ );
+\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(33),
+ Q => \^m_payload_i_reg[61]_0\(33),
+ R => '0'
+ );
+\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(34),
+ Q => \^m_payload_i_reg[61]_0\(34),
+ R => '0'
+ );
+\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(35),
+ Q => \^m_payload_i_reg[61]_0\(35),
+ R => '0'
+ );
+\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(36),
+ Q => \^m_payload_i_reg[61]_0\(36),
+ R => '0'
+ );
+\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(38),
+ Q => \^m_payload_i_reg[61]_0\(37),
+ R => '0'
+ );
+\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(39),
+ Q => \^m_payload_i_reg[61]_0\(38),
+ R => '0'
+ );
+\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(3),
+ Q => \^m_payload_i_reg[61]_0\(3),
+ R => '0'
+ );
+\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(44),
+ Q => \^m_payload_i_reg[61]_0\(39),
+ R => '0'
+ );
+\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(45),
+ Q => \^m_payload_i_reg[61]_0\(40),
+ R => '0'
+ );
+\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(46),
+ Q => \^m_payload_i_reg[61]_0\(41),
+ R => '0'
+ );
+\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(47),
+ Q => \^m_payload_i_reg[61]_0\(42),
+ R => '0'
+ );
+\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(4),
+ Q => \^m_payload_i_reg[61]_0\(4),
+ R => '0'
+ );
+\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(50),
+ Q => \^m_payload_i_reg[61]_0\(43),
+ R => '0'
+ );
+\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(51),
+ Q => \^m_payload_i_reg[61]_0\(44),
+ R => '0'
+ );
+\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(52),
+ Q => \^m_payload_i_reg[61]_0\(45),
+ R => '0'
+ );
+\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(53),
+ Q => \^m_payload_i_reg[61]_0\(46),
+ R => '0'
+ );
+\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(54),
+ Q => \^m_payload_i_reg[61]_0\(47),
+ R => '0'
+ );
+\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(55),
+ Q => \^m_payload_i_reg[61]_0\(48),
+ R => '0'
+ );
+\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(56),
+ Q => \^m_payload_i_reg[61]_0\(49),
+ R => '0'
+ );
+\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(57),
+ Q => \^m_payload_i_reg[61]_0\(50),
+ R => '0'
+ );
+\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(58),
+ Q => \^m_payload_i_reg[61]_0\(51),
+ R => '0'
+ );
+\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(59),
+ Q => \^m_payload_i_reg[61]_0\(52),
+ R => '0'
+ );
+\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(5),
+ Q => \^m_payload_i_reg[61]_0\(5),
+ R => '0'
+ );
+\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(60),
+ Q => \^m_payload_i_reg[61]_0\(53),
+ R => '0'
+ );
+\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(61),
+ Q => \^m_payload_i_reg[61]_0\(54),
+ R => '0'
+ );
+\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(6),
+ Q => \^m_payload_i_reg[61]_0\(6),
+ R => '0'
+ );
+\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(7),
+ Q => \^m_payload_i_reg[61]_0\(7),
+ R => '0'
+ );
+\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(8),
+ Q => \^m_payload_i_reg[61]_0\(8),
+ R => '0'
+ );
+\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => E(0),
+ D => skid_buffer(9),
+ Q => \^m_payload_i_reg[61]_0\(9),
+ R => '0'
+ );
+\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF4F"
+ )
+ port map (
+ I0 => b_push,
+ I1 => \^m_valid_i_reg_0\,
+ I2 => \^s_ready_i_reg_0\,
+ I3 => s_axi_awvalid,
+ O => m_valid_i0
+ );
+m_valid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_valid_i0,
+ Q => \^m_valid_i_reg_0\,
+ R => m_valid_i_reg_1
+ );
+next_pending_r_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFE0000"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(42),
+ I1 => \^m_payload_i_reg[61]_0\(39),
+ I2 => \^m_payload_i_reg[61]_0\(40),
+ I3 => \^m_payload_i_reg[61]_0\(41),
+ I4 => \wrap_cnt_r_reg[0]\,
+ O => \m_payload_i_reg[47]_1\
+ );
+\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \aresetn_d_reg_n_0_[0]\,
+ O => \^aresetn_d_reg[0]_0\
+ );
+s_ready_i_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BFBB"
+ )
+ port map (
+ I0 => b_push,
+ I1 => \^m_valid_i_reg_0\,
+ I2 => s_axi_awvalid,
+ I3 => \^s_ready_i_reg_0\,
+ O => s_ready_i0
+ );
+s_ready_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => s_ready_i0,
+ Q => \^s_ready_i_reg_0\,
+ R => \^aresetn_d_reg[0]_0\
+ );
+\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(0),
+ Q => \skid_buffer_reg_n_0_[0]\,
+ R => '0'
+ );
+\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(10),
+ Q => \skid_buffer_reg_n_0_[10]\,
+ R => '0'
+ );
+\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(11),
+ Q => \skid_buffer_reg_n_0_[11]\,
+ R => '0'
+ );
+\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(12),
+ Q => \skid_buffer_reg_n_0_[12]\,
+ R => '0'
+ );
+\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(13),
+ Q => \skid_buffer_reg_n_0_[13]\,
+ R => '0'
+ );
+\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(14),
+ Q => \skid_buffer_reg_n_0_[14]\,
+ R => '0'
+ );
+\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(15),
+ Q => \skid_buffer_reg_n_0_[15]\,
+ R => '0'
+ );
+\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(16),
+ Q => \skid_buffer_reg_n_0_[16]\,
+ R => '0'
+ );
+\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(17),
+ Q => \skid_buffer_reg_n_0_[17]\,
+ R => '0'
+ );
+\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(18),
+ Q => \skid_buffer_reg_n_0_[18]\,
+ R => '0'
+ );
+\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(19),
+ Q => \skid_buffer_reg_n_0_[19]\,
+ R => '0'
+ );
+\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(1),
+ Q => \skid_buffer_reg_n_0_[1]\,
+ R => '0'
+ );
+\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(20),
+ Q => \skid_buffer_reg_n_0_[20]\,
+ R => '0'
+ );
+\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(21),
+ Q => \skid_buffer_reg_n_0_[21]\,
+ R => '0'
+ );
+\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(22),
+ Q => \skid_buffer_reg_n_0_[22]\,
+ R => '0'
+ );
+\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(23),
+ Q => \skid_buffer_reg_n_0_[23]\,
+ R => '0'
+ );
+\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(24),
+ Q => \skid_buffer_reg_n_0_[24]\,
+ R => '0'
+ );
+\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(25),
+ Q => \skid_buffer_reg_n_0_[25]\,
+ R => '0'
+ );
+\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(26),
+ Q => \skid_buffer_reg_n_0_[26]\,
+ R => '0'
+ );
+\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(27),
+ Q => \skid_buffer_reg_n_0_[27]\,
+ R => '0'
+ );
+\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(28),
+ Q => \skid_buffer_reg_n_0_[28]\,
+ R => '0'
+ );
+\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(29),
+ Q => \skid_buffer_reg_n_0_[29]\,
+ R => '0'
+ );
+\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(2),
+ Q => \skid_buffer_reg_n_0_[2]\,
+ R => '0'
+ );
+\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(30),
+ Q => \skid_buffer_reg_n_0_[30]\,
+ R => '0'
+ );
+\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(31),
+ Q => \skid_buffer_reg_n_0_[31]\,
+ R => '0'
+ );
+\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awprot(0),
+ Q => \skid_buffer_reg_n_0_[32]\,
+ R => '0'
+ );
+\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awprot(1),
+ Q => \skid_buffer_reg_n_0_[33]\,
+ R => '0'
+ );
+\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awprot(2),
+ Q => \skid_buffer_reg_n_0_[34]\,
+ R => '0'
+ );
+\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awsize(0),
+ Q => \skid_buffer_reg_n_0_[35]\,
+ R => '0'
+ );
+\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awsize(1),
+ Q => \skid_buffer_reg_n_0_[36]\,
+ R => '0'
+ );
+\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awburst(0),
+ Q => \skid_buffer_reg_n_0_[38]\,
+ R => '0'
+ );
+\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awburst(1),
+ Q => \skid_buffer_reg_n_0_[39]\,
+ R => '0'
+ );
+\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(3),
+ Q => \skid_buffer_reg_n_0_[3]\,
+ R => '0'
+ );
+\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awlen(0),
+ Q => \skid_buffer_reg_n_0_[44]\,
+ R => '0'
+ );
+\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awlen(1),
+ Q => \skid_buffer_reg_n_0_[45]\,
+ R => '0'
+ );
+\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awlen(2),
+ Q => \skid_buffer_reg_n_0_[46]\,
+ R => '0'
+ );
+\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awlen(3),
+ Q => \skid_buffer_reg_n_0_[47]\,
+ R => '0'
+ );
+\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(4),
+ Q => \skid_buffer_reg_n_0_[4]\,
+ R => '0'
+ );
+\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(0),
+ Q => \skid_buffer_reg_n_0_[50]\,
+ R => '0'
+ );
+\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(1),
+ Q => \skid_buffer_reg_n_0_[51]\,
+ R => '0'
+ );
+\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(2),
+ Q => \skid_buffer_reg_n_0_[52]\,
+ R => '0'
+ );
+\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(3),
+ Q => \skid_buffer_reg_n_0_[53]\,
+ R => '0'
+ );
+\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(4),
+ Q => \skid_buffer_reg_n_0_[54]\,
+ R => '0'
+ );
+\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(5),
+ Q => \skid_buffer_reg_n_0_[55]\,
+ R => '0'
+ );
+\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(6),
+ Q => \skid_buffer_reg_n_0_[56]\,
+ R => '0'
+ );
+\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(7),
+ Q => \skid_buffer_reg_n_0_[57]\,
+ R => '0'
+ );
+\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(8),
+ Q => \skid_buffer_reg_n_0_[58]\,
+ R => '0'
+ );
+\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(9),
+ Q => \skid_buffer_reg_n_0_[59]\,
+ R => '0'
+ );
+\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(5),
+ Q => \skid_buffer_reg_n_0_[5]\,
+ R => '0'
+ );
+\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(10),
+ Q => \skid_buffer_reg_n_0_[60]\,
+ R => '0'
+ );
+\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awid(11),
+ Q => \skid_buffer_reg_n_0_[61]\,
+ R => '0'
+ );
+\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(6),
+ Q => \skid_buffer_reg_n_0_[6]\,
+ R => '0'
+ );
+\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(7),
+ Q => \skid_buffer_reg_n_0_[7]\,
+ R => '0'
+ );
+\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(8),
+ Q => \skid_buffer_reg_n_0_[8]\,
+ R => '0'
+ );
+\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => s_axi_awaddr(9),
+ Q => \skid_buffer_reg_n_0_[9]\,
+ R => '0'
+ );
+\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AA8A"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(0),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(39),
+ I3 => \^m_payload_i_reg[61]_0\(36),
+ O => \m_payload_i_reg[6]_0\(0)
+ );
+\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF470000"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(39),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(40),
+ I3 => \^m_payload_i_reg[61]_0\(36),
+ I4 => \^m_payload_i_reg[61]_0\(1),
+ O => \m_payload_i_reg[6]_0\(1)
+ );
+\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"A0A002A2AAAA02A2"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(2),
+ I1 => \^m_payload_i_reg[61]_0\(41),
+ I2 => \^m_payload_i_reg[61]_0\(35),
+ I3 => \^m_payload_i_reg[61]_0\(40),
+ I4 => \^m_payload_i_reg[61]_0\(36),
+ I5 => \^m_payload_i_reg[61]_0\(39),
+ O => \m_payload_i_reg[6]_0\(2)
+ );
+\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4747000000FF0000"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(39),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(40),
+ I3 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
+ I4 => \^m_payload_i_reg[61]_0\(3),
+ I5 => \^m_payload_i_reg[61]_0\(36),
+ O => \m_payload_i_reg[6]_0\(3)
+ );
+\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(41),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(42),
+ O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
+ );
+\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002A0A2AA02AAA2A"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(4),
+ I1 => \^m_payload_i_reg[61]_0\(42),
+ I2 => \^m_payload_i_reg[61]_0\(35),
+ I3 => \^m_payload_i_reg[61]_0\(36),
+ I4 => \^m_payload_i_reg[61]_0\(41),
+ I5 => \^m_payload_i_reg[61]_0\(40),
+ O => \m_payload_i_reg[6]_0\(4)
+ );
+\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"47FF0000"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(41),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(42),
+ I3 => \^m_payload_i_reg[61]_0\(36),
+ I4 => \^m_payload_i_reg[61]_0\(5),
+ O => \m_payload_i_reg[6]_0\(5)
+ );
+\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2AAA"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[61]_0\(6),
+ I1 => \^m_payload_i_reg[61]_0\(35),
+ I2 => \^m_payload_i_reg[61]_0\(36),
+ I3 => \^m_payload_i_reg[61]_0\(42),
+ O => \m_payload_i_reg[6]_0\(6)
+ );
+\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"A0AFA0AFA0AFA1AE"
+ )
+ port map (
+ I0 => \^m_payload_i_reg[44]_0\,
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \wrap_cnt_r_reg[0]\,
+ I3 => Q(0),
+ I4 => \^m_payload_i_reg[47]_0\,
+ I5 => \^axaddr_offset_r_reg[2]\,
+ O => D(0)
+ );
+\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \wrap_cnt_r[3]_i_2_n_0\,
+ I1 => \^wrap_second_len_r_reg[1]\,
+ O => D(1)
+ );
+\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \wrap_cnt_r[3]_i_2_n_0\,
+ I1 => \^wrap_second_len_r_reg[1]\,
+ I2 => \^wrap_second_len\(1),
+ O => D(2)
+ );
+\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => \^wrap_second_len_r_reg[1]\,
+ I1 => \wrap_cnt_r[3]_i_2_n_0\,
+ I2 => \^wrap_second_len\(1),
+ I3 => \^wrap_second_len\(2),
+ O => D(3)
+ );
+\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5555FFFC0000AAA8"
+ )
+ port map (
+ I0 => \wrap_cnt_r_reg[0]\,
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^m_payload_i_reg[47]_0\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => Q(0),
+ O => \wrap_cnt_r[3]_i_2_n_0\
+ );
+\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"33333330AAAAAAAA"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^m_payload_i_reg[44]_0\,
+ I2 => \^m_payload_i_reg[47]_0\,
+ I3 => \^axaddr_offset_r_reg[2]\,
+ I4 => \^axaddr_offset_r_reg[1]\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len\(0)
+ );
+\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FF0000FCAAAAAAAA"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \^m_payload_i_reg[47]_0\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^axaddr_offset_r_reg[1]\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len_r_reg[1]\
+ );
+\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F0F0F00CAAAAAAAA"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^m_payload_i_reg[47]_0\,
+ I2 => \^axaddr_offset_r_reg[2]\,
+ I3 => \^axaddr_offset_r_reg[1]\,
+ I4 => \^m_payload_i_reg[44]_0\,
+ I5 => \wrap_cnt_r_reg[0]\,
+ O => \^wrap_second_len\(1)
+ );
+\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFCAAAA0000AAAA"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => \^axaddr_offset_r_reg[1]\,
+ I2 => \^m_payload_i_reg[44]_0\,
+ I3 => \^axaddr_offset_r_reg[2]\,
+ I4 => \wrap_cnt_r_reg[0]\,
+ I5 => \^m_payload_i_reg[47]_0\,
+ O => \^wrap_second_len\(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1\ is
+ port (
+ m_valid_i_reg_0 : out STD_LOGIC;
+ s_ready_i_reg_0 : out STD_LOGIC;
+ \m_payload_i_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
+ m_valid_i_reg_1 : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ s_ready_i_reg_1 : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ si_rs_bvalid : in STD_LOGIC;
+ \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \skid_buffer_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_19_axic_register_slice";
+end \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1\;
+
+architecture STRUCTURE of \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1\ is
+ signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
+ signal m_valid_i0 : STD_LOGIC;
+ signal \^m_valid_i_reg_0\ : STD_LOGIC;
+ signal p_1_in : STD_LOGIC;
+ signal s_ready_i0 : STD_LOGIC;
+ signal \^s_ready_i_reg_0\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair91";
+ attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair86";
+ attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair85";
+ attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair86";
+ attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair85";
+ attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair91";
+ attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair90";
+ attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair90";
+ attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair89";
+ attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair89";
+ attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair88";
+ attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair88";
+ attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair87";
+ attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair87";
+begin
+ m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
+ s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
+\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[1]_0\(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[0]\,
+ O => \m_payload_i[0]_i_1__1_n_0\
+ );
+\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[10]\,
+ O => \m_payload_i[10]_i_1__1_n_0\
+ );
+\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[11]\,
+ O => \m_payload_i[11]_i_1__1_n_0\
+ );
+\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[12]\,
+ O => \m_payload_i[12]_i_1__1_n_0\
+ );
+\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s_axi_bready,
+ I1 => \^m_valid_i_reg_0\,
+ O => p_1_in
+ );
+\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[13]\,
+ O => \m_payload_i[13]_i_2_n_0\
+ );
+\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[1]_0\(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[1]\,
+ O => \m_payload_i[1]_i_1__1_n_0\
+ );
+\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[2]\,
+ O => \m_payload_i[2]_i_1__1_n_0\
+ );
+\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[3]\,
+ O => \m_payload_i[3]_i_1__1_n_0\
+ );
+\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[4]\,
+ O => \m_payload_i[4]_i_1__1_n_0\
+ );
+\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[5]\,
+ O => \m_payload_i[5]_i_1__1_n_0\
+ );
+\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[6]\,
+ O => \m_payload_i[6]_i_1__1_n_0\
+ );
+\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[7]\,
+ O => \m_payload_i[7]_i_1__1_n_0\
+ );
+\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[8]\,
+ O => \m_payload_i[8]_i_1__1_n_0\
+ );
+\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \out\(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[9]\,
+ O => \m_payload_i[9]_i_1__1_n_0\
+ );
+\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[0]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(0),
+ R => '0'
+ );
+\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[10]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(10),
+ R => '0'
+ );
+\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[11]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(11),
+ R => '0'
+ );
+\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[12]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(12),
+ R => '0'
+ );
+\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[13]_i_2_n_0\,
+ Q => \m_payload_i_reg[13]_0\(13),
+ R => '0'
+ );
+\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[1]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(1),
+ R => '0'
+ );
+\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[2]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(2),
+ R => '0'
+ );
+\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[3]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(3),
+ R => '0'
+ );
+\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[4]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(4),
+ R => '0'
+ );
+\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[5]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(5),
+ R => '0'
+ );
+\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[6]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(6),
+ R => '0'
+ );
+\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[7]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(7),
+ R => '0'
+ );
+\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[8]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(8),
+ R => '0'
+ );
+\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[9]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[13]_0\(9),
+ R => '0'
+ );
+\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF4F"
+ )
+ port map (
+ I0 => s_axi_bready,
+ I1 => \^m_valid_i_reg_0\,
+ I2 => \^s_ready_i_reg_0\,
+ I3 => si_rs_bvalid,
+ O => m_valid_i0
+ );
+m_valid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_valid_i0,
+ Q => \^m_valid_i_reg_0\,
+ R => m_valid_i_reg_1
+ );
+\s_ready_i_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF4F"
+ )
+ port map (
+ I0 => si_rs_bvalid,
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \^m_valid_i_reg_0\,
+ I3 => s_axi_bready,
+ O => s_ready_i0
+ );
+s_ready_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => s_ready_i0,
+ Q => \^s_ready_i_reg_0\,
+ R => s_ready_i_reg_1
+ );
+\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[1]_0\(0),
+ Q => \skid_buffer_reg_n_0_[0]\,
+ R => '0'
+ );
+\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(8),
+ Q => \skid_buffer_reg_n_0_[10]\,
+ R => '0'
+ );
+\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(9),
+ Q => \skid_buffer_reg_n_0_[11]\,
+ R => '0'
+ );
+\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(10),
+ Q => \skid_buffer_reg_n_0_[12]\,
+ R => '0'
+ );
+\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(11),
+ Q => \skid_buffer_reg_n_0_[13]\,
+ R => '0'
+ );
+\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[1]_0\(1),
+ Q => \skid_buffer_reg_n_0_[1]\,
+ R => '0'
+ );
+\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(0),
+ Q => \skid_buffer_reg_n_0_[2]\,
+ R => '0'
+ );
+\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(1),
+ Q => \skid_buffer_reg_n_0_[3]\,
+ R => '0'
+ );
+\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(2),
+ Q => \skid_buffer_reg_n_0_[4]\,
+ R => '0'
+ );
+\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(3),
+ Q => \skid_buffer_reg_n_0_[5]\,
+ R => '0'
+ );
+\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(4),
+ Q => \skid_buffer_reg_n_0_[6]\,
+ R => '0'
+ );
+\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(5),
+ Q => \skid_buffer_reg_n_0_[7]\,
+ R => '0'
+ );
+\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(6),
+ Q => \skid_buffer_reg_n_0_[8]\,
+ R => '0'
+ );
+\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \out\(7),
+ Q => \skid_buffer_reg_n_0_[9]\,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2\ is
+ port (
+ m_valid_i_reg_0 : out STD_LOGIC;
+ s_ready_i_reg_0 : out STD_LOGIC;
+ \m_payload_i_reg[46]_0\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
+ m_valid_i_reg_1 : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ s_ready_i_reg_1 : in STD_LOGIC;
+ si_rs_rvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ \skid_buffer_reg[46]_0\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
+ \skid_buffer_reg[33]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_19_axic_register_slice";
+end \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2\;
+
+architecture STRUCTURE of \TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2\ is
+ signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[31]_i_1__0_n_0\ : STD_LOGIC;
+ signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
+ signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
+ signal m_valid_i0 : STD_LOGIC;
+ signal \^m_valid_i_reg_0\ : STD_LOGIC;
+ signal p_1_in : STD_LOGIC;
+ signal s_ready_i0 : STD_LOGIC;
+ signal \^s_ready_i_reg_0\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
+ signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair110";
+ attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair109";
+ attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair109";
+ attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair108";
+ attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair108";
+ attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair107";
+ attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair107";
+ attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair106";
+ attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair106";
+ attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair105";
+ attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair114";
+ attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair105";
+ attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair104";
+ attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair104";
+ attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair103";
+ attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair103";
+ attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair102";
+ attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair102";
+ attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair101";
+ attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair101";
+ attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair100";
+ attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair114";
+ attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair100";
+ attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair99";
+ attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair99";
+ attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair98";
+ attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair98";
+ attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair97";
+ attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair97";
+ attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair96";
+ attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair96";
+ attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair95";
+ attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair113";
+ attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair95";
+ attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair94";
+ attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair94";
+ attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair93";
+ attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair92";
+ attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair93";
+ attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair92";
+ attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair113";
+ attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair112";
+ attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair112";
+ attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
+ attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair111";
+ attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
+begin
+ m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
+ s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
+\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[0]\,
+ O => \m_payload_i[0]_i_1__2_n_0\
+ );
+\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[10]\,
+ O => \m_payload_i[10]_i_1__2_n_0\
+ );
+\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[11]\,
+ O => \m_payload_i[11]_i_1__2_n_0\
+ );
+\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(12),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[12]\,
+ O => \m_payload_i[12]_i_1__2_n_0\
+ );
+\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(13),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[13]\,
+ O => \m_payload_i[13]_i_1__2_n_0\
+ );
+\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(14),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[14]\,
+ O => \m_payload_i[14]_i_1__1_n_0\
+ );
+\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(15),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[15]\,
+ O => \m_payload_i[15]_i_1__1_n_0\
+ );
+\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(16),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[16]\,
+ O => \m_payload_i[16]_i_1__1_n_0\
+ );
+\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(17),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[17]\,
+ O => \m_payload_i[17]_i_1__1_n_0\
+ );
+\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(18),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[18]\,
+ O => \m_payload_i[18]_i_1__1_n_0\
+ );
+\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(19),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[19]\,
+ O => \m_payload_i[19]_i_1__1_n_0\
+ );
+\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[1]\,
+ O => \m_payload_i[1]_i_1__2_n_0\
+ );
+\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(20),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[20]\,
+ O => \m_payload_i[20]_i_1__1_n_0\
+ );
+\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(21),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[21]\,
+ O => \m_payload_i[21]_i_1__1_n_0\
+ );
+\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(22),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[22]\,
+ O => \m_payload_i[22]_i_1__1_n_0\
+ );
+\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(23),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[23]\,
+ O => \m_payload_i[23]_i_1__1_n_0\
+ );
+\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(24),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[24]\,
+ O => \m_payload_i[24]_i_1__1_n_0\
+ );
+\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(25),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[25]\,
+ O => \m_payload_i[25]_i_1__1_n_0\
+ );
+\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(26),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[26]\,
+ O => \m_payload_i[26]_i_1__1_n_0\
+ );
+\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(27),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[27]\,
+ O => \m_payload_i[27]_i_1__1_n_0\
+ );
+\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(28),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[28]\,
+ O => \m_payload_i[28]_i_1__1_n_0\
+ );
+\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(29),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[29]\,
+ O => \m_payload_i[29]_i_1__1_n_0\
+ );
+\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[2]\,
+ O => \m_payload_i[2]_i_1__2_n_0\
+ );
+\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(30),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[30]\,
+ O => \m_payload_i[30]_i_1__1_n_0\
+ );
+\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(31),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[31]\,
+ O => \m_payload_i[31]_i_1__0_n_0\
+ );
+\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(32),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[32]\,
+ O => \m_payload_i[32]_i_1__1_n_0\
+ );
+\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(33),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[33]\,
+ O => \m_payload_i[33]_i_1__1_n_0\
+ );
+\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(0),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[34]\,
+ O => \m_payload_i[34]_i_1__1_n_0\
+ );
+\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(1),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[35]\,
+ O => \m_payload_i[35]_i_1__1_n_0\
+ );
+\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(2),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[36]\,
+ O => \m_payload_i[36]_i_1__1_n_0\
+ );
+\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[37]\,
+ O => \m_payload_i[37]_i_1_n_0\
+ );
+\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[38]\,
+ O => \m_payload_i[38]_i_1__1_n_0\
+ );
+\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[39]\,
+ O => \m_payload_i[39]_i_1__1_n_0\
+ );
+\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(3),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[3]\,
+ O => \m_payload_i[3]_i_1__2_n_0\
+ );
+\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[40]\,
+ O => \m_payload_i[40]_i_1_n_0\
+ );
+\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[41]\,
+ O => \m_payload_i[41]_i_1_n_0\
+ );
+\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[42]\,
+ O => \m_payload_i[42]_i_1_n_0\
+ );
+\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[43]\,
+ O => \m_payload_i[43]_i_1_n_0\
+ );
+\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(10),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[44]\,
+ O => \m_payload_i[44]_i_1__1_n_0\
+ );
+\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(11),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[45]\,
+ O => \m_payload_i[45]_i_1__1_n_0\
+ );
+\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s_axi_rready,
+ I1 => \^m_valid_i_reg_0\,
+ O => p_1_in
+ );
+\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[46]_0\(12),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[46]\,
+ O => \m_payload_i[46]_i_2_n_0\
+ );
+\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(4),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[4]\,
+ O => \m_payload_i[4]_i_1__2_n_0\
+ );
+\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(5),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[5]\,
+ O => \m_payload_i[5]_i_1__2_n_0\
+ );
+\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(6),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[6]\,
+ O => \m_payload_i[6]_i_1__2_n_0\
+ );
+\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(7),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[7]\,
+ O => \m_payload_i[7]_i_1__2_n_0\
+ );
+\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(8),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[8]\,
+ O => \m_payload_i[8]_i_1__2_n_0\
+ );
+\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \skid_buffer_reg[33]_0\(9),
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \skid_buffer_reg_n_0_[9]\,
+ O => \m_payload_i[9]_i_1__2_n_0\
+ );
+\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[0]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(0),
+ R => '0'
+ );
+\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[10]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(10),
+ R => '0'
+ );
+\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[11]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(11),
+ R => '0'
+ );
+\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[12]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(12),
+ R => '0'
+ );
+\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[13]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(13),
+ R => '0'
+ );
+\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[14]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(14),
+ R => '0'
+ );
+\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[15]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(15),
+ R => '0'
+ );
+\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[16]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(16),
+ R => '0'
+ );
+\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[17]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(17),
+ R => '0'
+ );
+\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[18]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(18),
+ R => '0'
+ );
+\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[19]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(19),
+ R => '0'
+ );
+\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[1]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(1),
+ R => '0'
+ );
+\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[20]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(20),
+ R => '0'
+ );
+\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[21]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(21),
+ R => '0'
+ );
+\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[22]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(22),
+ R => '0'
+ );
+\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[23]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(23),
+ R => '0'
+ );
+\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[24]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(24),
+ R => '0'
+ );
+\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[25]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(25),
+ R => '0'
+ );
+\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[26]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(26),
+ R => '0'
+ );
+\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[27]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(27),
+ R => '0'
+ );
+\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[28]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(28),
+ R => '0'
+ );
+\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[29]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(29),
+ R => '0'
+ );
+\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[2]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(2),
+ R => '0'
+ );
+\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[30]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(30),
+ R => '0'
+ );
+\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[31]_i_1__0_n_0\,
+ Q => \m_payload_i_reg[46]_0\(31),
+ R => '0'
+ );
+\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[32]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(32),
+ R => '0'
+ );
+\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[33]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(33),
+ R => '0'
+ );
+\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[34]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(34),
+ R => '0'
+ );
+\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[35]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(35),
+ R => '0'
+ );
+\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[36]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(36),
+ R => '0'
+ );
+\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[37]_i_1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(37),
+ R => '0'
+ );
+\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[38]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(38),
+ R => '0'
+ );
+\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[39]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(39),
+ R => '0'
+ );
+\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[3]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(3),
+ R => '0'
+ );
+\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[40]_i_1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(40),
+ R => '0'
+ );
+\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[41]_i_1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(41),
+ R => '0'
+ );
+\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[42]_i_1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(42),
+ R => '0'
+ );
+\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[43]_i_1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(43),
+ R => '0'
+ );
+\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[44]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(44),
+ R => '0'
+ );
+\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[45]_i_1__1_n_0\,
+ Q => \m_payload_i_reg[46]_0\(45),
+ R => '0'
+ );
+\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[46]_i_2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(46),
+ R => '0'
+ );
+\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[4]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(4),
+ R => '0'
+ );
+\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[5]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(5),
+ R => '0'
+ );
+\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[6]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(6),
+ R => '0'
+ );
+\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[7]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(7),
+ R => '0'
+ );
+\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[8]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(8),
+ R => '0'
+ );
+\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => p_1_in,
+ D => \m_payload_i[9]_i_1__2_n_0\,
+ Q => \m_payload_i_reg[46]_0\(9),
+ R => '0'
+ );
+m_valid_i_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF4F"
+ )
+ port map (
+ I0 => s_axi_rready,
+ I1 => \^m_valid_i_reg_0\,
+ I2 => \^s_ready_i_reg_0\,
+ I3 => si_rs_rvalid,
+ O => m_valid_i0
+ );
+m_valid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_valid_i0,
+ Q => \^m_valid_i_reg_0\,
+ R => m_valid_i_reg_1
+ );
+s_ready_i_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF4F"
+ )
+ port map (
+ I0 => si_rs_rvalid,
+ I1 => \^s_ready_i_reg_0\,
+ I2 => \^m_valid_i_reg_0\,
+ I3 => s_axi_rready,
+ O => s_ready_i0
+ );
+s_ready_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => s_ready_i0,
+ Q => \^s_ready_i_reg_0\,
+ R => s_ready_i_reg_1
+ );
+\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(0),
+ Q => \skid_buffer_reg_n_0_[0]\,
+ R => '0'
+ );
+\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(10),
+ Q => \skid_buffer_reg_n_0_[10]\,
+ R => '0'
+ );
+\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(11),
+ Q => \skid_buffer_reg_n_0_[11]\,
+ R => '0'
+ );
+\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(12),
+ Q => \skid_buffer_reg_n_0_[12]\,
+ R => '0'
+ );
+\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(13),
+ Q => \skid_buffer_reg_n_0_[13]\,
+ R => '0'
+ );
+\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(14),
+ Q => \skid_buffer_reg_n_0_[14]\,
+ R => '0'
+ );
+\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(15),
+ Q => \skid_buffer_reg_n_0_[15]\,
+ R => '0'
+ );
+\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(16),
+ Q => \skid_buffer_reg_n_0_[16]\,
+ R => '0'
+ );
+\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(17),
+ Q => \skid_buffer_reg_n_0_[17]\,
+ R => '0'
+ );
+\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(18),
+ Q => \skid_buffer_reg_n_0_[18]\,
+ R => '0'
+ );
+\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(19),
+ Q => \skid_buffer_reg_n_0_[19]\,
+ R => '0'
+ );
+\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(1),
+ Q => \skid_buffer_reg_n_0_[1]\,
+ R => '0'
+ );
+\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(20),
+ Q => \skid_buffer_reg_n_0_[20]\,
+ R => '0'
+ );
+\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(21),
+ Q => \skid_buffer_reg_n_0_[21]\,
+ R => '0'
+ );
+\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(22),
+ Q => \skid_buffer_reg_n_0_[22]\,
+ R => '0'
+ );
+\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(23),
+ Q => \skid_buffer_reg_n_0_[23]\,
+ R => '0'
+ );
+\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(24),
+ Q => \skid_buffer_reg_n_0_[24]\,
+ R => '0'
+ );
+\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(25),
+ Q => \skid_buffer_reg_n_0_[25]\,
+ R => '0'
+ );
+\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(26),
+ Q => \skid_buffer_reg_n_0_[26]\,
+ R => '0'
+ );
+\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(27),
+ Q => \skid_buffer_reg_n_0_[27]\,
+ R => '0'
+ );
+\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(28),
+ Q => \skid_buffer_reg_n_0_[28]\,
+ R => '0'
+ );
+\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(29),
+ Q => \skid_buffer_reg_n_0_[29]\,
+ R => '0'
+ );
+\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(2),
+ Q => \skid_buffer_reg_n_0_[2]\,
+ R => '0'
+ );
+\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(30),
+ Q => \skid_buffer_reg_n_0_[30]\,
+ R => '0'
+ );
+\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(31),
+ Q => \skid_buffer_reg_n_0_[31]\,
+ R => '0'
+ );
+\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(32),
+ Q => \skid_buffer_reg_n_0_[32]\,
+ R => '0'
+ );
+\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(33),
+ Q => \skid_buffer_reg_n_0_[33]\,
+ R => '0'
+ );
+\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(0),
+ Q => \skid_buffer_reg_n_0_[34]\,
+ R => '0'
+ );
+\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(1),
+ Q => \skid_buffer_reg_n_0_[35]\,
+ R => '0'
+ );
+\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(2),
+ Q => \skid_buffer_reg_n_0_[36]\,
+ R => '0'
+ );
+\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(3),
+ Q => \skid_buffer_reg_n_0_[37]\,
+ R => '0'
+ );
+\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(4),
+ Q => \skid_buffer_reg_n_0_[38]\,
+ R => '0'
+ );
+\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(5),
+ Q => \skid_buffer_reg_n_0_[39]\,
+ R => '0'
+ );
+\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(3),
+ Q => \skid_buffer_reg_n_0_[3]\,
+ R => '0'
+ );
+\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(6),
+ Q => \skid_buffer_reg_n_0_[40]\,
+ R => '0'
+ );
+\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(7),
+ Q => \skid_buffer_reg_n_0_[41]\,
+ R => '0'
+ );
+\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(8),
+ Q => \skid_buffer_reg_n_0_[42]\,
+ R => '0'
+ );
+\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(9),
+ Q => \skid_buffer_reg_n_0_[43]\,
+ R => '0'
+ );
+\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(10),
+ Q => \skid_buffer_reg_n_0_[44]\,
+ R => '0'
+ );
+\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(11),
+ Q => \skid_buffer_reg_n_0_[45]\,
+ R => '0'
+ );
+\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[46]_0\(12),
+ Q => \skid_buffer_reg_n_0_[46]\,
+ R => '0'
+ );
+\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(4),
+ Q => \skid_buffer_reg_n_0_[4]\,
+ R => '0'
+ );
+\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(5),
+ Q => \skid_buffer_reg_n_0_[5]\,
+ R => '0'
+ );
+\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(6),
+ Q => \skid_buffer_reg_n_0_[6]\,
+ R => '0'
+ );
+\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(7),
+ Q => \skid_buffer_reg_n_0_[7]\,
+ R => '0'
+ );
+\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(8),
+ Q => \skid_buffer_reg_n_0_[8]\,
+ R => '0'
+ );
+\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => \^s_ready_i_reg_0\,
+ D => \skid_buffer_reg[33]_0\(9),
+ Q => \skid_buffer_reg_n_0_[9]\,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel is
+ port (
+ si_rs_bvalid : out STD_LOGIC;
+ b_full : out STD_LOGIC;
+ cnt_read : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_bready : out STD_LOGIC;
+ \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \s_bresp_acc_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ areset_d1 : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ si_rs_bready : in STD_LOGIC;
+ m_axi_bvalid : in STD_LOGIC;
+ b_push : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel is
+ signal bid_fifo_0_n_5 : STD_LOGIC;
+ signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
+ signal bresp_cnt_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal bresp_empty : STD_LOGIC;
+ signal bresp_push : STD_LOGIC;
+ signal mhandshake : STD_LOGIC;
+ signal mhandshake_r : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal s_bresp_acc0 : STD_LOGIC;
+ signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
+ signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
+ signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
+ signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
+ signal shandshake : STD_LOGIC;
+ signal shandshake_r : STD_LOGIC;
+ signal \^si_rs_bvalid\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair133";
+ attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair133";
+ attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair132";
+ attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair132";
+ attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair134";
+ attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair134";
+begin
+ si_rs_bvalid <= \^si_rs_bvalid\;
+bid_fifo_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo
+ port map (
+ Q(7 downto 0) => bresp_cnt_reg(7 downto 0),
+ SR(0) => s_bresp_acc0,
+ aclk => aclk,
+ addr(1 downto 0) => cnt_read(1 downto 0),
+ areset_d1 => areset_d1,
+ b_full => b_full,
+ b_push => b_push,
+ bresp_empty => bresp_empty,
+ bresp_push => bresp_push,
+ \in\(15 downto 0) => \in\(15 downto 0),
+ mhandshake_r => mhandshake_r,
+ \out\(11 downto 0) => \out\(11 downto 0),
+ shandshake_r => shandshake_r,
+ shandshake_r_reg => bid_fifo_0_n_5,
+ si_rs_bready => si_rs_bready,
+ si_rs_bvalid => \^si_rs_bvalid\
+ );
+\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => bresp_cnt_reg(0),
+ O => p_0_in(0)
+ );
+\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => bresp_cnt_reg(0),
+ I1 => bresp_cnt_reg(1),
+ O => p_0_in(1)
+ );
+\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => bresp_cnt_reg(0),
+ I1 => bresp_cnt_reg(1),
+ I2 => bresp_cnt_reg(2),
+ O => p_0_in(2)
+ );
+\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => bresp_cnt_reg(1),
+ I1 => bresp_cnt_reg(0),
+ I2 => bresp_cnt_reg(2),
+ I3 => bresp_cnt_reg(3),
+ O => p_0_in(3)
+ );
+\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => bresp_cnt_reg(2),
+ I1 => bresp_cnt_reg(0),
+ I2 => bresp_cnt_reg(1),
+ I3 => bresp_cnt_reg(3),
+ I4 => bresp_cnt_reg(4),
+ O => p_0_in(4)
+ );
+\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF80000000"
+ )
+ port map (
+ I0 => bresp_cnt_reg(3),
+ I1 => bresp_cnt_reg(1),
+ I2 => bresp_cnt_reg(0),
+ I3 => bresp_cnt_reg(2),
+ I4 => bresp_cnt_reg(4),
+ I5 => bresp_cnt_reg(5),
+ O => p_0_in(5)
+ );
+\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \bresp_cnt[7]_i_3_n_0\,
+ I1 => bresp_cnt_reg(6),
+ O => p_0_in(6)
+ );
+\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \bresp_cnt[7]_i_3_n_0\,
+ I1 => bresp_cnt_reg(6),
+ I2 => bresp_cnt_reg(7),
+ O => p_0_in(7)
+ );
+\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => bresp_cnt_reg(5),
+ I1 => bresp_cnt_reg(3),
+ I2 => bresp_cnt_reg(1),
+ I3 => bresp_cnt_reg(0),
+ I4 => bresp_cnt_reg(2),
+ I5 => bresp_cnt_reg(4),
+ O => \bresp_cnt[7]_i_3_n_0\
+ );
+\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(0),
+ Q => bresp_cnt_reg(0),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(1),
+ Q => bresp_cnt_reg(1),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(2),
+ Q => bresp_cnt_reg(2),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(3),
+ Q => bresp_cnt_reg(3),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(4),
+ Q => bresp_cnt_reg(4),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(5),
+ Q => bresp_cnt_reg(5),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(6),
+ Q => bresp_cnt_reg(6),
+ R => s_bresp_acc0
+ );
+\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => mhandshake_r,
+ D => p_0_in(7),
+ Q => bresp_cnt_reg(7),
+ R => s_bresp_acc0
+ );
+bresp_fifo_0: entity work.\TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0\
+ port map (
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ bresp_empty => bresp_empty,
+ bresp_push => bresp_push,
+ \in\(1) => \s_bresp_acc_reg_n_0_[1]\,
+ \in\(0) => \s_bresp_acc_reg_n_0_[0]\,
+ m_axi_bready => m_axi_bready,
+ m_axi_bvalid => m_axi_bvalid,
+ mhandshake => mhandshake,
+ mhandshake_r => mhandshake_r,
+ \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]_0\(1 downto 0),
+ shandshake_r => shandshake_r
+ );
+bvalid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => bid_fifo_0_n_5,
+ Q => \^si_rs_bvalid\,
+ R => '0'
+ );
+mhandshake_r_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => mhandshake,
+ Q => mhandshake_r,
+ R => areset_d1
+ );
+\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000EACECCCC"
+ )
+ port map (
+ I0 => m_axi_bresp(0),
+ I1 => \s_bresp_acc_reg_n_0_[0]\,
+ I2 => \s_bresp_acc_reg_n_0_[1]\,
+ I3 => m_axi_bresp(1),
+ I4 => mhandshake,
+ I5 => s_bresp_acc0,
+ O => \s_bresp_acc[0]_i_1_n_0\
+ );
+\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00EA"
+ )
+ port map (
+ I0 => \s_bresp_acc_reg_n_0_[1]\,
+ I1 => m_axi_bresp(1),
+ I2 => mhandshake,
+ I3 => s_bresp_acc0,
+ O => \s_bresp_acc[1]_i_1_n_0\
+ );
+\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_bresp_acc[0]_i_1_n_0\,
+ Q => \s_bresp_acc_reg_n_0_[0]\,
+ R => '0'
+ );
+\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_bresp_acc[1]_i_1_n_0\,
+ Q => \s_bresp_acc_reg_n_0_[1]\,
+ R => '0'
+ );
+shandshake_r_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \^si_rs_bvalid\,
+ I1 => si_rs_bready,
+ O => shandshake
+ );
+shandshake_r_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => shandshake,
+ Q => shandshake_r,
+ R => areset_d1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator is
+ port (
+ sel_first_reg_0 : out STD_LOGIC;
+ sel_first_reg_1 : out STD_LOGIC;
+ sel_first : out STD_LOGIC;
+ \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[2]\ : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[3]\ : out STD_LOGIC;
+ next_pending : out STD_LOGIC;
+ \axlen_cnt_reg[2]_0\ : out STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg_2 : out STD_LOGIC;
+ \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_i : in STD_LOGIC;
+ sel_first_reg_3 : in STD_LOGIC;
+ sel_first_reg_4 : in STD_LOGIC;
+ \next\ : in STD_LOGIC;
+ \axlen_cnt_reg[2]_1\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
+ next_pending_r_reg : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ si_rs_awvalid : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC;
+ axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_awaddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_awaddr[0]_0\ : in STD_LOGIC;
+ \axaddr_wrap_reg[0]\ : in STD_LOGIC;
+ \axlen_cnt_reg[8]\ : in STD_LOGIC;
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axlen_cnt_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator is
+ signal axaddr_wrap : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal incr_cmd_0_n_3 : STD_LOGIC;
+ signal incr_next_pending : STD_LOGIC;
+ signal m_axi_awaddr_0_sn_1 : STD_LOGIC;
+ signal s_axburst_eq0 : STD_LOGIC;
+ signal s_axburst_eq1 : STD_LOGIC;
+ signal \^sel_first\ : STD_LOGIC;
+ signal wrap_cmd_0_n_14 : STD_LOGIC;
+ signal wrap_next_pending : STD_LOGIC;
+begin
+ m_axi_awaddr_0_sn_1 <= m_axi_awaddr_0_sp_1;
+ sel_first <= \^sel_first\;
+incr_cmd_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd
+ port map (
+ E(0) => E(0),
+ Q(10 downto 0) => axaddr_wrap(10 downto 0),
+ S(3 downto 0) => S(3 downto 0),
+ aclk => aclk,
+ axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
+ \axaddr_incr_reg[11]_0\(0) => \axaddr_incr_reg[11]\(0),
+ \axlen_cnt_reg[0]_0\(1 downto 0) => \axlen_cnt_reg[0]\(1 downto 0),
+ \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\,
+ \axlen_cnt_reg[2]_1\(17 downto 11) => \axlen_cnt_reg[2]_1\(18 downto 12),
+ \axlen_cnt_reg[2]_1\(10 downto 0) => \axlen_cnt_reg[2]_1\(10 downto 0),
+ \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]_0\,
+ \axlen_cnt_reg[4]_0\ => \axaddr_wrap_reg[0]\,
+ \axlen_cnt_reg[8]_0\ => \axlen_cnt_reg[8]\,
+ incr_next_pending => incr_next_pending,
+ m_axi_awaddr(10 downto 0) => m_axi_awaddr(10 downto 0),
+ \m_axi_awaddr[0]_0\ => \m_axi_awaddr[0]_0\,
+ m_axi_awaddr_0_sp_1 => m_axi_awaddr_0_sn_1,
+ \m_payload_i_reg[39]\ => incr_cmd_0_n_3,
+ \next\ => \next\,
+ next_pending_r_reg_0 => next_pending_r_reg,
+ sel_first => \^sel_first\,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => sel_first_reg_1,
+ sel_first_reg_1 => sel_first_reg_2,
+ sel_first_reg_2 => sel_first_reg_3,
+ si_rs_awvalid => si_rs_awvalid,
+ wrap_next_pending => wrap_next_pending
+ );
+\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axburst_eq1,
+ I1 => \axlen_cnt_reg[2]_1\(15),
+ I2 => s_axburst_eq0,
+ O => next_pending
+ );
+s_axburst_eq0_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => incr_cmd_0_n_3,
+ Q => s_axburst_eq0,
+ R => '0'
+ );
+s_axburst_eq1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => wrap_cmd_0_n_14,
+ Q => s_axburst_eq1,
+ R => '0'
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_i,
+ Q => sel_first_reg_0,
+ R => '0'
+ );
+wrap_cmd_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd
+ port map (
+ D(3 downto 0) => D(3 downto 0),
+ E(0) => E(0),
+ Q(11) => \axaddr_wrap_reg[11]\(0),
+ Q(10 downto 0) => axaddr_wrap(10 downto 0),
+ aclk => aclk,
+ \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
+ \axaddr_wrap_reg[0]_0\ => \axaddr_wrap_reg[0]\,
+ \axlen_cnt_reg[0]_0\(0) => Q(0),
+ \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]_0\,
+ \axlen_cnt_reg[2]_1\(16 downto 15) => \axlen_cnt_reg[2]_1\(18 downto 17),
+ \axlen_cnt_reg[2]_1\(14) => \axlen_cnt_reg[2]_1\(15),
+ \axlen_cnt_reg[2]_1\(13 downto 0) => \axlen_cnt_reg[2]_1\(13 downto 0),
+ \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]\,
+ \axlen_cnt_reg[3]_1\(1 downto 0) => \axlen_cnt_reg[3]_1\(1 downto 0),
+ incr_next_pending => incr_next_pending,
+ \m_payload_i_reg[39]\ => wrap_cmd_0_n_14,
+ \next\ => \next\,
+ next_pending_r_reg_0 => next_pending_r_reg,
+ sel_first => \^sel_first\,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => sel_first_reg_4,
+ \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
+ \wrap_cnt_r_reg[3]_0\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0),
+ wrap_next_pending => wrap_next_pending,
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
+ \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1 is
+ port (
+ sel_first_reg_0 : out STD_LOGIC;
+ sel_first_reg_1 : out STD_LOGIC;
+ sel_first_reg_2 : out STD_LOGIC;
+ O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_wrap_reg[11]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axlen_cnt_reg[2]\ : out STD_LOGIC;
+ r_rlast : out STD_LOGIC;
+ next_pending : out STD_LOGIC;
+ \axlen_cnt_reg[4]\ : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg_3 : out STD_LOGIC;
+ \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ sel_first_i : in STD_LOGIC;
+ sel_first_reg_4 : in STD_LOGIC;
+ sel_first_reg_5 : in STD_LOGIC;
+ \axlen_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ next_pending_r_reg : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ r_push : in STD_LOGIC;
+ \axlen_cnt_reg[3]_0\ : in STD_LOGIC;
+ \axaddr_incr_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_araddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_araddr[0]_0\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ si_rs_arvalid : in STD_LOGIC;
+ \axaddr_wrap_reg[0]\ : in STD_LOGIC;
+ \axlen_cnt_reg[8]\ : in STD_LOGIC;
+ axaddr_offset : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ \axaddr_wrap_reg[11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \axaddr_incr_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_arready : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_19_b2s_cmd_translator";
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1 is
+ signal incr_cmd_0_n_3 : STD_LOGIC;
+ signal incr_next_pending : STD_LOGIC;
+ signal m_axi_araddr_0_sn_1 : STD_LOGIC;
+ signal s_axburst_eq0 : STD_LOGIC;
+ signal s_axburst_eq1 : STD_LOGIC;
+ signal \^sel_first_reg_2\ : STD_LOGIC;
+ signal wrap_cmd_0_n_10 : STD_LOGIC;
+ signal wrap_cmd_0_n_11 : STD_LOGIC;
+ signal wrap_cmd_0_n_12 : STD_LOGIC;
+ signal wrap_cmd_0_n_13 : STD_LOGIC;
+ signal wrap_cmd_0_n_14 : STD_LOGIC;
+ signal wrap_cmd_0_n_15 : STD_LOGIC;
+ signal wrap_cmd_0_n_16 : STD_LOGIC;
+ signal wrap_cmd_0_n_17 : STD_LOGIC;
+ signal wrap_cmd_0_n_26 : STD_LOGIC;
+ signal wrap_cmd_0_n_7 : STD_LOGIC;
+ signal wrap_cmd_0_n_8 : STD_LOGIC;
+ signal wrap_cmd_0_n_9 : STD_LOGIC;
+ signal wrap_next_pending : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_2\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair16";
+begin
+ m_axi_araddr_0_sn_1 <= m_axi_araddr_0_sp_1;
+ sel_first_reg_2 <= \^sel_first_reg_2\;
+\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axburst_eq1,
+ I1 => \axlen_cnt_reg[3]\(15),
+ I2 => s_axburst_eq0,
+ O => next_pending
+ );
+incr_cmd_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_incr_cmd_2
+ port map (
+ E(0) => E(0),
+ Q(10) => wrap_cmd_0_n_7,
+ Q(9) => wrap_cmd_0_n_8,
+ Q(8) => wrap_cmd_0_n_9,
+ Q(7) => wrap_cmd_0_n_10,
+ Q(6) => wrap_cmd_0_n_11,
+ Q(5) => wrap_cmd_0_n_12,
+ Q(4) => wrap_cmd_0_n_13,
+ Q(3) => wrap_cmd_0_n_14,
+ Q(2) => wrap_cmd_0_n_15,
+ Q(1) => wrap_cmd_0_n_16,
+ Q(0) => wrap_cmd_0_n_17,
+ S(3 downto 0) => S(3 downto 0),
+ aclk => aclk,
+ \axaddr_incr_reg[0]_0\(0) => \axaddr_incr_reg[0]\(0),
+ \axaddr_incr_reg[11]_0\(0) => \axaddr_incr_reg[11]\(0),
+ \axaddr_incr_reg[11]_1\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
+ \axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
+ \axaddr_incr_reg[7]_0\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
+ \axlen_cnt_reg[0]_0\(1 downto 0) => Q(1 downto 0),
+ \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\,
+ \axlen_cnt_reg[2]_1\(17 downto 11) => \axlen_cnt_reg[3]\(18 downto 12),
+ \axlen_cnt_reg[2]_1\(10 downto 0) => \axlen_cnt_reg[3]\(10 downto 0),
+ \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]_0\,
+ \axlen_cnt_reg[4]_0\ => \axaddr_wrap_reg[0]\,
+ \axlen_cnt_reg[8]_0\ => \axlen_cnt_reg[8]\,
+ incr_next_pending => incr_next_pending,
+ m_axi_araddr(10 downto 0) => m_axi_araddr(10 downto 0),
+ \m_axi_araddr[0]_0\ => \m_axi_araddr[0]_0\,
+ \m_axi_araddr[0]_1\ => \^sel_first_reg_2\,
+ m_axi_araddr_0_sp_1 => m_axi_araddr_0_sn_1,
+ m_axi_arready => m_axi_arready,
+ \m_payload_i_reg[39]\ => incr_cmd_0_n_3,
+ next_pending_r_reg_0 => next_pending_r_reg,
+ r_push => r_push,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => sel_first_reg_1,
+ sel_first_reg_1 => sel_first_reg_3,
+ sel_first_reg_2 => sel_first_reg_4,
+ si_rs_arvalid => si_rs_arvalid,
+ wrap_next_pending => wrap_next_pending
+ );
+r_rlast_r_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"1D"
+ )
+ port map (
+ I0 => s_axburst_eq0,
+ I1 => \axlen_cnt_reg[3]\(15),
+ I2 => s_axburst_eq1,
+ O => r_rlast
+ );
+s_axburst_eq0_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => incr_cmd_0_n_3,
+ Q => s_axburst_eq0,
+ R => '0'
+ );
+s_axburst_eq1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => wrap_cmd_0_n_26,
+ Q => s_axburst_eq1,
+ R => '0'
+ );
+sel_first_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => sel_first_i,
+ Q => sel_first_reg_0,
+ R => '0'
+ );
+wrap_cmd_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wrap_cmd_3
+ port map (
+ D(3 downto 0) => D(3 downto 0),
+ E(0) => E(0),
+ O(3 downto 0) => O(3 downto 0),
+ Q(11) => \axaddr_wrap_reg[11]_0\(0),
+ Q(10) => wrap_cmd_0_n_7,
+ Q(9) => wrap_cmd_0_n_8,
+ Q(8) => wrap_cmd_0_n_9,
+ Q(7) => wrap_cmd_0_n_10,
+ Q(6) => wrap_cmd_0_n_11,
+ Q(5) => wrap_cmd_0_n_12,
+ Q(4) => wrap_cmd_0_n_13,
+ Q(3) => wrap_cmd_0_n_14,
+ Q(2) => wrap_cmd_0_n_15,
+ Q(1) => wrap_cmd_0_n_16,
+ Q(0) => wrap_cmd_0_n_17,
+ aclk => aclk,
+ axaddr_offset(3 downto 0) => axaddr_offset(3 downto 0),
+ \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
+ \axaddr_wrap_reg[0]_0\ => \axaddr_wrap_reg[0]\,
+ \axaddr_wrap_reg[11]_0\(3 downto 0) => \axaddr_wrap_reg[11]\(3 downto 0),
+ \axaddr_wrap_reg[11]_1\(11 downto 0) => \axaddr_wrap_reg[11]_1\(11 downto 0),
+ \axaddr_wrap_reg[7]_0\(3 downto 0) => \axaddr_wrap_reg[7]\(3 downto 0),
+ \axlen_cnt_reg[3]_0\(11 downto 7) => \axlen_cnt_reg[3]\(19 downto 15),
+ \axlen_cnt_reg[3]_0\(6 downto 0) => \axlen_cnt_reg[3]\(13 downto 7),
+ \axlen_cnt_reg[3]_1\(0) => Q(1),
+ \axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
+ incr_next_pending => incr_next_pending,
+ \m_payload_i_reg[39]\ => wrap_cmd_0_n_26,
+ next_pending_r_reg_0 => next_pending_r_reg,
+ r_push => r_push,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => \^sel_first_reg_2\,
+ sel_first_reg_1 => sel_first_reg_5,
+ si_rs_arvalid => si_rs_arvalid,
+ \wrap_boundary_axaddr_r_reg[11]_0\(11 downto 0) => \wrap_boundary_axaddr_r_reg[11]\(11 downto 0),
+ \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
+ \wrap_cnt_r_reg[3]_0\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0),
+ wrap_next_pending => wrap_next_pending,
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel is
+ port (
+ r_full : out STD_LOGIC;
+ m_axi_rready : out STD_LOGIC;
+ si_rs_rvalid : out STD_LOGIC;
+ \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
+ r_push_r_reg_0 : out STD_LOGIC_VECTOR ( 12 downto 0 );
+ r_push : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ r_rlast : in STD_LOGIC;
+ m_axi_rvalid : in STD_LOGIC;
+ si_rs_rready : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
+ D : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ areset_d1 : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel is
+ signal a_full0 : STD_LOGIC;
+ signal r_push_r : STD_LOGIC;
+ signal rd_a_full : STD_LOGIC;
+ signal \rd_en__1\ : STD_LOGIC;
+ signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
+ signal transaction_fifo_0_n_1 : STD_LOGIC;
+ signal wr_en0 : STD_LOGIC;
+begin
+\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(0),
+ Q => trans_in(1),
+ R => '0'
+ );
+\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(10),
+ Q => trans_in(11),
+ R => '0'
+ );
+\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(11),
+ Q => trans_in(12),
+ R => '0'
+ );
+\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(1),
+ Q => trans_in(2),
+ R => '0'
+ );
+\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(2),
+ Q => trans_in(3),
+ R => '0'
+ );
+\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(3),
+ Q => trans_in(4),
+ R => '0'
+ );
+\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(4),
+ Q => trans_in(5),
+ R => '0'
+ );
+\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(5),
+ Q => trans_in(6),
+ R => '0'
+ );
+\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(6),
+ Q => trans_in(7),
+ R => '0'
+ );
+\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(7),
+ Q => trans_in(8),
+ R => '0'
+ );
+\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(8),
+ Q => trans_in(9),
+ R => '0'
+ );
+\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => D(9),
+ Q => trans_in(10),
+ R => '0'
+ );
+r_push_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => r_push,
+ Q => r_push_r,
+ R => '0'
+ );
+r_rlast_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => r_rlast,
+ Q => trans_in(0),
+ R => '0'
+ );
+rd_data_fifo_0: entity work.\TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1\
+ port map (
+ E(0) => transaction_fifo_0_n_1,
+ a_full0 => a_full0,
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \in\(33 downto 0) => \in\(33 downto 0),
+ m_axi_rready => m_axi_rready,
+ m_axi_rvalid => m_axi_rvalid,
+ \out\(33 downto 0) => \out\(33 downto 0),
+ rd_a_full => rd_a_full,
+ \rd_en__1\ => \rd_en__1\,
+ wr_en0 => wr_en0
+ );
+transaction_fifo_0: entity work.\TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2\
+ port map (
+ E(0) => transaction_fifo_0_n_1,
+ a_full0 => a_full0,
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \in\(12 downto 0) => trans_in(12 downto 0),
+ r_full => r_full,
+ r_push_r => r_push_r,
+ r_push_r_reg(12 downto 0) => r_push_r_reg_0(12 downto 0),
+ rd_a_full => rd_a_full,
+ \rd_en__1\ => \rd_en__1\,
+ si_rs_rready => si_rs_rready,
+ si_rs_rvalid => si_rs_rvalid,
+ wr_en0 => wr_en0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice is
+ port (
+ s_ready_i_reg : out STD_LOGIC;
+ s_ready_i_reg_0 : out STD_LOGIC;
+ si_rs_awvalid : out STD_LOGIC;
+ m_valid_i_reg : out STD_LOGIC;
+ si_rs_bready : out STD_LOGIC;
+ si_rs_arvalid : out STD_LOGIC;
+ m_valid_i_reg_0 : out STD_LOGIC;
+ si_rs_rready : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ axaddr_offset_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[47]\ : out STD_LOGIC;
+ \m_payload_i_reg[61]\ : out STD_LOGIC_VECTOR ( 54 downto 0 );
+ wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[47]_0\ : out STD_LOGIC;
+ \m_payload_i_reg[47]_1\ : out STD_LOGIC;
+ \m_payload_i_reg[61]_0\ : out STD_LOGIC_VECTOR ( 54 downto 0 );
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_payload_i_reg[47]_2\ : out STD_LOGIC;
+ \m_payload_i_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ \m_payload_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]\ : out STD_LOGIC;
+ \m_payload_i_reg[38]\ : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[39]_0\ : out STD_LOGIC;
+ \m_payload_i_reg[38]_0\ : out STD_LOGIC;
+ \m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
+ \m_payload_i_reg[46]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
+ aclk : in STD_LOGIC;
+ s_ready_i0 : in STD_LOGIC;
+ m_valid_i0 : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+ \wrap_cnt_r_reg[0]\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ b_push : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ \wrap_cnt_r_reg[0]_0\ : in STD_LOGIC;
+ \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_offset_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_offset_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ si_rs_rvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ si_rs_bvalid : in STD_LOGIC;
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ \m_axi_awaddr[11]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_awaddr[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_awaddr[11]_1\ : in STD_LOGIC;
+ sel_first_1 : in STD_LOGIC;
+ sel_first : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ \m_axi_araddr[11]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_araddr[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_axi_araddr[11]_1\ : in STD_LOGIC;
+ sel_first_2 : in STD_LOGIC;
+ \m_axi_araddr[11]_2\ : in STD_LOGIC;
+ \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \skid_buffer_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \skid_buffer_reg[46]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
+ \skid_buffer_reg[33]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice is
+ signal \ar.ar_pipe_n_2\ : STD_LOGIC;
+ signal \aw.aw_pipe_n_1\ : STD_LOGIC;
+ signal \aw.aw_pipe_n_94\ : STD_LOGIC;
+begin
+\ar.ar_pipe\: entity work.TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice
+ port map (
+ O(3 downto 0) => O(3 downto 0),
+ Q(54 downto 0) => \m_payload_i_reg[61]_0\(54 downto 0),
+ aclk => aclk,
+ \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\,
+ \aresetn_d_reg[1]_inv_1\ => \aw.aw_pipe_n_94\,
+ \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
+ \axaddr_offset_r_reg[0]\(1 downto 0) => \axaddr_offset_r_reg[0]_0\(1 downto 0),
+ \axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
+ \axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
+ m_axi_araddr(0) => m_axi_araddr(0),
+ \m_axi_araddr[11]\(0) => \m_axi_araddr[11]\(0),
+ \m_axi_araddr[11]_0\(0) => \m_axi_araddr[11]_0\(0),
+ \m_axi_araddr[11]_1\ => \m_axi_araddr[11]_1\,
+ \m_axi_araddr[11]_2\ => \m_axi_araddr[11]_2\,
+ \m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]\(0),
+ \m_payload_i_reg[38]_0\ => \m_payload_i_reg[38]_0\,
+ \m_payload_i_reg[39]_0\ => \m_payload_i_reg[39]_0\,
+ \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
+ \m_payload_i_reg[44]_0\ => axaddr_offset_0(0),
+ \m_payload_i_reg[47]_0\ => axaddr_offset_0(3),
+ \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_1\,
+ \m_payload_i_reg[47]_2\ => \m_payload_i_reg[47]_2\,
+ \m_payload_i_reg[6]_0\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
+ \m_payload_i_reg[7]_0\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
+ m_valid_i0 => m_valid_i0,
+ m_valid_i_reg_0 => si_rs_arvalid,
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
+ s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
+ s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
+ s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
+ s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
+ s_ready_i0 => s_ready_i0,
+ s_ready_i_reg_0 => s_ready_i_reg_0,
+ s_ready_i_reg_1 => \aw.aw_pipe_n_1\,
+ sel_first_2 => sel_first_2,
+ \wrap_cnt_r_reg[0]\ => \wrap_cnt_r_reg[0]_0\,
+ \wrap_second_len_r_reg[1]\(3 downto 0) => \wrap_second_len_r_reg[1]\(3 downto 0),
+ \wrap_second_len_r_reg[1]_0\ => \wrap_second_len_r_reg[3]\(1),
+ \wrap_second_len_r_reg[3]\(2 downto 1) => \wrap_second_len_r_reg[3]\(3 downto 2),
+ \wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
+ );
+\aw.aw_pipe\: entity work.TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice_0
+ port map (
+ D(3 downto 0) => D(3 downto 0),
+ E(0) => E(0),
+ Q(3 downto 0) => Q(3 downto 0),
+ S(3 downto 0) => S(3 downto 0),
+ aclk => aclk,
+ aresetn => aresetn,
+ \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_1\,
+ \aresetn_d_reg[0]_1\ => \aw.aw_pipe_n_94\,
+ axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
+ \axaddr_offset_r_reg[0]\(1 downto 0) => \axaddr_offset_r_reg[0]\(1 downto 0),
+ \axaddr_offset_r_reg[1]\ => axaddr_offset(1),
+ \axaddr_offset_r_reg[2]\ => axaddr_offset(2),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
+ b_push => b_push,
+ m_axi_awaddr(0) => m_axi_awaddr(0),
+ \m_axi_awaddr[11]\(0) => \m_axi_awaddr[11]\(0),
+ \m_axi_awaddr[11]_0\(0) => \m_axi_awaddr[11]_0\(0),
+ \m_axi_awaddr[11]_1\ => \m_axi_awaddr[11]_1\,
+ \m_payload_i_reg[38]_0\ => \m_payload_i_reg[38]\,
+ \m_payload_i_reg[39]_0\ => \m_payload_i_reg[39]\,
+ \m_payload_i_reg[44]_0\ => axaddr_offset(0),
+ \m_payload_i_reg[47]_0\ => axaddr_offset(3),
+ \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]\,
+ \m_payload_i_reg[47]_2\ => \m_payload_i_reg[47]_0\,
+ \m_payload_i_reg[61]_0\(54 downto 0) => \m_payload_i_reg[61]\(54 downto 0),
+ \m_payload_i_reg[6]_0\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
+ m_valid_i_reg_0 => si_rs_awvalid,
+ m_valid_i_reg_1 => \ar.ar_pipe_n_2\,
+ s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
+ s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
+ s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
+ s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
+ s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
+ s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_ready_i_reg_0 => s_ready_i_reg,
+ sel_first => sel_first,
+ sel_first_1 => sel_first_1,
+ \wrap_cnt_r_reg[0]\ => \wrap_cnt_r_reg[0]\,
+ wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2),
+ wrap_second_len(0) => wrap_second_len(0),
+ \wrap_second_len_r_reg[1]\ => wrap_second_len(1)
+ );
+\b.b_pipe\: entity work.\TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized1\
+ port map (
+ aclk => aclk,
+ \m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
+ m_valid_i_reg_0 => m_valid_i_reg,
+ m_valid_i_reg_1 => \ar.ar_pipe_n_2\,
+ \out\(11 downto 0) => \out\(11 downto 0),
+ s_axi_bready => s_axi_bready,
+ s_ready_i_reg_0 => si_rs_bready,
+ s_ready_i_reg_1 => \aw.aw_pipe_n_1\,
+ si_rs_bvalid => si_rs_bvalid,
+ \skid_buffer_reg[1]_0\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
+ );
+\r.r_pipe\: entity work.\TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axic_register_slice__parameterized2\
+ port map (
+ aclk => aclk,
+ \m_payload_i_reg[46]_0\(46 downto 0) => \m_payload_i_reg[46]\(46 downto 0),
+ m_valid_i_reg_0 => m_valid_i_reg_0,
+ m_valid_i_reg_1 => \ar.ar_pipe_n_2\,
+ s_axi_rready => s_axi_rready,
+ s_ready_i_reg_0 => si_rs_rready,
+ s_ready_i_reg_1 => \aw.aw_pipe_n_1\,
+ si_rs_rvalid => si_rs_rvalid,
+ \skid_buffer_reg[33]_0\(33 downto 0) => \skid_buffer_reg[33]\(33 downto 0),
+ \skid_buffer_reg[46]_0\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel is
+ port (
+ sel_first : out STD_LOGIC;
+ sel_first_reg : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_ready_i0 : out STD_LOGIC;
+ m_valid_i0 : out STD_LOGIC;
+ \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_state_reg[1]\ : out STD_LOGIC;
+ r_push : out STD_LOGIC;
+ m_axi_arvalid : out STD_LOGIC;
+ r_rlast : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg_0 : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_arid_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ si_rs_arvalid : in STD_LOGIC;
+ m_axi_arready : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_ready_i_reg : in STD_LOGIC;
+ \s_arid_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ next_pending_r_reg : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC;
+ \axlen_cnt_reg[3]\ : in STD_LOGIC;
+ r_full : in STD_LOGIC;
+ O : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_araddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_araddr[0]_0\ : in STD_LOGIC;
+ axaddr_offset : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel is
+ signal \^fsm_sequential_state_reg[1]\ : STD_LOGIC;
+ signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_10 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_13 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_18 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_19 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_22 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_5 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
+ signal ar_cmd_fsm_0_n_7 : STD_LOGIC;
+ signal cmd_translator_0_n_0 : STD_LOGIC;
+ signal cmd_translator_0_n_10 : STD_LOGIC;
+ signal cmd_translator_0_n_11 : STD_LOGIC;
+ signal cmd_translator_0_n_12 : STD_LOGIC;
+ signal cmd_translator_0_n_13 : STD_LOGIC;
+ signal cmd_translator_0_n_14 : STD_LOGIC;
+ signal cmd_translator_0_n_17 : STD_LOGIC;
+ signal cmd_translator_0_n_20 : STD_LOGIC;
+ signal cmd_translator_0_n_3 : STD_LOGIC;
+ signal cmd_translator_0_n_4 : STD_LOGIC;
+ signal cmd_translator_0_n_41 : STD_LOGIC;
+ signal cmd_translator_0_n_42 : STD_LOGIC;
+ signal cmd_translator_0_n_43 : STD_LOGIC;
+ signal cmd_translator_0_n_44 : STD_LOGIC;
+ signal cmd_translator_0_n_45 : STD_LOGIC;
+ signal cmd_translator_0_n_46 : STD_LOGIC;
+ signal cmd_translator_0_n_47 : STD_LOGIC;
+ signal cmd_translator_0_n_48 : STD_LOGIC;
+ signal cmd_translator_0_n_49 : STD_LOGIC;
+ signal cmd_translator_0_n_5 : STD_LOGIC;
+ signal cmd_translator_0_n_50 : STD_LOGIC;
+ signal cmd_translator_0_n_51 : STD_LOGIC;
+ signal cmd_translator_0_n_52 : STD_LOGIC;
+ signal cmd_translator_0_n_6 : STD_LOGIC;
+ signal cmd_translator_0_n_7 : STD_LOGIC;
+ signal cmd_translator_0_n_8 : STD_LOGIC;
+ signal cmd_translator_0_n_9 : STD_LOGIC;
+ signal m_axi_araddr_0_sn_1 : STD_LOGIC;
+ signal next_pending : STD_LOGIC;
+ signal \^r_push\ : STD_LOGIC;
+ signal \^sel_first\ : STD_LOGIC;
+ signal sel_first_i : STD_LOGIC;
+ signal \^sel_first_reg\ : STD_LOGIC;
+begin
+ \FSM_sequential_state_reg[1]\ <= \^fsm_sequential_state_reg[1]\;
+ Q(1 downto 0) <= \^q\(1 downto 0);
+ m_axi_araddr_0_sn_1 <= m_axi_araddr_0_sp_1;
+ r_push <= \^r_push\;
+ sel_first <= \^sel_first\;
+ sel_first_reg <= \^sel_first_reg\;
+ar_cmd_fsm_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm
+ port map (
+ D(11) => ar_cmd_fsm_0_n_11,
+ D(10) => ar_cmd_fsm_0_n_12,
+ D(9) => ar_cmd_fsm_0_n_13,
+ D(8) => ar_cmd_fsm_0_n_14,
+ D(7) => ar_cmd_fsm_0_n_15,
+ D(6) => ar_cmd_fsm_0_n_16,
+ D(5) => ar_cmd_fsm_0_n_17,
+ D(4) => ar_cmd_fsm_0_n_18,
+ D(3) => ar_cmd_fsm_0_n_19,
+ D(2) => ar_cmd_fsm_0_n_20,
+ D(1) => ar_cmd_fsm_0_n_21,
+ D(0) => ar_cmd_fsm_0_n_22,
+ E(0) => \^fsm_sequential_state_reg[1]\,
+ \FSM_sequential_state_reg[1]_0\ => ar_cmd_fsm_0_n_0,
+ \FSM_sequential_state_reg[1]_1\(0) => E(0),
+ O(3) => cmd_translator_0_n_3,
+ O(2) => cmd_translator_0_n_4,
+ O(1) => cmd_translator_0_n_5,
+ O(0) => cmd_translator_0_n_6,
+ Q(1 downto 0) => \^q\(1 downto 0),
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \axaddr_incr_reg[0]\ => \^sel_first\,
+ \axaddr_wrap_reg[11]\(11 downto 0) => \s_arid_r_reg[11]_1\(11 downto 0),
+ \axaddr_wrap_reg[11]_0\(11) => cmd_translator_0_n_41,
+ \axaddr_wrap_reg[11]_0\(10) => cmd_translator_0_n_42,
+ \axaddr_wrap_reg[11]_0\(9) => cmd_translator_0_n_43,
+ \axaddr_wrap_reg[11]_0\(8) => cmd_translator_0_n_44,
+ \axaddr_wrap_reg[11]_0\(7) => cmd_translator_0_n_45,
+ \axaddr_wrap_reg[11]_0\(6) => cmd_translator_0_n_46,
+ \axaddr_wrap_reg[11]_0\(5) => cmd_translator_0_n_47,
+ \axaddr_wrap_reg[11]_0\(4) => cmd_translator_0_n_48,
+ \axaddr_wrap_reg[11]_0\(3) => cmd_translator_0_n_49,
+ \axaddr_wrap_reg[11]_0\(2) => cmd_translator_0_n_50,
+ \axaddr_wrap_reg[11]_0\(1) => cmd_translator_0_n_51,
+ \axaddr_wrap_reg[11]_0\(0) => cmd_translator_0_n_52,
+ \axaddr_wrap_reg[11]_1\(3) => cmd_translator_0_n_11,
+ \axaddr_wrap_reg[11]_1\(2) => cmd_translator_0_n_12,
+ \axaddr_wrap_reg[11]_1\(1) => cmd_translator_0_n_13,
+ \axaddr_wrap_reg[11]_1\(0) => cmd_translator_0_n_14,
+ \axaddr_wrap_reg[11]_2\ => cmd_translator_0_n_20,
+ \axaddr_wrap_reg[7]\(3) => cmd_translator_0_n_7,
+ \axaddr_wrap_reg[7]\(2) => cmd_translator_0_n_8,
+ \axaddr_wrap_reg[7]\(1) => cmd_translator_0_n_9,
+ \axaddr_wrap_reg[7]\(0) => cmd_translator_0_n_10,
+ \axlen_cnt_reg[8]\ => cmd_translator_0_n_17,
+ m_axi_arready => m_axi_arready,
+ m_axi_arready_0 => ar_cmd_fsm_0_n_5,
+ m_axi_arready_1 => ar_cmd_fsm_0_n_6,
+ m_axi_arready_2 => ar_cmd_fsm_0_n_7,
+ m_axi_arready_3 => \^r_push\,
+ m_axi_arvalid => m_axi_arvalid,
+ m_valid_i0 => m_valid_i0,
+ next_pending => next_pending,
+ r_full => r_full,
+ s_axi_arvalid => s_axi_arvalid,
+ s_ready_i0 => s_ready_i0,
+ s_ready_i_reg => s_ready_i_reg,
+ sel_first_i => sel_first_i,
+ sel_first_reg(0) => ar_cmd_fsm_0_n_10,
+ sel_first_reg_0 => \^sel_first_reg\,
+ sel_first_reg_1 => cmd_translator_0_n_0,
+ si_rs_arvalid => si_rs_arvalid
+ );
+cmd_translator_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator_1
+ port map (
+ D(3 downto 0) => D(3 downto 0),
+ E(0) => \^fsm_sequential_state_reg[1]\,
+ O(3) => cmd_translator_0_n_3,
+ O(2) => cmd_translator_0_n_4,
+ O(1) => cmd_translator_0_n_5,
+ O(0) => cmd_translator_0_n_6,
+ Q(1 downto 0) => \^q\(1 downto 0),
+ S(3 downto 0) => S(3 downto 0),
+ aclk => aclk,
+ \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_10,
+ \axaddr_incr_reg[11]\(0) => \axaddr_incr_reg[11]\(0),
+ \axaddr_incr_reg[11]_0\(3 downto 0) => O(3 downto 0),
+ \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
+ \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
+ axaddr_offset(3 downto 0) => axaddr_offset(3 downto 0),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
+ \axaddr_wrap_reg[0]\ => ar_cmd_fsm_0_n_5,
+ \axaddr_wrap_reg[11]\(3) => cmd_translator_0_n_11,
+ \axaddr_wrap_reg[11]\(2) => cmd_translator_0_n_12,
+ \axaddr_wrap_reg[11]\(1) => cmd_translator_0_n_13,
+ \axaddr_wrap_reg[11]\(0) => cmd_translator_0_n_14,
+ \axaddr_wrap_reg[11]_0\(0) => \axaddr_wrap_reg[11]\(0),
+ \axaddr_wrap_reg[11]_1\(11) => ar_cmd_fsm_0_n_11,
+ \axaddr_wrap_reg[11]_1\(10) => ar_cmd_fsm_0_n_12,
+ \axaddr_wrap_reg[11]_1\(9) => ar_cmd_fsm_0_n_13,
+ \axaddr_wrap_reg[11]_1\(8) => ar_cmd_fsm_0_n_14,
+ \axaddr_wrap_reg[11]_1\(7) => ar_cmd_fsm_0_n_15,
+ \axaddr_wrap_reg[11]_1\(6) => ar_cmd_fsm_0_n_16,
+ \axaddr_wrap_reg[11]_1\(5) => ar_cmd_fsm_0_n_17,
+ \axaddr_wrap_reg[11]_1\(4) => ar_cmd_fsm_0_n_18,
+ \axaddr_wrap_reg[11]_1\(3) => ar_cmd_fsm_0_n_19,
+ \axaddr_wrap_reg[11]_1\(2) => ar_cmd_fsm_0_n_20,
+ \axaddr_wrap_reg[11]_1\(1) => ar_cmd_fsm_0_n_21,
+ \axaddr_wrap_reg[11]_1\(0) => ar_cmd_fsm_0_n_22,
+ \axaddr_wrap_reg[7]\(3) => cmd_translator_0_n_7,
+ \axaddr_wrap_reg[7]\(2) => cmd_translator_0_n_8,
+ \axaddr_wrap_reg[7]\(1) => cmd_translator_0_n_9,
+ \axaddr_wrap_reg[7]\(0) => cmd_translator_0_n_10,
+ \axlen_cnt_reg[2]\ => cmd_translator_0_n_17,
+ \axlen_cnt_reg[3]\(19 downto 0) => \s_arid_r_reg[11]_1\(19 downto 0),
+ \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]\,
+ \axlen_cnt_reg[4]\ => cmd_translator_0_n_20,
+ \axlen_cnt_reg[8]\ => ar_cmd_fsm_0_n_0,
+ m_axi_araddr(10 downto 0) => m_axi_araddr(10 downto 0),
+ \m_axi_araddr[0]_0\ => \m_axi_araddr[0]_0\,
+ m_axi_araddr_0_sp_1 => m_axi_araddr_0_sn_1,
+ m_axi_arready => m_axi_arready,
+ next_pending => next_pending,
+ next_pending_r_reg => next_pending_r_reg,
+ r_push => \^r_push\,
+ r_rlast => r_rlast,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => cmd_translator_0_n_0,
+ sel_first_reg_1 => \^sel_first\,
+ sel_first_reg_2 => \^sel_first_reg\,
+ sel_first_reg_3 => sel_first_reg_0,
+ sel_first_reg_4 => ar_cmd_fsm_0_n_7,
+ sel_first_reg_5 => ar_cmd_fsm_0_n_6,
+ si_rs_arvalid => si_rs_arvalid,
+ \wrap_boundary_axaddr_r_reg[11]\(11) => cmd_translator_0_n_41,
+ \wrap_boundary_axaddr_r_reg[11]\(10) => cmd_translator_0_n_42,
+ \wrap_boundary_axaddr_r_reg[11]\(9) => cmd_translator_0_n_43,
+ \wrap_boundary_axaddr_r_reg[11]\(8) => cmd_translator_0_n_44,
+ \wrap_boundary_axaddr_r_reg[11]\(7) => cmd_translator_0_n_45,
+ \wrap_boundary_axaddr_r_reg[11]\(6) => cmd_translator_0_n_46,
+ \wrap_boundary_axaddr_r_reg[11]\(5) => cmd_translator_0_n_47,
+ \wrap_boundary_axaddr_r_reg[11]\(4) => cmd_translator_0_n_48,
+ \wrap_boundary_axaddr_r_reg[11]\(3) => cmd_translator_0_n_49,
+ \wrap_boundary_axaddr_r_reg[11]\(2) => cmd_translator_0_n_50,
+ \wrap_boundary_axaddr_r_reg[11]\(1) => cmd_translator_0_n_51,
+ \wrap_boundary_axaddr_r_reg[11]\(0) => cmd_translator_0_n_52,
+ \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
+ \wrap_cnt_r_reg[3]\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0),
+ \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0)
+ );
+\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(20),
+ Q => \s_arid_r_reg[11]_0\(0),
+ R => '0'
+ );
+\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(30),
+ Q => \s_arid_r_reg[11]_0\(10),
+ R => '0'
+ );
+\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(31),
+ Q => \s_arid_r_reg[11]_0\(11),
+ R => '0'
+ );
+\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(21),
+ Q => \s_arid_r_reg[11]_0\(1),
+ R => '0'
+ );
+\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(22),
+ Q => \s_arid_r_reg[11]_0\(2),
+ R => '0'
+ );
+\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(23),
+ Q => \s_arid_r_reg[11]_0\(3),
+ R => '0'
+ );
+\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(24),
+ Q => \s_arid_r_reg[11]_0\(4),
+ R => '0'
+ );
+\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(25),
+ Q => \s_arid_r_reg[11]_0\(5),
+ R => '0'
+ );
+\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(26),
+ Q => \s_arid_r_reg[11]_0\(6),
+ R => '0'
+ );
+\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(27),
+ Q => \s_arid_r_reg[11]_0\(7),
+ R => '0'
+ );
+\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(28),
+ Q => \s_arid_r_reg[11]_0\(8),
+ R => '0'
+ );
+\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_arid_r_reg[11]_1\(29),
+ Q => \s_arid_r_reg[11]_0\(9),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel is
+ port (
+ sel_first_0 : out STD_LOGIC;
+ sel_first : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \state_reg[1]\ : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ b_push : out STD_LOGIC;
+ m_axi_awvalid : out STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ sel_first_reg : out STD_LOGIC;
+ \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ aclk : in STD_LOGIC;
+ si_rs_awvalid : in STD_LOGIC;
+ \s_awid_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ next_pending_r_reg : in STD_LOGIC;
+ areset_d1 : in STD_LOGIC;
+ \axlen_cnt_reg[3]\ : in STD_LOGIC;
+ m_axi_awready : in STD_LOGIC;
+ b_full : in STD_LOGIC;
+ cnt_read : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_awaddr_0_sp_1 : in STD_LOGIC;
+ \m_axi_awaddr[0]_0\ : in STD_LOGIC;
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel is
+ signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
+ signal aw_cmd_fsm_0_n_4 : STD_LOGIC;
+ signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
+ signal aw_cmd_fsm_0_n_6 : STD_LOGIC;
+ signal aw_cmd_fsm_0_n_8 : STD_LOGIC;
+ signal aw_cmd_fsm_0_n_9 : STD_LOGIC;
+ signal cmd_translator_0_n_0 : STD_LOGIC;
+ signal cmd_translator_0_n_5 : STD_LOGIC;
+ signal cmd_translator_0_n_6 : STD_LOGIC;
+ signal cmd_translator_0_n_7 : STD_LOGIC;
+ signal cmd_translator_0_n_9 : STD_LOGIC;
+ signal m_axi_awaddr_0_sn_1 : STD_LOGIC;
+ signal \next\ : STD_LOGIC;
+ signal next_pending : STD_LOGIC;
+ signal \^sel_first\ : STD_LOGIC;
+ signal \^sel_first_0\ : STD_LOGIC;
+ signal sel_first_i : STD_LOGIC;
+ signal \^state_reg[1]\ : STD_LOGIC;
+begin
+ Q(1 downto 0) <= \^q\(1 downto 0);
+ m_axi_awaddr_0_sn_1 <= m_axi_awaddr_0_sp_1;
+ sel_first <= \^sel_first\;
+ sel_first_0 <= \^sel_first_0\;
+ \state_reg[1]\ <= \^state_reg[1]\;
+aw_cmd_fsm_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm
+ port map (
+ D(1) => aw_cmd_fsm_0_n_8,
+ D(0) => aw_cmd_fsm_0_n_9,
+ E(0) => \^state_reg[1]\,
+ Q(1 downto 0) => \^q\(1 downto 0),
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \axlen_cnt_reg[0]\(0) => cmd_translator_0_n_6,
+ \axlen_cnt_reg[0]_0\ => cmd_translator_0_n_7,
+ \axlen_cnt_reg[3]\(1) => \s_awid_r_reg[11]_0\(19),
+ \axlen_cnt_reg[3]\(0) => \s_awid_r_reg[11]_0\(16),
+ \axlen_cnt_reg[3]_0\ => cmd_translator_0_n_9,
+ \axlen_cnt_reg[8]\ => cmd_translator_0_n_5,
+ b_full => b_full,
+ b_push => b_push,
+ cnt_read(1 downto 0) => cnt_read(1 downto 0),
+ m_axi_awready => m_axi_awready,
+ m_axi_awvalid => m_axi_awvalid,
+ m_valid_i_reg => aw_cmd_fsm_0_n_0,
+ m_valid_i_reg_0 => aw_cmd_fsm_0_n_4,
+ m_valid_i_reg_1(0) => E(0),
+ \next\ => \next\,
+ next_pending => next_pending,
+ sel_first => \^sel_first\,
+ sel_first_i => sel_first_i,
+ sel_first_reg => aw_cmd_fsm_0_n_5,
+ sel_first_reg_0 => aw_cmd_fsm_0_n_6,
+ sel_first_reg_1 => \^sel_first_0\,
+ sel_first_reg_2 => cmd_translator_0_n_0,
+ si_rs_awvalid => si_rs_awvalid
+ );
+cmd_translator_0: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_cmd_translator
+ port map (
+ D(3 downto 0) => D(3 downto 0),
+ E(0) => \^state_reg[1]\,
+ Q(0) => cmd_translator_0_n_6,
+ S(3 downto 0) => S(3 downto 0),
+ aclk => aclk,
+ axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
+ \axaddr_incr_reg[11]\(0) => \axaddr_incr_reg[11]\(0),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
+ \axaddr_wrap_reg[0]\ => aw_cmd_fsm_0_n_4,
+ \axaddr_wrap_reg[11]\(0) => \axaddr_wrap_reg[11]\(0),
+ \axlen_cnt_reg[0]\(1 downto 0) => \^q\(1 downto 0),
+ \axlen_cnt_reg[2]\ => cmd_translator_0_n_5,
+ \axlen_cnt_reg[2]_0\ => cmd_translator_0_n_9,
+ \axlen_cnt_reg[2]_1\(18 downto 0) => \s_awid_r_reg[11]_0\(18 downto 0),
+ \axlen_cnt_reg[3]\ => cmd_translator_0_n_7,
+ \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]\,
+ \axlen_cnt_reg[3]_1\(1) => aw_cmd_fsm_0_n_8,
+ \axlen_cnt_reg[3]_1\(0) => aw_cmd_fsm_0_n_9,
+ \axlen_cnt_reg[8]\ => aw_cmd_fsm_0_n_0,
+ m_axi_awaddr(10 downto 0) => m_axi_awaddr(10 downto 0),
+ \m_axi_awaddr[0]_0\ => \m_axi_awaddr[0]_0\,
+ m_axi_awaddr_0_sp_1 => m_axi_awaddr_0_sn_1,
+ \next\ => \next\,
+ next_pending => next_pending,
+ next_pending_r_reg => next_pending_r_reg,
+ sel_first => \^sel_first\,
+ sel_first_i => sel_first_i,
+ sel_first_reg_0 => cmd_translator_0_n_0,
+ sel_first_reg_1 => \^sel_first_0\,
+ sel_first_reg_2 => sel_first_reg,
+ sel_first_reg_3 => aw_cmd_fsm_0_n_6,
+ sel_first_reg_4 => aw_cmd_fsm_0_n_5,
+ si_rs_awvalid => si_rs_awvalid,
+ \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
+ \wrap_cnt_r_reg[3]\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0),
+ \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
+ );
+\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(20),
+ Q => \in\(4),
+ R => '0'
+ );
+\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(30),
+ Q => \in\(14),
+ R => '0'
+ );
+\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(31),
+ Q => \in\(15),
+ R => '0'
+ );
+\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(21),
+ Q => \in\(5),
+ R => '0'
+ );
+\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(22),
+ Q => \in\(6),
+ R => '0'
+ );
+\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(23),
+ Q => \in\(7),
+ R => '0'
+ );
+\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(24),
+ Q => \in\(8),
+ R => '0'
+ );
+\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(25),
+ Q => \in\(9),
+ R => '0'
+ );
+\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(26),
+ Q => \in\(10),
+ R => '0'
+ );
+\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(27),
+ Q => \in\(11),
+ R => '0'
+ );
+\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(28),
+ Q => \in\(12),
+ R => '0'
+ );
+\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(29),
+ Q => \in\(13),
+ R => '0'
+ );
+\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(16),
+ Q => \in\(0),
+ R => '0'
+ );
+\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(17),
+ Q => \in\(1),
+ R => '0'
+ );
+\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(18),
+ Q => \in\(2),
+ R => '0'
+ );
+\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => aclk,
+ CE => '1',
+ D => \s_awid_r_reg[11]_0\(19),
+ Q => \in\(3),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s is
+ port (
+ s_axi_awready : out STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
+ \m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ \m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ \m_payload_i_reg[46]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
+ m_axi_awvalid : out STD_LOGIC;
+ m_axi_bready : out STD_LOGIC;
+ m_axi_arvalid : out STD_LOGIC;
+ m_axi_rready : out STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_arready : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ aclk : in STD_LOGIC;
+ \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_awready : in STD_LOGIC;
+ m_axi_bvalid : in STD_LOGIC;
+ m_axi_rvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ aresetn : in STD_LOGIC
+ );
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s is
+ signal \RD.ar_channel_0_n_1\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_23\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_45\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_46\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_6\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_7\ : STD_LOGIC;
+ signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
+ signal SI_REG_n_108 : STD_LOGIC;
+ signal SI_REG_n_109 : STD_LOGIC;
+ signal SI_REG_n_127 : STD_LOGIC;
+ signal SI_REG_n_128 : STD_LOGIC;
+ signal SI_REG_n_129 : STD_LOGIC;
+ signal SI_REG_n_16 : STD_LOGIC;
+ signal SI_REG_n_169 : STD_LOGIC;
+ signal SI_REG_n_17 : STD_LOGIC;
+ signal SI_REG_n_170 : STD_LOGIC;
+ signal SI_REG_n_171 : STD_LOGIC;
+ signal SI_REG_n_172 : STD_LOGIC;
+ signal SI_REG_n_173 : STD_LOGIC;
+ signal SI_REG_n_174 : STD_LOGIC;
+ signal SI_REG_n_175 : STD_LOGIC;
+ signal SI_REG_n_176 : STD_LOGIC;
+ signal SI_REG_n_177 : STD_LOGIC;
+ signal SI_REG_n_178 : STD_LOGIC;
+ signal SI_REG_n_179 : STD_LOGIC;
+ signal SI_REG_n_18 : STD_LOGIC;
+ signal SI_REG_n_180 : STD_LOGIC;
+ signal SI_REG_n_181 : STD_LOGIC;
+ signal SI_REG_n_182 : STD_LOGIC;
+ signal SI_REG_n_183 : STD_LOGIC;
+ signal SI_REG_n_185 : STD_LOGIC;
+ signal SI_REG_n_186 : STD_LOGIC;
+ signal SI_REG_n_188 : STD_LOGIC;
+ signal SI_REG_n_189 : STD_LOGIC;
+ signal SI_REG_n_19 : STD_LOGIC;
+ signal SI_REG_n_36 : STD_LOGIC;
+ signal SI_REG_n_37 : STD_LOGIC;
+ signal SI_REG_n_38 : STD_LOGIC;
+ signal SI_REG_n_39 : STD_LOGIC;
+ signal SI_REG_n_40 : STD_LOGIC;
+ signal SI_REG_n_41 : STD_LOGIC;
+ signal SI_REG_n_42 : STD_LOGIC;
+ signal SI_REG_n_43 : STD_LOGIC;
+ signal SI_REG_n_44 : STD_LOGIC;
+ signal SI_REG_n_45 : STD_LOGIC;
+ signal SI_REG_n_46 : STD_LOGIC;
+ signal SI_REG_n_47 : STD_LOGIC;
+ signal SI_REG_n_48 : STD_LOGIC;
+ signal SI_REG_n_66 : STD_LOGIC;
+ signal \WR.aw_channel_0_n_21\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_46\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_47\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_48\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_49\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_5\ : STD_LOGIC;
+ signal \WR.aw_channel_0_n_6\ : STD_LOGIC;
+ signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
+ signal \ar.ar_pipe/p_1_in\ : STD_LOGIC;
+ signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC;
+ signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal areset_d1 : STD_LOGIC;
+ signal areset_d1_i_1_n_0 : STD_LOGIC;
+ signal \aw.aw_pipe/p_1_in\ : STD_LOGIC;
+ signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 to 11 );
+ signal axsize : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal b_full : STD_LOGIC;
+ signal b_push : STD_LOGIC;
+ signal \bid_fifo_0/cnt_read\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
+ signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
+ signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal r_full : STD_LOGIC;
+ signal r_push : STD_LOGIC;
+ signal r_rlast : STD_LOGIC;
+ signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal \^s_axi_arready\ : STD_LOGIC;
+ signal sel_first : STD_LOGIC;
+ signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal si_rs_arvalid : STD_LOGIC;
+ signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal si_rs_awvalid : STD_LOGIC;
+ signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal si_rs_bready : STD_LOGIC;
+ signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal si_rs_bvalid : STD_LOGIC;
+ signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal si_rs_rlast : STD_LOGIC;
+ signal si_rs_rready : STD_LOGIC;
+ signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal si_rs_rvalid : STD_LOGIC;
+ signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
+begin
+ s_axi_arready <= \^s_axi_arready\;
+\RD.ar_channel_0\: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_ar_channel
+ port map (
+ D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 0),
+ E(0) => \ar.ar_pipe/p_1_in\,
+ \FSM_sequential_state_reg[1]\ => \RD.ar_channel_0_n_8\,
+ O(3) => SI_REG_n_44,
+ O(2) => SI_REG_n_45,
+ O(1) => SI_REG_n_46,
+ O(0) => SI_REG_n_47,
+ Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
+ S(3) => \RD.ar_channel_0_n_45\,
+ S(2) => \RD.ar_channel_0_n_46\,
+ S(1) => \RD.ar_channel_0_n_47\,
+ S(0) => \RD.ar_channel_0_n_48\,
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \axaddr_incr_reg[11]\(0) => \RD.ar_channel_0_n_7\,
+ \axaddr_incr_reg[3]\(3) => SI_REG_n_36,
+ \axaddr_incr_reg[3]\(2) => SI_REG_n_37,
+ \axaddr_incr_reg[3]\(1) => SI_REG_n_38,
+ \axaddr_incr_reg[3]\(0) => SI_REG_n_39,
+ \axaddr_incr_reg[7]\(3) => SI_REG_n_40,
+ \axaddr_incr_reg[7]\(2) => SI_REG_n_41,
+ \axaddr_incr_reg[7]\(1) => SI_REG_n_42,
+ \axaddr_incr_reg[7]\(0) => SI_REG_n_43,
+ axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 0),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
+ \axaddr_wrap_reg[11]\(0) => \RD.ar_channel_0_n_6\,
+ \axlen_cnt_reg[3]\ => SI_REG_n_169,
+ m_axi_araddr(10 downto 0) => m_axi_araddr(10 downto 0),
+ \m_axi_araddr[0]_0\ => SI_REG_n_189,
+ m_axi_araddr_0_sp_1 => SI_REG_n_188,
+ m_axi_arready => m_axi_arready,
+ m_axi_arvalid => m_axi_arvalid,
+ m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
+ next_pending_r_reg => SI_REG_n_109,
+ r_full => r_full,
+ r_push => r_push,
+ r_rlast => r_rlast,
+ \s_arid_r_reg[11]_0\(11 downto 0) => s_arid_r(11 downto 0),
+ \s_arid_r_reg[11]_1\(31 downto 20) => s_arid(11 downto 0),
+ \s_arid_r_reg[11]_1\(19 downto 16) => si_rs_arlen(3 downto 0),
+ \s_arid_r_reg[11]_1\(15) => si_rs_arburst(1),
+ \s_arid_r_reg[11]_1\(14) => SI_REG_n_127,
+ \s_arid_r_reg[11]_1\(13) => SI_REG_n_128,
+ \s_arid_r_reg[11]_1\(12) => SI_REG_n_129,
+ \s_arid_r_reg[11]_1\(11 downto 0) => si_rs_araddr(11 downto 0),
+ s_axi_arvalid => s_axi_arvalid,
+ s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
+ s_ready_i_reg => \^s_axi_arready\,
+ sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
+ sel_first_reg => \RD.ar_channel_0_n_1\,
+ sel_first_reg_0 => \RD.ar_channel_0_n_23\,
+ si_rs_arvalid => si_rs_arvalid,
+ \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_177,
+ \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_178,
+ \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_179,
+ \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_180,
+ \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_181,
+ \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_182,
+ \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_183,
+ \wrap_cnt_r_reg[3]\(3) => SI_REG_n_16,
+ \wrap_cnt_r_reg[3]\(2) => SI_REG_n_17,
+ \wrap_cnt_r_reg[3]\(1) => SI_REG_n_18,
+ \wrap_cnt_r_reg[3]\(0) => SI_REG_n_19,
+ \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0)
+ );
+\RD.r_channel_0\: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_r_channel
+ port map (
+ D(11 downto 0) => s_arid_r(11 downto 0),
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ \in\(33 downto 0) => \in\(33 downto 0),
+ m_axi_rready => m_axi_rready,
+ m_axi_rvalid => m_axi_rvalid,
+ \out\(33 downto 32) => si_rs_rresp(1 downto 0),
+ \out\(31 downto 0) => si_rs_rdata(31 downto 0),
+ r_full => r_full,
+ r_push => r_push,
+ r_push_r_reg_0(12 downto 1) => si_rs_rid(11 downto 0),
+ r_push_r_reg_0(0) => si_rs_rlast,
+ r_rlast => r_rlast,
+ si_rs_rready => si_rs_rready,
+ si_rs_rvalid => si_rs_rvalid
+ );
+SI_REG: entity work.TopLevel_auto_pc_0_axi_register_slice_v2_1_19_axi_register_slice
+ port map (
+ D(3 downto 0) => wrap_cnt(3 downto 0),
+ E(0) => \aw.aw_pipe/p_1_in\,
+ O(3) => SI_REG_n_44,
+ O(2) => SI_REG_n_45,
+ O(1) => SI_REG_n_46,
+ O(0) => SI_REG_n_47,
+ Q(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
+ S(3) => \WR.aw_channel_0_n_46\,
+ S(2) => \WR.aw_channel_0_n_47\,
+ S(1) => \WR.aw_channel_0_n_48\,
+ S(0) => \WR.aw_channel_0_n_49\,
+ aclk => aclk,
+ aresetn => aresetn,
+ axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
+ \axaddr_incr_reg[3]\(3) => \RD.ar_channel_0_n_45\,
+ \axaddr_incr_reg[3]\(2) => \RD.ar_channel_0_n_46\,
+ \axaddr_incr_reg[3]\(1) => \RD.ar_channel_0_n_47\,
+ \axaddr_incr_reg[3]\(0) => \RD.ar_channel_0_n_48\,
+ axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_1\(3 downto 0),
+ axaddr_offset_0(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 0),
+ \axaddr_offset_r_reg[0]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
+ \axaddr_offset_r_reg[0]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
+ \axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
+ b_push => b_push,
+ m_axi_araddr(0) => m_axi_araddr(11),
+ \m_axi_araddr[11]\(0) => \RD.ar_channel_0_n_6\,
+ \m_axi_araddr[11]_0\(0) => \RD.ar_channel_0_n_7\,
+ \m_axi_araddr[11]_1\ => \RD.ar_channel_0_n_23\,
+ \m_axi_araddr[11]_2\ => \RD.ar_channel_0_n_1\,
+ m_axi_awaddr(0) => m_axi_awaddr(11),
+ \m_axi_awaddr[11]\(0) => axaddr_wrap(11),
+ \m_axi_awaddr[11]_0\(0) => \WR.aw_channel_0_n_5\,
+ \m_axi_awaddr[11]_1\ => \WR.aw_channel_0_n_21\,
+ \m_payload_i_reg[0]\(0) => \ar.ar_pipe/p_1_in\,
+ \m_payload_i_reg[13]\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
+ \m_payload_i_reg[38]\ => SI_REG_n_186,
+ \m_payload_i_reg[38]_0\ => SI_REG_n_189,
+ \m_payload_i_reg[39]\ => SI_REG_n_185,
+ \m_payload_i_reg[39]_0\ => SI_REG_n_188,
+ \m_payload_i_reg[3]\(3) => SI_REG_n_36,
+ \m_payload_i_reg[3]\(2) => SI_REG_n_37,
+ \m_payload_i_reg[3]\(1) => SI_REG_n_38,
+ \m_payload_i_reg[3]\(0) => SI_REG_n_39,
+ \m_payload_i_reg[46]\(46 downto 0) => \m_payload_i_reg[46]\(46 downto 0),
+ \m_payload_i_reg[47]\ => SI_REG_n_48,
+ \m_payload_i_reg[47]_0\ => SI_REG_n_108,
+ \m_payload_i_reg[47]_1\ => SI_REG_n_109,
+ \m_payload_i_reg[47]_2\ => SI_REG_n_169,
+ \m_payload_i_reg[61]\(54 downto 43) => s_awid(11 downto 0),
+ \m_payload_i_reg[61]\(42 downto 39) => si_rs_awlen(3 downto 0),
+ \m_payload_i_reg[61]\(38) => si_rs_awburst(1),
+ \m_payload_i_reg[61]\(37) => SI_REG_n_66,
+ \m_payload_i_reg[61]\(36 downto 35) => axsize(1 downto 0),
+ \m_payload_i_reg[61]\(34 downto 12) => Q(22 downto 0),
+ \m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0),
+ \m_payload_i_reg[61]_0\(54 downto 43) => s_arid(11 downto 0),
+ \m_payload_i_reg[61]_0\(42 downto 39) => si_rs_arlen(3 downto 0),
+ \m_payload_i_reg[61]_0\(38) => si_rs_arburst(1),
+ \m_payload_i_reg[61]_0\(37) => SI_REG_n_127,
+ \m_payload_i_reg[61]_0\(36) => SI_REG_n_128,
+ \m_payload_i_reg[61]_0\(35) => SI_REG_n_129,
+ \m_payload_i_reg[61]_0\(34 downto 12) => \m_payload_i_reg[34]\(22 downto 0),
+ \m_payload_i_reg[61]_0\(11 downto 0) => si_rs_araddr(11 downto 0),
+ \m_payload_i_reg[6]\(6) => SI_REG_n_170,
+ \m_payload_i_reg[6]\(5) => SI_REG_n_171,
+ \m_payload_i_reg[6]\(4) => SI_REG_n_172,
+ \m_payload_i_reg[6]\(3) => SI_REG_n_173,
+ \m_payload_i_reg[6]\(2) => SI_REG_n_174,
+ \m_payload_i_reg[6]\(1) => SI_REG_n_175,
+ \m_payload_i_reg[6]\(0) => SI_REG_n_176,
+ \m_payload_i_reg[6]_0\(6) => SI_REG_n_177,
+ \m_payload_i_reg[6]_0\(5) => SI_REG_n_178,
+ \m_payload_i_reg[6]_0\(4) => SI_REG_n_179,
+ \m_payload_i_reg[6]_0\(3) => SI_REG_n_180,
+ \m_payload_i_reg[6]_0\(2) => SI_REG_n_181,
+ \m_payload_i_reg[6]_0\(1) => SI_REG_n_182,
+ \m_payload_i_reg[6]_0\(0) => SI_REG_n_183,
+ \m_payload_i_reg[7]\(3) => SI_REG_n_40,
+ \m_payload_i_reg[7]\(2) => SI_REG_n_41,
+ \m_payload_i_reg[7]\(1) => SI_REG_n_42,
+ \m_payload_i_reg[7]\(0) => SI_REG_n_43,
+ m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
+ m_valid_i_reg => s_axi_bvalid,
+ m_valid_i_reg_0 => s_axi_rvalid,
+ \out\(11 downto 0) => si_rs_bid(11 downto 0),
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
+ s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
+ s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
+ s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
+ s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
+ s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
+ s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
+ s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
+ s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
+ s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
+ s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_rready => s_axi_rready,
+ s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
+ s_ready_i_reg => s_axi_awready,
+ s_ready_i_reg_0 => \^s_axi_arready\,
+ sel_first => sel_first,
+ sel_first_1 => \cmd_translator_0/incr_cmd_0/sel_first_4\,
+ sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
+ si_rs_arvalid => si_rs_arvalid,
+ si_rs_awvalid => si_rs_awvalid,
+ si_rs_bready => si_rs_bready,
+ si_rs_bvalid => si_rs_bvalid,
+ si_rs_rready => si_rs_rready,
+ si_rs_rvalid => si_rs_rvalid,
+ \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
+ \skid_buffer_reg[33]\(33 downto 32) => si_rs_rresp(1 downto 0),
+ \skid_buffer_reg[33]\(31 downto 0) => si_rs_rdata(31 downto 0),
+ \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
+ \skid_buffer_reg[46]\(0) => si_rs_rlast,
+ \wrap_cnt_r_reg[0]\ => \WR.aw_channel_0_n_6\,
+ \wrap_cnt_r_reg[0]_0\ => \RD.ar_channel_0_n_8\,
+ wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_0\(3 downto 0),
+ \wrap_second_len_r_reg[1]\(3) => SI_REG_n_16,
+ \wrap_second_len_r_reg[1]\(2) => SI_REG_n_17,
+ \wrap_second_len_r_reg[1]\(1) => SI_REG_n_18,
+ \wrap_second_len_r_reg[1]\(0) => SI_REG_n_19,
+ \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 0),
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0)
+ );
+\WR.aw_channel_0\: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_aw_channel
+ port map (
+ D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_1\(3 downto 0),
+ E(0) => \aw.aw_pipe/p_1_in\,
+ Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
+ S(3) => \WR.aw_channel_0_n_46\,
+ S(2) => \WR.aw_channel_0_n_47\,
+ S(1) => \WR.aw_channel_0_n_48\,
+ S(0) => \WR.aw_channel_0_n_49\,
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
+ \axaddr_incr_reg[11]\(0) => \WR.aw_channel_0_n_5\,
+ \axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
+ \axaddr_wrap_reg[11]\(0) => axaddr_wrap(11),
+ \axlen_cnt_reg[3]\ => SI_REG_n_108,
+ b_full => b_full,
+ b_push => b_push,
+ cnt_read(1 downto 0) => \bid_fifo_0/cnt_read\(1 downto 0),
+ \in\(15 downto 4) => b_awid(11 downto 0),
+ \in\(3 downto 0) => b_awlen(3 downto 0),
+ m_axi_awaddr(10 downto 0) => m_axi_awaddr(10 downto 0),
+ \m_axi_awaddr[0]_0\ => SI_REG_n_186,
+ m_axi_awaddr_0_sp_1 => SI_REG_n_185,
+ m_axi_awready => m_axi_awready,
+ m_axi_awvalid => m_axi_awvalid,
+ next_pending_r_reg => SI_REG_n_48,
+ \s_awid_r_reg[11]_0\(31 downto 20) => s_awid(11 downto 0),
+ \s_awid_r_reg[11]_0\(19 downto 16) => si_rs_awlen(3 downto 0),
+ \s_awid_r_reg[11]_0\(15) => si_rs_awburst(1),
+ \s_awid_r_reg[11]_0\(14) => SI_REG_n_66,
+ \s_awid_r_reg[11]_0\(13 downto 12) => axsize(1 downto 0),
+ \s_awid_r_reg[11]_0\(11 downto 0) => si_rs_awaddr(11 downto 0),
+ sel_first => sel_first,
+ sel_first_0 => \cmd_translator_0/incr_cmd_0/sel_first_4\,
+ sel_first_reg => \WR.aw_channel_0_n_21\,
+ si_rs_awvalid => si_rs_awvalid,
+ \state_reg[1]\ => \WR.aw_channel_0_n_6\,
+ \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_170,
+ \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_171,
+ \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_172,
+ \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_173,
+ \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_174,
+ \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_175,
+ \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_176,
+ \wrap_cnt_r_reg[3]\(3 downto 0) => wrap_cnt(3 downto 0),
+ \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
+ \wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_0\(3 downto 0)
+ );
+\WR.b_channel_0\: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s_b_channel
+ port map (
+ aclk => aclk,
+ areset_d1 => areset_d1,
+ b_full => b_full,
+ b_push => b_push,
+ cnt_read(1 downto 0) => \bid_fifo_0/cnt_read\(1 downto 0),
+ \in\(15 downto 4) => b_awid(11 downto 0),
+ \in\(3 downto 0) => b_awlen(3 downto 0),
+ m_axi_bready => m_axi_bready,
+ m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
+ m_axi_bvalid => m_axi_bvalid,
+ \out\(11 downto 0) => si_rs_bid(11 downto 0),
+ \s_bresp_acc_reg[1]_0\(1 downto 0) => si_rs_bresp(1 downto 0),
+ si_rs_bready => si_rs_bready,
+ si_rs_bvalid => si_rs_bvalid
+ );
+areset_d1_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => aresetn,
+ O => areset_d1_i_1_n_0
+ );
+areset_d1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => areset_d1_i_1_n_0,
+ Q => areset_d1,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter is
+ port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wlast : in STD_LOGIC;
+ s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rlast : out STD_LOGIC;
+ s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_awvalid : out STD_LOGIC;
+ m_axi_awready : in STD_LOGIC;
+ m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_wlast : out STD_LOGIC;
+ m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_wvalid : out STD_LOGIC;
+ m_axi_wready : in STD_LOGIC;
+ m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_bvalid : in STD_LOGIC;
+ m_axi_bready : out STD_LOGIC;
+ m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_arvalid : out STD_LOGIC;
+ m_axi_arready : in STD_LOGIC;
+ m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_rlast : in STD_LOGIC;
+ m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_rvalid : in STD_LOGIC;
+ m_axi_rready : out STD_LOGIC
+ );
+ attribute C_AXI_ADDR_WIDTH : integer;
+ attribute C_AXI_ADDR_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 32;
+ attribute C_AXI_ARUSER_WIDTH : integer;
+ attribute C_AXI_ARUSER_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_AWUSER_WIDTH : integer;
+ attribute C_AXI_AWUSER_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_BUSER_WIDTH : integer;
+ attribute C_AXI_BUSER_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_DATA_WIDTH : integer;
+ attribute C_AXI_DATA_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 32;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 12;
+ attribute C_AXI_RUSER_WIDTH : integer;
+ attribute C_AXI_RUSER_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_SUPPORTS_READ : integer;
+ attribute C_AXI_SUPPORTS_READ of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
+ attribute C_AXI_SUPPORTS_USER_SIGNALS of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 0;
+ attribute C_AXI_SUPPORTS_WRITE : integer;
+ attribute C_AXI_SUPPORTS_WRITE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_AXI_WUSER_WIDTH : integer;
+ attribute C_AXI_WUSER_WIDTH of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "zynq";
+ attribute C_IGNORE_ID : integer;
+ attribute C_IGNORE_ID of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 0;
+ attribute C_M_AXI_PROTOCOL : integer;
+ attribute C_M_AXI_PROTOCOL of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 2;
+ attribute C_S_AXI_PROTOCOL : integer;
+ attribute C_S_AXI_PROTOCOL of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute C_TRANSLATION_MODE : integer;
+ attribute C_TRANSLATION_MODE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 2;
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "yes";
+ attribute P_AXI3 : integer;
+ attribute P_AXI3 of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute P_AXI4 : integer;
+ attribute P_AXI4 of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 0;
+ attribute P_AXILITE : integer;
+ attribute P_AXILITE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 2;
+ attribute P_AXILITE_SIZE : string;
+ attribute P_AXILITE_SIZE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "3'b010";
+ attribute P_CONVERSION : integer;
+ attribute P_CONVERSION of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 2;
+ attribute P_DECERR : string;
+ attribute P_DECERR of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "2'b11";
+ attribute P_INCR : string;
+ attribute P_INCR of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "2'b01";
+ attribute P_PROTECTION : integer;
+ attribute P_PROTECTION of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is 1;
+ attribute P_SLVERR : string;
+ attribute P_SLVERR of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter : entity is "2'b10";
+end TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter;
+
+architecture STRUCTURE of TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter is
+ signal \<const0>\ : STD_LOGIC;
+ signal \<const1>\ : STD_LOGIC;
+ signal \^m_axi_wready\ : STD_LOGIC;
+ signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^s_axi_wvalid\ : STD_LOGIC;
+begin
+ \^m_axi_wready\ <= m_axi_wready;
+ \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
+ \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
+ \^s_axi_wvalid\ <= s_axi_wvalid;
+ m_axi_arburst(1) <= \<const0>\;
+ m_axi_arburst(0) <= \<const1>\;
+ m_axi_arcache(3) <= \<const0>\;
+ m_axi_arcache(2) <= \<const0>\;
+ m_axi_arcache(1) <= \<const0>\;
+ m_axi_arcache(0) <= \<const0>\;
+ m_axi_arid(11) <= \<const0>\;
+ m_axi_arid(10) <= \<const0>\;
+ m_axi_arid(9) <= \<const0>\;
+ m_axi_arid(8) <= \<const0>\;
+ m_axi_arid(7) <= \<const0>\;
+ m_axi_arid(6) <= \<const0>\;
+ m_axi_arid(5) <= \<const0>\;
+ m_axi_arid(4) <= \<const0>\;
+ m_axi_arid(3) <= \<const0>\;
+ m_axi_arid(2) <= \<const0>\;
+ m_axi_arid(1) <= \<const0>\;
+ m_axi_arid(0) <= \<const0>\;
+ m_axi_arlen(7) <= \<const0>\;
+ m_axi_arlen(6) <= \<const0>\;
+ m_axi_arlen(5) <= \<const0>\;
+ m_axi_arlen(4) <= \<const0>\;
+ m_axi_arlen(3) <= \<const0>\;
+ m_axi_arlen(2) <= \<const0>\;
+ m_axi_arlen(1) <= \<const0>\;
+ m_axi_arlen(0) <= \<const0>\;
+ m_axi_arlock(0) <= \<const0>\;
+ m_axi_arqos(3) <= \<const0>\;
+ m_axi_arqos(2) <= \<const0>\;
+ m_axi_arqos(1) <= \<const0>\;
+ m_axi_arqos(0) <= \<const0>\;
+ m_axi_arregion(3) <= \<const0>\;
+ m_axi_arregion(2) <= \<const0>\;
+ m_axi_arregion(1) <= \<const0>\;
+ m_axi_arregion(0) <= \<const0>\;
+ m_axi_arsize(2) <= \<const0>\;
+ m_axi_arsize(1) <= \<const1>\;
+ m_axi_arsize(0) <= \<const0>\;
+ m_axi_aruser(0) <= \<const0>\;
+ m_axi_awburst(1) <= \<const0>\;
+ m_axi_awburst(0) <= \<const1>\;
+ m_axi_awcache(3) <= \<const0>\;
+ m_axi_awcache(2) <= \<const0>\;
+ m_axi_awcache(1) <= \<const0>\;
+ m_axi_awcache(0) <= \<const0>\;
+ m_axi_awid(11) <= \<const0>\;
+ m_axi_awid(10) <= \<const0>\;
+ m_axi_awid(9) <= \<const0>\;
+ m_axi_awid(8) <= \<const0>\;
+ m_axi_awid(7) <= \<const0>\;
+ m_axi_awid(6) <= \<const0>\;
+ m_axi_awid(5) <= \<const0>\;
+ m_axi_awid(4) <= \<const0>\;
+ m_axi_awid(3) <= \<const0>\;
+ m_axi_awid(2) <= \<const0>\;
+ m_axi_awid(1) <= \<const0>\;
+ m_axi_awid(0) <= \<const0>\;
+ m_axi_awlen(7) <= \<const0>\;
+ m_axi_awlen(6) <= \<const0>\;
+ m_axi_awlen(5) <= \<const0>\;
+ m_axi_awlen(4) <= \<const0>\;
+ m_axi_awlen(3) <= \<const0>\;
+ m_axi_awlen(2) <= \<const0>\;
+ m_axi_awlen(1) <= \<const0>\;
+ m_axi_awlen(0) <= \<const0>\;
+ m_axi_awlock(0) <= \<const0>\;
+ m_axi_awqos(3) <= \<const0>\;
+ m_axi_awqos(2) <= \<const0>\;
+ m_axi_awqos(1) <= \<const0>\;
+ m_axi_awqos(0) <= \<const0>\;
+ m_axi_awregion(3) <= \<const0>\;
+ m_axi_awregion(2) <= \<const0>\;
+ m_axi_awregion(1) <= \<const0>\;
+ m_axi_awregion(0) <= \<const0>\;
+ m_axi_awsize(2) <= \<const0>\;
+ m_axi_awsize(1) <= \<const1>\;
+ m_axi_awsize(0) <= \<const0>\;
+ m_axi_awuser(0) <= \<const0>\;
+ m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
+ m_axi_wid(11) <= \<const0>\;
+ m_axi_wid(10) <= \<const0>\;
+ m_axi_wid(9) <= \<const0>\;
+ m_axi_wid(8) <= \<const0>\;
+ m_axi_wid(7) <= \<const0>\;
+ m_axi_wid(6) <= \<const0>\;
+ m_axi_wid(5) <= \<const0>\;
+ m_axi_wid(4) <= \<const0>\;
+ m_axi_wid(3) <= \<const0>\;
+ m_axi_wid(2) <= \<const0>\;
+ m_axi_wid(1) <= \<const0>\;
+ m_axi_wid(0) <= \<const0>\;
+ m_axi_wlast <= \<const1>\;
+ m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
+ m_axi_wuser(0) <= \<const0>\;
+ m_axi_wvalid <= \^s_axi_wvalid\;
+ s_axi_buser(0) <= \<const0>\;
+ s_axi_ruser(0) <= \<const0>\;
+ s_axi_wready <= \^m_axi_wready\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+VCC: unisim.vcomponents.VCC
+ port map (
+ P => \<const1>\
+ );
+\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_b2s
+ port map (
+ Q(22 downto 20) => m_axi_awprot(2 downto 0),
+ Q(19 downto 0) => m_axi_awaddr(31 downto 12),
+ aclk => aclk,
+ aresetn => aresetn,
+ \in\(33 downto 32) => m_axi_rresp(1 downto 0),
+ \in\(31 downto 0) => m_axi_rdata(31 downto 0),
+ m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
+ m_axi_arready => m_axi_arready,
+ m_axi_arvalid => m_axi_arvalid,
+ m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
+ m_axi_awready => m_axi_awready,
+ m_axi_awvalid => m_axi_awvalid,
+ m_axi_bready => m_axi_bready,
+ m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
+ m_axi_bvalid => m_axi_bvalid,
+ m_axi_rready => m_axi_rready,
+ m_axi_rvalid => m_axi_rvalid,
+ \m_payload_i_reg[13]\(13 downto 2) => s_axi_bid(11 downto 0),
+ \m_payload_i_reg[13]\(1 downto 0) => s_axi_bresp(1 downto 0),
+ \m_payload_i_reg[34]\(22 downto 20) => m_axi_arprot(2 downto 0),
+ \m_payload_i_reg[34]\(19 downto 0) => m_axi_araddr(31 downto 12),
+ \m_payload_i_reg[46]\(46 downto 35) => s_axi_rid(11 downto 0),
+ \m_payload_i_reg[46]\(34) => s_axi_rlast,
+ \m_payload_i_reg[46]\(33 downto 32) => s_axi_rresp(1 downto 0),
+ \m_payload_i_reg[46]\(31 downto 0) => s_axi_rdata(31 downto 0),
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
+ s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
+ s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
+ s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
+ s_axi_arready => s_axi_arready,
+ s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
+ s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
+ s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
+ s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
+ s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
+ s_axi_awready => s_axi_awready,
+ s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rready => s_axi_rready,
+ s_axi_rvalid => s_axi_rvalid
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_auto_pc_0 is
+ port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wlast : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rlast : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_awvalid : out STD_LOGIC;
+ m_axi_awready : in STD_LOGIC;
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_wvalid : out STD_LOGIC;
+ m_axi_wready : in STD_LOGIC;
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_bvalid : in STD_LOGIC;
+ m_axi_bready : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arvalid : out STD_LOGIC;
+ m_axi_arready : in STD_LOGIC;
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_rvalid : in STD_LOGIC;
+ m_axi_rready : out STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of TopLevel_auto_pc_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of TopLevel_auto_pc_0 : entity is "TopLevel_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}";
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of TopLevel_auto_pc_0 : entity is "yes";
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of TopLevel_auto_pc_0 : entity is "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1";
+end TopLevel_auto_pc_0;
+
+architecture STRUCTURE of TopLevel_auto_pc_0 is
+ signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ attribute C_AXI_ADDR_WIDTH : integer;
+ attribute C_AXI_ADDR_WIDTH of inst : label is 32;
+ attribute C_AXI_ARUSER_WIDTH : integer;
+ attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
+ attribute C_AXI_AWUSER_WIDTH : integer;
+ attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
+ attribute C_AXI_BUSER_WIDTH : integer;
+ attribute C_AXI_BUSER_WIDTH of inst : label is 1;
+ attribute C_AXI_DATA_WIDTH : integer;
+ attribute C_AXI_DATA_WIDTH of inst : label is 32;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of inst : label is 12;
+ attribute C_AXI_RUSER_WIDTH : integer;
+ attribute C_AXI_RUSER_WIDTH of inst : label is 1;
+ attribute C_AXI_SUPPORTS_READ : integer;
+ attribute C_AXI_SUPPORTS_READ of inst : label is 1;
+ attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
+ attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
+ attribute C_AXI_SUPPORTS_WRITE : integer;
+ attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
+ attribute C_AXI_WUSER_WIDTH : integer;
+ attribute C_AXI_WUSER_WIDTH of inst : label is 1;
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of inst : label is "zynq";
+ attribute C_IGNORE_ID : integer;
+ attribute C_IGNORE_ID of inst : label is 0;
+ attribute C_M_AXI_PROTOCOL : integer;
+ attribute C_M_AXI_PROTOCOL of inst : label is 2;
+ attribute C_S_AXI_PROTOCOL : integer;
+ attribute C_S_AXI_PROTOCOL of inst : label is 1;
+ attribute C_TRANSLATION_MODE : integer;
+ attribute C_TRANSLATION_MODE of inst : label is 2;
+ attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
+ attribute P_AXI3 : integer;
+ attribute P_AXI3 of inst : label is 1;
+ attribute P_AXI4 : integer;
+ attribute P_AXI4 of inst : label is 0;
+ attribute P_AXILITE : integer;
+ attribute P_AXILITE of inst : label is 2;
+ attribute P_AXILITE_SIZE : string;
+ attribute P_AXILITE_SIZE of inst : label is "3'b010";
+ attribute P_CONVERSION : integer;
+ attribute P_CONVERSION of inst : label is 2;
+ attribute P_DECERR : string;
+ attribute P_DECERR of inst : label is "2'b11";
+ attribute P_INCR : string;
+ attribute P_INCR of inst : label is "2'b01";
+ attribute P_PROTECTION : integer;
+ attribute P_PROTECTION of inst : label is 1;
+ attribute P_SLVERR : string;
+ attribute P_SLVERR of inst : label is "2'b10";
+ attribute X_INTERFACE_INFO : string;
+ attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
+ attribute X_INTERFACE_PARAMETER : string;
+ attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
+ attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
+ attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
+ attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
+ attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
+ attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
+ attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
+ attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
+ attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
+ attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
+ attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
+ attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
+ attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+ attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+ attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+ attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+ attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+ attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+ attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
+ attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+ attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+ attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
+ attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+ attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+ attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
+ attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
+ attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
+ attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
+ attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
+ attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
+ attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
+ attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
+ attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
+ attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+ attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
+ attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
+ attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
+ attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
+ attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
+ attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
+ attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
+ attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
+ attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+ attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
+ attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
+ attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
+ attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
+ attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
+ attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
+ attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
+ attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
+ attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
+ attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+ attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+ attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
+ attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+ attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+ attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
+ attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+begin
+inst: entity work.TopLevel_auto_pc_0_axi_protocol_converter_v2_1_19_axi_protocol_converter
+ port map (
+ aclk => aclk,
+ aresetn => aresetn,
+ m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
+ m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
+ m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
+ m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
+ m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
+ m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
+ m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
+ m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
+ m_axi_arready => m_axi_arready,
+ m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
+ m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
+ m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
+ m_axi_arvalid => m_axi_arvalid,
+ m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
+ m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
+ m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
+ m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
+ m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
+ m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
+ m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
+ m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
+ m_axi_awready => m_axi_awready,
+ m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
+ m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
+ m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
+ m_axi_awvalid => m_axi_awvalid,
+ m_axi_bid(11 downto 0) => B"000000000000",
+ m_axi_bready => m_axi_bready,
+ m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
+ m_axi_buser(0) => '0',
+ m_axi_bvalid => m_axi_bvalid,
+ m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
+ m_axi_rid(11 downto 0) => B"000000000000",
+ m_axi_rlast => '1',
+ m_axi_rready => m_axi_rready,
+ m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
+ m_axi_ruser(0) => '0',
+ m_axi_rvalid => m_axi_rvalid,
+ m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
+ m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
+ m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
+ m_axi_wready => m_axi_wready,
+ m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
+ m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
+ m_axi_wvalid => m_axi_wvalid,
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
+ s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
+ s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
+ s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
+ s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
+ s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
+ s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
+ s_axi_arready => s_axi_arready,
+ s_axi_arregion(3 downto 0) => B"0000",
+ s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
+ s_axi_aruser(0) => '0',
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
+ s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
+ s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
+ s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
+ s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
+ s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
+ s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
+ s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
+ s_axi_awready => s_axi_awready,
+ s_axi_awregion(3 downto 0) => B"0000",
+ s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
+ s_axi_awuser(0) => '0',
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
+ s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
+ s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
+ s_axi_rlast => s_axi_rlast,
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
+ s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
+ s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
+ s_axi_wlast => s_axi_wlast,
+ s_axi_wready => s_axi_wready,
+ s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
+ s_axi_wuser(0) => '0',
+ s_axi_wvalid => s_axi_wvalid
+ );
+end STRUCTURE;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.v
new file mode 100644
index 0000000..3015b7d
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.v
@@ -0,0 +1,87 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Mon Oct 14 17:17:36 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub -rename_top TopLevel_auto_pc_0 -prefix
+// TopLevel_auto_pc_0_ TopLevel_auto_pc_0_stub.v
+// Design : TopLevel_auto_pc_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1" *)
+module TopLevel_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
+ s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
+ s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
+ s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
+ s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
+ s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
+ s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
+ m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
+ m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
+ m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
+ input aclk;
+ input aresetn;
+ input [11:0]s_axi_awid;
+ input [31:0]s_axi_awaddr;
+ input [3:0]s_axi_awlen;
+ input [2:0]s_axi_awsize;
+ input [1:0]s_axi_awburst;
+ input [1:0]s_axi_awlock;
+ input [3:0]s_axi_awcache;
+ input [2:0]s_axi_awprot;
+ input [3:0]s_axi_awqos;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [11:0]s_axi_wid;
+ input [31:0]s_axi_wdata;
+ input [3:0]s_axi_wstrb;
+ input s_axi_wlast;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [11:0]s_axi_bid;
+ output [1:0]s_axi_bresp;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [11:0]s_axi_arid;
+ input [31:0]s_axi_araddr;
+ input [3:0]s_axi_arlen;
+ input [2:0]s_axi_arsize;
+ input [1:0]s_axi_arburst;
+ input [1:0]s_axi_arlock;
+ input [3:0]s_axi_arcache;
+ input [2:0]s_axi_arprot;
+ input [3:0]s_axi_arqos;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [11:0]s_axi_rid;
+ output [31:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rlast;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ output [31:0]m_axi_awaddr;
+ output [2:0]m_axi_awprot;
+ output m_axi_awvalid;
+ input m_axi_awready;
+ output [31:0]m_axi_wdata;
+ output [3:0]m_axi_wstrb;
+ output m_axi_wvalid;
+ input m_axi_wready;
+ input [1:0]m_axi_bresp;
+ input m_axi_bvalid;
+ output m_axi_bready;
+ output [31:0]m_axi_araddr;
+ output [2:0]m_axi_arprot;
+ output m_axi_arvalid;
+ input m_axi_arready;
+ input [31:0]m_axi_rdata;
+ input [1:0]m_axi_rresp;
+ input m_axi_rvalid;
+ output m_axi_rready;
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.vhdl
new file mode 100644
index 0000000..aa29fc5
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/TopLevel_auto_pc_0_stub.vhdl
@@ -0,0 +1,88 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Mon Oct 14 17:17:36 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub -rename_top TopLevel_auto_pc_0 -prefix
+-- TopLevel_auto_pc_0_ TopLevel_auto_pc_0_stub.vhdl
+-- Design : TopLevel_auto_pc_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity TopLevel_auto_pc_0 is
+ Port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wlast : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rlast : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_awvalid : out STD_LOGIC;
+ m_axi_awready : in STD_LOGIC;
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ m_axi_wvalid : out STD_LOGIC;
+ m_axi_wready : in STD_LOGIC;
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_bvalid : in STD_LOGIC;
+ m_axi_bready : out STD_LOGIC;
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arvalid : out STD_LOGIC;
+ m_axi_arready : in STD_LOGIC;
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_rvalid : in STD_LOGIC;
+ m_axi_rready : out STD_LOGIC
+ );
+
+end TopLevel_auto_pc_0;
+
+architecture stub of TopLevel_auto_pc_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1";
+begin
+end;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/sim/TopLevel_auto_pc_0.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/sim/TopLevel_auto_pc_0.v
new file mode 100644
index 0000000..3b95f96
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/sim/TopLevel_auto_pc_0.v
@@ -0,0 +1,354 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 19
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module TopLevel_auto_pc_0 (
+ aclk,
+ aresetn,
+ s_axi_awid,
+ s_axi_awaddr,
+ s_axi_awlen,
+ s_axi_awsize,
+ s_axi_awburst,
+ s_axi_awlock,
+ s_axi_awcache,
+ s_axi_awprot,
+ s_axi_awqos,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wid,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wlast,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bid,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_arid,
+ s_axi_araddr,
+ s_axi_arlen,
+ s_axi_arsize,
+ s_axi_arburst,
+ s_axi_arlock,
+ s_axi_arcache,
+ s_axi_arprot,
+ s_axi_arqos,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rid,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rlast,
+ s_axi_rvalid,
+ s_axi_rready,
+ m_axi_awaddr,
+ m_axi_awprot,
+ m_axi_awvalid,
+ m_axi_awready,
+ m_axi_wdata,
+ m_axi_wstrb,
+ m_axi_wvalid,
+ m_axi_wready,
+ m_axi_bresp,
+ m_axi_bvalid,
+ m_axi_bready,
+ m_axi_araddr,
+ m_axi_arprot,
+ m_axi_arvalid,
+ m_axi_arready,
+ m_axi_rdata,
+ m_axi_rresp,
+ m_axi_rvalid,
+ m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
+S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+ axi_protocol_converter_v2_1_19_axi_protocol_converter #(
+ .C_FAMILY("zynq"),
+ .C_M_AXI_PROTOCOL(2),
+ .C_S_AXI_PROTOCOL(1),
+ .C_IGNORE_ID(0),
+ .C_AXI_ID_WIDTH(12),
+ .C_AXI_ADDR_WIDTH(32),
+ .C_AXI_DATA_WIDTH(32),
+ .C_AXI_SUPPORTS_WRITE(1),
+ .C_AXI_SUPPORTS_READ(1),
+ .C_AXI_SUPPORTS_USER_SIGNALS(0),
+ .C_AXI_AWUSER_WIDTH(1),
+ .C_AXI_ARUSER_WIDTH(1),
+ .C_AXI_WUSER_WIDTH(1),
+ .C_AXI_RUSER_WIDTH(1),
+ .C_AXI_BUSER_WIDTH(1),
+ .C_TRANSLATION_MODE(2)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awsize(s_axi_awsize),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awlock(s_axi_awlock),
+ .s_axi_awcache(s_axi_awcache),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awregion(4'H0),
+ .s_axi_awqos(s_axi_awqos),
+ .s_axi_awuser(1'H0),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_wid(s_axi_wid),
+ .s_axi_wdata(s_axi_wdata),
+ .s_axi_wstrb(s_axi_wstrb),
+ .s_axi_wlast(s_axi_wlast),
+ .s_axi_wuser(1'H0),
+ .s_axi_wvalid(s_axi_wvalid),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_bid(s_axi_bid),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_buser(),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arsize(s_axi_arsize),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arlock(s_axi_arlock),
+ .s_axi_arcache(s_axi_arcache),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arregion(4'H0),
+ .s_axi_arqos(s_axi_arqos),
+ .s_axi_aruser(1'H0),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_rid(s_axi_rid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rlast(s_axi_rlast),
+ .s_axi_ruser(),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_rready(s_axi_rready),
+ .m_axi_awid(),
+ .m_axi_awaddr(m_axi_awaddr),
+ .m_axi_awlen(),
+ .m_axi_awsize(),
+ .m_axi_awburst(),
+ .m_axi_awlock(),
+ .m_axi_awcache(),
+ .m_axi_awprot(m_axi_awprot),
+ .m_axi_awregion(),
+ .m_axi_awqos(),
+ .m_axi_awuser(),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_wid(),
+ .m_axi_wdata(m_axi_wdata),
+ .m_axi_wstrb(m_axi_wstrb),
+ .m_axi_wlast(),
+ .m_axi_wuser(),
+ .m_axi_wvalid(m_axi_wvalid),
+ .m_axi_wready(m_axi_wready),
+ .m_axi_bid(12'H000),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_buser(1'H0),
+ .m_axi_bvalid(m_axi_bvalid),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_arid(),
+ .m_axi_araddr(m_axi_araddr),
+ .m_axi_arlen(),
+ .m_axi_arsize(),
+ .m_axi_arburst(),
+ .m_axi_arlock(),
+ .m_axi_arcache(),
+ .m_axi_arprot(m_axi_arprot),
+ .m_axi_arregion(),
+ .m_axi_arqos(),
+ .m_axi_aruser(),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_rid(12'H000),
+ .m_axi_rdata(m_axi_rdata),
+ .m_axi_rresp(m_axi_rresp),
+ .m_axi_rlast(1'H1),
+ .m_axi_ruser(1'H0),
+ .m_axi_rvalid(m_axi_rvalid),
+ .m_axi_rready(m_axi_rready)
+ );
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/synth/TopLevel_auto_pc_0.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/synth/TopLevel_auto_pc_0.v
new file mode 100644
index 0000000..e31d977
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_auto_pc_0/synth/TopLevel_auto_pc_0.v
@@ -0,0 +1,356 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 19
+
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1" *)
+(* CHECK_LICENSE_TYPE = "TopLevel_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}" *)
+(* CORE_GENERATION_INFO = "TopLevel_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=19,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WI\
+DTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module TopLevel_auto_pc_0 (
+ aclk,
+ aresetn,
+ s_axi_awid,
+ s_axi_awaddr,
+ s_axi_awlen,
+ s_axi_awsize,
+ s_axi_awburst,
+ s_axi_awlock,
+ s_axi_awcache,
+ s_axi_awprot,
+ s_axi_awqos,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wid,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wlast,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bid,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_arid,
+ s_axi_araddr,
+ s_axi_arlen,
+ s_axi_arsize,
+ s_axi_arburst,
+ s_axi_arlock,
+ s_axi_arcache,
+ s_axi_arprot,
+ s_axi_arqos,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rid,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rlast,
+ s_axi_rvalid,
+ s_axi_rready,
+ m_axi_awaddr,
+ m_axi_awprot,
+ m_axi_awvalid,
+ m_axi_awready,
+ m_axi_wdata,
+ m_axi_wstrb,
+ m_axi_wvalid,
+ m_axi_wready,
+ m_axi_bresp,
+ m_axi_bvalid,
+ m_axi_bready,
+ m_axi_araddr,
+ m_axi_arprot,
+ m_axi_arvalid,
+ m_axi_arready,
+ m_axi_rdata,
+ m_axi_rresp,
+ m_axi_rvalid,
+ m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
+S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+ axi_protocol_converter_v2_1_19_axi_protocol_converter #(
+ .C_FAMILY("zynq"),
+ .C_M_AXI_PROTOCOL(2),
+ .C_S_AXI_PROTOCOL(1),
+ .C_IGNORE_ID(0),
+ .C_AXI_ID_WIDTH(12),
+ .C_AXI_ADDR_WIDTH(32),
+ .C_AXI_DATA_WIDTH(32),
+ .C_AXI_SUPPORTS_WRITE(1),
+ .C_AXI_SUPPORTS_READ(1),
+ .C_AXI_SUPPORTS_USER_SIGNALS(0),
+ .C_AXI_AWUSER_WIDTH(1),
+ .C_AXI_ARUSER_WIDTH(1),
+ .C_AXI_WUSER_WIDTH(1),
+ .C_AXI_RUSER_WIDTH(1),
+ .C_AXI_BUSER_WIDTH(1),
+ .C_TRANSLATION_MODE(2)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .s_axi_awid(s_axi_awid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awlen(s_axi_awlen),
+ .s_axi_awsize(s_axi_awsize),
+ .s_axi_awburst(s_axi_awburst),
+ .s_axi_awlock(s_axi_awlock),
+ .s_axi_awcache(s_axi_awcache),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awregion(4'H0),
+ .s_axi_awqos(s_axi_awqos),
+ .s_axi_awuser(1'H0),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_wid(s_axi_wid),
+ .s_axi_wdata(s_axi_wdata),
+ .s_axi_wstrb(s_axi_wstrb),
+ .s_axi_wlast(s_axi_wlast),
+ .s_axi_wuser(1'H0),
+ .s_axi_wvalid(s_axi_wvalid),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_bid(s_axi_bid),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_buser(),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_arid(s_axi_arid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arlen(s_axi_arlen),
+ .s_axi_arsize(s_axi_arsize),
+ .s_axi_arburst(s_axi_arburst),
+ .s_axi_arlock(s_axi_arlock),
+ .s_axi_arcache(s_axi_arcache),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arregion(4'H0),
+ .s_axi_arqos(s_axi_arqos),
+ .s_axi_aruser(1'H0),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_rid(s_axi_rid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rlast(s_axi_rlast),
+ .s_axi_ruser(),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_rready(s_axi_rready),
+ .m_axi_awid(),
+ .m_axi_awaddr(m_axi_awaddr),
+ .m_axi_awlen(),
+ .m_axi_awsize(),
+ .m_axi_awburst(),
+ .m_axi_awlock(),
+ .m_axi_awcache(),
+ .m_axi_awprot(m_axi_awprot),
+ .m_axi_awregion(),
+ .m_axi_awqos(),
+ .m_axi_awuser(),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_wid(),
+ .m_axi_wdata(m_axi_wdata),
+ .m_axi_wstrb(m_axi_wstrb),
+ .m_axi_wlast(),
+ .m_axi_wuser(),
+ .m_axi_wvalid(m_axi_wvalid),
+ .m_axi_wready(m_axi_wready),
+ .m_axi_bid(12'H000),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_buser(1'H0),
+ .m_axi_bvalid(m_axi_bvalid),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_arid(),
+ .m_axi_araddr(m_axi_araddr),
+ .m_axi_arlen(),
+ .m_axi_arsize(),
+ .m_axi_arburst(),
+ .m_axi_arlock(),
+ .m_axi_arcache(),
+ .m_axi_arprot(m_axi_arprot),
+ .m_axi_arregion(),
+ .m_axi_arqos(),
+ .m_axi_aruser(),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_rid(12'H000),
+ .m_axi_rdata(m_axi_rdata),
+ .m_axi_rresp(m_axi_rresp),
+ .m_axi_rlast(1'H1),
+ .m_axi_ruser(1'H0),
+ .m_axi_rvalid(m_axi_rvalid),
+ .m_axi_rready(m_axi_rready)
+ );
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.dcp b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.dcp
new file mode 100755
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literal 0
HcmV?d00001
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xci b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xci
index cdc5405..f2b1577 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xci
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xci
@@ -14,7 +14,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
@@ -29,10 +29,10 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
@@ -41,7 +41,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
@@ -109,10 +109,8 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xml
index 55548e1..a8ed23b 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xml
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0.xml
@@ -344,7 +344,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -353,7 +353,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -380,7 +380,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -389,7 +389,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -398,7 +398,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -480,7 +480,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1713,6 +1713,159 @@ interrupt is set.
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsynthesis</spirit:name>
+ <spirit:displayName>VHDL Synthesis</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>axi_iic</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:03 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:d91695c9</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_synthesisconstraints</spirit:name>
+ <spirit:displayName>Synthesis Constraints</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:d91695c9</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+ <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>TopLevel_axi_iic_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:03 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:d91695c9</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
+ <spirit:displayName>VHDL Simulation</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>axi_iic</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 00:11:30 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:0b10a320</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+ <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>TopLevel_axi_iic_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:03 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:0b10a320</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_implementation</spirit:name>
+ <spirit:displayName>Implementation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:03 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:d91695c9</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_externalfiles</spirit:name>
+ <spirit:displayName>External Files</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:18 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:d91695c9</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>s_axi_aclk</spirit:name>
@@ -1721,7 +1874,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1733,7 +1887,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1748,7 +1903,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1764,7 +1920,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1776,7 +1933,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1788,7 +1946,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1804,7 +1963,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1820,7 +1980,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1832,7 +1993,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1844,7 +2006,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1860,7 +2023,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1872,7 +2036,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1884,7 +2049,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1900,7 +2066,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1912,7 +2079,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1924,7 +2092,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1940,7 +2109,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1956,7 +2126,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1968,7 +2139,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1980,7 +2152,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1992,7 +2165,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2004,7 +2178,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2016,7 +2191,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2028,7 +2204,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2040,7 +2217,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2052,7 +2230,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2068,7 +2247,8 @@ interrupt is set.
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2147,6 +2327,218 @@ interrupt is set.
<spirit:enumeration spirit:text="10 bit">10_bit</spirit:enumeration>
</spirit:choice>
</spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>lib_pkg_v1_0_2</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_pkg" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="7b6d6b71">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
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+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
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+ <spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:name>
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+ <spirit:name>../../ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>axi_lite_ipif_v3_0_4</spirit:logicalName>
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+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_lite_ipif" xilinx:version="3.0" xilinx:isGenerated="true" xilinx:checksum="db189391">
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+ <spirit:fileType>vhdlSource</spirit:fileType>
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+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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+ <spirit:name>sim/TopLevel_axi_iic_0_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_axi_iic_0_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
<spirit:description>AXI IIC controller</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -2311,10 +2703,8 @@ interrupt is set.
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_board.xdc b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_board.xdc
new file mode 100644
index 0000000..3422a8e
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_ooc.xdc b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_ooc.xdc
new file mode 100644
index 0000000..ebc0a44
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_ooc.xdc
@@ -0,0 +1,50 @@
+
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+create_clock -name s_axi_clk -period 10.000 [get_ports s_axi_aclk]
+##set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.v
new file mode 100644
index 0000000..dc5e9be
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.v
@@ -0,0 +1,10687 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Mon Oct 14 17:13:30 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode funcsim -rename_top TopLevel_axi_iic_0_0 -prefix
+// TopLevel_axi_iic_0_0_ TopLevel_axi_iic_0_0_sim_netlist.v
+// Design : TopLevel_axi_iic_0_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module TopLevel_axi_iic_0_0_SRL_FIFO
+ (Rc_Data_Exists,
+ Rc_addr,
+ Rc_fifo_data,
+ msms_set_i_reg,
+ D,
+ \Addr_Counters[1].FDRE_I_0 ,
+ Bus2IIC_Reset,
+ D_0,
+ s_axi_aclk,
+ \s_axi_rdata_i[7]_i_11 ,
+ Q,
+ Msms_set,
+ \Addr_Counters[0].FDRE_I_0 ,
+ \Addr_Counters[0].FDRE_I_1 ,
+ Rc_fifo_rd,
+ Rc_fifo_rd_d,
+ Rc_fifo_wr_d,
+ Rc_fifo_wr);
+ output Rc_Data_Exists;
+ output [0:3]Rc_addr;
+ output [0:7]Rc_fifo_data;
+ output msms_set_i_reg;
+ output [1:0]D;
+ output \Addr_Counters[1].FDRE_I_0 ;
+ input Bus2IIC_Reset;
+ input D_0;
+ input s_axi_aclk;
+ input [7:0]\s_axi_rdata_i[7]_i_11 ;
+ input [3:0]Q;
+ input Msms_set;
+ input \Addr_Counters[0].FDRE_I_0 ;
+ input \Addr_Counters[0].FDRE_I_1 ;
+ input Rc_fifo_rd;
+ input Rc_fifo_rd_d;
+ input Rc_fifo_wr_d;
+ input Rc_fifo_wr;
+
+ wire \Addr_Counters[0].FDRE_I_0 ;
+ wire \Addr_Counters[0].FDRE_I_1 ;
+ wire \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ;
+ wire \Addr_Counters[1].FDRE_I_0 ;
+ wire \Addr_Counters[3].XORCY_I_i_1__1_n_0 ;
+ wire Bus2IIC_Reset;
+ wire CI;
+ wire [1:0]D;
+ wire D_0;
+ wire Msms_set;
+ wire [3:0]Q;
+ wire \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ;
+ wire \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ;
+ wire Rc_Data_Exists;
+ wire [0:3]Rc_addr;
+ wire [0:7]Rc_fifo_data;
+ wire Rc_fifo_rd;
+ wire Rc_fifo_rd_d;
+ wire Rc_fifo_wr;
+ wire Rc_fifo_wr_d;
+ wire S;
+ wire S0_out;
+ wire S1_out;
+ wire addr_cy_1;
+ wire addr_cy_2;
+ wire addr_cy_3;
+ wire msms_set_i_reg;
+ wire s_axi_aclk;
+ wire [7:0]\s_axi_rdata_i[7]_i_11 ;
+ wire sum_A_0;
+ wire sum_A_1;
+ wire sum_A_2;
+ wire sum_A_3;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
+
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[0].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Rc_Data_Exists),
+ .D(sum_A_3),
+ .Q(Rc_addr[0]),
+ .R(Bus2IIC_Reset));
+ (* OPT_MODIFIED = "MLO" *)
+ (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
+ (* XILINX_TRANSFORM_PINMAP = "LO:O" *)
+ (* box_type = "PRIMITIVE" *)
+ CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
+ (.CI(1'b0),
+ .CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
+ .CYINIT(CI),
+ .DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],Rc_addr[2],Rc_addr[1],Rc_addr[0]}),
+ .O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
+ .S({\Addr_Counters[3].XORCY_I_i_1__1_n_0 ,S0_out,S1_out,S}));
+ LUT4 #(
+ .INIT(16'hA208))
+ \Addr_Counters[0].MUXCY_L_I_i_1__1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
+ .I1(Rc_fifo_rd),
+ .I2(Rc_fifo_rd_d),
+ .I3(Rc_addr[0]),
+ .O(S));
+ LUT6 #(
+ .INIT(64'hFFFF7FFF00000000))
+ \Addr_Counters[0].MUXCY_L_I_i_2__0
+ (.I0(Rc_addr[1]),
+ .I1(Rc_addr[2]),
+ .I2(Rc_addr[3]),
+ .I3(Rc_addr[0]),
+ .I4(\Addr_Counters[0].FDRE_I_0 ),
+ .I5(\Addr_Counters[0].FDRE_I_1 ),
+ .O(CI));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFF4))
+ \Addr_Counters[0].MUXCY_L_I_i_3__1
+ (.I0(Rc_fifo_wr_d),
+ .I1(Rc_fifo_wr),
+ .I2(Rc_addr[0]),
+ .I3(Rc_addr[3]),
+ .I4(Rc_addr[2]),
+ .I5(Rc_addr[1]),
+ .O(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[1].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Rc_Data_Exists),
+ .D(sum_A_2),
+ .Q(Rc_addr[1]),
+ .R(Bus2IIC_Reset));
+ LUT4 #(
+ .INIT(16'hA208))
+ \Addr_Counters[1].MUXCY_L_I_i_1__1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
+ .I1(Rc_fifo_rd),
+ .I2(Rc_fifo_rd_d),
+ .I3(Rc_addr[1]),
+ .O(S1_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[2].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Rc_Data_Exists),
+ .D(sum_A_1),
+ .Q(Rc_addr[2]),
+ .R(Bus2IIC_Reset));
+ LUT4 #(
+ .INIT(16'hA208))
+ \Addr_Counters[2].MUXCY_L_I_i_1__1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
+ .I1(Rc_fifo_rd),
+ .I2(Rc_fifo_rd_d),
+ .I3(Rc_addr[2]),
+ .O(S0_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[3].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Rc_Data_Exists),
+ .D(sum_A_0),
+ .Q(Rc_addr[3]),
+ .R(Bus2IIC_Reset));
+ LUT4 #(
+ .INIT(16'hA208))
+ \Addr_Counters[3].XORCY_I_i_1__1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
+ .I1(Rc_fifo_rd),
+ .I2(Rc_fifo_rd_d),
+ .I3(Rc_addr[3]),
+ .O(\Addr_Counters[3].XORCY_I_i_1__1_n_0 ));
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ Data_Exists_DFF
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(D_0),
+ .Q(Rc_Data_Exists),
+ .R(Bus2IIC_Reset));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ Data_Exists_DFF_i_2__0
+ (.I0(Rc_addr[1]),
+ .I1(Rc_addr[2]),
+ .I2(Rc_addr[3]),
+ .I3(Rc_addr[0]),
+ .O(\Addr_Counters[1].FDRE_I_0 ));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[0].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[0].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [7]),
+ .Q(Rc_fifo_data[0]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[1].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[1].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [6]),
+ .Q(Rc_fifo_data[1]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[2].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[2].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [5]),
+ .Q(Rc_fifo_data[2]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[3].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[3].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [4]),
+ .Q(Rc_fifo_data[3]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[4].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[4].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [3]),
+ .Q(Rc_fifo_data[4]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[5].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[5].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [2]),
+ .Q(Rc_fifo_data[5]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[6].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[6].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [1]),
+ .Q(Rc_fifo_data[6]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[7].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[7].SRL16E_I
+ (.A0(Rc_addr[0]),
+ .A1(Rc_addr[1]),
+ .A2(Rc_addr[2]),
+ .A3(Rc_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(\s_axi_rdata_i[7]_i_11 [0]),
+ .Q(Rc_fifo_data[7]));
+ LUT6 #(
+ .INIT(64'h0001000000000001))
+ \RD_FIFO_CNTRL.ro_prev_i_i_1
+ (.I0(Bus2IIC_Reset),
+ .I1(Msms_set),
+ .I2(\RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ),
+ .I3(\RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ),
+ .I4(Q[3]),
+ .I5(Rc_addr[3]),
+ .O(msms_set_i_reg));
+ LUT4 #(
+ .INIT(16'h6FF6))
+ \RD_FIFO_CNTRL.ro_prev_i_i_2
+ (.I0(Rc_addr[1]),
+ .I1(Q[1]),
+ .I2(Rc_addr[2]),
+ .I3(Q[2]),
+ .O(\RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT3 #(
+ .INIT(8'h6F))
+ \RD_FIFO_CNTRL.ro_prev_i_i_3
+ (.I0(Rc_addr[0]),
+ .I1(Q[0]),
+ .I2(Rc_Data_Exists),
+ .O(\RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \sr_i[1]_i_1
+ (.I0(Rc_Data_Exists),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \sr_i[2]_i_1
+ (.I0(Rc_addr[1]),
+ .I1(Rc_addr[2]),
+ .I2(Rc_addr[3]),
+ .I3(Rc_addr[0]),
+ .O(D[0]));
+endmodule
+
+(* ORIG_REF_NAME = "SRL_FIFO" *)
+module TopLevel_axi_iic_0_0_SRL_FIFO_0
+ (Tx_data_exists,
+ Tx_addr,
+ Tx_fifo_data,
+ \Addr_Counters[0].FDRE_I_0 ,
+ Data_Exists_DFF_0,
+ p_0_in,
+ Data_Exists_DFF_1,
+ shift_reg_ld_reg,
+ Tx_fifo_rst,
+ s_axi_aclk,
+ s_axi_wdata,
+ Data_Exists_DFF_2,
+ \Addr_Counters[0].FDRE_I_1 ,
+ Tx_fifo_wr,
+ Tx_fifo_wr_d,
+ rdCntrFrmTxFifo,
+ Tx_fifo_rd_d,
+ Tx_fifo_rd,
+ dynamic_MSMS,
+ shift_reg_ld,
+ \data_int_reg[0] );
+ output Tx_data_exists;
+ output [0:3]Tx_addr;
+ output [0:7]Tx_fifo_data;
+ output [0:0]\Addr_Counters[0].FDRE_I_0 ;
+ output Data_Exists_DFF_0;
+ output p_0_in;
+ output Data_Exists_DFF_1;
+ output [0:0]shift_reg_ld_reg;
+ input Tx_fifo_rst;
+ input s_axi_aclk;
+ input [7:0]s_axi_wdata;
+ input Data_Exists_DFF_2;
+ input \Addr_Counters[0].FDRE_I_1 ;
+ input Tx_fifo_wr;
+ input Tx_fifo_wr_d;
+ input rdCntrFrmTxFifo;
+ input Tx_fifo_rd_d;
+ input Tx_fifo_rd;
+ input [0:0]dynamic_MSMS;
+ input shift_reg_ld;
+ input \data_int_reg[0] ;
+
+ wire [0:0]\Addr_Counters[0].FDRE_I_0 ;
+ wire \Addr_Counters[0].FDRE_I_1 ;
+ wire \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ;
+ wire \Addr_Counters[3].XORCY_I_i_1__0_n_0 ;
+ wire CI;
+ wire D;
+ wire Data_Exists_DFF_0;
+ wire Data_Exists_DFF_1;
+ wire Data_Exists_DFF_2;
+ wire Data_Exists_DFF_i_3_n_0;
+ wire S;
+ wire S0_out;
+ wire S1_out;
+ wire [0:3]Tx_addr;
+ wire Tx_data_exists;
+ wire [0:7]Tx_fifo_data;
+ wire Tx_fifo_rd;
+ wire Tx_fifo_rd_d;
+ wire Tx_fifo_rst;
+ wire Tx_fifo_wr;
+ wire Tx_fifo_wr_d;
+ wire addr_cy_1;
+ wire addr_cy_2;
+ wire addr_cy_3;
+ wire \data_int_reg[0] ;
+ wire [0:0]dynamic_MSMS;
+ wire p_0_in;
+ wire rdCntrFrmTxFifo;
+ wire s_axi_aclk;
+ wire [7:0]s_axi_wdata;
+ wire shift_reg_ld;
+ wire [0:0]shift_reg_ld_reg;
+ wire sum_A_0;
+ wire sum_A_1;
+ wire sum_A_2;
+ wire sum_A_3;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
+
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[0].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Tx_data_exists),
+ .D(sum_A_3),
+ .Q(Tx_addr[0]),
+ .R(Tx_fifo_rst));
+ (* OPT_MODIFIED = "MLO" *)
+ (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
+ (* XILINX_TRANSFORM_PINMAP = "LO:O" *)
+ (* box_type = "PRIMITIVE" *)
+ CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
+ (.CI(1'b0),
+ .CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
+ .CYINIT(CI),
+ .DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],Tx_addr[2],Tx_addr[1],Tx_addr[0]}),
+ .O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
+ .S({\Addr_Counters[3].XORCY_I_i_1__0_n_0 ,S0_out,S1_out,S}));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[0].MUXCY_L_I_i_1__0
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(Tx_addr[0]),
+ .O(S));
+ LUT6 #(
+ .INIT(64'h7FFFFFFF00000000))
+ \Addr_Counters[0].MUXCY_L_I_i_2__1
+ (.I0(Data_Exists_DFF_2),
+ .I1(Tx_addr[0]),
+ .I2(Tx_addr[3]),
+ .I3(Tx_addr[2]),
+ .I4(Tx_addr[1]),
+ .I5(\Addr_Counters[0].FDRE_I_1 ),
+ .O(CI));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFF4))
+ \Addr_Counters[0].MUXCY_L_I_i_3__0
+ (.I0(Tx_fifo_wr_d),
+ .I1(Tx_fifo_wr),
+ .I2(Tx_addr[1]),
+ .I3(Tx_addr[2]),
+ .I4(Tx_addr[3]),
+ .I5(Tx_addr[0]),
+ .O(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[1].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Tx_data_exists),
+ .D(sum_A_2),
+ .Q(Tx_addr[1]),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[1].MUXCY_L_I_i_1__0
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(Tx_addr[1]),
+ .O(S1_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[2].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Tx_data_exists),
+ .D(sum_A_1),
+ .Q(Tx_addr[2]),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[2].MUXCY_L_I_i_1__0
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(Tx_addr[2]),
+ .O(S0_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[3].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Tx_data_exists),
+ .D(sum_A_0),
+ .Q(Tx_addr[3]),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[3].XORCY_I_i_1__0
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(Tx_addr[3]),
+ .O(\Addr_Counters[3].XORCY_I_i_1__0_n_0 ));
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ Data_Exists_DFF
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(D),
+ .Q(Tx_data_exists),
+ .R(Tx_fifo_rst));
+ (* SOFT_HLUTNM = "soft_lutpair36" *)
+ LUT5 #(
+ .INIT(32'hFFF20022))
+ Data_Exists_DFF_i_1__0
+ (.I0(Tx_fifo_wr),
+ .I1(Tx_fifo_wr_d),
+ .I2(Data_Exists_DFF_2),
+ .I3(Data_Exists_DFF_i_3_n_0),
+ .I4(Tx_data_exists),
+ .O(D));
+ (* SOFT_HLUTNM = "soft_lutpair37" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ Data_Exists_DFF_i_3
+ (.I0(Tx_addr[0]),
+ .I1(Tx_addr[3]),
+ .I2(Tx_addr[2]),
+ .I3(Tx_addr[1]),
+ .O(Data_Exists_DFF_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ \FIFO_GEN_DTR.IIC2Bus_IntrEvent[7]_i_1
+ (.I0(Tx_addr[3]),
+ .O(p_0_in));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[0].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[0].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[7]),
+ .Q(Tx_fifo_data[0]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[1].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[1].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[6]),
+ .Q(Tx_fifo_data[1]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[2].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[2].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[5]),
+ .Q(Tx_fifo_data[2]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[3].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[3].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[4]),
+ .Q(Tx_fifo_data[3]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[4].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[4].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[3]),
+ .Q(Tx_fifo_data[4]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[5].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[5].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[2]),
+ .Q(Tx_fifo_data[5]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[6].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[6].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[1]),
+ .Q(Tx_fifo_data[6]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[7].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[7].SRL16E_I
+ (.A0(Tx_addr[0]),
+ .A1(Tx_addr[1]),
+ .A2(Tx_addr[2]),
+ .A3(Tx_addr[3]),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(s_axi_wdata[0]),
+ .Q(Tx_fifo_data[7]));
+ LUT2 #(
+ .INIT(4'h7))
+ \cr_i[5]_i_2
+ (.I0(Tx_data_exists),
+ .I1(dynamic_MSMS),
+ .O(Data_Exists_DFF_1));
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[0]_i_1
+ (.I0(Tx_fifo_data[7]),
+ .I1(shift_reg_ld),
+ .I2(\data_int_reg[0] ),
+ .O(shift_reg_ld_reg));
+ (* SOFT_HLUTNM = "soft_lutpair36" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \sr_i[0]_i_1
+ (.I0(Tx_data_exists),
+ .O(Data_Exists_DFF_0));
+ (* SOFT_HLUTNM = "soft_lutpair37" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \sr_i[3]_i_1
+ (.I0(Tx_addr[0]),
+ .I1(Tx_addr[3]),
+ .I2(Tx_addr[2]),
+ .I3(Tx_addr[1]),
+ .O(\Addr_Counters[0].FDRE_I_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "SRL_FIFO" *)
+module TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0
+ (Data_Exists_DFF_0,
+ dynamic_MSMS,
+ Data_Exists_DFF_1,
+ \Addr_Counters[1].FDRE_I_0 ,
+ Tx_fifo_rst,
+ D,
+ s_axi_aclk,
+ ctrlFifoDin,
+ rdCntrFrmTxFifo,
+ Tx_fifo_rd_d,
+ Tx_fifo_rd,
+ \Addr_Counters[0].FDRE_I_0 ,
+ \Addr_Counters[0].FDRE_I_1 ,
+ Tx_data_exists);
+ output Data_Exists_DFF_0;
+ output [0:1]dynamic_MSMS;
+ output Data_Exists_DFF_1;
+ output \Addr_Counters[1].FDRE_I_0 ;
+ input Tx_fifo_rst;
+ input D;
+ input s_axi_aclk;
+ input [0:1]ctrlFifoDin;
+ input rdCntrFrmTxFifo;
+ input Tx_fifo_rd_d;
+ input Tx_fifo_rd;
+ input \Addr_Counters[0].FDRE_I_0 ;
+ input \Addr_Counters[0].FDRE_I_1 ;
+ input Tx_data_exists;
+
+ wire \Addr_Counters[0].FDRE_I_0 ;
+ wire \Addr_Counters[0].FDRE_I_1 ;
+ wire \Addr_Counters[0].FDRE_I_n_0 ;
+ wire \Addr_Counters[0].MUXCY_L_I_i_3_n_0 ;
+ wire \Addr_Counters[1].FDRE_I_0 ;
+ wire \Addr_Counters[1].FDRE_I_n_0 ;
+ wire \Addr_Counters[2].FDRE_I_n_0 ;
+ wire \Addr_Counters[3].FDRE_I_n_0 ;
+ wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
+ wire CI;
+ wire D;
+ wire Data_Exists_DFF_0;
+ wire Data_Exists_DFF_1;
+ wire S;
+ wire S0_out;
+ wire S1_out;
+ wire Tx_data_exists;
+ wire Tx_fifo_rd;
+ wire Tx_fifo_rd_d;
+ wire Tx_fifo_rst;
+ wire addr_cy_1;
+ wire addr_cy_2;
+ wire addr_cy_3;
+ wire [0:1]ctrlFifoDin;
+ wire [0:1]dynamic_MSMS;
+ wire rdCntrFrmTxFifo;
+ wire s_axi_aclk;
+ wire sum_A_0;
+ wire sum_A_1;
+ wire sum_A_2;
+ wire sum_A_3;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
+ wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
+
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[0].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Data_Exists_DFF_0),
+ .D(sum_A_3),
+ .Q(\Addr_Counters[0].FDRE_I_n_0 ),
+ .R(Tx_fifo_rst));
+ (* OPT_MODIFIED = "MLO" *)
+ (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
+ (* XILINX_TRANSFORM_PINMAP = "LO:O" *)
+ (* box_type = "PRIMITIVE" *)
+ CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
+ (.CI(1'b0),
+ .CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
+ .CYINIT(CI),
+ .DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
+ .O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
+ .S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[0].MUXCY_L_I_i_1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(\Addr_Counters[0].FDRE_I_n_0 ),
+ .O(S));
+ LUT6 #(
+ .INIT(64'h2AAAAAAAAAAAAAAA))
+ \Addr_Counters[0].MUXCY_L_I_i_2
+ (.I0(\Addr_Counters[0].FDRE_I_0 ),
+ .I1(\Addr_Counters[2].FDRE_I_n_0 ),
+ .I2(\Addr_Counters[3].FDRE_I_n_0 ),
+ .I3(\Addr_Counters[1].FDRE_I_n_0 ),
+ .I4(\Addr_Counters[0].FDRE_I_n_0 ),
+ .I5(\Addr_Counters[0].FDRE_I_1 ),
+ .O(CI));
+ (* SOFT_HLUTNM = "soft_lutpair35" *)
+ LUT5 #(
+ .INIT(32'hFFFFFFFE))
+ \Addr_Counters[0].MUXCY_L_I_i_3
+ (.I0(\Addr_Counters[0].FDRE_I_0 ),
+ .I1(\Addr_Counters[2].FDRE_I_n_0 ),
+ .I2(\Addr_Counters[0].FDRE_I_n_0 ),
+ .I3(\Addr_Counters[3].FDRE_I_n_0 ),
+ .I4(\Addr_Counters[1].FDRE_I_n_0 ),
+ .O(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[1].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Data_Exists_DFF_0),
+ .D(sum_A_2),
+ .Q(\Addr_Counters[1].FDRE_I_n_0 ),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[1].MUXCY_L_I_i_1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(\Addr_Counters[1].FDRE_I_n_0 ),
+ .O(S1_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[2].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Data_Exists_DFF_0),
+ .D(sum_A_1),
+ .Q(\Addr_Counters[2].FDRE_I_n_0 ),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[2].MUXCY_L_I_i_1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(\Addr_Counters[2].FDRE_I_n_0 ),
+ .O(S0_out));
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \Addr_Counters[3].FDRE_I
+ (.C(s_axi_aclk),
+ .CE(Data_Exists_DFF_0),
+ .D(sum_A_0),
+ .Q(\Addr_Counters[3].FDRE_I_n_0 ),
+ .R(Tx_fifo_rst));
+ LUT5 #(
+ .INIT(32'h20228A88))
+ \Addr_Counters[3].XORCY_I_i_1
+ (.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
+ .I1(rdCntrFrmTxFifo),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .I4(\Addr_Counters[3].FDRE_I_n_0 ),
+ .O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ Data_Exists_DFF
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(D),
+ .Q(Data_Exists_DFF_0),
+ .R(Tx_fifo_rst));
+ (* SOFT_HLUTNM = "soft_lutpair35" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ Data_Exists_DFF_i_3__0
+ (.I0(\Addr_Counters[1].FDRE_I_n_0 ),
+ .I1(\Addr_Counters[3].FDRE_I_n_0 ),
+ .I2(\Addr_Counters[0].FDRE_I_n_0 ),
+ .I3(\Addr_Counters[2].FDRE_I_n_0 ),
+ .O(\Addr_Counters[1].FDRE_I_0 ));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[0].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[0].SRL16E_I
+ (.A0(\Addr_Counters[0].FDRE_I_n_0 ),
+ .A1(\Addr_Counters[1].FDRE_I_n_0 ),
+ .A2(\Addr_Counters[2].FDRE_I_n_0 ),
+ .A3(\Addr_Counters[3].FDRE_I_n_0 ),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(ctrlFifoDin[0]),
+ .Q(dynamic_MSMS[0]));
+ (* box_type = "PRIMITIVE" *)
+ (* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM " *)
+ (* srl_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[1].SRL16E_I " *)
+ SRL16E #(
+ .INIT(16'h0000),
+ .IS_CLK_INVERTED(1'b0))
+ \FIFO_RAM[1].SRL16E_I
+ (.A0(\Addr_Counters[0].FDRE_I_n_0 ),
+ .A1(\Addr_Counters[1].FDRE_I_n_0 ),
+ .A2(\Addr_Counters[2].FDRE_I_n_0 ),
+ .A3(\Addr_Counters[3].FDRE_I_n_0 ),
+ .CE(CI),
+ .CLK(s_axi_aclk),
+ .D(ctrlFifoDin[1]),
+ .Q(dynamic_MSMS[1]));
+ LUT4 #(
+ .INIT(16'hF7FF))
+ \cr_i[2]_i_3
+ (.I0(dynamic_MSMS[1]),
+ .I1(Tx_data_exists),
+ .I2(Tx_fifo_rd_d),
+ .I3(Tx_fifo_rd),
+ .O(Data_Exists_DFF_1));
+endmodule
+
+(* CHECK_LICENSE_TYPE = "TopLevel_axi_iic_0_0,axi_iic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_iic,Vivado 2019.1" *)
+(* NotValidForBitStream *)
+module TopLevel_axi_iic_0_0
+ (s_axi_aclk,
+ s_axi_aresetn,
+ iic2intc_irpt,
+ s_axi_awaddr,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_araddr,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rvalid,
+ s_axi_rready,
+ sda_i,
+ sda_o,
+ sda_t,
+ scl_i,
+ scl_o,
+ scl_t,
+ gpo);
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, INSERT_VIP 0" *) input s_axi_aclk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
+ (* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) output iic2intc_irpt;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_I" *) (* x_interface_parameter = "XIL_INTERFACENAME IIC, BOARD.ASSOCIATED_PARAM IIC_BOARD_INTERFACE" *) input sda_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_O" *) output sda_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_T" *) output sda_t;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_I" *) input scl_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_O" *) output scl_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_T" *) output scl_t;
+ output [0:0]gpo;
+
+ wire [0:0]gpo;
+ wire iic2intc_irpt;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arready;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awready;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [1:0]s_axi_bresp;
+ wire s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire s_axi_rready;
+ wire [1:0]s_axi_rresp;
+ wire s_axi_rvalid;
+ wire [31:0]s_axi_wdata;
+ wire s_axi_wready;
+ wire [3:0]s_axi_wstrb;
+ wire s_axi_wvalid;
+ wire scl_i;
+ wire scl_o;
+ wire scl_t;
+ wire sda_i;
+ wire sda_o;
+ wire sda_t;
+
+ (* C_DEFAULT_VALUE = "8'b00000000" *)
+ (* C_FAMILY = "zynq" *)
+ (* C_GPO_WIDTH = "1" *)
+ (* C_IIC_FREQ = "100000" *)
+ (* C_SCL_INERTIAL_DELAY = "0" *)
+ (* C_SDA_INERTIAL_DELAY = "0" *)
+ (* C_SDA_LEVEL = "1" *)
+ (* C_SMBUS_PMBUS_HOST = "0" *)
+ (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
+ (* C_S_AXI_ADDR_WIDTH = "9" *)
+ (* C_S_AXI_DATA_WIDTH = "32" *)
+ (* C_TEN_BIT_ADR = "0" *)
+ (* downgradeipidentifiedwarnings = "yes" *)
+ TopLevel_axi_iic_0_0_axi_iic U0
+ (.gpo(gpo),
+ .iic2intc_irpt(iic2intc_irpt),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_wdata(s_axi_wdata),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wstrb(s_axi_wstrb),
+ .s_axi_wvalid(s_axi_wvalid),
+ .scl_i(scl_i),
+ .scl_o(scl_o),
+ .scl_t(scl_t),
+ .sda_i(sda_i),
+ .sda_o(sda_o),
+ .sda_t(sda_t));
+endmodule
+
+module TopLevel_axi_iic_0_0_address_decoder
+ (\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ,
+ Bus_RNW_reg_reg_0,
+ is_write_reg,
+ is_read_reg,
+ irpt_wrack,
+ E,
+ reset_trig0,
+ sw_rst_cond,
+ AXI_IP2Bus_Error,
+ \s_axi_wdata[5] ,
+ Bus2IIC_WrCE,
+ \bus2ip_addr_i_reg[3] ,
+ D,
+ Bus2IIC_RdCE,
+ \FSM_onehot_state_reg[2] ,
+ \s_axi_wdata[31] ,
+ s_axi_wdata_0_sp_1,
+ AXI_IP2Bus_WrAck20,
+ AXI_IP2Bus_RdAck20,
+ Q,
+ s_axi_aclk,
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 ,
+ s_axi_aresetn,
+ s_axi_arready,
+ AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2,
+ s_axi_awready,
+ AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2,
+ s_axi_awready_0,
+ sw_rst_cond_d1,
+ s_axi_wdata,
+ \cr_i_reg[2] ,
+ \cr_i_reg[2]_0 ,
+ firstDynStartSeen,
+ \cr_i_reg[2]_1 ,
+ \s_axi_rdata_i_reg[8] ,
+ \s_axi_rdata_i_reg[0] ,
+ \s_axi_rdata_i_reg[0]_0 ,
+ \s_axi_rdata_i_reg[1] ,
+ \s_axi_rdata_i_reg[1]_0 ,
+ \s_axi_rdata_i_reg[7] ,
+ p_1_in8_in,
+ \s_axi_rdata_i_reg[4] ,
+ \s_axi_rdata_i_reg[5] ,
+ p_1_in5_in,
+ \s_axi_rdata_i_reg[6] ,
+ p_1_in2_in,
+ \s_axi_rdata_i_reg[7]_0 ,
+ p_1_in,
+ cr_txModeSelect_set,
+ cr_txModeSelect_clr,
+ \s_axi_rdata_i_reg[0]_1 ,
+ p_1_in17_in,
+ \s_axi_rdata_i_reg[2] ,
+ p_1_in14_in,
+ \s_axi_rdata_i_reg[3] ,
+ p_1_in11_in,
+ ipif_glbl_irpt_enable_reg,
+ \s_axi_bresp_i_reg[1] ,
+ s_axi_bresp,
+ gpo,
+ AXI_IP2Bus_WrAck2_reg);
+ output \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ;
+ output Bus_RNW_reg_reg_0;
+ output is_write_reg;
+ output is_read_reg;
+ output irpt_wrack;
+ output [0:0]E;
+ output reset_trig0;
+ output sw_rst_cond;
+ output AXI_IP2Bus_Error;
+ output [1:0]\s_axi_wdata[5] ;
+ output [11:0]Bus2IIC_WrCE;
+ output \bus2ip_addr_i_reg[3] ;
+ output [8:0]D;
+ output [0:0]Bus2IIC_RdCE;
+ output \FSM_onehot_state_reg[2] ;
+ output \s_axi_wdata[31] ;
+ output s_axi_wdata_0_sp_1;
+ output AXI_IP2Bus_WrAck20;
+ output AXI_IP2Bus_RdAck20;
+ input Q;
+ input s_axi_aclk;
+ input [8:0]\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 ;
+ input s_axi_aresetn;
+ input s_axi_arready;
+ input AXI_IP2Bus_RdAck1;
+ input AXI_IP2Bus_RdAck2;
+ input s_axi_awready;
+ input AXI_IP2Bus_WrAck1;
+ input AXI_IP2Bus_WrAck2;
+ input [3:0]s_axi_awready_0;
+ input sw_rst_cond_d1;
+ input [5:0]s_axi_wdata;
+ input \cr_i_reg[2] ;
+ input [1:0]\cr_i_reg[2]_0 ;
+ input firstDynStartSeen;
+ input \cr_i_reg[2]_1 ;
+ input \s_axi_rdata_i_reg[8] ;
+ input \s_axi_rdata_i_reg[0] ;
+ input \s_axi_rdata_i_reg[0]_0 ;
+ input \s_axi_rdata_i_reg[1] ;
+ input \s_axi_rdata_i_reg[1]_0 ;
+ input [7:0]\s_axi_rdata_i_reg[7] ;
+ input p_1_in8_in;
+ input \s_axi_rdata_i_reg[4] ;
+ input \s_axi_rdata_i_reg[5] ;
+ input p_1_in5_in;
+ input \s_axi_rdata_i_reg[6] ;
+ input p_1_in2_in;
+ input \s_axi_rdata_i_reg[7]_0 ;
+ input p_1_in;
+ input cr_txModeSelect_set;
+ input cr_txModeSelect_clr;
+ input \s_axi_rdata_i_reg[0]_1 ;
+ input p_1_in17_in;
+ input \s_axi_rdata_i_reg[2] ;
+ input p_1_in14_in;
+ input \s_axi_rdata_i_reg[3] ;
+ input p_1_in11_in;
+ input ipif_glbl_irpt_enable_reg;
+ input [0:0]\s_axi_bresp_i_reg[1] ;
+ input [0:0]s_axi_bresp;
+ input [0:0]gpo;
+ input AXI_IP2Bus_WrAck2_reg;
+
+ wire [2:0]AXI_Bus2IP_CS;
+ wire AXI_IP2Bus_Error;
+ wire AXI_IP2Bus_RdAck1;
+ wire AXI_IP2Bus_RdAck2;
+ wire AXI_IP2Bus_RdAck20;
+ wire AXI_IP2Bus_WrAck1;
+ wire AXI_IP2Bus_WrAck2;
+ wire AXI_IP2Bus_WrAck20;
+ wire AXI_IP2Bus_WrAck2_reg;
+ wire [0:0]Bus2IIC_RdCE;
+ wire [11:0]Bus2IIC_WrCE;
+ wire Bus_RNW_reg_i_1_n_0;
+ wire Bus_RNW_reg_reg_0;
+ wire [8:0]D;
+ wire [0:0]E;
+ wire \FSM_onehot_state_reg[2] ;
+ wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ;
+ wire \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ;
+ wire \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ;
+ wire \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ;
+ wire \MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0 ;
+ wire [8:0]\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 ;
+ wire Q;
+ wire \bus2ip_addr_i_reg[3] ;
+ wire \cr_i_reg[2] ;
+ wire [1:0]\cr_i_reg[2]_0 ;
+ wire \cr_i_reg[2]_1 ;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire cs_ce_clr;
+ wire firstDynStartSeen;
+ wire [0:0]gpo;
+ wire ipif_glbl_irpt_enable_reg;
+ wire irpt_wrack;
+ wire is_read_reg;
+ wire is_write_reg;
+ wire p_10_in;
+ wire p_11_in;
+ wire p_12_in;
+ wire p_13_in;
+ wire p_14_in;
+ wire p_15_in;
+ wire p_16_in;
+ wire p_16_out;
+ wire p_17_in;
+ wire p_17_out;
+ wire p_18_in;
+ wire p_1_in;
+ wire p_1_in11_in;
+ wire p_1_in14_in;
+ wire p_1_in17_in;
+ wire p_1_in2_in;
+ wire p_1_in5_in;
+ wire p_1_in8_in;
+ wire p_25_in;
+ wire p_28_in;
+ wire p_2_in;
+ wire p_3_in;
+ wire p_4_in;
+ wire p_5_in;
+ wire p_5_out;
+ wire p_6_in;
+ wire p_7_in;
+ wire p_7_out;
+ wire p_8_in;
+ wire p_8_out;
+ wire p_9_in;
+ wire pselect_hit_i_0;
+ wire pselect_hit_i_2;
+ wire reset_trig0;
+ wire s_axi_aclk;
+ wire s_axi_aresetn;
+ wire s_axi_arready;
+ wire s_axi_awready;
+ wire [3:0]s_axi_awready_0;
+ wire [0:0]s_axi_bresp;
+ wire [0:0]\s_axi_bresp_i_reg[1] ;
+ wire \s_axi_rdata_i[0]_i_4_n_0 ;
+ wire \s_axi_rdata_i[1]_i_4_n_0 ;
+ wire \s_axi_rdata_i[7]_i_3_n_0 ;
+ wire \s_axi_rdata_i[7]_i_4_n_0 ;
+ wire \s_axi_rdata_i[7]_i_5_n_0 ;
+ wire \s_axi_rdata_i[9]_i_10_n_0 ;
+ wire \s_axi_rdata_i[9]_i_5_n_0 ;
+ wire \s_axi_rdata_i[9]_i_7_n_0 ;
+ wire \s_axi_rdata_i[9]_i_8_n_0 ;
+ wire \s_axi_rdata_i[9]_i_9_n_0 ;
+ wire \s_axi_rdata_i_reg[0] ;
+ wire \s_axi_rdata_i_reg[0]_0 ;
+ wire \s_axi_rdata_i_reg[0]_1 ;
+ wire \s_axi_rdata_i_reg[1] ;
+ wire \s_axi_rdata_i_reg[1]_0 ;
+ wire \s_axi_rdata_i_reg[2] ;
+ wire \s_axi_rdata_i_reg[3] ;
+ wire \s_axi_rdata_i_reg[4] ;
+ wire \s_axi_rdata_i_reg[5] ;
+ wire \s_axi_rdata_i_reg[6] ;
+ wire [7:0]\s_axi_rdata_i_reg[7] ;
+ wire \s_axi_rdata_i_reg[7]_0 ;
+ wire \s_axi_rdata_i_reg[8] ;
+ wire [5:0]s_axi_wdata;
+ wire \s_axi_wdata[31] ;
+ wire [1:0]\s_axi_wdata[5] ;
+ wire s_axi_wdata_0_sn_1;
+ wire s_axi_wready_INST_0_i_1_n_0;
+ wire sw_rst_cond;
+ wire sw_rst_cond_d1;
+
+ assign s_axi_wdata_0_sp_1 = s_axi_wdata_0_sn_1;
+ (* SOFT_HLUTNM = "soft_lutpair42" *)
+ LUT4 #(
+ .INIT(16'hFE00))
+ AXI_IP2Bus_RdAck2_i_1
+ (.I0(AXI_Bus2IP_CS[1]),
+ .I1(AXI_Bus2IP_CS[2]),
+ .I2(AXI_Bus2IP_CS[0]),
+ .I3(AXI_IP2Bus_WrAck2_reg),
+ .O(AXI_IP2Bus_RdAck20));
+ (* SOFT_HLUTNM = "soft_lutpair42" *)
+ LUT4 #(
+ .INIT(16'h00FE))
+ AXI_IP2Bus_WrAck2_i_1
+ (.I0(AXI_Bus2IP_CS[1]),
+ .I1(AXI_Bus2IP_CS[2]),
+ .I2(AXI_Bus2IP_CS[0]),
+ .I3(AXI_IP2Bus_WrAck2_reg),
+ .O(AXI_IP2Bus_WrAck20));
+ (* SOFT_HLUTNM = "soft_lutpair49" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ Bus_RNW_reg_i_1
+ (.I0(AXI_IP2Bus_WrAck2_reg),
+ .I1(Q),
+ .I2(Bus_RNW_reg_reg_0),
+ .O(Bus_RNW_reg_i_1_n_0));
+ FDRE Bus_RNW_reg_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Bus_RNW_reg_i_1_n_0),
+ .Q(Bus_RNW_reg_reg_0),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair53" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \FIFO_GEN_DTR.Tx_fifo_wr_i_1
+ (.I0(p_16_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[10]));
+ (* SOFT_HLUTNM = "soft_lutpair41" *)
+ LUT5 #(
+ .INIT(32'h02000000))
+ \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
+ (.I0(pselect_hit_i_2),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(p_5_out));
+ FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(p_5_out),
+ .Q(p_25_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000000004))
+ \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I1(pselect_hit_i_0),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
+ .Q(p_18_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000000020))
+ \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
+ (.I0(pselect_hit_i_0),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .O(p_16_out));
+ FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(p_16_out),
+ .Q(p_17_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0001000000000000))
+ \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I5(pselect_hit_i_0),
+ .O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ),
+ .Q(p_16_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000000080))
+ \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I2(pselect_hit_i_0),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .O(\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ),
+ .Q(p_15_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000001000))
+ \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(pselect_hit_i_0),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .O(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ),
+ .Q(p_14_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000010000000))
+ \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(pselect_hit_i_0),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ),
+ .Q(p_13_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000010000000))
+ \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(pselect_hit_i_0),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .O(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ),
+ .Q(p_12_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0008000000000000))
+ \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I5(pselect_hit_i_0),
+ .O(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ),
+ .Q(p_11_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000040000))
+ \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ),
+ .Q(p_10_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000004000))
+ \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I1(pselect_hit_i_0),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ),
+ .Q(p_9_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0100000000000000))
+ \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I3(pselect_hit_i_0),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ),
+ .Q(p_8_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000040000000))
+ \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ),
+ .Q(p_7_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000004000))
+ \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ),
+ .Q(p_6_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000040000000))
+ \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ),
+ .Q(p_5_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0008000000000000))
+ \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I1(pselect_hit_i_0),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ),
+ .Q(p_4_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h4000000000000000))
+ \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .O(\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[32].ce_out_i_reg[32]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ),
+ .Q(p_3_in),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000000400))
+ \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I1(pselect_hit_i_0),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ));
+ FDRE \GEN_BKEND_CE_REGISTERS[33].ce_out_i_reg[33]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ),
+ .Q(p_2_in),
+ .R(cs_ce_clr));
+ LUT3 #(
+ .INIT(8'hFB))
+ \GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_1
+ (.I0(is_write_reg),
+ .I1(s_axi_aresetn),
+ .I2(is_read_reg),
+ .O(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000200000))
+ \GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_2
+ (.I0(pselect_hit_i_0),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .O(p_17_out));
+ (* SOFT_HLUTNM = "soft_lutpair48" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_3
+ (.I0(Q),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .O(pselect_hit_i_0));
+ FDRE \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg[34]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(p_17_out),
+ .Q(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
+ .R(cs_ce_clr));
+ (* SOFT_HLUTNM = "soft_lutpair41" *)
+ LUT5 #(
+ .INIT(32'h08000000))
+ \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
+ (.I0(pselect_hit_i_2),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .O(p_8_out));
+ FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(p_8_out),
+ .Q(p_28_in),
+ .R(cs_ce_clr));
+ LUT5 #(
+ .INIT(32'h00020000))
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
+ (.I0(pselect_hit_i_2),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .O(p_7_out));
+ FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(p_7_out),
+ .Q(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .R(cs_ce_clr));
+ (* SOFT_HLUTNM = "soft_lutpair43" *)
+ LUT4 #(
+ .INIT(16'hFB08))
+ \GPO_GEN.gpo_i[31]_i_2
+ (.I0(s_axi_wdata[0]),
+ .I1(p_9_in),
+ .I2(Bus_RNW_reg_reg_0),
+ .I3(gpo),
+ .O(s_axi_wdata_0_sn_1));
+ (* SOFT_HLUTNM = "soft_lutpair48" *)
+ LUT4 #(
+ .INIT(16'h0010))
+ \MEM_DECODE_GEN[0].cs_out_i[0]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [7]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I2(Q),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .O(pselect_hit_i_2));
+ FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(pselect_hit_i_2),
+ .Q(AXI_Bus2IP_CS[2]),
+ .R(cs_ce_clr));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \MEM_DECODE_GEN[1].cs_out_i[1]_i_1
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [2]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I2(\MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0 ),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .I5(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [7]),
+ .O(\MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ));
+ LUT2 #(
+ .INIT(4'hB))
+ \MEM_DECODE_GEN[1].cs_out_i[1]_i_2
+ (.I0(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .O(\MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0 ));
+ FDRE \MEM_DECODE_GEN[1].cs_out_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ),
+ .Q(AXI_Bus2IP_CS[1]),
+ .R(cs_ce_clr));
+ FDRE \MEM_DECODE_GEN[2].cs_out_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Q),
+ .D(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [8]),
+ .Q(AXI_Bus2IP_CS[0]),
+ .R(cs_ce_clr));
+ (* SOFT_HLUTNM = "soft_lutpair46" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \RD_FIFO_CNTRL.Rc_fifo_rd_i_1
+ (.I0(Bus_RNW_reg_reg_0),
+ .I1(p_15_in),
+ .O(Bus2IIC_RdCE));
+ (* SOFT_HLUTNM = "soft_lutpair47" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1
+ (.I0(p_10_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[8]));
+ (* SOFT_HLUTNM = "soft_lutpair44" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \adr_i[0]_i_1
+ (.I0(p_14_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[9]));
+ (* SOFT_HLUTNM = "soft_lutpair43" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \cr_i[0]_i_1
+ (.I0(p_18_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[11]));
+ LUT6 #(
+ .INIT(64'hB888B888B8BBB888))
+ \cr_i[2]_i_1
+ (.I0(s_axi_wdata[4]),
+ .I1(Bus2IIC_WrCE[11]),
+ .I2(\cr_i_reg[2] ),
+ .I3(\cr_i_reg[2]_0 [1]),
+ .I4(firstDynStartSeen),
+ .I5(\cr_i_reg[2]_1 ),
+ .O(\s_axi_wdata[5] [1]));
+ LUT6 #(
+ .INIT(64'h08080808FBFBFB08))
+ \cr_i[4]_i_1
+ (.I0(s_axi_wdata[3]),
+ .I1(p_18_in),
+ .I2(Bus_RNW_reg_reg_0),
+ .I3(\cr_i_reg[2]_0 [0]),
+ .I4(cr_txModeSelect_set),
+ .I5(cr_txModeSelect_clr),
+ .O(\s_axi_wdata[5] [0]));
+ (* SOFT_HLUTNM = "soft_lutpair40" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \ip_irpt_enable_reg[7]_i_1
+ (.I0(p_25_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(E));
+ (* SOFT_HLUTNM = "soft_lutpair44" *)
+ LUT4 #(
+ .INIT(16'hFB08))
+ ipif_glbl_irpt_enable_reg_i_1
+ (.I0(s_axi_wdata[5]),
+ .I1(p_28_in),
+ .I2(Bus_RNW_reg_reg_0),
+ .I3(ipif_glbl_irpt_enable_reg),
+ .O(\s_axi_wdata[31] ));
+ (* SOFT_HLUTNM = "soft_lutpair38" *)
+ LUT4 #(
+ .INIT(16'h0F0E))
+ irpt_wrack_d1_i_1
+ (.I0(p_25_in),
+ .I1(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .I2(Bus_RNW_reg_reg_0),
+ .I3(p_28_in),
+ .O(irpt_wrack));
+ LUT2 #(
+ .INIT(4'h2))
+ reset_trig_i_1
+ (.I0(sw_rst_cond),
+ .I1(sw_rst_cond_d1),
+ .O(reset_trig0));
+ LUT4 #(
+ .INIT(16'h4F44))
+ s_axi_arready_INST_0
+ (.I0(s_axi_wready_INST_0_i_1_n_0),
+ .I1(s_axi_arready),
+ .I2(AXI_IP2Bus_RdAck1),
+ .I3(AXI_IP2Bus_RdAck2),
+ .O(is_read_reg));
+ LUT3 #(
+ .INIT(8'hB8))
+ \s_axi_bresp_i[1]_i_1
+ (.I0(AXI_IP2Bus_Error),
+ .I1(\s_axi_bresp_i_reg[1] ),
+ .I2(s_axi_bresp),
+ .O(\FSM_onehot_state_reg[2] ));
+ LUT5 #(
+ .INIT(32'hFFFF1011))
+ \s_axi_rdata_i[0]_i_1
+ (.I0(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[0] ),
+ .I2(\s_axi_rdata_i_reg[0]_0 ),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I4(\s_axi_rdata_i[0]_i_4_n_0 ),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair40" *)
+ LUT5 #(
+ .INIT(32'h8C808080))
+ \s_axi_rdata_i[0]_i_4
+ (.I0(\s_axi_rdata_i_reg[0]_1 ),
+ .I1(Bus_RNW_reg_reg_0),
+ .I2(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [0]),
+ .I4(p_25_in),
+ .O(\s_axi_rdata_i[0]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFF1011))
+ \s_axi_rdata_i[1]_i_1
+ (.I0(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[1] ),
+ .I2(\s_axi_rdata_i_reg[1]_0 ),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I4(\s_axi_rdata_i[1]_i_4_n_0 ),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair39" *)
+ LUT5 #(
+ .INIT(32'h8C808080))
+ \s_axi_rdata_i[1]_i_4
+ (.I0(p_1_in17_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .I2(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [1]),
+ .I4(p_25_in),
+ .O(\s_axi_rdata_i[1]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFF4444444F444))
+ \s_axi_rdata_i[2]_i_1
+ (.I0(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[2] ),
+ .I2(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [2]),
+ .I4(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I5(p_1_in14_in),
+ .O(D[2]));
+ (* SOFT_HLUTNM = "soft_lutpair38" *)
+ LUT5 #(
+ .INIT(32'h00000080))
+ \s_axi_rdata_i[31]_i_1
+ (.I0(p_28_in),
+ .I1(ipif_glbl_irpt_enable_reg),
+ .I2(Bus_RNW_reg_reg_0),
+ .I3(p_25_in),
+ .I4(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .O(D[8]));
+ LUT6 #(
+ .INIT(64'hFFFFF4444444F444))
+ \s_axi_rdata_i[3]_i_1
+ (.I0(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[3] ),
+ .I2(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [3]),
+ .I4(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I5(p_1_in11_in),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hF808F808F808FFFF))
+ \s_axi_rdata_i[4]_i_1
+ (.I0(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I1(\s_axi_rdata_i_reg[7] [4]),
+ .I2(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I3(p_1_in8_in),
+ .I4(\s_axi_rdata_i_reg[4] ),
+ .I5(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .O(D[4]));
+ LUT6 #(
+ .INIT(64'hFFFFF1111111F111))
+ \s_axi_rdata_i[5]_i_1
+ (.I0(\s_axi_rdata_i_reg[5] ),
+ .I1(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I2(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [5]),
+ .I4(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I5(p_1_in5_in),
+ .O(D[5]));
+ LUT6 #(
+ .INIT(64'hFFFFF1111111F111))
+ \s_axi_rdata_i[6]_i_1
+ (.I0(\s_axi_rdata_i_reg[6] ),
+ .I1(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I2(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [6]),
+ .I4(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I5(p_1_in2_in),
+ .O(D[6]));
+ LUT6 #(
+ .INIT(64'hFFFFF1111111F111))
+ \s_axi_rdata_i[7]_i_1
+ (.I0(\s_axi_rdata_i_reg[7]_0 ),
+ .I1(\s_axi_rdata_i[7]_i_3_n_0 ),
+ .I2(\s_axi_rdata_i[7]_i_4_n_0 ),
+ .I3(\s_axi_rdata_i_reg[7] [7]),
+ .I4(\s_axi_rdata_i[7]_i_5_n_0 ),
+ .I5(p_1_in),
+ .O(D[7]));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \s_axi_rdata_i[7]_i_3
+ (.I0(\s_axi_rdata_i[9]_i_5_n_0 ),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [7]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [0]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [1]),
+ .O(\s_axi_rdata_i[7]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair53" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \s_axi_rdata_i[7]_i_4
+ (.I0(Bus_RNW_reg_reg_0),
+ .I1(p_25_in),
+ .O(\s_axi_rdata_i[7]_i_4_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair39" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \s_axi_rdata_i[7]_i_5
+ (.I0(Bus_RNW_reg_reg_0),
+ .I1(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ),
+ .O(\s_axi_rdata_i[7]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \s_axi_rdata_i[9]_i_10
+ (.I0(p_8_in),
+ .I1(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
+ .I2(p_5_in),
+ .I3(p_18_in),
+ .I4(p_16_in),
+ .I5(p_17_in),
+ .O(\s_axi_rdata_i[9]_i_10_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFEABFF))
+ \s_axi_rdata_i[9]_i_4
+ (.I0(\s_axi_rdata_i[9]_i_5_n_0 ),
+ .I1(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [3]),
+ .I2(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [4]),
+ .I3(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [5]),
+ .I4(\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 [6]),
+ .I5(\s_axi_rdata_i_reg[8] ),
+ .O(\bus2ip_addr_i_reg[3] ));
+ LUT5 #(
+ .INIT(32'h0100FFFF))
+ \s_axi_rdata_i[9]_i_5
+ (.I0(\s_axi_rdata_i[9]_i_7_n_0 ),
+ .I1(\s_axi_rdata_i[9]_i_8_n_0 ),
+ .I2(\s_axi_rdata_i[9]_i_9_n_0 ),
+ .I3(\s_axi_rdata_i[9]_i_10_n_0 ),
+ .I4(Bus_RNW_reg_reg_0),
+ .O(\s_axi_rdata_i[9]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair47" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \s_axi_rdata_i[9]_i_7
+ (.I0(p_11_in),
+ .I1(p_9_in),
+ .I2(p_10_in),
+ .I3(p_3_in),
+ .O(\s_axi_rdata_i[9]_i_7_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair45" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \s_axi_rdata_i[9]_i_8
+ (.I0(p_14_in),
+ .I1(p_6_in),
+ .I2(p_13_in),
+ .I3(p_2_in),
+ .O(\s_axi_rdata_i[9]_i_8_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair46" *)
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \s_axi_rdata_i[9]_i_9
+ (.I0(p_15_in),
+ .I1(p_4_in),
+ .I2(p_12_in),
+ .I3(p_7_in),
+ .O(\s_axi_rdata_i[9]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'h4444404444444444))
+ \s_axi_rresp_i[1]_i_1
+ (.I0(Bus_RNW_reg_reg_0),
+ .I1(AXI_Bus2IP_CS[1]),
+ .I2(s_axi_wdata[0]),
+ .I3(s_axi_wdata[1]),
+ .I4(s_axi_wdata[2]),
+ .I5(s_axi_wdata[3]),
+ .O(AXI_IP2Bus_Error));
+ LUT4 #(
+ .INIT(16'h4F44))
+ s_axi_wready_INST_0
+ (.I0(s_axi_wready_INST_0_i_1_n_0),
+ .I1(s_axi_awready),
+ .I2(AXI_IP2Bus_WrAck1),
+ .I3(AXI_IP2Bus_WrAck2),
+ .O(is_write_reg));
+ LUT4 #(
+ .INIT(16'hFFEF))
+ s_axi_wready_INST_0_i_1
+ (.I0(s_axi_awready_0[1]),
+ .I1(s_axi_awready_0[0]),
+ .I2(s_axi_awready_0[3]),
+ .I3(s_axi_awready_0[2]),
+ .O(s_axi_wready_INST_0_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000040000000000))
+ sw_rst_cond_d1_i_1
+ (.I0(Bus_RNW_reg_reg_0),
+ .I1(AXI_Bus2IP_CS[1]),
+ .I2(s_axi_wdata[0]),
+ .I3(s_axi_wdata[1]),
+ .I4(s_axi_wdata[2]),
+ .I5(s_axi_wdata[3]),
+ .O(sw_rst_cond));
+ (* SOFT_HLUTNM = "soft_lutpair51" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_tbuf_i[9]_i_1
+ (.I0(p_4_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[3]));
+ (* SOFT_HLUTNM = "soft_lutpair52" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_thddat_i[9]_i_1
+ (.I0(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[0]));
+ (* SOFT_HLUTNM = "soft_lutpair45" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_thdsta_i[9]_i_1
+ (.I0(p_6_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[5]));
+ (* SOFT_HLUTNM = "soft_lutpair52" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_thigh_i[9]_i_1
+ (.I0(p_3_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[2]));
+ (* SOFT_HLUTNM = "soft_lutpair50" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_tlow_i[9]_i_1
+ (.I0(p_2_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[1]));
+ (* SOFT_HLUTNM = "soft_lutpair51" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_tsudat_i[9]_i_1
+ (.I0(p_5_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[4]));
+ (* SOFT_HLUTNM = "soft_lutpair49" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_tsusta_i[9]_i_1
+ (.I0(p_8_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[7]));
+ (* SOFT_HLUTNM = "soft_lutpair50" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \timing_param_tsusto_i[9]_i_1
+ (.I0(p_7_in),
+ .I1(Bus_RNW_reg_reg_0),
+ .O(Bus2IIC_WrCE[6]));
+endmodule
+
+(* C_DEFAULT_VALUE = "8'b00000000" *) (* C_FAMILY = "zynq" *) (* C_GPO_WIDTH = "1" *)
+(* C_IIC_FREQ = "100000" *) (* C_SCL_INERTIAL_DELAY = "0" *) (* C_SDA_INERTIAL_DELAY = "0" *)
+(* C_SDA_LEVEL = "1" *) (* C_SMBUS_PMBUS_HOST = "0" *) (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
+(* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_TEN_BIT_ADR = "0" *)
+(* downgradeipidentifiedwarnings = "yes" *)
+module TopLevel_axi_iic_0_0_axi_iic
+ (s_axi_aclk,
+ s_axi_aresetn,
+ iic2intc_irpt,
+ s_axi_awaddr,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_araddr,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rvalid,
+ s_axi_rready,
+ sda_i,
+ sda_o,
+ sda_t,
+ scl_i,
+ scl_o,
+ scl_t,
+ gpo);
+ input s_axi_aclk;
+ input s_axi_aresetn;
+ output iic2intc_irpt;
+ input [8:0]s_axi_awaddr;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [31:0]s_axi_wdata;
+ input [3:0]s_axi_wstrb;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [1:0]s_axi_bresp;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [8:0]s_axi_araddr;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [31:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ input sda_i;
+ output sda_o;
+ output sda_t;
+ input scl_i;
+ output scl_o;
+ output scl_t;
+ output [0:0]gpo;
+
+ wire \<const0> ;
+ wire [0:0]gpo;
+ wire iic2intc_irpt;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arready;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awready;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [1:1]\^s_axi_bresp ;
+ wire s_axi_bvalid;
+ wire [31:0]\^s_axi_rdata ;
+ wire s_axi_rready;
+ wire [1:1]\^s_axi_rresp ;
+ wire s_axi_rvalid;
+ wire [31:0]s_axi_wdata;
+ wire s_axi_wvalid;
+ wire scl_i;
+ wire scl_t;
+ wire sda_i;
+ wire sda_t;
+
+ assign s_axi_bresp[1] = \^s_axi_bresp [1];
+ assign s_axi_bresp[0] = \<const0> ;
+ assign s_axi_rdata[31] = \^s_axi_rdata [31];
+ assign s_axi_rdata[30] = \<const0> ;
+ assign s_axi_rdata[29] = \<const0> ;
+ assign s_axi_rdata[28] = \<const0> ;
+ assign s_axi_rdata[27] = \<const0> ;
+ assign s_axi_rdata[26] = \<const0> ;
+ assign s_axi_rdata[25] = \<const0> ;
+ assign s_axi_rdata[24] = \<const0> ;
+ assign s_axi_rdata[23] = \<const0> ;
+ assign s_axi_rdata[22] = \<const0> ;
+ assign s_axi_rdata[21] = \<const0> ;
+ assign s_axi_rdata[20] = \<const0> ;
+ assign s_axi_rdata[19] = \<const0> ;
+ assign s_axi_rdata[18] = \<const0> ;
+ assign s_axi_rdata[17] = \<const0> ;
+ assign s_axi_rdata[16] = \<const0> ;
+ assign s_axi_rdata[15] = \<const0> ;
+ assign s_axi_rdata[14] = \<const0> ;
+ assign s_axi_rdata[13] = \<const0> ;
+ assign s_axi_rdata[12] = \<const0> ;
+ assign s_axi_rdata[11] = \<const0> ;
+ assign s_axi_rdata[10] = \<const0> ;
+ assign s_axi_rdata[9:0] = \^s_axi_rdata [9:0];
+ assign s_axi_rresp[1] = \^s_axi_rresp [1];
+ assign s_axi_rresp[0] = \<const0> ;
+ assign s_axi_wready = s_axi_awready;
+ assign scl_o = \<const0> ;
+ assign sda_o = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ TopLevel_axi_iic_0_0_iic X_IIC
+ (.gpo(gpo),
+ .iic2intc_irpt(iic2intc_irpt),
+ .is_read_reg(s_axi_arready),
+ .is_write_reg(s_axi_awready),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(\^s_axi_bresp ),
+ .s_axi_bvalid_i_reg(s_axi_bvalid),
+ .s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [9:0]}),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(\^s_axi_rresp ),
+ .s_axi_rvalid_i_reg(s_axi_rvalid),
+ .s_axi_wdata({s_axi_wdata[31],s_axi_wdata[9:0]}),
+ .s_axi_wvalid(s_axi_wvalid),
+ .scl_i(scl_i),
+ .scl_t(scl_t),
+ .sda_i(sda_i),
+ .sda_t(sda_t));
+endmodule
+
+module TopLevel_axi_iic_0_0_axi_ipif_ssp1
+ (s_axi_rresp,
+ Bus2IIC_Reset,
+ Q,
+ s_axi_rvalid_i_reg,
+ s_axi_bvalid_i_reg,
+ s_axi_bresp,
+ is_write_reg,
+ is_read_reg,
+ ctrlFifoDin,
+ \s_axi_wdata[5] ,
+ Bus2IIC_WrCE,
+ \bus2ip_addr_i_reg[3] ,
+ Bus2IIC_RdCE,
+ iic2intc_irpt,
+ s_axi_wdata_0_sp_1,
+ s_axi_rdata,
+ s_axi_aclk,
+ s_axi_arvalid,
+ Rc_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_7 ,
+ \s_axi_rdata_i_reg[7]_i_7_0 ,
+ Tx_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_6 ,
+ \s_axi_rdata_i_reg[7]_i_6_0 ,
+ \s_axi_rdata_i[7]_i_8 ,
+ \s_axi_rdata_i[7]_i_8_0 ,
+ \s_axi_rdata_i[0]_i_2 ,
+ s_axi_aresetn,
+ s_axi_wvalid,
+ s_axi_awvalid,
+ IIC2Bus_IntrEvent,
+ s_axi_wdata,
+ Tx_fifo_rst,
+ \cr_i_reg[2] ,
+ firstDynStartSeen,
+ \cr_i_reg[2]_0 ,
+ Rc_addr,
+ \s_axi_rdata_i_reg[7]_i_6_1 ,
+ \s_axi_rdata_i_reg[1] ,
+ \s_axi_rdata_i_reg[4]_i_2 ,
+ \s_axi_rdata_i_reg[5]_i_2 ,
+ \s_axi_rdata_i_reg[6]_i_2 ,
+ \s_axi_rdata_i_reg[7]_i_2 ,
+ cr_txModeSelect_set,
+ cr_txModeSelect_clr,
+ s_axi_rready,
+ s_axi_bready,
+ \s_axi_rdata_i_reg[7]_i_6_2 ,
+ \s_axi_rdata_i_reg[3] ,
+ Tx_addr,
+ \s_axi_rdata_i[3]_i_2 ,
+ \s_axi_rdata_i[3]_i_2_0 ,
+ \s_axi_rdata_i_reg[2] ,
+ \s_axi_rdata_i[2]_i_2 ,
+ \s_axi_rdata_i[1]_i_2 ,
+ \s_axi_rdata_i[0]_i_2_0 ,
+ s_axi_araddr,
+ s_axi_awaddr,
+ gpo,
+ D);
+ output [0:0]s_axi_rresp;
+ output Bus2IIC_Reset;
+ output [4:0]Q;
+ output s_axi_rvalid_i_reg;
+ output s_axi_bvalid_i_reg;
+ output [0:0]s_axi_bresp;
+ output is_write_reg;
+ output is_read_reg;
+ output [0:1]ctrlFifoDin;
+ output [1:0]\s_axi_wdata[5] ;
+ output [11:0]Bus2IIC_WrCE;
+ output \bus2ip_addr_i_reg[3] ;
+ output [0:0]Bus2IIC_RdCE;
+ output iic2intc_irpt;
+ output s_axi_wdata_0_sp_1;
+ output [10:0]s_axi_rdata;
+ input s_axi_aclk;
+ input s_axi_arvalid;
+ input [0:7]Rc_fifo_data;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7 ;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ input [5:0]Tx_fifo_data;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6 ;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ input [5:0]\s_axi_rdata_i[7]_i_8 ;
+ input [4:0]\s_axi_rdata_i[7]_i_8_0 ;
+ input [0:0]\s_axi_rdata_i[0]_i_2 ;
+ input s_axi_aresetn;
+ input s_axi_wvalid;
+ input s_axi_awvalid;
+ input [0:7]IIC2Bus_IntrEvent;
+ input [10:0]s_axi_wdata;
+ input Tx_fifo_rst;
+ input \cr_i_reg[2] ;
+ input firstDynStartSeen;
+ input \cr_i_reg[2]_0 ;
+ input [1:0]Rc_addr;
+ input [4:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ input \s_axi_rdata_i_reg[1] ;
+ input \s_axi_rdata_i_reg[4]_i_2 ;
+ input \s_axi_rdata_i_reg[5]_i_2 ;
+ input \s_axi_rdata_i_reg[6]_i_2 ;
+ input \s_axi_rdata_i_reg[7]_i_2 ;
+ input cr_txModeSelect_set;
+ input cr_txModeSelect_clr;
+ input s_axi_rready;
+ input s_axi_bready;
+ input [3:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ input \s_axi_rdata_i_reg[3] ;
+ input [0:3]Tx_addr;
+ input [3:0]\s_axi_rdata_i[3]_i_2 ;
+ input \s_axi_rdata_i[3]_i_2_0 ;
+ input \s_axi_rdata_i_reg[2] ;
+ input \s_axi_rdata_i[2]_i_2 ;
+ input \s_axi_rdata_i[1]_i_2 ;
+ input \s_axi_rdata_i[0]_i_2_0 ;
+ input [8:0]s_axi_araddr;
+ input [8:0]s_axi_awaddr;
+ input [0:0]gpo;
+ input [1:0]D;
+
+ wire AXI_Bus2IP_Reset;
+ wire [10:10]AXI_Bus2IP_WrCE;
+ wire AXI_IP2Bus_RdAck1;
+ wire AXI_IP2Bus_RdAck2;
+ wire AXI_IP2Bus_RdAck20;
+ wire AXI_IP2Bus_WrAck1;
+ wire AXI_IP2Bus_WrAck2;
+ wire AXI_IP2Bus_WrAck20;
+ wire AXI_LITE_IPIF_I_n_33;
+ wire [0:0]Bus2IIC_RdCE;
+ wire Bus2IIC_Reset;
+ wire [11:0]Bus2IIC_WrCE;
+ wire [1:0]D;
+ wire [0:7]IIC2Bus_IntrEvent;
+ wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
+ wire \I_SLAVE_ATTACHMENT/I_DECODER/p_27_in ;
+ wire [4:0]Q;
+ wire [1:0]Rc_addr;
+ wire [0:7]Rc_fifo_data;
+ wire [0:3]Tx_addr;
+ wire [5:0]Tx_fifo_data;
+ wire Tx_fifo_rst;
+ wire X_INTERRUPT_CONTROL_n_0;
+ wire X_INTERRUPT_CONTROL_n_17;
+ wire \bus2ip_addr_i_reg[3] ;
+ wire \cr_i_reg[2] ;
+ wire \cr_i_reg[2]_0 ;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire [0:1]ctrlFifoDin;
+ wire firstDynStartSeen;
+ wire [0:0]gpo;
+ wire iic2intc_irpt;
+ wire ipif_glbl_irpt_enable_reg;
+ wire irpt_wrack;
+ wire is_read_reg;
+ wire is_write_reg;
+ wire p_0_in;
+ wire p_0_in10_in;
+ wire p_0_in13_in;
+ wire p_0_in16_in;
+ wire p_0_in1_in;
+ wire p_0_in4_in;
+ wire p_0_in7_in;
+ wire p_1_in;
+ wire p_1_in11_in;
+ wire p_1_in14_in;
+ wire p_1_in17_in;
+ wire p_1_in2_in;
+ wire p_1_in5_in;
+ wire p_1_in8_in;
+ wire reset_trig0;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [0:0]s_axi_bresp;
+ wire s_axi_bvalid_i_reg;
+ wire [10:0]s_axi_rdata;
+ wire [0:0]\s_axi_rdata_i[0]_i_2 ;
+ wire \s_axi_rdata_i[0]_i_2_0 ;
+ wire \s_axi_rdata_i[1]_i_2 ;
+ wire \s_axi_rdata_i[2]_i_2 ;
+ wire [3:0]\s_axi_rdata_i[3]_i_2 ;
+ wire \s_axi_rdata_i[3]_i_2_0 ;
+ wire [5:0]\s_axi_rdata_i[7]_i_8 ;
+ wire [4:0]\s_axi_rdata_i[7]_i_8_0 ;
+ wire \s_axi_rdata_i_reg[1] ;
+ wire \s_axi_rdata_i_reg[2] ;
+ wire \s_axi_rdata_i_reg[3] ;
+ wire \s_axi_rdata_i_reg[4]_i_2 ;
+ wire \s_axi_rdata_i_reg[5]_i_2 ;
+ wire \s_axi_rdata_i_reg[6]_i_2 ;
+ wire \s_axi_rdata_i_reg[7]_i_2 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ wire [4:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ wire [3:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ wire s_axi_rready;
+ wire [0:0]s_axi_rresp;
+ wire s_axi_rvalid_i_reg;
+ wire [10:0]s_axi_wdata;
+ wire [1:0]\s_axi_wdata[5] ;
+ wire s_axi_wdata_0_sn_1;
+ wire s_axi_wvalid;
+ wire sw_rst_cond;
+ wire sw_rst_cond_d1;
+
+ assign s_axi_wdata_0_sp_1 = s_axi_wdata_0_sn_1;
+ FDRE AXI_IP2Bus_RdAck1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AXI_IP2Bus_RdAck2),
+ .Q(AXI_IP2Bus_RdAck1),
+ .R(1'b0));
+ FDRE AXI_IP2Bus_RdAck2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AXI_IP2Bus_RdAck20),
+ .Q(AXI_IP2Bus_RdAck2),
+ .R(1'b0));
+ FDRE AXI_IP2Bus_WrAck1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AXI_IP2Bus_WrAck2),
+ .Q(AXI_IP2Bus_WrAck1),
+ .R(1'b0));
+ FDRE AXI_IP2Bus_WrAck2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AXI_IP2Bus_WrAck20),
+ .Q(AXI_IP2Bus_WrAck2),
+ .R(1'b0));
+ TopLevel_axi_iic_0_0_axi_lite_ipif AXI_LITE_IPIF_I
+ (.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
+ .AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
+ .AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
+ .AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
+ .AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
+ .AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
+ .AXI_IP2Bus_WrAck20(AXI_IP2Bus_WrAck20),
+ .Bus2IIC_RdCE(Bus2IIC_RdCE),
+ .Bus2IIC_WrCE(Bus2IIC_WrCE),
+ .Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+ .D(D),
+ .E(AXI_Bus2IP_WrCE),
+ .Q(Q),
+ .Rc_addr(Rc_addr),
+ .Rc_fifo_data(Rc_fifo_data),
+ .Tx_addr(Tx_addr),
+ .Tx_fifo_data(Tx_fifo_data),
+ .\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3] ),
+ .\cr_i_reg[2] (\cr_i_reg[2] ),
+ .\cr_i_reg[2]_0 (\cr_i_reg[2]_0 ),
+ .cr_txModeSelect_clr(cr_txModeSelect_clr),
+ .cr_txModeSelect_set(cr_txModeSelect_set),
+ .firstDynStartSeen(firstDynStartSeen),
+ .gpo(gpo),
+ .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+ .irpt_wrack(irpt_wrack),
+ .is_read_reg(is_read_reg),
+ .is_write_reg(is_write_reg),
+ .p_1_in(p_1_in),
+ .p_1_in11_in(p_1_in11_in),
+ .p_1_in14_in(p_1_in14_in),
+ .p_1_in17_in(p_1_in17_in),
+ .p_1_in2_in(p_1_in2_in),
+ .p_1_in5_in(p_1_in5_in),
+ .p_1_in8_in(p_1_in8_in),
+ .p_27_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_27_in ),
+ .reset_trig0(reset_trig0),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_bvalid_i_reg(s_axi_bvalid_i_reg),
+ .s_axi_rdata(s_axi_rdata),
+ .\s_axi_rdata_i[0]_i_2 (\s_axi_rdata_i[0]_i_2 ),
+ .\s_axi_rdata_i[0]_i_2_0 (\s_axi_rdata_i[0]_i_2_0 ),
+ .\s_axi_rdata_i[1]_i_2 (\s_axi_rdata_i[1]_i_2 ),
+ .\s_axi_rdata_i[2]_i_2 (\s_axi_rdata_i[2]_i_2 ),
+ .\s_axi_rdata_i[3]_i_2 (\s_axi_rdata_i[3]_i_2 ),
+ .\s_axi_rdata_i[3]_i_2_0 (\s_axi_rdata_i[3]_i_2_0 ),
+ .\s_axi_rdata_i[7]_i_8 (\s_axi_rdata_i[7]_i_8 ),
+ .\s_axi_rdata_i[7]_i_8_0 (\s_axi_rdata_i[7]_i_8_0 ),
+ .\s_axi_rdata_i_reg[0] (X_INTERRUPT_CONTROL_n_0),
+ .\s_axi_rdata_i_reg[1] (\s_axi_rdata_i_reg[1] ),
+ .\s_axi_rdata_i_reg[2] (\s_axi_rdata_i_reg[2] ),
+ .\s_axi_rdata_i_reg[3] (\s_axi_rdata_i_reg[3] ),
+ .\s_axi_rdata_i_reg[4]_i_2 (\s_axi_rdata_i_reg[4]_i_2 ),
+ .\s_axi_rdata_i_reg[5]_i_2 (\s_axi_rdata_i_reg[5]_i_2 ),
+ .\s_axi_rdata_i_reg[6]_i_2 (\s_axi_rdata_i_reg[6]_i_2 ),
+ .\s_axi_rdata_i_reg[7] ({p_0_in16_in,p_0_in13_in,p_0_in10_in,p_0_in7_in,p_0_in4_in,p_0_in1_in,p_0_in,X_INTERRUPT_CONTROL_n_17}),
+ .\s_axi_rdata_i_reg[7]_i_2 (\s_axi_rdata_i_reg[7]_i_2 ),
+ .\s_axi_rdata_i_reg[7]_i_6 (\s_axi_rdata_i_reg[7]_i_6 ),
+ .\s_axi_rdata_i_reg[7]_i_6_0 (\s_axi_rdata_i_reg[7]_i_6_0 ),
+ .\s_axi_rdata_i_reg[7]_i_6_1 (\s_axi_rdata_i_reg[7]_i_6_1 ),
+ .\s_axi_rdata_i_reg[7]_i_6_2 (\s_axi_rdata_i_reg[7]_i_6_2 ),
+ .\s_axi_rdata_i_reg[7]_i_7 (\s_axi_rdata_i_reg[7]_i_7 ),
+ .\s_axi_rdata_i_reg[7]_i_7_0 (\s_axi_rdata_i_reg[7]_i_7_0 ),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rvalid_i_reg(s_axi_rvalid_i_reg),
+ .s_axi_wdata({s_axi_wdata[10],s_axi_wdata[5],s_axi_wdata[3:0]}),
+ .\s_axi_wdata[31] (AXI_LITE_IPIF_I_n_33),
+ .\s_axi_wdata[5] (\s_axi_wdata[5] ),
+ .s_axi_wdata_0_sp_1(s_axi_wdata_0_sn_1),
+ .s_axi_wvalid(s_axi_wvalid),
+ .sw_rst_cond(sw_rst_cond),
+ .sw_rst_cond_d1(sw_rst_cond_d1));
+ TopLevel_axi_iic_0_0_interrupt_control X_INTERRUPT_CONTROL
+ (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+ .E(AXI_Bus2IP_WrCE),
+ .\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (X_INTERRUPT_CONTROL_n_0),
+ .IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
+ .Q({p_0_in16_in,p_0_in13_in,p_0_in10_in,p_0_in7_in,p_0_in4_in,p_0_in1_in,p_0_in,X_INTERRUPT_CONTROL_n_17}),
+ .SR(Bus2IIC_Reset),
+ .iic2intc_irpt(iic2intc_irpt),
+ .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+ .ipif_glbl_irpt_enable_reg_reg_0(AXI_LITE_IPIF_I_n_33),
+ .irpt_wrack(irpt_wrack),
+ .p_1_in(p_1_in),
+ .p_1_in11_in(p_1_in11_in),
+ .p_1_in14_in(p_1_in14_in),
+ .p_1_in17_in(p_1_in17_in),
+ .p_1_in2_in(p_1_in2_in),
+ .p_1_in5_in(p_1_in5_in),
+ .p_1_in8_in(p_1_in8_in),
+ .p_27_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_27_in ),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_wdata(s_axi_wdata[7:0]));
+ TopLevel_axi_iic_0_0_soft_reset X_SOFT_RESET
+ (.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
+ .SR(Bus2IIC_Reset),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .ctrlFifoDin(ctrlFifoDin),
+ .reset_trig0(reset_trig0),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_wdata(s_axi_wdata[9:8]),
+ .sw_rst_cond(sw_rst_cond),
+ .sw_rst_cond_d1(sw_rst_cond_d1));
+endmodule
+
+module TopLevel_axi_iic_0_0_axi_lite_ipif
+ (p_27_in,
+ s_axi_rresp,
+ Bus_RNW_reg,
+ s_axi_rvalid_i_reg,
+ s_axi_bvalid_i_reg,
+ s_axi_bresp,
+ Q,
+ is_write_reg,
+ is_read_reg,
+ irpt_wrack,
+ E,
+ reset_trig0,
+ sw_rst_cond,
+ \s_axi_wdata[5] ,
+ Bus2IIC_WrCE,
+ \bus2ip_addr_i_reg[3] ,
+ Bus2IIC_RdCE,
+ \s_axi_wdata[31] ,
+ s_axi_wdata_0_sp_1,
+ s_axi_rdata,
+ AXI_IP2Bus_WrAck20,
+ AXI_IP2Bus_RdAck20,
+ AXI_Bus2IP_Reset,
+ s_axi_aclk,
+ s_axi_arvalid,
+ Rc_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_7 ,
+ \s_axi_rdata_i_reg[7]_i_7_0 ,
+ Tx_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_6 ,
+ \s_axi_rdata_i_reg[7]_i_6_0 ,
+ \s_axi_rdata_i[7]_i_8 ,
+ \s_axi_rdata_i[7]_i_8_0 ,
+ \s_axi_rdata_i[0]_i_2 ,
+ s_axi_aresetn,
+ AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2,
+ s_axi_wvalid,
+ s_axi_awvalid,
+ AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2,
+ sw_rst_cond_d1,
+ s_axi_wdata,
+ \cr_i_reg[2] ,
+ firstDynStartSeen,
+ \cr_i_reg[2]_0 ,
+ Rc_addr,
+ \s_axi_rdata_i_reg[7]_i_6_1 ,
+ \s_axi_rdata_i_reg[1] ,
+ \s_axi_rdata_i_reg[7] ,
+ p_1_in8_in,
+ \s_axi_rdata_i_reg[4]_i_2 ,
+ p_1_in5_in,
+ \s_axi_rdata_i_reg[5]_i_2 ,
+ p_1_in2_in,
+ \s_axi_rdata_i_reg[6]_i_2 ,
+ p_1_in,
+ \s_axi_rdata_i_reg[7]_i_2 ,
+ cr_txModeSelect_set,
+ cr_txModeSelect_clr,
+ s_axi_rready,
+ s_axi_bready,
+ \s_axi_rdata_i_reg[0] ,
+ p_1_in17_in,
+ p_1_in14_in,
+ p_1_in11_in,
+ ipif_glbl_irpt_enable_reg,
+ \s_axi_rdata_i_reg[7]_i_6_2 ,
+ \s_axi_rdata_i_reg[3] ,
+ Tx_addr,
+ \s_axi_rdata_i[3]_i_2 ,
+ \s_axi_rdata_i[3]_i_2_0 ,
+ \s_axi_rdata_i_reg[2] ,
+ \s_axi_rdata_i[2]_i_2 ,
+ \s_axi_rdata_i[1]_i_2 ,
+ \s_axi_rdata_i[0]_i_2_0 ,
+ s_axi_araddr,
+ s_axi_awaddr,
+ gpo,
+ D);
+ output p_27_in;
+ output [0:0]s_axi_rresp;
+ output Bus_RNW_reg;
+ output s_axi_rvalid_i_reg;
+ output s_axi_bvalid_i_reg;
+ output [0:0]s_axi_bresp;
+ output [4:0]Q;
+ output is_write_reg;
+ output is_read_reg;
+ output irpt_wrack;
+ output [0:0]E;
+ output reset_trig0;
+ output sw_rst_cond;
+ output [1:0]\s_axi_wdata[5] ;
+ output [11:0]Bus2IIC_WrCE;
+ output \bus2ip_addr_i_reg[3] ;
+ output [0:0]Bus2IIC_RdCE;
+ output \s_axi_wdata[31] ;
+ output s_axi_wdata_0_sp_1;
+ output [10:0]s_axi_rdata;
+ output AXI_IP2Bus_WrAck20;
+ output AXI_IP2Bus_RdAck20;
+ input AXI_Bus2IP_Reset;
+ input s_axi_aclk;
+ input s_axi_arvalid;
+ input [0:7]Rc_fifo_data;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7 ;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ input [5:0]Tx_fifo_data;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6 ;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ input [5:0]\s_axi_rdata_i[7]_i_8 ;
+ input [4:0]\s_axi_rdata_i[7]_i_8_0 ;
+ input [0:0]\s_axi_rdata_i[0]_i_2 ;
+ input s_axi_aresetn;
+ input AXI_IP2Bus_RdAck1;
+ input AXI_IP2Bus_RdAck2;
+ input s_axi_wvalid;
+ input s_axi_awvalid;
+ input AXI_IP2Bus_WrAck1;
+ input AXI_IP2Bus_WrAck2;
+ input sw_rst_cond_d1;
+ input [5:0]s_axi_wdata;
+ input \cr_i_reg[2] ;
+ input firstDynStartSeen;
+ input \cr_i_reg[2]_0 ;
+ input [1:0]Rc_addr;
+ input [4:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ input \s_axi_rdata_i_reg[1] ;
+ input [7:0]\s_axi_rdata_i_reg[7] ;
+ input p_1_in8_in;
+ input \s_axi_rdata_i_reg[4]_i_2 ;
+ input p_1_in5_in;
+ input \s_axi_rdata_i_reg[5]_i_2 ;
+ input p_1_in2_in;
+ input \s_axi_rdata_i_reg[6]_i_2 ;
+ input p_1_in;
+ input \s_axi_rdata_i_reg[7]_i_2 ;
+ input cr_txModeSelect_set;
+ input cr_txModeSelect_clr;
+ input s_axi_rready;
+ input s_axi_bready;
+ input \s_axi_rdata_i_reg[0] ;
+ input p_1_in17_in;
+ input p_1_in14_in;
+ input p_1_in11_in;
+ input ipif_glbl_irpt_enable_reg;
+ input [3:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ input \s_axi_rdata_i_reg[3] ;
+ input [0:3]Tx_addr;
+ input [3:0]\s_axi_rdata_i[3]_i_2 ;
+ input \s_axi_rdata_i[3]_i_2_0 ;
+ input \s_axi_rdata_i_reg[2] ;
+ input \s_axi_rdata_i[2]_i_2 ;
+ input \s_axi_rdata_i[1]_i_2 ;
+ input \s_axi_rdata_i[0]_i_2_0 ;
+ input [8:0]s_axi_araddr;
+ input [8:0]s_axi_awaddr;
+ input [0:0]gpo;
+ input [1:0]D;
+
+ wire AXI_Bus2IP_Reset;
+ wire AXI_IP2Bus_RdAck1;
+ wire AXI_IP2Bus_RdAck2;
+ wire AXI_IP2Bus_RdAck20;
+ wire AXI_IP2Bus_WrAck1;
+ wire AXI_IP2Bus_WrAck2;
+ wire AXI_IP2Bus_WrAck20;
+ wire [0:0]Bus2IIC_RdCE;
+ wire [11:0]Bus2IIC_WrCE;
+ wire Bus_RNW_reg;
+ wire [1:0]D;
+ wire [0:0]E;
+ wire [4:0]Q;
+ wire [1:0]Rc_addr;
+ wire [0:7]Rc_fifo_data;
+ wire [0:3]Tx_addr;
+ wire [5:0]Tx_fifo_data;
+ wire \bus2ip_addr_i_reg[3] ;
+ wire \cr_i_reg[2] ;
+ wire \cr_i_reg[2]_0 ;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire firstDynStartSeen;
+ wire [0:0]gpo;
+ wire ipif_glbl_irpt_enable_reg;
+ wire irpt_wrack;
+ wire is_read_reg;
+ wire is_write_reg;
+ wire p_1_in;
+ wire p_1_in11_in;
+ wire p_1_in14_in;
+ wire p_1_in17_in;
+ wire p_1_in2_in;
+ wire p_1_in5_in;
+ wire p_1_in8_in;
+ wire p_27_in;
+ wire reset_trig0;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [0:0]s_axi_bresp;
+ wire s_axi_bvalid_i_reg;
+ wire [10:0]s_axi_rdata;
+ wire [0:0]\s_axi_rdata_i[0]_i_2 ;
+ wire \s_axi_rdata_i[0]_i_2_0 ;
+ wire \s_axi_rdata_i[1]_i_2 ;
+ wire \s_axi_rdata_i[2]_i_2 ;
+ wire [3:0]\s_axi_rdata_i[3]_i_2 ;
+ wire \s_axi_rdata_i[3]_i_2_0 ;
+ wire [5:0]\s_axi_rdata_i[7]_i_8 ;
+ wire [4:0]\s_axi_rdata_i[7]_i_8_0 ;
+ wire \s_axi_rdata_i_reg[0] ;
+ wire \s_axi_rdata_i_reg[1] ;
+ wire \s_axi_rdata_i_reg[2] ;
+ wire \s_axi_rdata_i_reg[3] ;
+ wire \s_axi_rdata_i_reg[4]_i_2 ;
+ wire \s_axi_rdata_i_reg[5]_i_2 ;
+ wire \s_axi_rdata_i_reg[6]_i_2 ;
+ wire [7:0]\s_axi_rdata_i_reg[7] ;
+ wire \s_axi_rdata_i_reg[7]_i_2 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ wire [4:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ wire [3:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ wire s_axi_rready;
+ wire [0:0]s_axi_rresp;
+ wire s_axi_rvalid_i_reg;
+ wire [5:0]s_axi_wdata;
+ wire \s_axi_wdata[31] ;
+ wire [1:0]\s_axi_wdata[5] ;
+ wire s_axi_wdata_0_sn_1;
+ wire s_axi_wvalid;
+ wire sw_rst_cond;
+ wire sw_rst_cond_d1;
+
+ assign s_axi_wdata_0_sp_1 = s_axi_wdata_0_sn_1;
+ TopLevel_axi_iic_0_0_slave_attachment I_SLAVE_ATTACHMENT
+ (.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
+ .AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
+ .AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
+ .AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
+ .AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
+ .AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
+ .AXI_IP2Bus_WrAck20(AXI_IP2Bus_WrAck20),
+ .Bus2IIC_RdCE(Bus2IIC_RdCE),
+ .Bus2IIC_WrCE(Bus2IIC_WrCE),
+ .Bus_RNW_reg_reg(Bus_RNW_reg),
+ .D(D),
+ .E(E),
+ .\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] (p_27_in),
+ .Q(Q),
+ .Rc_addr(Rc_addr),
+ .Rc_fifo_data(Rc_fifo_data),
+ .Tx_addr(Tx_addr),
+ .Tx_fifo_data(Tx_fifo_data),
+ .\bus2ip_addr_i_reg[3]_0 (\bus2ip_addr_i_reg[3] ),
+ .\cr_i_reg[2] (\cr_i_reg[2] ),
+ .\cr_i_reg[2]_0 (\cr_i_reg[2]_0 ),
+ .cr_txModeSelect_clr(cr_txModeSelect_clr),
+ .cr_txModeSelect_set(cr_txModeSelect_set),
+ .firstDynStartSeen(firstDynStartSeen),
+ .gpo(gpo),
+ .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+ .irpt_wrack(irpt_wrack),
+ .is_read_reg_0(is_read_reg),
+ .is_write_reg_0(is_write_reg),
+ .p_1_in(p_1_in),
+ .p_1_in11_in(p_1_in11_in),
+ .p_1_in14_in(p_1_in14_in),
+ .p_1_in17_in(p_1_in17_in),
+ .p_1_in2_in(p_1_in2_in),
+ .p_1_in5_in(p_1_in5_in),
+ .p_1_in8_in(p_1_in8_in),
+ .reset_trig0(reset_trig0),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_bvalid_i_reg_0(s_axi_bvalid_i_reg),
+ .s_axi_rdata(s_axi_rdata),
+ .\s_axi_rdata_i[0]_i_2_0 (\s_axi_rdata_i[0]_i_2 ),
+ .\s_axi_rdata_i[0]_i_2_1 (\s_axi_rdata_i[0]_i_2_0 ),
+ .\s_axi_rdata_i[1]_i_2_0 (\s_axi_rdata_i[1]_i_2 ),
+ .\s_axi_rdata_i[2]_i_2_0 (\s_axi_rdata_i[2]_i_2 ),
+ .\s_axi_rdata_i[3]_i_2_0 (\s_axi_rdata_i[3]_i_2 ),
+ .\s_axi_rdata_i[3]_i_2_1 (\s_axi_rdata_i[3]_i_2_0 ),
+ .\s_axi_rdata_i[7]_i_8_0 (\s_axi_rdata_i[7]_i_8 ),
+ .\s_axi_rdata_i[7]_i_8_1 (\s_axi_rdata_i[7]_i_8_0 ),
+ .\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i_reg[0] ),
+ .\s_axi_rdata_i_reg[1]_0 (\s_axi_rdata_i_reg[1] ),
+ .\s_axi_rdata_i_reg[2]_0 (\s_axi_rdata_i_reg[2] ),
+ .\s_axi_rdata_i_reg[3]_0 (\s_axi_rdata_i_reg[3] ),
+ .\s_axi_rdata_i_reg[4]_i_2_0 (\s_axi_rdata_i_reg[4]_i_2 ),
+ .\s_axi_rdata_i_reg[5]_i_2_0 (\s_axi_rdata_i_reg[5]_i_2 ),
+ .\s_axi_rdata_i_reg[6]_i_2_0 (\s_axi_rdata_i_reg[6]_i_2 ),
+ .\s_axi_rdata_i_reg[7]_0 (\s_axi_rdata_i_reg[7] ),
+ .\s_axi_rdata_i_reg[7]_i_2_0 (\s_axi_rdata_i_reg[7]_i_2 ),
+ .\s_axi_rdata_i_reg[7]_i_6_0 (\s_axi_rdata_i_reg[7]_i_6 ),
+ .\s_axi_rdata_i_reg[7]_i_6_1 (\s_axi_rdata_i_reg[7]_i_6_0 ),
+ .\s_axi_rdata_i_reg[7]_i_6_2 (\s_axi_rdata_i_reg[7]_i_6_1 ),
+ .\s_axi_rdata_i_reg[7]_i_6_3 (\s_axi_rdata_i_reg[7]_i_6_2 ),
+ .\s_axi_rdata_i_reg[7]_i_7_0 (\s_axi_rdata_i_reg[7]_i_7 ),
+ .\s_axi_rdata_i_reg[7]_i_7_1 (\s_axi_rdata_i_reg[7]_i_7_0 ),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
+ .s_axi_wdata(s_axi_wdata),
+ .\s_axi_wdata[31] (\s_axi_wdata[31] ),
+ .\s_axi_wdata[5] (\s_axi_wdata[5] ),
+ .s_axi_wdata_0_sp_1(s_axi_wdata_0_sn_1),
+ .s_axi_wvalid(s_axi_wvalid),
+ .sw_rst_cond(sw_rst_cond),
+ .sw_rst_cond_d1(sw_rst_cond_d1));
+endmodule
+
+module TopLevel_axi_iic_0_0_cdc_sync
+ (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ,
+ sda_rin_d1,
+ sda_i,
+ s_axi_aclk);
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ;
+ input sda_rin_d1;
+ input sda_i;
+ input s_axi_aclk;
+
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ;
+ wire s_axi_aclk;
+ wire s_level_out_d1_cdc_to;
+ wire s_level_out_d2;
+ wire s_level_out_d3;
+ wire sda_i;
+ wire sda_rin_d1;
+
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sda_i),
+ .Q(s_level_out_d1_cdc_to),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d1_cdc_to),
+ .Q(s_level_out_d2),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d2),
+ .Q(s_level_out_d3),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d3),
+ .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ),
+ .R(1'b0));
+ LUT2 #(
+ .INIT(4'h2))
+ detect_stop_b_i_3
+ (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ),
+ .I1(sda_rin_d1),
+ .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "cdc_sync" *)
+module TopLevel_axi_iic_0_0_cdc_sync_4
+ (scl_rising_edge0,
+ scndry_out,
+ scl_rin_d1,
+ scl_i,
+ s_axi_aclk);
+ output scl_rising_edge0;
+ output scndry_out;
+ input scl_rin_d1;
+ input scl_i;
+ input s_axi_aclk;
+
+ wire s_axi_aclk;
+ wire s_level_out_d1_cdc_to;
+ wire s_level_out_d2;
+ wire s_level_out_d3;
+ wire scl_i;
+ wire scl_rin_d1;
+ wire scl_rising_edge0;
+ wire scndry_out;
+
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_i),
+ .Q(s_level_out_d1_cdc_to),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d1_cdc_to),
+ .Q(s_level_out_d2),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d2),
+ .Q(s_level_out_d3),
+ .R(1'b0));
+ (* ASYNC_REG *)
+ (* XILINX_LEGACY_PRIM = "FDR" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0))
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_level_out_d3),
+ .Q(scndry_out),
+ .R(1'b0));
+ LUT2 #(
+ .INIT(4'h2))
+ scl_rising_edge_i_1
+ (.I0(scndry_out),
+ .I1(scl_rin_d1),
+ .O(scl_rising_edge0));
+endmodule
+
+module TopLevel_axi_iic_0_0_debounce
+ (scl_rising_edge0,
+ scndry_out,
+ scl_rin_d1,
+ scl_i,
+ s_axi_aclk);
+ output scl_rising_edge0;
+ output scndry_out;
+ input scl_rin_d1;
+ input scl_i;
+ input s_axi_aclk;
+
+ wire s_axi_aclk;
+ wire scl_i;
+ wire scl_rin_d1;
+ wire scl_rising_edge0;
+ wire scndry_out;
+
+ TopLevel_axi_iic_0_0_cdc_sync_4 INPUT_DOUBLE_REGS
+ (.s_axi_aclk(s_axi_aclk),
+ .scl_i(scl_i),
+ .scl_rin_d1(scl_rin_d1),
+ .scl_rising_edge0(scl_rising_edge0),
+ .scndry_out(scndry_out));
+endmodule
+
+(* ORIG_REF_NAME = "debounce" *)
+module TopLevel_axi_iic_0_0_debounce_3
+ (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
+ sda_rin_d1,
+ sda_i,
+ s_axi_aclk);
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ input sda_rin_d1;
+ input sda_i;
+ input s_axi_aclk;
+
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ wire s_axi_aclk;
+ wire sda_i;
+ wire sda_rin_d1;
+
+ TopLevel_axi_iic_0_0_cdc_sync INPUT_DOUBLE_REGS
+ (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
+ .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ),
+ .s_axi_aclk(s_axi_aclk),
+ .sda_i(sda_i),
+ .sda_rin_d1(sda_rin_d1));
+endmodule
+
+module TopLevel_axi_iic_0_0_dynamic_master
+ (rdCntrFrmTxFifo,
+ rxCntDone,
+ firstDynStartSeen,
+ cr_txModeSelect_set,
+ cr_txModeSelect_clr,
+ \rdByteCntr_reg[2]_0 ,
+ rdCntrFrmTxFifo_reg_0,
+ Tx_fifo_rst,
+ ackDataState,
+ s_axi_aclk,
+ p_3_in,
+ Tx_fifo_data,
+ earlyAckDataState,
+ firstDynStartSeen_reg_0,
+ Tx_fifo_rd_d,
+ Tx_fifo_rd,
+ earlyAckHdr,
+ Tx_data_exists);
+ output rdCntrFrmTxFifo;
+ output rxCntDone;
+ output firstDynStartSeen;
+ output cr_txModeSelect_set;
+ output cr_txModeSelect_clr;
+ output \rdByteCntr_reg[2]_0 ;
+ output rdCntrFrmTxFifo_reg_0;
+ input Tx_fifo_rst;
+ input ackDataState;
+ input s_axi_aclk;
+ input p_3_in;
+ input [0:7]Tx_fifo_data;
+ input earlyAckDataState;
+ input firstDynStartSeen_reg_0;
+ input Tx_fifo_rd_d;
+ input Tx_fifo_rd;
+ input earlyAckHdr;
+ input Tx_data_exists;
+
+ wire Cr_txModeSelect_clr_i_1_n_0;
+ wire Cr_txModeSelect_set_i_1_n_0;
+ wire Tx_data_exists;
+ wire [0:7]Tx_fifo_data;
+ wire Tx_fifo_rd;
+ wire Tx_fifo_rd_d;
+ wire Tx_fifo_rst;
+ wire ackDataState;
+ wire ackDataState_d1;
+ wire callingReadAccess;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire earlyAckDataState;
+ wire earlyAckDataState_d1;
+ wire earlyAckHdr;
+ wire firstDynStartSeen;
+ wire firstDynStartSeen_reg_0;
+ wire [7:0]p_0_in__1;
+ wire p_3_in;
+ wire \rdByteCntr[0]_i_1_n_0 ;
+ wire \rdByteCntr[0]_i_3_n_0 ;
+ wire \rdByteCntr[0]_i_4_n_0 ;
+ wire \rdByteCntr[1]_i_2_n_0 ;
+ wire [0:7]rdByteCntr_reg;
+ wire \rdByteCntr_reg[2]_0 ;
+ wire rdCntrFrmTxFifo;
+ wire rdCntrFrmTxFifo0;
+ wire rdCntrFrmTxFifo_reg_0;
+ wire rxCntDone;
+ wire rxCntDone0;
+ wire s_axi_aclk;
+
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'h0080))
+ Cr_txModeSelect_clr_i_1
+ (.I0(callingReadAccess),
+ .I1(firstDynStartSeen),
+ .I2(earlyAckHdr),
+ .I3(Tx_fifo_rst),
+ .O(Cr_txModeSelect_clr_i_1_n_0));
+ FDRE Cr_txModeSelect_clr_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Cr_txModeSelect_clr_i_1_n_0),
+ .Q(cr_txModeSelect_clr),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ Cr_txModeSelect_set_i_1
+ (.I0(callingReadAccess),
+ .I1(firstDynStartSeen),
+ .I2(earlyAckHdr),
+ .I3(Tx_fifo_rst),
+ .O(Cr_txModeSelect_set_i_1_n_0));
+ FDRE Cr_txModeSelect_set_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Cr_txModeSelect_set_i_1_n_0),
+ .Q(cr_txModeSelect_set),
+ .R(1'b0));
+ LUT3 #(
+ .INIT(8'h45))
+ Data_Exists_DFF_i_2__1
+ (.I0(rdCntrFrmTxFifo),
+ .I1(Tx_fifo_rd_d),
+ .I2(Tx_fifo_rd),
+ .O(rdCntrFrmTxFifo_reg_0));
+ FDRE ackDataState_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(ackDataState),
+ .Q(ackDataState_d1),
+ .R(Tx_fifo_rst));
+ FDRE callingReadAccess_reg
+ (.C(s_axi_aclk),
+ .CE(p_3_in),
+ .D(Tx_fifo_data[7]),
+ .Q(callingReadAccess),
+ .R(Tx_fifo_rst));
+ FDRE earlyAckDataState_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(earlyAckDataState),
+ .Q(earlyAckDataState_d1),
+ .R(Tx_fifo_rst));
+ FDRE firstDynStartSeen_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(firstDynStartSeen_reg_0),
+ .Q(firstDynStartSeen),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'hBAAA))
+ \rdByteCntr[0]_i_1
+ (.I0(rdCntrFrmTxFifo),
+ .I1(earlyAckDataState_d1),
+ .I2(earlyAckDataState),
+ .I3(\rdByteCntr[0]_i_3_n_0 ),
+ .O(\rdByteCntr[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hB88BB8B8))
+ \rdByteCntr[0]_i_2
+ (.I0(Tx_fifo_data[0]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[0]),
+ .I3(rdByteCntr_reg[1]),
+ .I4(\rdByteCntr[0]_i_4_n_0 ),
+ .O(p_0_in__1[7]));
+ LUT5 #(
+ .INIT(32'hFFFFFFFE))
+ \rdByteCntr[0]_i_3
+ (.I0(\rdByteCntr[1]_i_2_n_0 ),
+ .I1(rdByteCntr_reg[1]),
+ .I2(rdByteCntr_reg[0]),
+ .I3(rdByteCntr_reg[3]),
+ .I4(rdByteCntr_reg[2]),
+ .O(\rdByteCntr[0]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \rdByteCntr[0]_i_4
+ (.I0(rdByteCntr_reg[4]),
+ .I1(rdByteCntr_reg[7]),
+ .I2(rdByteCntr_reg[6]),
+ .I3(rdByteCntr_reg[5]),
+ .I4(rdByteCntr_reg[3]),
+ .I5(rdByteCntr_reg[2]),
+ .O(\rdByteCntr[0]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hB8B8B8B8B8B8B88B))
+ \rdByteCntr[1]_i_1
+ (.I0(Tx_fifo_data[1]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[1]),
+ .I3(rdByteCntr_reg[2]),
+ .I4(rdByteCntr_reg[3]),
+ .I5(\rdByteCntr[1]_i_2_n_0 ),
+ .O(p_0_in__1[6]));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \rdByteCntr[1]_i_2
+ (.I0(rdByteCntr_reg[4]),
+ .I1(rdByteCntr_reg[7]),
+ .I2(rdByteCntr_reg[6]),
+ .I3(rdByteCntr_reg[5]),
+ .O(\rdByteCntr[1]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8B8B88B))
+ \rdByteCntr[2]_i_1
+ (.I0(Tx_fifo_data[2]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[2]),
+ .I3(\rdByteCntr[1]_i_2_n_0 ),
+ .I4(rdByteCntr_reg[3]),
+ .O(p_0_in__1[5]));
+ LUT4 #(
+ .INIT(16'hB88B))
+ \rdByteCntr[3]_i_1
+ (.I0(Tx_fifo_data[3]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[3]),
+ .I3(\rdByteCntr[1]_i_2_n_0 ),
+ .O(p_0_in__1[4]));
+ LUT6 #(
+ .INIT(64'hBBBBBBB88888888B))
+ \rdByteCntr[4]_i_1
+ (.I0(Tx_fifo_data[4]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[5]),
+ .I3(rdByteCntr_reg[6]),
+ .I4(rdByteCntr_reg[7]),
+ .I5(rdByteCntr_reg[4]),
+ .O(p_0_in__1[3]));
+ LUT5 #(
+ .INIT(32'hBBB8888B))
+ \rdByteCntr[5]_i_1
+ (.I0(Tx_fifo_data[5]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[7]),
+ .I3(rdByteCntr_reg[6]),
+ .I4(rdByteCntr_reg[5]),
+ .O(p_0_in__1[2]));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT4 #(
+ .INIT(16'hB88B))
+ \rdByteCntr[6]_i_1
+ (.I0(Tx_fifo_data[6]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[7]),
+ .I3(rdByteCntr_reg[6]),
+ .O(p_0_in__1[1]));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT3 #(
+ .INIT(8'h8B))
+ \rdByteCntr[7]_i_1
+ (.I0(Tx_fifo_data[7]),
+ .I1(rdCntrFrmTxFifo),
+ .I2(rdByteCntr_reg[7]),
+ .O(p_0_in__1[0]));
+ FDRE \rdByteCntr_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[7]),
+ .Q(rdByteCntr_reg[0]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[6]),
+ .Q(rdByteCntr_reg[1]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[5]),
+ .Q(rdByteCntr_reg[2]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[4]),
+ .Q(rdByteCntr_reg[3]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[4]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[3]),
+ .Q(rdByteCntr_reg[4]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[5]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[2]),
+ .Q(rdByteCntr_reg[5]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[6]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[1]),
+ .Q(rdByteCntr_reg[6]),
+ .R(Tx_fifo_rst));
+ FDRE \rdByteCntr_reg[7]
+ (.C(s_axi_aclk),
+ .CE(\rdByteCntr[0]_i_1_n_0 ),
+ .D(p_0_in__1[0]),
+ .Q(rdByteCntr_reg[7]),
+ .R(Tx_fifo_rst));
+ LUT3 #(
+ .INIT(8'h80))
+ rdCntrFrmTxFifo_i_1
+ (.I0(callingReadAccess),
+ .I1(earlyAckHdr),
+ .I2(Tx_data_exists),
+ .O(rdCntrFrmTxFifo0));
+ FDRE rdCntrFrmTxFifo_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(rdCntrFrmTxFifo0),
+ .Q(rdCntrFrmTxFifo),
+ .R(Tx_fifo_rst));
+ LUT3 #(
+ .INIT(8'h04))
+ rxCntDone_i_1
+ (.I0(ackDataState_d1),
+ .I1(ackDataState),
+ .I2(\rdByteCntr_reg[2]_0 ),
+ .O(rxCntDone0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFEFFFFFFFF))
+ rxCntDone_i_2
+ (.I0(rdByteCntr_reg[2]),
+ .I1(rdByteCntr_reg[3]),
+ .I2(rdByteCntr_reg[0]),
+ .I3(rdByteCntr_reg[1]),
+ .I4(\rdByteCntr[1]_i_2_n_0 ),
+ .I5(callingReadAccess),
+ .O(\rdByteCntr_reg[2]_0 ));
+ FDRE rxCntDone_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(rxCntDone0),
+ .Q(rxCntDone),
+ .R(Tx_fifo_rst));
+endmodule
+
+module TopLevel_axi_iic_0_0_filter
+ (scl_rising_edge0,
+ scndry_out,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
+ scl_rin_d1,
+ sda_rin_d1,
+ scl_i,
+ s_axi_aclk,
+ sda_i);
+ output scl_rising_edge0;
+ output scndry_out;
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
+ output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ input scl_rin_d1;
+ input sda_rin_d1;
+ input scl_i;
+ input s_axi_aclk;
+ input sda_i;
+
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
+ wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
+ wire s_axi_aclk;
+ wire scl_i;
+ wire scl_rin_d1;
+ wire scl_rising_edge0;
+ wire scndry_out;
+ wire sda_i;
+ wire sda_rin_d1;
+
+ TopLevel_axi_iic_0_0_debounce SCL_DEBOUNCE
+ (.s_axi_aclk(s_axi_aclk),
+ .scl_i(scl_i),
+ .scl_rin_d1(scl_rin_d1),
+ .scl_rising_edge0(scl_rising_edge0),
+ .scndry_out(scndry_out));
+ TopLevel_axi_iic_0_0_debounce_3 SDA_DEBOUNCE
+ (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
+ .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ),
+ .s_axi_aclk(s_axi_aclk),
+ .sda_i(sda_i),
+ .sda_rin_d1(sda_rin_d1));
+endmodule
+
+module TopLevel_axi_iic_0_0_iic
+ (s_axi_rdata,
+ s_axi_rresp,
+ is_write_reg,
+ is_read_reg,
+ sda_t,
+ s_axi_rvalid_i_reg,
+ s_axi_bvalid_i_reg,
+ iic2intc_irpt,
+ gpo,
+ scl_t,
+ s_axi_bresp,
+ s_axi_aclk,
+ s_axi_wvalid,
+ s_axi_awvalid,
+ s_axi_arvalid,
+ s_axi_wdata,
+ scl_i,
+ sda_i,
+ s_axi_aresetn,
+ s_axi_rready,
+ s_axi_bready,
+ s_axi_araddr,
+ s_axi_awaddr);
+ output [10:0]s_axi_rdata;
+ output [0:0]s_axi_rresp;
+ output is_write_reg;
+ output is_read_reg;
+ output sda_t;
+ output s_axi_rvalid_i_reg;
+ output s_axi_bvalid_i_reg;
+ output iic2intc_irpt;
+ output [0:0]gpo;
+ output scl_t;
+ output [0:0]s_axi_bresp;
+ input s_axi_aclk;
+ input s_axi_wvalid;
+ input s_axi_awvalid;
+ input s_axi_arvalid;
+ input [10:0]s_axi_wdata;
+ input scl_i;
+ input sda_i;
+ input s_axi_aresetn;
+ input s_axi_rready;
+ input s_axi_bready;
+ input [8:0]s_axi_araddr;
+ input [8:0]s_axi_awaddr;
+
+ wire Aas;
+ wire Abgc;
+ wire [0:6]Adr;
+ wire Al;
+ wire Bb;
+ wire [2:6]Bus2IIC_Addr;
+ wire [3:3]Bus2IIC_RdCE;
+ wire Bus2IIC_Reset;
+ wire [0:17]Bus2IIC_WrCE;
+ wire [0:9]\CLKCNT/q_int_reg ;
+ wire [0:7]Cr;
+ wire D;
+ wire DYN_MASTER_I_n_5;
+ wire DYN_MASTER_I_n_6;
+ wire D_0;
+ wire [0:7]Data_i2c;
+ wire FILTER_I_n_2;
+ wire [22:23]IIC2Bus_Data;
+ wire [0:7]IIC2Bus_IntrEvent;
+ wire IIC_CONTROL_I_n_31;
+ wire IIC_CONTROL_I_n_43;
+ wire IIC_CONTROL_I_n_44;
+ wire Msms_set;
+ wire New_rcv_dta;
+ wire READ_FIFO_I_n_13;
+ wire READ_FIFO_I_n_16;
+ wire REG_INTERFACE_I_n_100;
+ wire REG_INTERFACE_I_n_101;
+ wire REG_INTERFACE_I_n_102;
+ wire REG_INTERFACE_I_n_103;
+ wire REG_INTERFACE_I_n_104;
+ wire REG_INTERFACE_I_n_105;
+ wire REG_INTERFACE_I_n_107;
+ wire REG_INTERFACE_I_n_110;
+ wire REG_INTERFACE_I_n_111;
+ wire REG_INTERFACE_I_n_112;
+ wire REG_INTERFACE_I_n_113;
+ wire REG_INTERFACE_I_n_114;
+ wire REG_INTERFACE_I_n_115;
+ wire REG_INTERFACE_I_n_126;
+ wire REG_INTERFACE_I_n_127;
+ wire REG_INTERFACE_I_n_128;
+ wire REG_INTERFACE_I_n_129;
+ wire REG_INTERFACE_I_n_130;
+ wire REG_INTERFACE_I_n_131;
+ wire REG_INTERFACE_I_n_132;
+ wire REG_INTERFACE_I_n_133;
+ wire REG_INTERFACE_I_n_135;
+ wire REG_INTERFACE_I_n_136;
+ wire REG_INTERFACE_I_n_25;
+ wire REG_INTERFACE_I_n_26;
+ wire REG_INTERFACE_I_n_27;
+ wire REG_INTERFACE_I_n_28;
+ wire REG_INTERFACE_I_n_37;
+ wire REG_INTERFACE_I_n_38;
+ wire REG_INTERFACE_I_n_39;
+ wire REG_INTERFACE_I_n_40;
+ wire REG_INTERFACE_I_n_49;
+ wire REG_INTERFACE_I_n_50;
+ wire REG_INTERFACE_I_n_51;
+ wire REG_INTERFACE_I_n_52;
+ wire REG_INTERFACE_I_n_59;
+ wire REG_INTERFACE_I_n_60;
+ wire REG_INTERFACE_I_n_61;
+ wire REG_INTERFACE_I_n_62;
+ wire REG_INTERFACE_I_n_69;
+ wire REG_INTERFACE_I_n_70;
+ wire REG_INTERFACE_I_n_71;
+ wire REG_INTERFACE_I_n_72;
+ wire REG_INTERFACE_I_n_73;
+ wire REG_INTERFACE_I_n_74;
+ wire REG_INTERFACE_I_n_75;
+ wire REG_INTERFACE_I_n_76;
+ wire REG_INTERFACE_I_n_82;
+ wire REG_INTERFACE_I_n_83;
+ wire REG_INTERFACE_I_n_84;
+ wire REG_INTERFACE_I_n_85;
+ wire REG_INTERFACE_I_n_91;
+ wire REG_INTERFACE_I_n_92;
+ wire REG_INTERFACE_I_n_93;
+ wire REG_INTERFACE_I_n_94;
+ wire Rc_Data_Exists;
+ wire [0:3]Rc_addr;
+ wire [0:7]Rc_fifo_data;
+ wire Rc_fifo_full;
+ wire Rc_fifo_rd;
+ wire Rc_fifo_rd_d;
+ wire Rc_fifo_wr;
+ wire Rc_fifo_wr_d;
+ wire Rdy_new_xmt;
+ wire Ro_prev;
+ wire [0:9]\SETUP_CNT/q_int_reg ;
+ wire Srw;
+ wire [7:0]Timing_param_tbuf;
+ wire [7:0]Timing_param_thdsta;
+ wire [7:0]Timing_param_thigh;
+ wire [7:0]Timing_param_tlow;
+ wire [3:0]Timing_param_tsudat;
+ wire [7:0]Timing_param_tsusta;
+ wire [7:0]Timing_param_tsusto;
+ wire [0:3]Tx_addr;
+ wire Tx_data_exists;
+ wire [0:7]Tx_fifo_data;
+ wire Tx_fifo_full;
+ wire Tx_fifo_rd;
+ wire Tx_fifo_rd_d;
+ wire Tx_fifo_rst;
+ wire Tx_fifo_wr;
+ wire Tx_fifo_wr_d;
+ wire Tx_under_prev;
+ wire Txer;
+ wire WRITE_FIFO_CTRL_I_n_0;
+ wire WRITE_FIFO_CTRL_I_n_3;
+ wire WRITE_FIFO_CTRL_I_n_4;
+ wire WRITE_FIFO_I_n_14;
+ wire WRITE_FIFO_I_n_16;
+ wire X_AXI_IPIF_SSP1_n_14;
+ wire X_AXI_IPIF_SSP1_n_15;
+ wire X_AXI_IPIF_SSP1_n_28;
+ wire X_AXI_IPIF_SSP1_n_31;
+ wire ackDataState;
+ wire clk_cnt_en1;
+ wire clk_cnt_en11_out;
+ wire clk_cnt_en12_out;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire [0:1]ctrlFifoDin;
+ wire [0:1]dynamic_MSMS;
+ wire earlyAckDataState;
+ wire earlyAckHdr;
+ wire firstDynStartSeen;
+ wire [0:0]gpo;
+ wire iic2intc_irpt;
+ wire is_read_reg;
+ wire is_write_reg;
+ wire new_rcv_dta_d1;
+ wire p_0_in;
+ wire [0:0]p_0_out;
+ wire p_1_in;
+ wire p_1_in4_in;
+ wire p_1_in6_in;
+ wire p_1_in__0;
+ wire [6:6]p_1_out;
+ wire [0:0]p_2_in__0;
+ wire p_3_in;
+ wire p_6_out;
+ wire rdCntrFrmTxFifo;
+ wire rxCntDone;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [0:0]s_axi_bresp;
+ wire s_axi_bvalid_i_reg;
+ wire [10:0]s_axi_rdata;
+ wire s_axi_rready;
+ wire [0:0]s_axi_rresp;
+ wire s_axi_rvalid_i_reg;
+ wire [10:0]s_axi_wdata;
+ wire s_axi_wvalid;
+ wire scl_clean;
+ wire scl_i;
+ wire scl_rin_d1;
+ wire scl_rising_edge0;
+ wire scl_t;
+ wire sda_clean;
+ wire sda_i;
+ wire sda_rin_d1;
+ wire sda_t;
+ wire shift_reg_ld;
+ wire [0:0]sr_i;
+ wire stop_scl_reg;
+
+ TopLevel_axi_iic_0_0_dynamic_master DYN_MASTER_I
+ (.Tx_data_exists(Tx_data_exists),
+ .Tx_fifo_data(Tx_fifo_data),
+ .Tx_fifo_rd(Tx_fifo_rd),
+ .Tx_fifo_rd_d(Tx_fifo_rd_d),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .ackDataState(ackDataState),
+ .cr_txModeSelect_clr(cr_txModeSelect_clr),
+ .cr_txModeSelect_set(cr_txModeSelect_set),
+ .earlyAckDataState(earlyAckDataState),
+ .earlyAckHdr(earlyAckHdr),
+ .firstDynStartSeen(firstDynStartSeen),
+ .firstDynStartSeen_reg_0(REG_INTERFACE_I_n_105),
+ .p_3_in(p_3_in),
+ .\rdByteCntr_reg[2]_0 (DYN_MASTER_I_n_5),
+ .rdCntrFrmTxFifo(rdCntrFrmTxFifo),
+ .rdCntrFrmTxFifo_reg_0(DYN_MASTER_I_n_6),
+ .rxCntDone(rxCntDone),
+ .s_axi_aclk(s_axi_aclk));
+ TopLevel_axi_iic_0_0_filter FILTER_I
+ (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (FILTER_I_n_2),
+ .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (sda_clean),
+ .s_axi_aclk(s_axi_aclk),
+ .scl_i(scl_i),
+ .scl_rin_d1(scl_rin_d1),
+ .scl_rising_edge0(scl_rising_edge0),
+ .scndry_out(scl_clean),
+ .sda_i(sda_i),
+ .sda_rin_d1(sda_rin_d1));
+ TopLevel_axi_iic_0_0_iic_control IIC_CONTROL_I
+ (.Aas(Aas),
+ .Bb(Bb),
+ .CO(clk_cnt_en1),
+ .D({Al,Txer,p_1_in__0,p_0_out}),
+ .E(Bus2IIC_WrCE[0]),
+ .\FSM_sequential_scl_state[0]_i_6_0 ({REG_INTERFACE_I_n_69,REG_INTERFACE_I_n_70,REG_INTERFACE_I_n_71,REG_INTERFACE_I_n_72}),
+ .\FSM_sequential_scl_state[1]_i_2_0 ({REG_INTERFACE_I_n_82,REG_INTERFACE_I_n_83,REG_INTERFACE_I_n_84,REG_INTERFACE_I_n_85}),
+ .\FSM_sequential_scl_state[3]_i_4 ({REG_INTERFACE_I_n_37,REG_INTERFACE_I_n_38,REG_INTERFACE_I_n_39,REG_INTERFACE_I_n_40}),
+ .\FSM_sequential_scl_state[3]_i_4_0 ({REG_INTERFACE_I_n_49,REG_INTERFACE_I_n_50,REG_INTERFACE_I_n_51,REG_INTERFACE_I_n_52}),
+ .\FSM_sequential_scl_state_reg[1]_0 (IIC_CONTROL_I_n_31),
+ .\FSM_sequential_scl_state_reg[2]_0 (IIC_CONTROL_I_n_43),
+ .\FSM_sequential_scl_state_reg[2]_1 ({REG_INTERFACE_I_n_73,REG_INTERFACE_I_n_74,REG_INTERFACE_I_n_75,REG_INTERFACE_I_n_76}),
+ .\FSM_sequential_scl_state_reg[3]_0 ({REG_INTERFACE_I_n_59,REG_INTERFACE_I_n_60,REG_INTERFACE_I_n_61,REG_INTERFACE_I_n_62}),
+ .\LEVEL_1_GEN.master_sda_reg_0 (REG_INTERFACE_I_n_102),
+ .Msms_set(Msms_set),
+ .New_rcv_dta(New_rcv_dta),
+ .Q({Cr[1],Cr[2],Cr[4],Cr[5],Cr[7]}),
+ .Rdy_new_xmt(Rdy_new_xmt),
+ .Ro_prev(Ro_prev),
+ .S({REG_INTERFACE_I_n_25,REG_INTERFACE_I_n_26,REG_INTERFACE_I_n_27,REG_INTERFACE_I_n_28}),
+ .Tx_data_exists(Tx_data_exists),
+ .Tx_fifo_data({Tx_fifo_data[0],Tx_fifo_data[1],Tx_fifo_data[2],Tx_fifo_data[3],Tx_fifo_data[4],Tx_fifo_data[5],Tx_fifo_data[6]}),
+ .Tx_under_prev(Tx_under_prev),
+ .aas_i_reg_0({Adr[0],Adr[1],Adr[2],Adr[3],Adr[4],Adr[5],Adr[6]}),
+ .ackDataState(ackDataState),
+ .\cr_i_reg[5] (WRITE_FIFO_I_n_16),
+ .\cr_i_reg[5]_0 (REG_INTERFACE_I_n_107),
+ .\data_i2c_i_reg[7]_0 ({Data_i2c[0],Data_i2c[1],Data_i2c[2],Data_i2c[3],Data_i2c[4],Data_i2c[5],Data_i2c[6],Data_i2c[7]}),
+ .\data_int_reg[0] (sda_clean),
+ .\data_int_reg[0]_0 (p_2_in__0),
+ .detect_stop_b_reg_0(FILTER_I_n_2),
+ .dynamic_MSMS(dynamic_MSMS[0]),
+ .earlyAckDataState(earlyAckDataState),
+ .earlyAckHdr(earlyAckHdr),
+ .new_rcv_dta_d1(new_rcv_dta_d1),
+ .p_6_out(p_6_out),
+ .\q_int_reg[0] ({\SETUP_CNT/q_int_reg [0],\SETUP_CNT/q_int_reg [1],\SETUP_CNT/q_int_reg [2],\SETUP_CNT/q_int_reg [3],\SETUP_CNT/q_int_reg [4],\SETUP_CNT/q_int_reg [5],\SETUP_CNT/q_int_reg [6],\SETUP_CNT/q_int_reg [7],\SETUP_CNT/q_int_reg [8],\SETUP_CNT/q_int_reg [9]}),
+ .\q_int_reg[0]_0 ({\CLKCNT/q_int_reg [0],\CLKCNT/q_int_reg [1],\CLKCNT/q_int_reg [2],\CLKCNT/q_int_reg [3],\CLKCNT/q_int_reg [4],\CLKCNT/q_int_reg [5],\CLKCNT/q_int_reg [6],\CLKCNT/q_int_reg [7],\CLKCNT/q_int_reg [8],\CLKCNT/q_int_reg [9]}),
+ .\q_int_reg[0]_1 (REG_INTERFACE_I_n_101),
+ .\q_int_reg[1] (REG_INTERFACE_I_n_103),
+ .\q_int_reg[4] (REG_INTERFACE_I_n_104),
+ .rxCntDone(rxCntDone),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_wdata(s_axi_wdata[2]),
+ .\s_axi_wdata[2] (IIC_CONTROL_I_n_44),
+ .scl_rin_d1(scl_rin_d1),
+ .scl_rising_edge0(scl_rising_edge0),
+ .scl_t(scl_t),
+ .scndry_out(scl_clean),
+ .sda_cout_reg_reg_0(REG_INTERFACE_I_n_132),
+ .sda_rin_d1(sda_rin_d1),
+ .sda_setup_reg_0({REG_INTERFACE_I_n_91,REG_INTERFACE_I_n_92,REG_INTERFACE_I_n_93,REG_INTERFACE_I_n_94}),
+ .sda_t(sda_t),
+ .shift_reg_ld(shift_reg_ld),
+ .sr_i(sr_i),
+ .srw_i_reg_0({Srw,Abgc}),
+ .stop_scl_reg(stop_scl_reg),
+ .\timing_param_tsusta_i_reg[9] (clk_cnt_en12_out),
+ .\timing_param_tsusto_i_reg[9] (clk_cnt_en11_out));
+ TopLevel_axi_iic_0_0_SRL_FIFO READ_FIFO_I
+ (.\Addr_Counters[0].FDRE_I_0 (REG_INTERFACE_I_n_136),
+ .\Addr_Counters[0].FDRE_I_1 (REG_INTERFACE_I_n_135),
+ .\Addr_Counters[1].FDRE_I_0 (READ_FIFO_I_n_16),
+ .Bus2IIC_Reset(Bus2IIC_Reset),
+ .D({p_1_out,Rc_fifo_full}),
+ .D_0(D),
+ .Msms_set(Msms_set),
+ .Q({p_1_in6_in,p_1_in4_in,p_1_in,REG_INTERFACE_I_n_126}),
+ .Rc_Data_Exists(Rc_Data_Exists),
+ .Rc_addr(Rc_addr),
+ .Rc_fifo_data(Rc_fifo_data),
+ .Rc_fifo_rd(Rc_fifo_rd),
+ .Rc_fifo_rd_d(Rc_fifo_rd_d),
+ .Rc_fifo_wr(Rc_fifo_wr),
+ .Rc_fifo_wr_d(Rc_fifo_wr_d),
+ .msms_set_i_reg(READ_FIFO_I_n_13),
+ .s_axi_aclk(s_axi_aclk),
+ .\s_axi_rdata_i[7]_i_11 ({Data_i2c[0],Data_i2c[1],Data_i2c[2],Data_i2c[3],Data_i2c[4],Data_i2c[5],Data_i2c[6],Data_i2c[7]}));
+ TopLevel_axi_iic_0_0_reg_interface REG_INTERFACE_I
+ (.Aas(Aas),
+ .Bus2IIC_RdCE(Bus2IIC_RdCE),
+ .Bus2IIC_Reset(Bus2IIC_Reset),
+ .Bus2IIC_WrCE({Bus2IIC_WrCE[0],Bus2IIC_WrCE[2],Bus2IIC_WrCE[4],Bus2IIC_WrCE[8],Bus2IIC_WrCE[10],Bus2IIC_WrCE[11],Bus2IIC_WrCE[12],Bus2IIC_WrCE[13],Bus2IIC_WrCE[14],Bus2IIC_WrCE[15],Bus2IIC_WrCE[16],Bus2IIC_WrCE[17]}),
+ .CO(clk_cnt_en1),
+ .D(Ro_prev),
+ .D_0(D_0),
+ .D_1(D),
+ .Data_Exists_DFF(WRITE_FIFO_CTRL_I_n_4),
+ .Data_Exists_DFF_0(WRITE_FIFO_CTRL_I_n_0),
+ .Data_Exists_DFF_1(READ_FIFO_I_n_16),
+ .\FIFO_GEN_DTR.Tx_fifo_rd_reg_0 (REG_INTERFACE_I_n_107),
+ .\FIFO_GEN_DTR.Tx_fifo_wr_reg_0 (REG_INTERFACE_I_n_133),
+ .\GPO_GEN.gpo_i_reg[31]_0 (REG_INTERFACE_I_n_131),
+ .\GPO_GEN.gpo_i_reg[31]_1 (X_AXI_IPIF_SSP1_n_31),
+ .IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
+ .\IIC2Bus_IntrEvent_reg[0]_0 ({Al,Txer,Tx_under_prev,p_1_in__0,p_0_out}),
+ .\IIC2Bus_IntrEvent_reg[5]_0 (REG_INTERFACE_I_n_129),
+ .\LEVEL_1_GEN.master_sda_reg (DYN_MASTER_I_n_5),
+ .Msms_set(Msms_set),
+ .New_rcv_dta(New_rcv_dta),
+ .Q({Cr[0],Cr[1],Cr[2],Cr[3],Cr[4],Cr[5],Cr[7]}),
+ .\RD_FIFO_CNTRL.Rc_fifo_rd_reg_0 (REG_INTERFACE_I_n_136),
+ .\RD_FIFO_CNTRL.Rc_fifo_wr_reg_0 (REG_INTERFACE_I_n_135),
+ .\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 ({p_1_in6_in,p_1_in4_in,p_1_in,REG_INTERFACE_I_n_126}),
+ .\RD_FIFO_CNTRL.ro_prev_i_reg_0 (READ_FIFO_I_n_13),
+ .Rc_Data_Exists(Rc_Data_Exists),
+ .Rc_addr({Rc_addr[2],Rc_addr[3]}),
+ .Rc_fifo_rd(Rc_fifo_rd),
+ .Rc_fifo_rd_d(Rc_fifo_rd_d),
+ .Rc_fifo_wr(Rc_fifo_wr),
+ .Rc_fifo_wr_d(Rc_fifo_wr_d),
+ .Rdy_new_xmt(Rdy_new_xmt),
+ .S({REG_INTERFACE_I_n_25,REG_INTERFACE_I_n_26,REG_INTERFACE_I_n_27,REG_INTERFACE_I_n_28}),
+ .Tx_data_exists(Tx_data_exists),
+ .Tx_fifo_data({Tx_fifo_data[4],Tx_fifo_data[5]}),
+ .Tx_fifo_rd(Tx_fifo_rd),
+ .Tx_fifo_rd_d(Tx_fifo_rd_d),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .Tx_fifo_wr(Tx_fifo_wr),
+ .Tx_fifo_wr_d(Tx_fifo_wr_d),
+ .Tx_fifo_wr_d_reg(REG_INTERFACE_I_n_100),
+ .\adr_i_reg[0]_0 ({Adr[0],Adr[1],Adr[2],Adr[3],Adr[4],Adr[5],Adr[6]}),
+ .\adr_i_reg[6]_0 (REG_INTERFACE_I_n_130),
+ .\bus2ip_addr_i_reg[2] ({IIC2Bus_Data[22],IIC2Bus_Data[23]}),
+ .\bus2ip_addr_i_reg[6] (REG_INTERFACE_I_n_115),
+ .\bus2ip_addr_i_reg[6]_0 (REG_INTERFACE_I_n_128),
+ .\cr_i_reg[2]_0 (REG_INTERFACE_I_n_104),
+ .\cr_i_reg[2]_1 (REG_INTERFACE_I_n_132),
+ .\cr_i_reg[2]_2 ({X_AXI_IPIF_SSP1_n_14,X_AXI_IPIF_SSP1_n_15,IIC_CONTROL_I_n_44}),
+ .\cr_i_reg[3]_0 (REG_INTERFACE_I_n_102),
+ .\cr_i_reg[7]_0 (REG_INTERFACE_I_n_101),
+ .dynamic_MSMS(dynamic_MSMS[1]),
+ .earlyAckDataState(earlyAckDataState),
+ .firstDynStartSeen(firstDynStartSeen),
+ .firstDynStartSeen_reg(REG_INTERFACE_I_n_105),
+ .firstDynStartSeen_reg_0(WRITE_FIFO_CTRL_I_n_3),
+ .gpo(gpo),
+ .new_rcv_dta_d1(new_rcv_dta_d1),
+ .\next_scl_state1_inferred__1/i__carry ({\CLKCNT/q_int_reg [0],\CLKCNT/q_int_reg [1],\CLKCNT/q_int_reg [2],\CLKCNT/q_int_reg [3],\CLKCNT/q_int_reg [4],\CLKCNT/q_int_reg [5],\CLKCNT/q_int_reg [6],\CLKCNT/q_int_reg [7],\CLKCNT/q_int_reg [8],\CLKCNT/q_int_reg [9]}),
+ .p_0_in(p_0_in),
+ .p_3_in(p_3_in),
+ .p_6_out(p_6_out),
+ .\q_int_reg[1] (clk_cnt_en11_out),
+ .\q_int_reg[1]_0 (clk_cnt_en12_out),
+ .\q_int_reg[1]_1 (IIC_CONTROL_I_n_31),
+ .rdCntrFrmTxFifo(rdCntrFrmTxFifo),
+ .s_axi_aclk(s_axi_aclk),
+ .\s_axi_rdata_i[0]_i_7 ({Bus2IIC_Addr[2],Bus2IIC_Addr[3],Bus2IIC_Addr[4],Bus2IIC_Addr[5],Bus2IIC_Addr[6]}),
+ .\s_axi_rdata_i_reg[8] (X_AXI_IPIF_SSP1_n_28),
+ .s_axi_wdata(s_axi_wdata[9:0]),
+ .\sda_setup0_inferred__0/i__carry ({\SETUP_CNT/q_int_reg [0],\SETUP_CNT/q_int_reg [1],\SETUP_CNT/q_int_reg [2],\SETUP_CNT/q_int_reg [3],\SETUP_CNT/q_int_reg [4],\SETUP_CNT/q_int_reg [5],\SETUP_CNT/q_int_reg [6],\SETUP_CNT/q_int_reg [7],\SETUP_CNT/q_int_reg [8],\SETUP_CNT/q_int_reg [9]}),
+ .\sr_i_reg[0]_0 (sr_i),
+ .\sr_i_reg[0]_1 (WRITE_FIFO_I_n_14),
+ .\sr_i_reg[1]_0 ({p_1_out,Rc_fifo_full,Tx_fifo_full,Srw,Bb,Abgc}),
+ .\sr_i_reg[4]_0 (REG_INTERFACE_I_n_114),
+ .\sr_i_reg[5]_0 (REG_INTERFACE_I_n_127),
+ .stop_scl_reg(stop_scl_reg),
+ .stop_scl_reg_reg(REG_INTERFACE_I_n_103),
+ .\timing_param_tbuf_i_reg[7]_0 ({Timing_param_tbuf[7:4],Timing_param_tbuf[1:0]}),
+ .\timing_param_tbuf_i_reg[9]_0 ({REG_INTERFACE_I_n_59,REG_INTERFACE_I_n_60,REG_INTERFACE_I_n_61,REG_INTERFACE_I_n_62}),
+ .\timing_param_thddat_i_reg[9]_0 ({REG_INTERFACE_I_n_69,REG_INTERFACE_I_n_70,REG_INTERFACE_I_n_71,REG_INTERFACE_I_n_72}),
+ .\timing_param_thdsta_i_reg[7]_0 ({Timing_param_thdsta[7:4],Timing_param_thdsta[0]}),
+ .\timing_param_thdsta_i_reg[9]_0 ({REG_INTERFACE_I_n_73,REG_INTERFACE_I_n_74,REG_INTERFACE_I_n_75,REG_INTERFACE_I_n_76}),
+ .\timing_param_thigh_i_reg[7]_0 (Timing_param_thigh),
+ .\timing_param_tlow_i_reg[7]_0 ({Timing_param_tlow[7:4],Timing_param_tlow[0]}),
+ .\timing_param_tlow_i_reg[9]_0 ({REG_INTERFACE_I_n_82,REG_INTERFACE_I_n_83,REG_INTERFACE_I_n_84,REG_INTERFACE_I_n_85}),
+ .\timing_param_tsudat_i_reg[3]_0 (Timing_param_tsudat),
+ .\timing_param_tsudat_i_reg[4]_0 (REG_INTERFACE_I_n_110),
+ .\timing_param_tsudat_i_reg[5]_0 (REG_INTERFACE_I_n_111),
+ .\timing_param_tsudat_i_reg[6]_0 (REG_INTERFACE_I_n_112),
+ .\timing_param_tsudat_i_reg[7]_0 (REG_INTERFACE_I_n_113),
+ .\timing_param_tsudat_i_reg[9]_0 ({REG_INTERFACE_I_n_91,REG_INTERFACE_I_n_92,REG_INTERFACE_I_n_93,REG_INTERFACE_I_n_94}),
+ .\timing_param_tsusta_i_reg[7]_0 ({Timing_param_tsusta[7:4],Timing_param_tsusta[1:0]}),
+ .\timing_param_tsusta_i_reg[9]_0 ({REG_INTERFACE_I_n_49,REG_INTERFACE_I_n_50,REG_INTERFACE_I_n_51,REG_INTERFACE_I_n_52}),
+ .\timing_param_tsusto_i_reg[7]_0 (Timing_param_tsusto),
+ .\timing_param_tsusto_i_reg[9]_0 ({REG_INTERFACE_I_n_37,REG_INTERFACE_I_n_38,REG_INTERFACE_I_n_39,REG_INTERFACE_I_n_40}));
+ FDRE Rc_fifo_rd_d_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Rc_fifo_rd),
+ .Q(Rc_fifo_rd_d),
+ .R(Bus2IIC_Reset));
+ FDRE Rc_fifo_wr_d_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Rc_fifo_wr),
+ .Q(Rc_fifo_wr_d),
+ .R(Bus2IIC_Reset));
+ FDRE Tx_fifo_rd_d_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Tx_fifo_rd),
+ .Q(Tx_fifo_rd_d),
+ .R(Bus2IIC_Reset));
+ FDRE Tx_fifo_wr_d_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Tx_fifo_wr),
+ .Q(Tx_fifo_wr_d),
+ .R(Bus2IIC_Reset));
+ TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0 WRITE_FIFO_CTRL_I
+ (.\Addr_Counters[0].FDRE_I_0 (REG_INTERFACE_I_n_100),
+ .\Addr_Counters[0].FDRE_I_1 (DYN_MASTER_I_n_6),
+ .\Addr_Counters[1].FDRE_I_0 (WRITE_FIFO_CTRL_I_n_4),
+ .D(D_0),
+ .Data_Exists_DFF_0(WRITE_FIFO_CTRL_I_n_0),
+ .Data_Exists_DFF_1(WRITE_FIFO_CTRL_I_n_3),
+ .Tx_data_exists(Tx_data_exists),
+ .Tx_fifo_rd(Tx_fifo_rd),
+ .Tx_fifo_rd_d(Tx_fifo_rd_d),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .ctrlFifoDin(ctrlFifoDin),
+ .dynamic_MSMS(dynamic_MSMS),
+ .rdCntrFrmTxFifo(rdCntrFrmTxFifo),
+ .s_axi_aclk(s_axi_aclk));
+ TopLevel_axi_iic_0_0_SRL_FIFO_0 WRITE_FIFO_I
+ (.\Addr_Counters[0].FDRE_I_0 (Tx_fifo_full),
+ .\Addr_Counters[0].FDRE_I_1 (REG_INTERFACE_I_n_133),
+ .Data_Exists_DFF_0(WRITE_FIFO_I_n_14),
+ .Data_Exists_DFF_1(WRITE_FIFO_I_n_16),
+ .Data_Exists_DFF_2(DYN_MASTER_I_n_6),
+ .Tx_addr(Tx_addr),
+ .Tx_data_exists(Tx_data_exists),
+ .Tx_fifo_data(Tx_fifo_data),
+ .Tx_fifo_rd(Tx_fifo_rd),
+ .Tx_fifo_rd_d(Tx_fifo_rd_d),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .Tx_fifo_wr(Tx_fifo_wr),
+ .Tx_fifo_wr_d(Tx_fifo_wr_d),
+ .\data_int_reg[0] (sda_clean),
+ .dynamic_MSMS(dynamic_MSMS[1]),
+ .p_0_in(p_0_in),
+ .rdCntrFrmTxFifo(rdCntrFrmTxFifo),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_wdata(s_axi_wdata[7:0]),
+ .shift_reg_ld(shift_reg_ld),
+ .shift_reg_ld_reg(p_2_in__0));
+ TopLevel_axi_iic_0_0_axi_ipif_ssp1 X_AXI_IPIF_SSP1
+ (.Bus2IIC_RdCE(Bus2IIC_RdCE),
+ .Bus2IIC_Reset(Bus2IIC_Reset),
+ .Bus2IIC_WrCE({Bus2IIC_WrCE[0],Bus2IIC_WrCE[2],Bus2IIC_WrCE[4],Bus2IIC_WrCE[8],Bus2IIC_WrCE[10],Bus2IIC_WrCE[11],Bus2IIC_WrCE[12],Bus2IIC_WrCE[13],Bus2IIC_WrCE[14],Bus2IIC_WrCE[15],Bus2IIC_WrCE[16],Bus2IIC_WrCE[17]}),
+ .D({IIC2Bus_Data[22],IIC2Bus_Data[23]}),
+ .IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
+ .Q({Bus2IIC_Addr[2],Bus2IIC_Addr[3],Bus2IIC_Addr[4],Bus2IIC_Addr[5],Bus2IIC_Addr[6]}),
+ .Rc_addr({Rc_addr[0],Rc_addr[1]}),
+ .Rc_fifo_data(Rc_fifo_data),
+ .Tx_addr(Tx_addr),
+ .Tx_fifo_data({Tx_fifo_data[0],Tx_fifo_data[1],Tx_fifo_data[2],Tx_fifo_data[3],Tx_fifo_data[6],Tx_fifo_data[7]}),
+ .Tx_fifo_rst(Tx_fifo_rst),
+ .\bus2ip_addr_i_reg[3] (X_AXI_IPIF_SSP1_n_28),
+ .\cr_i_reg[2] (IIC_CONTROL_I_n_43),
+ .\cr_i_reg[2]_0 (WRITE_FIFO_CTRL_I_n_3),
+ .cr_txModeSelect_clr(cr_txModeSelect_clr),
+ .cr_txModeSelect_set(cr_txModeSelect_set),
+ .ctrlFifoDin(ctrlFifoDin),
+ .firstDynStartSeen(firstDynStartSeen),
+ .gpo(gpo),
+ .iic2intc_irpt(iic2intc_irpt),
+ .is_read_reg(is_read_reg),
+ .is_write_reg(is_write_reg),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_bvalid_i_reg(s_axi_bvalid_i_reg),
+ .s_axi_rdata(s_axi_rdata),
+ .\s_axi_rdata_i[0]_i_2 (REG_INTERFACE_I_n_126),
+ .\s_axi_rdata_i[0]_i_2_0 (REG_INTERFACE_I_n_131),
+ .\s_axi_rdata_i[1]_i_2 (REG_INTERFACE_I_n_129),
+ .\s_axi_rdata_i[2]_i_2 (REG_INTERFACE_I_n_127),
+ .\s_axi_rdata_i[3]_i_2 (Timing_param_tsudat),
+ .\s_axi_rdata_i[3]_i_2_0 (REG_INTERFACE_I_n_114),
+ .\s_axi_rdata_i[7]_i_8 ({Cr[0],Cr[1],Cr[2],Cr[3],Cr[4],Cr[7]}),
+ .\s_axi_rdata_i[7]_i_8_0 ({Timing_param_tlow[7:4],Timing_param_tlow[0]}),
+ .\s_axi_rdata_i_reg[1] (REG_INTERFACE_I_n_130),
+ .\s_axi_rdata_i_reg[2] (REG_INTERFACE_I_n_128),
+ .\s_axi_rdata_i_reg[3] (REG_INTERFACE_I_n_115),
+ .\s_axi_rdata_i_reg[4]_i_2 (REG_INTERFACE_I_n_110),
+ .\s_axi_rdata_i_reg[5]_i_2 (REG_INTERFACE_I_n_111),
+ .\s_axi_rdata_i_reg[6]_i_2 (REG_INTERFACE_I_n_112),
+ .\s_axi_rdata_i_reg[7]_i_2 (REG_INTERFACE_I_n_113),
+ .\s_axi_rdata_i_reg[7]_i_6 ({Timing_param_tsusta[7:4],Timing_param_tsusta[1:0]}),
+ .\s_axi_rdata_i_reg[7]_i_6_0 ({Timing_param_tbuf[7:4],Timing_param_tbuf[1:0]}),
+ .\s_axi_rdata_i_reg[7]_i_6_1 ({Timing_param_thdsta[7:4],Timing_param_thdsta[0]}),
+ .\s_axi_rdata_i_reg[7]_i_6_2 ({Adr[0],Adr[1],Adr[2],Adr[3]}),
+ .\s_axi_rdata_i_reg[7]_i_7 (Timing_param_tsusto),
+ .\s_axi_rdata_i_reg[7]_i_7_0 (Timing_param_thigh),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_rvalid_i_reg(s_axi_rvalid_i_reg),
+ .s_axi_wdata(s_axi_wdata),
+ .\s_axi_wdata[5] ({X_AXI_IPIF_SSP1_n_14,X_AXI_IPIF_SSP1_n_15}),
+ .s_axi_wdata_0_sp_1(X_AXI_IPIF_SSP1_n_31),
+ .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module TopLevel_axi_iic_0_0_iic_control
+ (shift_reg_ld,
+ sda_rin_d1,
+ scl_rin_d1,
+ Tx_under_prev,
+ Bb,
+ D,
+ New_rcv_dta,
+ earlyAckHdr,
+ earlyAckDataState,
+ ackDataState,
+ CO,
+ \timing_param_tsusto_i_reg[9] ,
+ \timing_param_tsusta_i_reg[9] ,
+ stop_scl_reg,
+ Aas,
+ srw_i_reg_0,
+ Rdy_new_xmt,
+ \q_int_reg[0] ,
+ \FSM_sequential_scl_state_reg[1]_0 ,
+ \q_int_reg[0]_0 ,
+ sda_t,
+ \FSM_sequential_scl_state_reg[2]_0 ,
+ \s_axi_wdata[2] ,
+ scl_t,
+ p_6_out,
+ \data_i2c_i_reg[7]_0 ,
+ \q_int_reg[0]_1 ,
+ s_axi_aclk,
+ \data_int_reg[0] ,
+ scndry_out,
+ scl_rising_edge0,
+ Ro_prev,
+ Q,
+ sr_i,
+ S,
+ \FSM_sequential_scl_state[3]_i_4 ,
+ \FSM_sequential_scl_state[3]_i_4_0 ,
+ \FSM_sequential_scl_state_reg[3]_0 ,
+ \FSM_sequential_scl_state[0]_i_6_0 ,
+ \FSM_sequential_scl_state_reg[2]_1 ,
+ \FSM_sequential_scl_state[1]_i_2_0 ,
+ sda_setup_reg_0,
+ \q_int_reg[4] ,
+ \LEVEL_1_GEN.master_sda_reg_0 ,
+ \q_int_reg[1] ,
+ aas_i_reg_0,
+ s_axi_wdata,
+ E,
+ \cr_i_reg[5] ,
+ Tx_data_exists,
+ dynamic_MSMS,
+ \cr_i_reg[5]_0 ,
+ rxCntDone,
+ sda_cout_reg_reg_0,
+ Msms_set,
+ \data_int_reg[0]_0 ,
+ Tx_fifo_data,
+ new_rcv_dta_d1,
+ detect_stop_b_reg_0);
+ output shift_reg_ld;
+ output sda_rin_d1;
+ output scl_rin_d1;
+ output Tx_under_prev;
+ output Bb;
+ output [3:0]D;
+ output New_rcv_dta;
+ output earlyAckHdr;
+ output earlyAckDataState;
+ output ackDataState;
+ output [0:0]CO;
+ output [0:0]\timing_param_tsusto_i_reg[9] ;
+ output [0:0]\timing_param_tsusta_i_reg[9] ;
+ output stop_scl_reg;
+ output Aas;
+ output [1:0]srw_i_reg_0;
+ output Rdy_new_xmt;
+ output [9:0]\q_int_reg[0] ;
+ output \FSM_sequential_scl_state_reg[1]_0 ;
+ output [9:0]\q_int_reg[0]_0 ;
+ output sda_t;
+ output \FSM_sequential_scl_state_reg[2]_0 ;
+ output [0:0]\s_axi_wdata[2] ;
+ output scl_t;
+ output p_6_out;
+ output [7:0]\data_i2c_i_reg[7]_0 ;
+ input \q_int_reg[0]_1 ;
+ input s_axi_aclk;
+ input \data_int_reg[0] ;
+ input scndry_out;
+ input scl_rising_edge0;
+ input Ro_prev;
+ input [4:0]Q;
+ input [0:0]sr_i;
+ input [3:0]S;
+ input [3:0]\FSM_sequential_scl_state[3]_i_4 ;
+ input [3:0]\FSM_sequential_scl_state[3]_i_4_0 ;
+ input [3:0]\FSM_sequential_scl_state_reg[3]_0 ;
+ input [3:0]\FSM_sequential_scl_state[0]_i_6_0 ;
+ input [3:0]\FSM_sequential_scl_state_reg[2]_1 ;
+ input [3:0]\FSM_sequential_scl_state[1]_i_2_0 ;
+ input [3:0]sda_setup_reg_0;
+ input \q_int_reg[4] ;
+ input \LEVEL_1_GEN.master_sda_reg_0 ;
+ input \q_int_reg[1] ;
+ input [6:0]aas_i_reg_0;
+ input [0:0]s_axi_wdata;
+ input [0:0]E;
+ input \cr_i_reg[5] ;
+ input Tx_data_exists;
+ input [0:0]dynamic_MSMS;
+ input \cr_i_reg[5]_0 ;
+ input rxCntDone;
+ input sda_cout_reg_reg_0;
+ input Msms_set;
+ input [0:0]\data_int_reg[0]_0 ;
+ input [6:0]Tx_fifo_data;
+ input new_rcv_dta_d1;
+ input detect_stop_b_reg_0;
+
+ wire Aas;
+ wire AckDataState_i_1_n_0;
+ wire BITCNT_n_1;
+ wire BITCNT_n_2;
+ wire BITCNT_n_3;
+ wire BITCNT_n_4;
+ wire Bb;
+ wire [0:0]CO;
+ wire [3:0]D;
+ wire [0:0]E;
+ wire EarlyAckDataState0;
+ wire EarlyAckDataState_i_2_n_0;
+ wire EarlyAckHdr0;
+ wire \FSM_sequential_scl_state[0]_i_2_n_0 ;
+ wire \FSM_sequential_scl_state[0]_i_3_n_0 ;
+ wire \FSM_sequential_scl_state[0]_i_4_n_0 ;
+ wire \FSM_sequential_scl_state[0]_i_5_n_0 ;
+ wire [3:0]\FSM_sequential_scl_state[0]_i_6_0 ;
+ wire \FSM_sequential_scl_state[0]_i_6_n_0 ;
+ wire \FSM_sequential_scl_state[0]_i_7_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_1_n_0 ;
+ wire [3:0]\FSM_sequential_scl_state[1]_i_2_0 ;
+ wire \FSM_sequential_scl_state[1]_i_2_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_4_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_5_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_6_n_0 ;
+ wire \FSM_sequential_scl_state[1]_i_7_n_0 ;
+ wire \FSM_sequential_scl_state[2]_i_2_n_0 ;
+ wire \FSM_sequential_scl_state[3]_i_2_n_0 ;
+ wire [3:0]\FSM_sequential_scl_state[3]_i_4 ;
+ wire [3:0]\FSM_sequential_scl_state[3]_i_4_0 ;
+ wire \FSM_sequential_scl_state[3]_i_5_n_0 ;
+ wire \FSM_sequential_scl_state_reg[1]_0 ;
+ wire \FSM_sequential_scl_state_reg[2]_0 ;
+ wire [3:0]\FSM_sequential_scl_state_reg[2]_1 ;
+ wire [3:0]\FSM_sequential_scl_state_reg[3]_0 ;
+ wire \FSM_sequential_state[1]_i_4_n_0 ;
+ wire \FSM_sequential_state[1]_i_5_n_0 ;
+ wire \FSM_sequential_state[2]_i_4_n_0 ;
+ wire \FSM_sequential_state[2]_i_7_n_0 ;
+ wire \FSM_sequential_state[2]_i_9_n_0 ;
+ wire I2CDATA_REG_n_0;
+ wire I2CDATA_REG_n_2;
+ wire I2CDATA_REG_n_3;
+ wire I2CDATA_REG_n_4;
+ wire I2CDATA_REG_n_5;
+ wire I2CDATA_REG_n_6;
+ wire I2CDATA_REG_n_7;
+ wire I2CDATA_REG_n_8;
+ wire I2CDATA_REG_n_9;
+ wire I2CHEADER_REG_n_1;
+ wire I2CHEADER_REG_n_2;
+ wire I2CHEADER_REG_n_3;
+ wire I2CHEADER_REG_n_4;
+ wire I2CHEADER_REG_n_5;
+ wire I2CHEADER_REG_n_6;
+ wire I2CHEADER_REG_n_7;
+ wire \LEVEL_1_GEN.master_sda_reg_0 ;
+ wire \LEVEL_1_GEN.master_sda_reg_n_0 ;
+ wire Msms_set;
+ wire New_rcv_dta;
+ wire [4:0]Q;
+ wire Rdy_new_xmt;
+ wire Ro_prev;
+ wire [3:0]S;
+ wire SETUP_CNT_n_0;
+ wire Tx_data_exists;
+ wire [6:0]Tx_fifo_data;
+ wire Tx_under_prev;
+ wire aas_i_i_2_n_0;
+ wire [6:0]aas_i_reg_0;
+ wire ackDataState;
+ wire al_i_i_1_n_0;
+ wire al_i_i_2_n_0;
+ wire al_prevent;
+ wire al_prevent_i_1_n_0;
+ wire arb_lost;
+ wire arb_lost_i_1_n_0;
+ wire arb_lost_i_2_n_0;
+ wire arb_lost_i_3_n_0;
+ wire bit_cnt_en;
+ wire bit_cnt_en0;
+ wire bus_busy_d1;
+ wire bus_busy_i_1_n_0;
+ wire clk_cnt_en13_out;
+ wire clk_cnt_en1_carry_n_1;
+ wire clk_cnt_en1_carry_n_2;
+ wire clk_cnt_en1_carry_n_3;
+ wire \clk_cnt_en1_inferred__0/i__carry_n_1 ;
+ wire \clk_cnt_en1_inferred__0/i__carry_n_2 ;
+ wire \clk_cnt_en1_inferred__0/i__carry_n_3 ;
+ wire \clk_cnt_en1_inferred__1/i__carry_n_1 ;
+ wire \clk_cnt_en1_inferred__1/i__carry_n_2 ;
+ wire \clk_cnt_en1_inferred__1/i__carry_n_3 ;
+ wire \clk_cnt_en1_inferred__2/i__carry_n_1 ;
+ wire \clk_cnt_en1_inferred__2/i__carry_n_2 ;
+ wire \clk_cnt_en1_inferred__2/i__carry_n_3 ;
+ wire clk_cnt_en2;
+ wire clk_cnt_en2_carry_n_1;
+ wire clk_cnt_en2_carry_n_2;
+ wire clk_cnt_en2_carry_n_3;
+ wire \cr_i[5]_i_3_n_0 ;
+ wire \cr_i_reg[5] ;
+ wire \cr_i_reg[5]_0 ;
+ wire data_i2c_i0;
+ wire [7:0]\data_i2c_i_reg[7]_0 ;
+ wire \data_int_reg[0] ;
+ wire [0:0]\data_int_reg[0]_0 ;
+ wire detect_start;
+ wire detect_start_i_1_n_0;
+ wire detect_start_i_2_n_0;
+ wire detect_stop0;
+ wire detect_stop_b_i_1_n_0;
+ wire detect_stop_b_i_2_n_0;
+ wire detect_stop_b_reg_0;
+ wire detect_stop_b_reg_n_0;
+ wire detect_stop_i_1_n_0;
+ wire detect_stop_reg_n_0;
+ wire dtc_i_d1;
+ wire dtc_i_d2;
+ wire dtc_i_reg_n_0;
+ wire dtre_d1;
+ wire [0:0]dynamic_MSMS;
+ wire earlyAckDataState;
+ wire earlyAckHdr;
+ wire gen_start;
+ wire gen_start_i_1_n_0;
+ wire gen_stop;
+ wire gen_stop_d1;
+ wire gen_stop_i_1_n_0;
+ wire i2c_header_en;
+ wire i2c_header_en0;
+ wire master_slave;
+ wire master_slave_i_1_n_0;
+ wire msms_d1;
+ wire msms_d10;
+ wire msms_d1_i_2_n_0;
+ wire msms_d2;
+ wire msms_rst_i;
+ wire msms_rst_i_i_1_n_0;
+ wire new_rcv_dta_d1;
+ wire [3:0]next_scl_state;
+ wire next_scl_state10_out;
+ wire \next_scl_state1_inferred__0/i__carry_n_1 ;
+ wire \next_scl_state1_inferred__0/i__carry_n_2 ;
+ wire \next_scl_state1_inferred__0/i__carry_n_3 ;
+ wire \next_scl_state1_inferred__1/i__carry_n_0 ;
+ wire \next_scl_state1_inferred__1/i__carry_n_1 ;
+ wire \next_scl_state1_inferred__1/i__carry_n_2 ;
+ wire \next_scl_state1_inferred__1/i__carry_n_3 ;
+ wire p_6_out;
+ wire [9:0]\q_int_reg[0] ;
+ wire [9:0]\q_int_reg[0]_0 ;
+ wire \q_int_reg[0]_1 ;
+ wire \q_int_reg[1] ;
+ wire \q_int_reg[4] ;
+ wire rdy_new_xmt_i_i_1_n_0;
+ wire rdy_new_xmt_i_i_2_n_0;
+ wire ro_prev_d1;
+ wire rsta_d1;
+ wire rsta_tx_under_prev;
+ wire rsta_tx_under_prev_i_1_n_0;
+ wire rxCntDone;
+ wire s_axi_aclk;
+ wire [0:0]s_axi_wdata;
+ wire [0:0]\s_axi_wdata[2] ;
+ wire scl_cout_reg;
+ wire scl_cout_reg0;
+ wire scl_f_edg_d1;
+ wire scl_f_edg_d2;
+ wire scl_f_edg_d3;
+ wire scl_falling_edge;
+ wire scl_falling_edge0;
+ wire scl_rin_d1;
+ wire scl_rising_edge;
+ wire scl_rising_edge0;
+ wire [3:0]scl_state;
+ wire scl_t;
+ wire scndry_out;
+ wire sda_cout_reg;
+ wire sda_cout_reg_i_1_n_0;
+ wire sda_cout_reg_i_2_n_0;
+ wire sda_cout_reg_i_3_n_0;
+ wire sda_cout_reg_i_4_n_0;
+ wire sda_cout_reg_reg_0;
+ wire sda_rin_d1;
+ wire sda_sample;
+ wire sda_sample_i_1_n_0;
+ wire sda_setup;
+ wire \sda_setup0_inferred__0/i__carry_n_0 ;
+ wire \sda_setup0_inferred__0/i__carry_n_1 ;
+ wire \sda_setup0_inferred__0/i__carry_n_2 ;
+ wire \sda_setup0_inferred__0/i__carry_n_3 ;
+ wire sda_setup_i_1_n_0;
+ wire [3:0]sda_setup_reg_0;
+ wire sda_t;
+ wire [7:7]shift_reg;
+ wire shift_reg_en;
+ wire shift_reg_en0;
+ wire shift_reg_en_i_2_n_0;
+ wire shift_reg_ld;
+ wire shift_reg_ld0;
+ wire shift_reg_ld_d1;
+ wire shift_reg_ld_i_2_n_0;
+ wire slave_sda_reg_n_0;
+ wire sm_stop_i_1_n_0;
+ wire sm_stop_i_2_n_0;
+ wire sm_stop_i_3_n_0;
+ wire sm_stop_reg_n_0;
+ wire [0:0]sr_i;
+ wire [1:0]srw_i_reg_0;
+ wire state0;
+ wire [2:0]state__0;
+ wire stop_scl_reg;
+ wire stop_scl_reg_i_1_n_0;
+ wire stop_scl_reg_i_2_n_0;
+ wire stop_scl_reg_i_3_n_0;
+ wire stop_scl_reg_i_4_n_0;
+ wire stop_scl_reg_i_5_n_0;
+ wire stop_scl_reg_i_6_n_0;
+ wire [0:0]\timing_param_tsusta_i_reg[9] ;
+ wire [0:0]\timing_param_tsusto_i_reg[9] ;
+ wire tx_under_prev_d1;
+ wire tx_under_prev_i0;
+ wire tx_under_prev_i_i_1_n_0;
+ wire txer_edge_i_1_n_0;
+ wire txer_edge_i_2_n_0;
+ wire txer_i_i_1_n_0;
+ wire txer_i_reg_n_0;
+ wire [3:0]NLW_clk_cnt_en1_carry_O_UNCONNECTED;
+ wire [3:0]\NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED ;
+ wire [3:0]\NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED ;
+ wire [3:0]\NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED ;
+ wire [3:0]NLW_clk_cnt_en2_carry_O_UNCONNECTED;
+ wire [3:0]\NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED ;
+ wire [3:0]\NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED ;
+ wire [3:0]\NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED ;
+
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT3 #(
+ .INIT(8'h08))
+ AckDataState_i_1
+ (.I0(state__0[0]),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .O(AckDataState_i_1_n_0));
+ FDRE AckDataState_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AckDataState_i_1_n_0),
+ .Q(ackDataState),
+ .R(\q_int_reg[0]_1 ));
+ TopLevel_axi_iic_0_0_upcnt_n__parameterized0 BITCNT
+ (.EarlyAckDataState0(EarlyAckDataState0),
+ .EarlyAckDataState_reg(AckDataState_i_1_n_0),
+ .EarlyAckDataState_reg_0(EarlyAckDataState_i_2_n_0),
+ .\FSM_sequential_state_reg[0] (BITCNT_n_4),
+ .\FSM_sequential_state_reg[0]_0 (\FSM_sequential_state[2]_i_7_n_0 ),
+ .\FSM_sequential_state_reg[0]_1 (I2CHEADER_REG_n_6),
+ .\FSM_sequential_state_reg[1] (BITCNT_n_3),
+ .\FSM_sequential_state_reg[1]_0 (I2CHEADER_REG_n_1),
+ .\FSM_sequential_state_reg[1]_1 (detect_stop_reg_n_0),
+ .\FSM_sequential_state_reg[2] (BITCNT_n_2),
+ .\FSM_sequential_state_reg[2]_0 (I2CHEADER_REG_n_5),
+ .\FSM_sequential_state_reg[2]_1 (\FSM_sequential_state[2]_i_4_n_0 ),
+ .Q(Q[0]),
+ .bit_cnt_en(bit_cnt_en),
+ .detect_start(detect_start),
+ .dtc_i_reg(dtc_i_reg_n_0),
+ .\q_int_reg[0]_0 (\q_int_reg[0]_1 ),
+ .\q_int_reg[1]_0 (BITCNT_n_1),
+ .s_axi_aclk(s_axi_aclk),
+ .scl_falling_edge(scl_falling_edge),
+ .state0(state0),
+ .state__0(state__0));
+ TopLevel_axi_iic_0_0_upcnt_n CLKCNT
+ (.CO(clk_cnt_en2),
+ .\FSM_sequential_scl_state_reg[1] (\FSM_sequential_scl_state_reg[1]_0 ),
+ .Q(scl_state),
+ .arb_lost(arb_lost),
+ .\q_int_reg[0]_0 (\q_int_reg[0]_0 ),
+ .\q_int_reg[1]_0 (\q_int_reg[1] ),
+ .\q_int_reg[1]_1 (detect_stop_b_reg_n_0),
+ .\q_int_reg[1]_2 (clk_cnt_en13_out),
+ .\q_int_reg[4]_0 (\q_int_reg[4] ),
+ .\q_int_reg[9]_0 (\q_int_reg[0]_1 ),
+ .s_axi_aclk(s_axi_aclk),
+ .scndry_out(scndry_out));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT3 #(
+ .INIT(8'hFB))
+ EarlyAckDataState_i_2
+ (.I0(state__0[0]),
+ .I1(state__0[2]),
+ .I2(state__0[1]),
+ .O(EarlyAckDataState_i_2_n_0));
+ FDRE EarlyAckDataState_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(EarlyAckDataState0),
+ .Q(earlyAckDataState),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT4 #(
+ .INIT(16'h0080))
+ EarlyAckHdr_i_1
+ (.I0(scl_f_edg_d3),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .I3(state__0[0]),
+ .O(EarlyAckHdr0));
+ FDRE EarlyAckHdr_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(EarlyAckHdr0),
+ .Q(earlyAckHdr),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'h00000000ABABAFAA))
+ \FSM_sequential_scl_state[0]_i_2
+ (.I0(\FSM_sequential_scl_state[0]_i_4_n_0 ),
+ .I1(clk_cnt_en13_out),
+ .I2(scl_state[1]),
+ .I3(\FSM_sequential_scl_state[0]_i_5_n_0 ),
+ .I4(scl_state[0]),
+ .I5(\FSM_sequential_scl_state[0]_i_6_n_0 ),
+ .O(\FSM_sequential_scl_state[0]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h0A22FAEE))
+ \FSM_sequential_scl_state[0]_i_3
+ (.I0(\data_int_reg[0] ),
+ .I1(scl_state[2]),
+ .I2(scl_state[0]),
+ .I3(scl_state[3]),
+ .I4(clk_cnt_en13_out),
+ .O(\FSM_sequential_scl_state[0]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hEEFE4444EEFEF4F4))
+ \FSM_sequential_scl_state[0]_i_4
+ (.I0(scl_state[3]),
+ .I1(scl_state[2]),
+ .I2(scl_state[1]),
+ .I3(next_scl_state10_out),
+ .I4(scl_state[0]),
+ .I5(\data_int_reg[0] ),
+ .O(\FSM_sequential_scl_state[0]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000002228222A))
+ \FSM_sequential_scl_state[0]_i_5
+ (.I0(detect_stop_b_reg_n_0),
+ .I1(scl_state[3]),
+ .I2(scl_state[2]),
+ .I3(scl_state[1]),
+ .I4(clk_cnt_en13_out),
+ .I5(\FSM_sequential_scl_state[0]_i_7_n_0 ),
+ .O(\FSM_sequential_scl_state[0]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000FF55F0BB))
+ \FSM_sequential_scl_state[0]_i_6
+ (.I0(scndry_out),
+ .I1(clk_cnt_en2),
+ .I2(\next_scl_state1_inferred__1/i__carry_n_0 ),
+ .I3(scl_state[0]),
+ .I4(scl_state[1]),
+ .I5(\FSM_sequential_scl_state[1]_i_7_n_0 ),
+ .O(\FSM_sequential_scl_state[0]_i_6_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT3 #(
+ .INIT(8'hBF))
+ \FSM_sequential_scl_state[0]_i_7
+ (.I0(Bb),
+ .I1(gen_start),
+ .I2(master_slave),
+ .O(\FSM_sequential_scl_state[0]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'h4444444545454545))
+ \FSM_sequential_scl_state[1]_i_1
+ (.I0(scl_state[3]),
+ .I1(\FSM_sequential_scl_state[1]_i_2_n_0 ),
+ .I2(\FSM_sequential_scl_state[1]_i_3_n_0 ),
+ .I3(\FSM_sequential_scl_state[1]_i_4_n_0 ),
+ .I4(\FSM_sequential_scl_state[1]_i_5_n_0 ),
+ .I5(\FSM_sequential_scl_state[1]_i_6_n_0 ),
+ .O(\FSM_sequential_scl_state[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000006262EA62))
+ \FSM_sequential_scl_state[1]_i_2
+ (.I0(scl_state[1]),
+ .I1(scl_state[0]),
+ .I2(\next_scl_state1_inferred__1/i__carry_n_0 ),
+ .I3(Q[3]),
+ .I4(arb_lost),
+ .I5(\FSM_sequential_scl_state[1]_i_7_n_0 ),
+ .O(\FSM_sequential_scl_state[1]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT5 #(
+ .INIT(32'hFE44EE44))
+ \FSM_sequential_scl_state[1]_i_3
+ (.I0(scl_state[3]),
+ .I1(scl_state[2]),
+ .I2(scl_state[1]),
+ .I3(scl_state[0]),
+ .I4(next_scl_state10_out),
+ .O(\FSM_sequential_scl_state[1]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT5 #(
+ .INIT(32'h03FD0000))
+ \FSM_sequential_scl_state[1]_i_4
+ (.I0(clk_cnt_en13_out),
+ .I1(scl_state[1]),
+ .I2(scl_state[2]),
+ .I3(scl_state[3]),
+ .I4(detect_stop_b_reg_n_0),
+ .O(\FSM_sequential_scl_state[1]_i_4_n_0 ));
+ LUT4 #(
+ .INIT(16'hFFBF))
+ \FSM_sequential_scl_state[1]_i_5
+ (.I0(scl_state[0]),
+ .I1(master_slave),
+ .I2(gen_start),
+ .I3(Bb),
+ .O(\FSM_sequential_scl_state[1]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT3 #(
+ .INIT(8'h15))
+ \FSM_sequential_scl_state[1]_i_6
+ (.I0(scl_state[1]),
+ .I1(scl_state[0]),
+ .I2(clk_cnt_en13_out),
+ .O(\FSM_sequential_scl_state[1]_i_6_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT3 #(
+ .INIT(8'h35))
+ \FSM_sequential_scl_state[1]_i_7
+ (.I0(scl_state[2]),
+ .I1(scl_state[0]),
+ .I2(scl_state[3]),
+ .O(\FSM_sequential_scl_state[1]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000000000FF80))
+ \FSM_sequential_scl_state[2]_i_1
+ (.I0(next_scl_state10_out),
+ .I1(scl_state[0]),
+ .I2(scl_state[1]),
+ .I3(scl_state[2]),
+ .I4(\FSM_sequential_scl_state[2]_i_2_n_0 ),
+ .I5(scl_state[3]),
+ .O(next_scl_state[2]));
+ LUT6 #(
+ .INIT(64'hFE00000000000000))
+ \FSM_sequential_scl_state[2]_i_2
+ (.I0(Q[3]),
+ .I1(stop_scl_reg),
+ .I2(arb_lost),
+ .I3(scl_state[1]),
+ .I4(scl_state[0]),
+ .I5(scl_state[2]),
+ .O(\FSM_sequential_scl_state[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h545555FF555555FF))
+ \FSM_sequential_scl_state[3]_i_2
+ (.I0(scl_state[3]),
+ .I1(\q_int_reg[4] ),
+ .I2(arb_lost),
+ .I3(scl_state[1]),
+ .I4(scl_state[2]),
+ .I5(scl_state[0]),
+ .O(\FSM_sequential_scl_state[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h77777777000F0000))
+ \FSM_sequential_scl_state[3]_i_3
+ (.I0(clk_cnt_en13_out),
+ .I1(scl_state[0]),
+ .I2(\FSM_sequential_scl_state[3]_i_5_n_0 ),
+ .I3(arb_lost),
+ .I4(scl_state[2]),
+ .I5(scl_state[3]),
+ .O(next_scl_state[3]));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT4 #(
+ .INIT(16'hDFFF))
+ \FSM_sequential_scl_state[3]_i_5
+ (.I0(stop_scl_reg),
+ .I1(Q[3]),
+ .I2(scl_state[0]),
+ .I3(scl_state[1]),
+ .O(\FSM_sequential_scl_state[3]_i_5_n_0 ));
+ (* FSM_ENCODED_STATES = "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101" *)
+ FDRE \FSM_sequential_scl_state_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
+ .D(next_scl_state[0]),
+ .Q(scl_state[0]),
+ .R(\q_int_reg[0]_1 ));
+ MUXF7 \FSM_sequential_scl_state_reg[0]_i_1
+ (.I0(\FSM_sequential_scl_state[0]_i_2_n_0 ),
+ .I1(\FSM_sequential_scl_state[0]_i_3_n_0 ),
+ .O(next_scl_state[0]),
+ .S(scl_state[3]));
+ (* FSM_ENCODED_STATES = "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101" *)
+ FDRE \FSM_sequential_scl_state_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
+ .D(\FSM_sequential_scl_state[1]_i_1_n_0 ),
+ .Q(scl_state[1]),
+ .R(\q_int_reg[0]_1 ));
+ (* FSM_ENCODED_STATES = "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101" *)
+ FDRE \FSM_sequential_scl_state_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
+ .D(next_scl_state[2]),
+ .Q(scl_state[2]),
+ .R(\q_int_reg[0]_1 ));
+ (* FSM_ENCODED_STATES = "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101" *)
+ FDRE \FSM_sequential_scl_state_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
+ .D(next_scl_state[3]),
+ .Q(scl_state[3]),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT4 #(
+ .INIT(16'h4088))
+ \FSM_sequential_state[1]_i_4
+ (.I0(state__0[2]),
+ .I1(state__0[0]),
+ .I2(Ro_prev),
+ .I3(state__0[1]),
+ .O(\FSM_sequential_state[1]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFBAAAAFFFBFFFB))
+ \FSM_sequential_state[1]_i_5
+ (.I0(state__0[1]),
+ .I1(state__0[0]),
+ .I2(sda_sample),
+ .I3(arb_lost),
+ .I4(detect_start),
+ .I5(state__0[2]),
+ .O(\FSM_sequential_state[1]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT3 #(
+ .INIT(8'h34))
+ \FSM_sequential_state[2]_i_4
+ (.I0(Ro_prev),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .O(\FSM_sequential_state[2]_i_4_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \FSM_sequential_state[2]_i_5
+ (.I0(detect_stop_reg_n_0),
+ .I1(Q[0]),
+ .O(state0));
+ LUT3 #(
+ .INIT(8'h0D))
+ \FSM_sequential_state[2]_i_7
+ (.I0(ro_prev_d1),
+ .I1(Ro_prev),
+ .I2(scl_f_edg_d2),
+ .O(\FSM_sequential_state[2]_i_7_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT2 #(
+ .INIT(4'hE))
+ \FSM_sequential_state[2]_i_9
+ (.I0(arb_lost),
+ .I1(sda_sample),
+ .O(\FSM_sequential_state[2]_i_9_n_0 ));
+ (* FSM_ENCODED_STATES = "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000" *)
+ FDRE \FSM_sequential_state_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(BITCNT_n_4),
+ .Q(state__0[0]),
+ .R(1'b0));
+ (* FSM_ENCODED_STATES = "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000" *)
+ FDRE \FSM_sequential_state_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(BITCNT_n_3),
+ .Q(state__0[1]),
+ .R(1'b0));
+ (* FSM_ENCODED_STATES = "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000" *)
+ FDRE \FSM_sequential_state_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(BITCNT_n_2),
+ .Q(state__0[2]),
+ .R(1'b0));
+ TopLevel_axi_iic_0_0_shift8 I2CDATA_REG
+ (.\LEVEL_1_GEN.master_sda_reg (\LEVEL_1_GEN.master_sda_reg_0 ),
+ .\LEVEL_1_GEN.master_sda_reg_0 (Tx_under_prev),
+ .Q({shift_reg,I2CDATA_REG_n_2,I2CDATA_REG_n_3,I2CDATA_REG_n_4,I2CDATA_REG_n_5,I2CDATA_REG_n_6,I2CDATA_REG_n_7,I2CDATA_REG_n_8}),
+ .Tx_fifo_data(Tx_fifo_data),
+ .\data_int_reg[0]_0 (\data_int_reg[0]_0 ),
+ .\data_int_reg[1]_0 (shift_reg_ld),
+ .\data_int_reg[7]_0 (I2CDATA_REG_n_0),
+ .\data_int_reg[7]_1 (\q_int_reg[0]_1 ),
+ .s_axi_aclk(s_axi_aclk),
+ .shift_reg_en(shift_reg_en),
+ .slave_sda_reg(I2CHEADER_REG_n_2),
+ .state__0(state__0),
+ .tx_under_prev_i_reg(I2CDATA_REG_n_9));
+ TopLevel_axi_iic_0_0_shift8_1 I2CHEADER_REG
+ (.E(i2c_header_en),
+ .\FSM_sequential_state_reg[1] (\FSM_sequential_state[1]_i_4_n_0 ),
+ .\FSM_sequential_state_reg[1]_0 (\FSM_sequential_state[1]_i_5_n_0 ),
+ .\FSM_sequential_state_reg[2] (I2CHEADER_REG_n_5),
+ .\FSM_sequential_state_reg[2]_0 (\FSM_sequential_state[2]_i_9_n_0 ),
+ .Q({Q[4],Q[2],Q[0]}),
+ .Ro_prev(Ro_prev),
+ .aas_i_reg(I2CHEADER_REG_n_3),
+ .aas_i_reg_0(aas_i_i_2_n_0),
+ .aas_i_reg_1(Aas),
+ .aas_i_reg_2(detect_stop_reg_n_0),
+ .aas_i_reg_3(aas_i_reg_0),
+ .abgc_i_reg(I2CHEADER_REG_n_2),
+ .abgc_i_reg_0(srw_i_reg_0[0]),
+ .arb_lost(arb_lost),
+ .\cr_i_reg[4] (I2CHEADER_REG_n_1),
+ .\data_int_reg[0]_0 (I2CHEADER_REG_n_7),
+ .\data_int_reg[0]_1 (\q_int_reg[0]_1 ),
+ .\data_int_reg[0]_2 (\data_int_reg[0] ),
+ .detect_start(detect_start),
+ .detect_start_reg(I2CHEADER_REG_n_4),
+ .detect_start_reg_0(I2CHEADER_REG_n_6),
+ .master_slave(master_slave),
+ .s_axi_aclk(s_axi_aclk),
+ .sda_sample(sda_sample),
+ .shift_reg_ld0(shift_reg_ld0),
+ .shift_reg_ld_reg(shift_reg_ld_i_2_n_0),
+ .shift_reg_ld_reg_0(Tx_under_prev),
+ .srw_i_reg(srw_i_reg_0[1]),
+ .state__0(state__0));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \IIC2Bus_IntrEvent[4]_i_1
+ (.I0(Bb),
+ .O(D[1]));
+ LUT1 #(
+ .INIT(2'h1))
+ \IIC2Bus_IntrEvent[6]_i_1
+ (.I0(Aas),
+ .O(D[0]));
+ FDSE \LEVEL_1_GEN.master_sda_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I2CDATA_REG_n_9),
+ .Q(\LEVEL_1_GEN.master_sda_reg_n_0 ),
+ .S(\q_int_reg[0]_1 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \RD_FIFO_CNTRL.Rc_fifo_wr_i_1
+ (.I0(New_rcv_dta),
+ .I1(new_rcv_dta_d1),
+ .O(p_6_out));
+ TopLevel_axi_iic_0_0_upcnt_n_2 SETUP_CNT
+ (.Q(\q_int_reg[0] ),
+ .gen_stop(gen_stop),
+ .gen_stop_d1(gen_stop_d1),
+ .gen_stop_d1_reg(SETUP_CNT_n_0),
+ .\q_int[0]_i_3_0 (Q[3]),
+ .\q_int[0]_i_3_1 (Tx_under_prev),
+ .\q_int[0]_i_3_2 (sda_rin_d1),
+ .\q_int[0]_i_3_3 (\data_int_reg[0] ),
+ .\q_int_reg[0]_0 (\q_int_reg[0]_1 ),
+ .rsta_d1(rsta_d1),
+ .s_axi_aclk(s_axi_aclk),
+ .sda_setup(sda_setup),
+ .tx_under_prev_d1(tx_under_prev_d1));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT3 #(
+ .INIT(8'h40))
+ aas_i_i_2
+ (.I0(state__0[0]),
+ .I1(state__0[2]),
+ .I2(state__0[1]),
+ .O(aas_i_i_2_n_0));
+ FDRE aas_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I2CHEADER_REG_n_3),
+ .Q(Aas),
+ .R(1'b0));
+ FDRE abgc_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I2CHEADER_REG_n_4),
+ .Q(srw_i_reg_0[0]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'hE0E0E0E0E0EEE0E0))
+ al_i_i_1
+ (.I0(Q[3]),
+ .I1(master_slave),
+ .I2(al_i_i_2_n_0),
+ .I3(al_prevent),
+ .I4(detect_stop_reg_n_0),
+ .I5(sm_stop_reg_n_0),
+ .O(al_i_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT4 #(
+ .INIT(16'hFDDD))
+ al_i_i_2
+ (.I0(master_slave),
+ .I1(arb_lost),
+ .I2(bus_busy_d1),
+ .I3(gen_start),
+ .O(al_i_i_2_n_0));
+ FDRE al_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(al_i_i_1_n_0),
+ .Q(D[3]),
+ .R(\q_int_reg[0]_1 ));
+ LUT4 #(
+ .INIT(16'h5554))
+ al_prevent_i_1
+ (.I0(detect_start),
+ .I1(gen_stop),
+ .I2(sm_stop_reg_n_0),
+ .I3(al_prevent),
+ .O(al_prevent_i_1_n_0));
+ FDRE al_prevent_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(al_prevent_i_1_n_0),
+ .Q(al_prevent),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'h000000002AEA2A2A))
+ arb_lost_i_1
+ (.I0(arb_lost),
+ .I1(master_slave),
+ .I2(arb_lost_i_2_n_0),
+ .I3(\data_int_reg[0] ),
+ .I4(sda_cout_reg),
+ .I5(arb_lost_i_3_n_0),
+ .O(arb_lost_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT4 #(
+ .INIT(16'h0820))
+ arb_lost_i_2
+ (.I0(scl_rising_edge),
+ .I1(state__0[0]),
+ .I2(state__0[1]),
+ .I3(state__0[2]),
+ .O(arb_lost_i_2_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT5 #(
+ .INIT(32'h0009FFFF))
+ arb_lost_i_3
+ (.I0(scl_state[3]),
+ .I1(scl_state[0]),
+ .I2(scl_state[2]),
+ .I3(scl_state[1]),
+ .I4(Q[0]),
+ .O(arb_lost_i_3_n_0));
+ FDRE arb_lost_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(arb_lost_i_1_n_0),
+ .Q(arb_lost),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT4 #(
+ .INIT(16'h0848))
+ bit_cnt_en_i_1
+ (.I0(state__0[2]),
+ .I1(scl_falling_edge),
+ .I2(state__0[1]),
+ .I3(state__0[0]),
+ .O(bit_cnt_en0));
+ FDRE bit_cnt_en_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(bit_cnt_en0),
+ .Q(bit_cnt_en),
+ .R(\q_int_reg[0]_1 ));
+ FDRE bus_busy_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Bb),
+ .Q(bus_busy_d1),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'h00E0))
+ bus_busy_i_1
+ (.I0(Bb),
+ .I1(detect_start),
+ .I2(Q[0]),
+ .I3(detect_stop_reg_n_0),
+ .O(bus_busy_i_1_n_0));
+ FDRE bus_busy_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(bus_busy_i_1_n_0),
+ .Q(Bb),
+ .R(1'b0));
+ CARRY4 clk_cnt_en1_carry
+ (.CI(1'b0),
+ .CO({CO,clk_cnt_en1_carry_n_1,clk_cnt_en1_carry_n_2,clk_cnt_en1_carry_n_3}),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(NLW_clk_cnt_en1_carry_O_UNCONNECTED[3:0]),
+ .S(S));
+ CARRY4 \clk_cnt_en1_inferred__0/i__carry
+ (.CI(1'b0),
+ .CO({\timing_param_tsusto_i_reg[9] ,\clk_cnt_en1_inferred__0/i__carry_n_1 ,\clk_cnt_en1_inferred__0/i__carry_n_2 ,\clk_cnt_en1_inferred__0/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED [3:0]),
+ .S(\FSM_sequential_scl_state[3]_i_4 ));
+ CARRY4 \clk_cnt_en1_inferred__1/i__carry
+ (.CI(1'b0),
+ .CO({\timing_param_tsusta_i_reg[9] ,\clk_cnt_en1_inferred__1/i__carry_n_1 ,\clk_cnt_en1_inferred__1/i__carry_n_2 ,\clk_cnt_en1_inferred__1/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED [3:0]),
+ .S(\FSM_sequential_scl_state[3]_i_4_0 ));
+ CARRY4 \clk_cnt_en1_inferred__2/i__carry
+ (.CI(1'b0),
+ .CO({clk_cnt_en13_out,\clk_cnt_en1_inferred__2/i__carry_n_1 ,\clk_cnt_en1_inferred__2/i__carry_n_2 ,\clk_cnt_en1_inferred__2/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED [3:0]),
+ .S(\FSM_sequential_scl_state_reg[3]_0 ));
+ CARRY4 clk_cnt_en2_carry
+ (.CI(1'b0),
+ .CO({clk_cnt_en2,clk_cnt_en2_carry_n_1,clk_cnt_en2_carry_n_2,clk_cnt_en2_carry_n_3}),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(NLW_clk_cnt_en2_carry_O_UNCONNECTED[3:0]),
+ .S(\FSM_sequential_scl_state[0]_i_6_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'hFBFF))
+ \cr_i[2]_i_2
+ (.I0(scl_state[2]),
+ .I1(scl_state[1]),
+ .I2(scl_state[3]),
+ .I3(scl_state[0]),
+ .O(\FSM_sequential_scl_state_reg[2]_0 ));
+ LUT6 #(
+ .INIT(64'h88888888BBBB888B))
+ \cr_i[5]_i_1
+ (.I0(s_axi_wdata),
+ .I1(E),
+ .I2(Bb),
+ .I3(\cr_i_reg[5] ),
+ .I4(Q[1]),
+ .I5(\cr_i[5]_i_3_n_0 ),
+ .O(\s_axi_wdata[2] ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFF80))
+ \cr_i[5]_i_3
+ (.I0(Tx_data_exists),
+ .I1(dynamic_MSMS),
+ .I2(\cr_i_reg[5]_0 ),
+ .I3(msms_rst_i),
+ .I4(sm_stop_reg_n_0),
+ .I5(rxCntDone),
+ .O(\cr_i[5]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h00004000))
+ \data_i2c_i[7]_i_1
+ (.I0(state__0[2]),
+ .I1(state__0[1]),
+ .I2(state__0[0]),
+ .I3(scl_falling_edge),
+ .I4(Ro_prev),
+ .O(data_i2c_i0));
+ FDRE \data_i2c_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_8),
+ .Q(\data_i2c_i_reg[7]_0 [0]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_7),
+ .Q(\data_i2c_i_reg[7]_0 [1]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_6),
+ .Q(\data_i2c_i_reg[7]_0 [2]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_5),
+ .Q(\data_i2c_i_reg[7]_0 [3]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_4),
+ .Q(\data_i2c_i_reg[7]_0 [4]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_3),
+ .Q(\data_i2c_i_reg[7]_0 [5]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(I2CDATA_REG_n_2),
+ .Q(\data_i2c_i_reg[7]_0 [6]),
+ .R(\q_int_reg[0]_1 ));
+ FDRE \data_i2c_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(data_i2c_i0),
+ .D(shift_reg),
+ .Q(\data_i2c_i_reg[7]_0 [7]),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'h00000000FB080000))
+ detect_start_i_1
+ (.I0(scndry_out),
+ .I1(sda_rin_d1),
+ .I2(\data_int_reg[0] ),
+ .I3(detect_start),
+ .I4(Q[0]),
+ .I5(detect_start_i_2_n_0),
+ .O(detect_start_i_1_n_0));
+ LUT3 #(
+ .INIT(8'h08))
+ detect_start_i_2
+ (.I0(state__0[0]),
+ .I1(state__0[2]),
+ .I2(state__0[1]),
+ .O(detect_start_i_2_n_0));
+ FDRE detect_start_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(detect_start_i_1_n_0),
+ .Q(detect_start),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h00000000E2220000))
+ detect_stop_b_i_1
+ (.I0(detect_stop_b_reg_n_0),
+ .I1(detect_stop_b_i_2_n_0),
+ .I2(scndry_out),
+ .I3(detect_stop_b_reg_0),
+ .I4(Q[0]),
+ .I5(detect_start),
+ .O(detect_stop_b_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h4444444444444F44))
+ detect_stop_b_i_2
+ (.I0(sda_rin_d1),
+ .I1(\data_int_reg[0] ),
+ .I2(scl_state[0]),
+ .I3(scl_state[1]),
+ .I4(scl_state[3]),
+ .I5(scl_state[2]),
+ .O(detect_stop_b_i_2_n_0));
+ FDRE detect_stop_b_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(detect_stop_b_i_1_n_0),
+ .Q(detect_stop_b_reg_n_0),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h00000000F2020000))
+ detect_stop_i_1
+ (.I0(detect_stop_reg_n_0),
+ .I1(detect_stop0),
+ .I2(detect_stop_b_reg_0),
+ .I3(scndry_out),
+ .I4(Q[0]),
+ .I5(detect_start),
+ .O(detect_stop_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT2 #(
+ .INIT(4'h2))
+ detect_stop_i_2
+ (.I0(msms_d1),
+ .I1(msms_d2),
+ .O(detect_stop0));
+ FDRE detect_stop_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(detect_stop_i_1_n_0),
+ .Q(detect_stop_reg_n_0),
+ .R(1'b0));
+ FDRE dtc_i_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(dtc_i_reg_n_0),
+ .Q(dtc_i_d1),
+ .R(\q_int_reg[0]_1 ));
+ FDRE dtc_i_d2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(dtc_i_d1),
+ .Q(dtc_i_d2),
+ .R(\q_int_reg[0]_1 ));
+ FDRE dtc_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(BITCNT_n_1),
+ .Q(dtc_i_reg_n_0),
+ .R(\q_int_reg[0]_1 ));
+ FDRE dtre_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sr_i),
+ .Q(dtre_d1),
+ .R(\q_int_reg[0]_1 ));
+ LUT4 #(
+ .INIT(16'h7530))
+ gen_start_i_1
+ (.I0(detect_start),
+ .I1(msms_d2),
+ .I2(msms_d1),
+ .I3(gen_start),
+ .O(gen_start_i_1_n_0));
+ FDRE gen_start_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(gen_start_i_1_n_0),
+ .Q(gen_start),
+ .R(\q_int_reg[0]_1 ));
+ FDRE gen_stop_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(gen_stop),
+ .Q(gen_stop_d1),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT5 #(
+ .INIT(32'h55750030))
+ gen_stop_i_1
+ (.I0(detect_stop_reg_n_0),
+ .I1(msms_d1),
+ .I2(msms_d2),
+ .I3(arb_lost),
+ .I4(gen_stop),
+ .O(gen_stop_i_1_n_0));
+ FDRE gen_stop_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(gen_stop_i_1_n_0),
+ .Q(gen_stop),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ i2c_header_en_i_1
+ (.I0(scl_rising_edge),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .I3(state__0[0]),
+ .O(i2c_header_en0));
+ FDRE i2c_header_en_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(i2c_header_en0),
+ .Q(i2c_header_en),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT5 #(
+ .INIT(32'h4F400000))
+ master_slave_i_1
+ (.I0(arb_lost),
+ .I1(master_slave),
+ .I2(Bb),
+ .I3(msms_d1),
+ .I4(Q[0]),
+ .O(master_slave_i_1_n_0));
+ FDRE master_slave_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(master_slave_i_1_n_0),
+ .Q(master_slave),
+ .R(1'b0));
+ LUT2 #(
+ .INIT(4'h2))
+ msms_d1_i_1
+ (.I0(msms_d1_i_2_n_0),
+ .I1(msms_rst_i),
+ .O(msms_d10));
+ LUT6 #(
+ .INIT(64'hAABAAAAAAABAAABA))
+ msms_d1_i_2
+ (.I0(Q[1]),
+ .I1(txer_i_reg_n_0),
+ .I2(msms_d1),
+ .I3(Msms_set),
+ .I4(dtc_i_d2),
+ .I5(dtc_i_d1),
+ .O(msms_d1_i_2_n_0));
+ FDRE msms_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(msms_d10),
+ .Q(msms_d1),
+ .R(\q_int_reg[0]_1 ));
+ FDRE msms_d2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(msms_d1),
+ .Q(msms_d2),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'h0000000008FF0800))
+ msms_rst_i_i_1
+ (.I0(arb_lost_i_2_n_0),
+ .I1(sda_cout_reg),
+ .I2(\data_int_reg[0] ),
+ .I3(master_slave),
+ .I4(msms_rst_i),
+ .I5(arb_lost_i_3_n_0),
+ .O(msms_rst_i_i_1_n_0));
+ FDRE msms_rst_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(msms_rst_i_i_1_n_0),
+ .Q(msms_rst_i),
+ .R(1'b0));
+ FDRE new_rcv_dta_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(data_i2c_i0),
+ .Q(New_rcv_dta),
+ .R(\q_int_reg[0]_1 ));
+ CARRY4 \next_scl_state1_inferred__0/i__carry
+ (.CI(1'b0),
+ .CO({next_scl_state10_out,\next_scl_state1_inferred__0/i__carry_n_1 ,\next_scl_state1_inferred__0/i__carry_n_2 ,\next_scl_state1_inferred__0/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED [3:0]),
+ .S(\FSM_sequential_scl_state_reg[2]_1 ));
+ CARRY4 \next_scl_state1_inferred__1/i__carry
+ (.CI(1'b0),
+ .CO({\next_scl_state1_inferred__1/i__carry_n_0 ,\next_scl_state1_inferred__1/i__carry_n_1 ,\next_scl_state1_inferred__1/i__carry_n_2 ,\next_scl_state1_inferred__1/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED [3:0]),
+ .S(\FSM_sequential_scl_state[1]_i_2_0 ));
+ LUT6 #(
+ .INIT(64'h222F2F2F22202020))
+ rdy_new_xmt_i_i_1
+ (.I0(shift_reg_ld_d1),
+ .I1(shift_reg_ld),
+ .I2(rdy_new_xmt_i_i_2_n_0),
+ .I3(Q[1]),
+ .I4(detect_start_i_2_n_0),
+ .I5(Rdy_new_xmt),
+ .O(rdy_new_xmt_i_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'h04))
+ rdy_new_xmt_i_i_2
+ (.I0(state__0[0]),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .O(rdy_new_xmt_i_i_2_n_0));
+ FDRE rdy_new_xmt_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(rdy_new_xmt_i_i_1_n_0),
+ .Q(Rdy_new_xmt),
+ .R(\q_int_reg[0]_1 ));
+ FDRE ro_prev_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Ro_prev),
+ .Q(ro_prev_d1),
+ .R(\q_int_reg[0]_1 ));
+ FDRE rsta_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Q[3]),
+ .Q(rsta_d1),
+ .R(\q_int_reg[0]_1 ));
+ LUT5 #(
+ .INIT(32'hF0FF2020))
+ rsta_tx_under_prev_i_1
+ (.I0(Q[3]),
+ .I1(rsta_d1),
+ .I2(sr_i),
+ .I3(dtre_d1),
+ .I4(rsta_tx_under_prev),
+ .O(rsta_tx_under_prev_i_1_n_0));
+ FDRE rsta_tx_under_prev_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(rsta_tx_under_prev_i_1_n_0),
+ .Q(rsta_tx_under_prev),
+ .R(\q_int_reg[0]_1 ));
+ LUT4 #(
+ .INIT(16'h0151))
+ scl_cout_reg_i_1
+ (.I0(Ro_prev),
+ .I1(scl_state[2]),
+ .I2(scl_state[1]),
+ .I3(scl_state[3]),
+ .O(scl_cout_reg0));
+ FDSE scl_cout_reg_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_cout_reg0),
+ .Q(scl_cout_reg),
+ .S(\q_int_reg[0]_1 ));
+ FDRE scl_f_edg_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_falling_edge),
+ .Q(scl_f_edg_d1),
+ .R(\q_int_reg[0]_1 ));
+ FDRE scl_f_edg_d2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_f_edg_d1),
+ .Q(scl_f_edg_d2),
+ .R(\q_int_reg[0]_1 ));
+ FDRE scl_f_edg_d3_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_f_edg_d2),
+ .Q(scl_f_edg_d3),
+ .R(\q_int_reg[0]_1 ));
+ LUT2 #(
+ .INIT(4'h2))
+ scl_falling_edge_i_1
+ (.I0(scl_rin_d1),
+ .I1(scndry_out),
+ .O(scl_falling_edge0));
+ FDRE scl_falling_edge_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_falling_edge0),
+ .Q(scl_falling_edge),
+ .R(\q_int_reg[0]_1 ));
+ FDRE scl_rin_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scndry_out),
+ .Q(scl_rin_d1),
+ .R(1'b0));
+ FDRE scl_rising_edge_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(scl_rising_edge0),
+ .Q(scl_rising_edge),
+ .R(\q_int_reg[0]_1 ));
+ LUT4 #(
+ .INIT(16'h0004))
+ scl_t_INST_0
+ (.I0(sda_setup),
+ .I1(scl_cout_reg),
+ .I2(rsta_tx_under_prev),
+ .I3(Ro_prev),
+ .O(scl_t));
+ LUT4 #(
+ .INIT(16'hFE02))
+ sda_cout_reg_i_1
+ (.I0(sda_cout_reg_i_2_n_0),
+ .I1(scl_state[3]),
+ .I2(sda_cout_reg_i_3_n_0),
+ .I3(sda_cout_reg),
+ .O(sda_cout_reg_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000EA2A00000F0F))
+ sda_cout_reg_i_2
+ (.I0(sda_cout_reg_i_4_n_0),
+ .I1(scl_state[0]),
+ .I2(scl_state[1]),
+ .I3(\timing_param_tsusto_i_reg[9] ),
+ .I4(scl_state[3]),
+ .I5(scl_state[2]),
+ .O(sda_cout_reg_i_2_n_0));
+ LUT6 #(
+ .INIT(64'hAAAAA2AA66666666))
+ sda_cout_reg_i_3
+ (.I0(scl_state[0]),
+ .I1(scl_state[2]),
+ .I2(sda_cout_reg_reg_0),
+ .I3(\timing_param_tsusto_i_reg[9] ),
+ .I4(arb_lost),
+ .I5(scl_state[1]),
+ .O(sda_cout_reg_i_3_n_0));
+ LUT5 #(
+ .INIT(32'h1F1F1F00))
+ sda_cout_reg_i_4
+ (.I0(sm_stop_reg_n_0),
+ .I1(gen_stop),
+ .I2(txer_edge_i_2_n_0),
+ .I3(Q[3]),
+ .I4(\LEVEL_1_GEN.master_sda_reg_n_0 ),
+ .O(sda_cout_reg_i_4_n_0));
+ FDSE sda_cout_reg_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sda_cout_reg_i_1_n_0),
+ .Q(sda_cout_reg),
+ .S(\q_int_reg[0]_1 ));
+ FDRE sda_rin_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\data_int_reg[0] ),
+ .Q(sda_rin_d1),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ sda_sample_i_1
+ (.I0(\data_int_reg[0] ),
+ .I1(scl_rising_edge),
+ .I2(sda_sample),
+ .O(sda_sample_i_1_n_0));
+ FDRE sda_sample_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sda_sample_i_1_n_0),
+ .Q(sda_sample),
+ .R(\q_int_reg[0]_1 ));
+ CARRY4 \sda_setup0_inferred__0/i__carry
+ (.CI(1'b0),
+ .CO({\sda_setup0_inferred__0/i__carry_n_0 ,\sda_setup0_inferred__0/i__carry_n_1 ,\sda_setup0_inferred__0/i__carry_n_2 ,\sda_setup0_inferred__0/i__carry_n_3 }),
+ .CYINIT(1'b1),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(\NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED [3:0]),
+ .S(sda_setup_reg_0));
+ LUT5 #(
+ .INIT(32'h55FD00FC))
+ sda_setup_i_1
+ (.I0(\sda_setup0_inferred__0/i__carry_n_0 ),
+ .I1(Tx_under_prev),
+ .I2(SETUP_CNT_n_0),
+ .I3(scndry_out),
+ .I4(sda_setup),
+ .O(sda_setup_i_1_n_0));
+ FDRE sda_setup_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sda_setup_i_1_n_0),
+ .Q(sda_setup),
+ .R(\q_int_reg[0]_1 ));
+ LUT5 #(
+ .INIT(32'h0000EFE0))
+ sda_t_INST_0
+ (.I0(arb_lost),
+ .I1(sda_cout_reg),
+ .I2(master_slave),
+ .I3(slave_sda_reg_n_0),
+ .I4(stop_scl_reg),
+ .O(sda_t));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF08000000))
+ shift_reg_en_i_1
+ (.I0(master_slave),
+ .I1(scl_rising_edge),
+ .I2(state__0[1]),
+ .I3(state__0[2]),
+ .I4(state__0[0]),
+ .I5(shift_reg_en_i_2_n_0),
+ .O(shift_reg_en0));
+ LUT6 #(
+ .INIT(64'h0000045000000400))
+ shift_reg_en_i_2
+ (.I0(detect_start),
+ .I1(scl_rising_edge),
+ .I2(state__0[1]),
+ .I3(state__0[2]),
+ .I4(state__0[0]),
+ .I5(scl_f_edg_d2),
+ .O(shift_reg_en_i_2_n_0));
+ FDRE shift_reg_en_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(shift_reg_en0),
+ .Q(shift_reg_en),
+ .R(\q_int_reg[0]_1 ));
+ FDRE shift_reg_ld_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(shift_reg_ld),
+ .Q(shift_reg_ld_d1),
+ .R(\q_int_reg[0]_1 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT5 #(
+ .INIT(32'h00320002))
+ shift_reg_ld_i_2
+ (.I0(master_slave),
+ .I1(state__0[0]),
+ .I2(state__0[2]),
+ .I3(state__0[1]),
+ .I4(detect_start),
+ .O(shift_reg_ld_i_2_n_0));
+ FDRE shift_reg_ld_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(shift_reg_ld0),
+ .Q(shift_reg_ld),
+ .R(\q_int_reg[0]_1 ));
+ FDSE slave_sda_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I2CDATA_REG_n_0),
+ .Q(slave_sda_reg_n_0),
+ .S(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'h00000000BA8A0000))
+ sm_stop_i_1
+ (.I0(sm_stop_reg_n_0),
+ .I1(sm_stop_i_2_n_0),
+ .I2(sm_stop_i_3_n_0),
+ .I3(master_slave),
+ .I4(Q[0]),
+ .I5(detect_stop_reg_n_0),
+ .O(sm_stop_i_1_n_0));
+ LUT6 #(
+ .INIT(64'hFFFF45FFFFFFFFFF))
+ sm_stop_i_2
+ (.I0(scl_f_edg_d2),
+ .I1(Ro_prev),
+ .I2(ro_prev_d1),
+ .I3(sda_sample),
+ .I4(arb_lost),
+ .I5(master_slave),
+ .O(sm_stop_i_2_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT3 #(
+ .INIT(8'h24))
+ sm_stop_i_3
+ (.I0(state__0[2]),
+ .I1(state__0[0]),
+ .I2(state__0[1]),
+ .O(sm_stop_i_3_n_0));
+ FDRE sm_stop_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sm_stop_i_1_n_0),
+ .Q(sm_stop_reg_n_0),
+ .R(1'b0));
+ FDRE srw_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I2CHEADER_REG_n_7),
+ .Q(srw_i_reg_0[1]),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'hAABABBBAAA8A888A))
+ stop_scl_reg_i_1
+ (.I0(stop_scl_reg_i_2_n_0),
+ .I1(stop_scl_reg_i_3_n_0),
+ .I2(scl_state[3]),
+ .I3(scl_state[0]),
+ .I4(stop_scl_reg_i_4_n_0),
+ .I5(stop_scl_reg),
+ .O(stop_scl_reg_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT5 #(
+ .INIT(32'h00080800))
+ stop_scl_reg_i_2
+ (.I0(stop_scl_reg_i_5_n_0),
+ .I1(scl_state[2]),
+ .I2(scl_state[3]),
+ .I3(scl_state[0]),
+ .I4(scl_state[1]),
+ .O(stop_scl_reg_i_2_n_0));
+ LUT6 #(
+ .INIT(64'h0000000055557555))
+ stop_scl_reg_i_3
+ (.I0(scl_state[1]),
+ .I1(arb_lost),
+ .I2(\timing_param_tsusto_i_reg[9] ),
+ .I3(stop_scl_reg),
+ .I4(Q[3]),
+ .I5(stop_scl_reg_i_6_n_0),
+ .O(stop_scl_reg_i_3_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'h1))
+ stop_scl_reg_i_4
+ (.I0(scl_state[1]),
+ .I1(scl_state[2]),
+ .O(stop_scl_reg_i_4_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT5 #(
+ .INIT(32'hB5B5B500))
+ stop_scl_reg_i_5
+ (.I0(state__0[0]),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .I3(gen_stop),
+ .I4(sm_stop_reg_n_0),
+ .O(stop_scl_reg_i_5_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT3 #(
+ .INIT(8'hBA))
+ stop_scl_reg_i_6
+ (.I0(scl_state[3]),
+ .I1(scl_state[2]),
+ .I2(scl_state[1]),
+ .O(stop_scl_reg_i_6_n_0));
+ FDRE stop_scl_reg_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(stop_scl_reg_i_1_n_0),
+ .Q(stop_scl_reg),
+ .R(\q_int_reg[0]_1 ));
+ FDRE tx_under_prev_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Tx_under_prev),
+ .Q(tx_under_prev_d1),
+ .R(\q_int_reg[0]_1 ));
+ LUT5 #(
+ .INIT(32'hEEEAAAAA))
+ tx_under_prev_i_i_1
+ (.I0(tx_under_prev_i0),
+ .I1(sr_i),
+ .I2(state__0[1]),
+ .I3(state__0[0]),
+ .I4(Tx_under_prev),
+ .O(tx_under_prev_i_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0800000000000800))
+ tx_under_prev_i_i_2
+ (.I0(sm_stop_i_3_n_0),
+ .I1(scl_falling_edge),
+ .I2(gen_stop),
+ .I3(sr_i),
+ .I4(Aas),
+ .I5(srw_i_reg_0[1]),
+ .O(tx_under_prev_i0));
+ FDRE tx_under_prev_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(tx_under_prev_i_i_1_n_0),
+ .Q(Tx_under_prev),
+ .R(\q_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'hF5C500C000000000))
+ txer_edge_i_1
+ (.I0(scl_f_edg_d2),
+ .I1(sda_sample),
+ .I2(scl_falling_edge),
+ .I3(txer_edge_i_2_n_0),
+ .I4(D[2]),
+ .I5(Q[0]),
+ .O(txer_edge_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT3 #(
+ .INIT(8'hA7))
+ txer_edge_i_2
+ (.I0(state__0[2]),
+ .I1(state__0[1]),
+ .I2(state__0[0]),
+ .O(txer_edge_i_2_n_0));
+ FDRE txer_edge_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(txer_edge_i_1_n_0),
+ .Q(D[2]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'hFBFFBFBF08008080))
+ txer_i_i_1
+ (.I0(sda_sample),
+ .I1(scl_falling_edge),
+ .I2(state__0[0]),
+ .I3(state__0[1]),
+ .I4(state__0[2]),
+ .I5(txer_i_reg_n_0),
+ .O(txer_i_i_1_n_0));
+ FDRE txer_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(txer_i_i_1_n_0),
+ .Q(txer_i_reg_n_0),
+ .R(\q_int_reg[0]_1 ));
+endmodule
+
+module TopLevel_axi_iic_0_0_interrupt_control
+ (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
+ p_1_in17_in,
+ p_1_in14_in,
+ p_1_in11_in,
+ p_1_in8_in,
+ p_1_in5_in,
+ p_1_in2_in,
+ p_1_in,
+ ipif_glbl_irpt_enable_reg,
+ iic2intc_irpt,
+ Q,
+ SR,
+ irpt_wrack,
+ s_axi_aclk,
+ ipif_glbl_irpt_enable_reg_reg_0,
+ Bus_RNW_reg,
+ p_27_in,
+ IIC2Bus_IntrEvent,
+ s_axi_wdata,
+ E);
+ output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
+ output p_1_in17_in;
+ output p_1_in14_in;
+ output p_1_in11_in;
+ output p_1_in8_in;
+ output p_1_in5_in;
+ output p_1_in2_in;
+ output p_1_in;
+ output ipif_glbl_irpt_enable_reg;
+ output iic2intc_irpt;
+ output [7:0]Q;
+ input [0:0]SR;
+ input irpt_wrack;
+ input s_axi_aclk;
+ input ipif_glbl_irpt_enable_reg_reg_0;
+ input Bus_RNW_reg;
+ input p_27_in;
+ input [0:7]IIC2Bus_IntrEvent;
+ input [7:0]s_axi_wdata;
+ input [0:0]E;
+
+ wire Bus_RNW_reg;
+ wire [0:0]E;
+ wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ;
+ wire \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0 ;
+ wire [0:7]IIC2Bus_IntrEvent;
+ wire [7:0]Q;
+ wire [0:0]SR;
+ wire iic2intc_irpt;
+ wire iic2intc_irpt_INST_0_i_1_n_0;
+ wire iic2intc_irpt_INST_0_i_2_n_0;
+ wire iic2intc_irpt_INST_0_i_3_n_0;
+ wire iic2intc_irpt_INST_0_i_4_n_0;
+ wire ipif_glbl_irpt_enable_reg;
+ wire ipif_glbl_irpt_enable_reg_reg_0;
+ wire irpt_wrack;
+ wire irpt_wrack_d1;
+ wire p_1_in;
+ wire p_1_in11_in;
+ wire p_1_in14_in;
+ wire p_1_in17_in;
+ wire p_1_in2_in;
+ wire p_1_in5_in;
+ wire p_1_in8_in;
+ wire p_27_in;
+ wire s_axi_aclk;
+ wire [7:0]s_axi_wdata;
+
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[0]),
+ .I4(s_axi_wdata[0]),
+ .I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+ .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
+ .Q(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[1]),
+ .I4(s_axi_wdata[1]),
+ .I5(p_1_in17_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ),
+ .Q(p_1_in17_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[2]),
+ .I4(s_axi_wdata[2]),
+ .I5(p_1_in14_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ),
+ .Q(p_1_in14_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[3]),
+ .I4(s_axi_wdata[3]),
+ .I5(p_1_in11_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0 ),
+ .Q(p_1_in11_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[4]),
+ .I4(s_axi_wdata[4]),
+ .I5(p_1_in8_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ),
+ .Q(p_1_in8_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[5]),
+ .I4(s_axi_wdata[5]),
+ .I5(p_1_in5_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0 ),
+ .Q(p_1_in5_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[6]),
+ .I4(s_axi_wdata[6]),
+ .I5(p_1_in2_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ),
+ .Q(p_1_in2_in),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'hFFEFFFFFFF10FF00))
+ \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1
+ (.I0(irpt_wrack_d1),
+ .I1(Bus_RNW_reg),
+ .I2(p_27_in),
+ .I3(IIC2Bus_IntrEvent[7]),
+ .I4(s_axi_wdata[7]),
+ .I5(p_1_in),
+ .O(\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0 ));
+ FDRE \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0 ),
+ .Q(p_1_in),
+ .R(SR));
+ LUT5 #(
+ .INIT(32'hAAAAA8AA))
+ iic2intc_irpt_INST_0
+ (.I0(ipif_glbl_irpt_enable_reg),
+ .I1(iic2intc_irpt_INST_0_i_1_n_0),
+ .I2(iic2intc_irpt_INST_0_i_2_n_0),
+ .I3(iic2intc_irpt_INST_0_i_3_n_0),
+ .I4(iic2intc_irpt_INST_0_i_4_n_0),
+ .O(iic2intc_irpt));
+ LUT4 #(
+ .INIT(16'hF888))
+ iic2intc_irpt_INST_0_i_1
+ (.I0(Q[0]),
+ .I1(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+ .I2(Q[7]),
+ .I3(p_1_in),
+ .O(iic2intc_irpt_INST_0_i_1_n_0));
+ LUT4 #(
+ .INIT(16'hF888))
+ iic2intc_irpt_INST_0_i_2
+ (.I0(Q[4]),
+ .I1(p_1_in8_in),
+ .I2(Q[1]),
+ .I3(p_1_in17_in),
+ .O(iic2intc_irpt_INST_0_i_2_n_0));
+ LUT4 #(
+ .INIT(16'h0777))
+ iic2intc_irpt_INST_0_i_3
+ (.I0(Q[5]),
+ .I1(p_1_in5_in),
+ .I2(Q[3]),
+ .I3(p_1_in11_in),
+ .O(iic2intc_irpt_INST_0_i_3_n_0));
+ LUT4 #(
+ .INIT(16'hF888))
+ iic2intc_irpt_INST_0_i_4
+ (.I0(Q[6]),
+ .I1(p_1_in2_in),
+ .I2(Q[2]),
+ .I3(p_1_in14_in),
+ .O(iic2intc_irpt_INST_0_i_4_n_0));
+ FDRE \ip_irpt_enable_reg_reg[0]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[0]),
+ .Q(Q[0]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[1]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[1]),
+ .Q(Q[1]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[2]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[2]),
+ .Q(Q[2]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[3]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[3]),
+ .Q(Q[3]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[4]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[4]),
+ .Q(Q[4]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[5]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[5]),
+ .Q(Q[5]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[6]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[6]),
+ .Q(Q[6]),
+ .R(SR));
+ FDRE \ip_irpt_enable_reg_reg[7]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(s_axi_wdata[7]),
+ .Q(Q[7]),
+ .R(SR));
+ FDRE ipif_glbl_irpt_enable_reg_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(ipif_glbl_irpt_enable_reg_reg_0),
+ .Q(ipif_glbl_irpt_enable_reg),
+ .R(SR));
+ FDRE irpt_wrack_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(irpt_wrack),
+ .Q(irpt_wrack_d1),
+ .R(SR));
+endmodule
+
+module TopLevel_axi_iic_0_0_reg_interface
+ (IIC2Bus_IntrEvent,
+ Q,
+ Tx_fifo_wr,
+ Tx_fifo_rd,
+ Tx_fifo_rst,
+ new_rcv_dta_d1,
+ Rc_fifo_wr,
+ Rc_fifo_rd,
+ \sr_i_reg[0]_0 ,
+ gpo,
+ Msms_set,
+ D,
+ S,
+ \timing_param_thigh_i_reg[7]_0 ,
+ \timing_param_tsusto_i_reg[9]_0 ,
+ \timing_param_tsusto_i_reg[7]_0 ,
+ \timing_param_tsusta_i_reg[9]_0 ,
+ \timing_param_tsusta_i_reg[7]_0 ,
+ \timing_param_tbuf_i_reg[9]_0 ,
+ \timing_param_tbuf_i_reg[7]_0 ,
+ \timing_param_thddat_i_reg[9]_0 ,
+ \timing_param_thdsta_i_reg[9]_0 ,
+ \timing_param_thdsta_i_reg[7]_0 ,
+ \timing_param_tlow_i_reg[9]_0 ,
+ \timing_param_tlow_i_reg[7]_0 ,
+ \timing_param_tsudat_i_reg[9]_0 ,
+ \timing_param_tsudat_i_reg[3]_0 ,
+ D_0,
+ Tx_fifo_wr_d_reg,
+ \cr_i_reg[7]_0 ,
+ \cr_i_reg[3]_0 ,
+ stop_scl_reg_reg,
+ \cr_i_reg[2]_0 ,
+ firstDynStartSeen_reg,
+ p_3_in,
+ \FIFO_GEN_DTR.Tx_fifo_rd_reg_0 ,
+ \bus2ip_addr_i_reg[2] ,
+ \timing_param_tsudat_i_reg[4]_0 ,
+ \timing_param_tsudat_i_reg[5]_0 ,
+ \timing_param_tsudat_i_reg[6]_0 ,
+ \timing_param_tsudat_i_reg[7]_0 ,
+ \sr_i_reg[4]_0 ,
+ \bus2ip_addr_i_reg[6] ,
+ \adr_i_reg[0]_0 ,
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 ,
+ \sr_i_reg[5]_0 ,
+ \bus2ip_addr_i_reg[6]_0 ,
+ \IIC2Bus_IntrEvent_reg[5]_0 ,
+ \adr_i_reg[6]_0 ,
+ \GPO_GEN.gpo_i_reg[31]_0 ,
+ \cr_i_reg[2]_1 ,
+ \FIFO_GEN_DTR.Tx_fifo_wr_reg_0 ,
+ D_1,
+ \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0 ,
+ \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0 ,
+ Bus2IIC_Reset,
+ p_0_in,
+ s_axi_aclk,
+ Bus2IIC_WrCE,
+ Rdy_new_xmt,
+ New_rcv_dta,
+ p_6_out,
+ Bus2IIC_RdCE,
+ \sr_i_reg[0]_1 ,
+ Aas,
+ \GPO_GEN.gpo_i_reg[31]_1 ,
+ \RD_FIFO_CNTRL.ro_prev_i_reg_0 ,
+ \next_scl_state1_inferred__1/i__carry ,
+ \sda_setup0_inferred__0/i__carry ,
+ Tx_fifo_rd_d,
+ rdCntrFrmTxFifo,
+ Data_Exists_DFF,
+ Data_Exists_DFF_0,
+ Tx_fifo_wr_d,
+ \LEVEL_1_GEN.master_sda_reg ,
+ earlyAckDataState,
+ CO,
+ stop_scl_reg,
+ \q_int_reg[1] ,
+ \q_int_reg[1]_0 ,
+ \q_int_reg[1]_1 ,
+ firstDynStartSeen,
+ firstDynStartSeen_reg_0,
+ Tx_data_exists,
+ dynamic_MSMS,
+ \s_axi_rdata_i[0]_i_7 ,
+ \s_axi_rdata_i_reg[8] ,
+ Rc_addr,
+ Tx_fifo_data,
+ Rc_fifo_wr_d,
+ Rc_fifo_rd_d,
+ Data_Exists_DFF_1,
+ Rc_Data_Exists,
+ \sr_i_reg[1]_0 ,
+ s_axi_wdata,
+ \cr_i_reg[2]_2 ,
+ \IIC2Bus_IntrEvent_reg[0]_0 );
+ output [0:7]IIC2Bus_IntrEvent;
+ output [6:0]Q;
+ output Tx_fifo_wr;
+ output Tx_fifo_rd;
+ output Tx_fifo_rst;
+ output new_rcv_dta_d1;
+ output Rc_fifo_wr;
+ output Rc_fifo_rd;
+ output [0:0]\sr_i_reg[0]_0 ;
+ output [0:0]gpo;
+ output Msms_set;
+ output [0:0]D;
+ output [3:0]S;
+ output [7:0]\timing_param_thigh_i_reg[7]_0 ;
+ output [3:0]\timing_param_tsusto_i_reg[9]_0 ;
+ output [7:0]\timing_param_tsusto_i_reg[7]_0 ;
+ output [3:0]\timing_param_tsusta_i_reg[9]_0 ;
+ output [5:0]\timing_param_tsusta_i_reg[7]_0 ;
+ output [3:0]\timing_param_tbuf_i_reg[9]_0 ;
+ output [5:0]\timing_param_tbuf_i_reg[7]_0 ;
+ output [3:0]\timing_param_thddat_i_reg[9]_0 ;
+ output [3:0]\timing_param_thdsta_i_reg[9]_0 ;
+ output [4:0]\timing_param_thdsta_i_reg[7]_0 ;
+ output [3:0]\timing_param_tlow_i_reg[9]_0 ;
+ output [4:0]\timing_param_tlow_i_reg[7]_0 ;
+ output [3:0]\timing_param_tsudat_i_reg[9]_0 ;
+ output [3:0]\timing_param_tsudat_i_reg[3]_0 ;
+ output D_0;
+ output Tx_fifo_wr_d_reg;
+ output \cr_i_reg[7]_0 ;
+ output \cr_i_reg[3]_0 ;
+ output stop_scl_reg_reg;
+ output \cr_i_reg[2]_0 ;
+ output firstDynStartSeen_reg;
+ output p_3_in;
+ output \FIFO_GEN_DTR.Tx_fifo_rd_reg_0 ;
+ output [1:0]\bus2ip_addr_i_reg[2] ;
+ output \timing_param_tsudat_i_reg[4]_0 ;
+ output \timing_param_tsudat_i_reg[5]_0 ;
+ output \timing_param_tsudat_i_reg[6]_0 ;
+ output \timing_param_tsudat_i_reg[7]_0 ;
+ output \sr_i_reg[4]_0 ;
+ output \bus2ip_addr_i_reg[6] ;
+ output [6:0]\adr_i_reg[0]_0 ;
+ output [3:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 ;
+ output \sr_i_reg[5]_0 ;
+ output \bus2ip_addr_i_reg[6]_0 ;
+ output \IIC2Bus_IntrEvent_reg[5]_0 ;
+ output \adr_i_reg[6]_0 ;
+ output \GPO_GEN.gpo_i_reg[31]_0 ;
+ output \cr_i_reg[2]_1 ;
+ output \FIFO_GEN_DTR.Tx_fifo_wr_reg_0 ;
+ output D_1;
+ output \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0 ;
+ output \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0 ;
+ input Bus2IIC_Reset;
+ input p_0_in;
+ input s_axi_aclk;
+ input [11:0]Bus2IIC_WrCE;
+ input Rdy_new_xmt;
+ input New_rcv_dta;
+ input p_6_out;
+ input [0:0]Bus2IIC_RdCE;
+ input \sr_i_reg[0]_1 ;
+ input Aas;
+ input \GPO_GEN.gpo_i_reg[31]_1 ;
+ input \RD_FIFO_CNTRL.ro_prev_i_reg_0 ;
+ input [9:0]\next_scl_state1_inferred__1/i__carry ;
+ input [9:0]\sda_setup0_inferred__0/i__carry ;
+ input Tx_fifo_rd_d;
+ input rdCntrFrmTxFifo;
+ input Data_Exists_DFF;
+ input Data_Exists_DFF_0;
+ input Tx_fifo_wr_d;
+ input \LEVEL_1_GEN.master_sda_reg ;
+ input earlyAckDataState;
+ input [0:0]CO;
+ input stop_scl_reg;
+ input [0:0]\q_int_reg[1] ;
+ input [0:0]\q_int_reg[1]_0 ;
+ input \q_int_reg[1]_1 ;
+ input firstDynStartSeen;
+ input firstDynStartSeen_reg_0;
+ input Tx_data_exists;
+ input [0:0]dynamic_MSMS;
+ input [4:0]\s_axi_rdata_i[0]_i_7 ;
+ input \s_axi_rdata_i_reg[8] ;
+ input [1:0]Rc_addr;
+ input [1:0]Tx_fifo_data;
+ input Rc_fifo_wr_d;
+ input Rc_fifo_rd_d;
+ input Data_Exists_DFF_1;
+ input Rc_Data_Exists;
+ input [5:0]\sr_i_reg[1]_0 ;
+ input [9:0]s_axi_wdata;
+ input [2:0]\cr_i_reg[2]_2 ;
+ input [4:0]\IIC2Bus_IntrEvent_reg[0]_0 ;
+
+ wire Aas;
+ wire [0:0]Bus2IIC_RdCE;
+ wire Bus2IIC_Reset;
+ wire [11:0]Bus2IIC_WrCE;
+ wire [0:0]CO;
+ wire [6:6]Cr;
+ wire [0:0]D;
+ wire D_0;
+ wire D_1;
+ wire Data_Exists_DFF;
+ wire Data_Exists_DFF_0;
+ wire Data_Exists_DFF_1;
+ wire \FIFO_GEN_DTR.Tx_fifo_rd_reg_0 ;
+ wire \FIFO_GEN_DTR.Tx_fifo_wr_reg_0 ;
+ wire \GPO_GEN.gpo_i_reg[31]_0 ;
+ wire \GPO_GEN.gpo_i_reg[31]_1 ;
+ wire [0:7]IIC2Bus_IntrEvent;
+ wire [4:0]\IIC2Bus_IntrEvent_reg[0]_0 ;
+ wire \IIC2Bus_IntrEvent_reg[5]_0 ;
+ wire \LEVEL_1_GEN.master_sda_reg ;
+ wire Msms_set;
+ wire New_rcv_dta;
+ wire [6:0]Q;
+ wire \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0 ;
+ wire \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0 ;
+ wire [3:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 ;
+ wire \RD_FIFO_CNTRL.ro_prev_i_reg_0 ;
+ wire Rc_Data_Exists;
+ wire [1:0]Rc_addr;
+ wire Rc_fifo_rd;
+ wire Rc_fifo_rd_d;
+ wire Rc_fifo_wr;
+ wire Rc_fifo_wr_d;
+ wire Rdy_new_xmt;
+ wire [3:0]S;
+ wire [9:2]Timing_param_tbuf;
+ wire [9:0]Timing_param_thddat;
+ wire [9:1]Timing_param_thdsta;
+ wire [9:8]Timing_param_thigh;
+ wire [9:1]Timing_param_tlow;
+ wire [9:4]Timing_param_tsudat;
+ wire [9:2]Timing_param_tsusta;
+ wire [9:8]Timing_param_tsusto;
+ wire Tx_data_exists;
+ wire [1:0]Tx_fifo_data;
+ wire Tx_fifo_rd;
+ wire Tx_fifo_rd_d;
+ wire Tx_fifo_rst;
+ wire Tx_fifo_wr;
+ wire Tx_fifo_wr_d;
+ wire Tx_fifo_wr_d_reg;
+ wire [6:0]\adr_i_reg[0]_0 ;
+ wire \adr_i_reg[6]_0 ;
+ wire [1:0]\bus2ip_addr_i_reg[2] ;
+ wire \bus2ip_addr_i_reg[6] ;
+ wire \bus2ip_addr_i_reg[6]_0 ;
+ wire \cr_i_reg[2]_0 ;
+ wire \cr_i_reg[2]_1 ;
+ wire [2:0]\cr_i_reg[2]_2 ;
+ wire \cr_i_reg[3]_0 ;
+ wire \cr_i_reg[7]_0 ;
+ wire [0:0]dynamic_MSMS;
+ wire earlyAckDataState;
+ wire firstDynStartSeen;
+ wire firstDynStartSeen_reg;
+ wire firstDynStartSeen_reg_0;
+ wire [0:0]gpo;
+ wire msms_d1;
+ wire msms_set_i_i_1_n_0;
+ wire new_rcv_dta_d1;
+ wire [9:0]\next_scl_state1_inferred__1/i__carry ;
+ wire p_0_in;
+ wire p_3_in;
+ wire p_6_out;
+ wire [0:0]\q_int_reg[1] ;
+ wire [0:0]\q_int_reg[1]_0 ;
+ wire \q_int_reg[1]_1 ;
+ wire rdCntrFrmTxFifo;
+ wire s_axi_aclk;
+ wire [4:0]\s_axi_rdata_i[0]_i_7 ;
+ wire \s_axi_rdata_i[1]_i_9_n_0 ;
+ wire \s_axi_rdata_i[2]_i_7_n_0 ;
+ wire \s_axi_rdata_i[2]_i_8_n_0 ;
+ wire \s_axi_rdata_i[2]_i_9_n_0 ;
+ wire \s_axi_rdata_i[3]_i_7_n_0 ;
+ wire \s_axi_rdata_i[3]_i_8_n_0 ;
+ wire \s_axi_rdata_i[3]_i_9_n_0 ;
+ wire \s_axi_rdata_i[8]_i_2_n_0 ;
+ wire \s_axi_rdata_i[8]_i_3_n_0 ;
+ wire \s_axi_rdata_i[9]_i_2_n_0 ;
+ wire \s_axi_rdata_i[9]_i_3_n_0 ;
+ wire \s_axi_rdata_i_reg[8] ;
+ wire [9:0]s_axi_wdata;
+ wire [9:0]\sda_setup0_inferred__0/i__carry ;
+ wire [1:7]sr_i;
+ wire [0:0]\sr_i_reg[0]_0 ;
+ wire \sr_i_reg[0]_1 ;
+ wire [5:0]\sr_i_reg[1]_0 ;
+ wire \sr_i_reg[4]_0 ;
+ wire \sr_i_reg[5]_0 ;
+ wire stop_scl_reg;
+ wire stop_scl_reg_reg;
+ wire [5:0]\timing_param_tbuf_i_reg[7]_0 ;
+ wire [3:0]\timing_param_tbuf_i_reg[9]_0 ;
+ wire [3:0]\timing_param_thddat_i_reg[9]_0 ;
+ wire [4:0]\timing_param_thdsta_i_reg[7]_0 ;
+ wire [3:0]\timing_param_thdsta_i_reg[9]_0 ;
+ wire [7:0]\timing_param_thigh_i_reg[7]_0 ;
+ wire [4:0]\timing_param_tlow_i_reg[7]_0 ;
+ wire [3:0]\timing_param_tlow_i_reg[9]_0 ;
+ wire [3:0]\timing_param_tsudat_i_reg[3]_0 ;
+ wire \timing_param_tsudat_i_reg[4]_0 ;
+ wire \timing_param_tsudat_i_reg[5]_0 ;
+ wire \timing_param_tsudat_i_reg[6]_0 ;
+ wire \timing_param_tsudat_i_reg[7]_0 ;
+ wire [3:0]\timing_param_tsudat_i_reg[9]_0 ;
+ wire [5:0]\timing_param_tsusta_i_reg[7]_0 ;
+ wire [3:0]\timing_param_tsusta_i_reg[9]_0 ;
+ wire [7:0]\timing_param_tsusto_i_reg[7]_0 ;
+ wire [3:0]\timing_param_tsusto_i_reg[9]_0 ;
+
+ (* SOFT_HLUTNM = "soft_lutpair34" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \Addr_Counters[0].MUXCY_L_I_i_4
+ (.I0(Tx_fifo_wr),
+ .I1(Tx_fifo_wr_d),
+ .O(\FIFO_GEN_DTR.Tx_fifo_wr_reg_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \Addr_Counters[0].MUXCY_L_I_i_4__0
+ (.I0(Rc_fifo_rd),
+ .I1(Rc_fifo_rd_d),
+ .O(\RD_FIFO_CNTRL.Rc_fifo_rd_reg_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \Addr_Counters[0].MUXCY_L_I_i_5
+ (.I0(Rc_fifo_wr),
+ .I1(Rc_fifo_wr_d),
+ .O(\RD_FIFO_CNTRL.Rc_fifo_wr_reg_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFAAFB0000AAAA))
+ Data_Exists_DFF_i_1
+ (.I0(Tx_fifo_wr_d_reg),
+ .I1(Tx_fifo_rd),
+ .I2(Tx_fifo_rd_d),
+ .I3(rdCntrFrmTxFifo),
+ .I4(Data_Exists_DFF),
+ .I5(Data_Exists_DFF_0),
+ .O(D_0));
+ LUT6 #(
+ .INIT(64'hFFFFF2FF00002222))
+ Data_Exists_DFF_i_1__1
+ (.I0(Rc_fifo_wr),
+ .I1(Rc_fifo_wr_d),
+ .I2(Rc_fifo_rd_d),
+ .I3(Rc_fifo_rd),
+ .I4(Data_Exists_DFF_1),
+ .I5(Rc_Data_Exists),
+ .O(D_1));
+ (* SOFT_HLUTNM = "soft_lutpair34" *)
+ LUT4 #(
+ .INIT(16'hFFF4))
+ Data_Exists_DFF_i_2
+ (.I0(Tx_fifo_wr_d),
+ .I1(Tx_fifo_wr),
+ .I2(Bus2IIC_Reset),
+ .I3(Tx_fifo_rst),
+ .O(Tx_fifo_wr_d_reg));
+ FDRE \FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(p_0_in),
+ .Q(IIC2Bus_IntrEvent[7]),
+ .R(Bus2IIC_Reset));
+ FDRE \FIFO_GEN_DTR.Tx_fifo_rd_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Rdy_new_xmt),
+ .Q(Tx_fifo_rd),
+ .R(Bus2IIC_Reset));
+ FDSE \FIFO_GEN_DTR.Tx_fifo_rst_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Cr),
+ .Q(Tx_fifo_rst),
+ .S(Bus2IIC_Reset));
+ FDRE \FIFO_GEN_DTR.Tx_fifo_wr_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Bus2IIC_WrCE[10]),
+ .Q(Tx_fifo_wr),
+ .R(Bus2IIC_Reset));
+ LUT1 #(
+ .INIT(2'h1))
+ \FSM_sequential_scl_state[3]_i_1
+ (.I0(Q[0]),
+ .O(\cr_i_reg[7]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \FSM_sequential_scl_state[3]_i_4
+ (.I0(\q_int_reg[1]_0 ),
+ .I1(Q[4]),
+ .I2(\q_int_reg[1] ),
+ .I3(stop_scl_reg),
+ .I4(CO),
+ .O(\cr_i_reg[2]_0 ));
+ FDRE \GPO_GEN.gpo_i_reg[31]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\GPO_GEN.gpo_i_reg[31]_1 ),
+ .Q(gpo),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\IIC2Bus_IntrEvent_reg[0]_0 [4]),
+ .Q(IIC2Bus_IntrEvent[0]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\IIC2Bus_IntrEvent_reg[0]_0 [3]),
+ .Q(IIC2Bus_IntrEvent[1]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\IIC2Bus_IntrEvent_reg[0]_0 [2]),
+ .Q(IIC2Bus_IntrEvent[2]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(D),
+ .Q(IIC2Bus_IntrEvent[3]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[4]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\IIC2Bus_IntrEvent_reg[0]_0 [1]),
+ .Q(IIC2Bus_IntrEvent[4]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[5]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Aas),
+ .Q(IIC2Bus_IntrEvent[5]),
+ .R(Bus2IIC_Reset));
+ FDRE \IIC2Bus_IntrEvent_reg[6]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\IIC2Bus_IntrEvent_reg[0]_0 [0]),
+ .Q(IIC2Bus_IntrEvent[6]),
+ .R(Bus2IIC_Reset));
+ LUT3 #(
+ .INIT(8'hBA))
+ \LEVEL_1_GEN.master_sda_i_2
+ (.I0(Q[3]),
+ .I1(\LEVEL_1_GEN.master_sda_reg ),
+ .I2(earlyAckDataState),
+ .O(\cr_i_reg[3]_0 ));
+ FDRE \RD_FIFO_CNTRL.Rc_fifo_rd_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Bus2IIC_RdCE),
+ .Q(Rc_fifo_rd),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.Rc_fifo_wr_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(p_6_out),
+ .Q(Rc_fifo_wr),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[8]),
+ .D(s_axi_wdata[3]),
+ .Q(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [3]),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[8]),
+ .D(s_axi_wdata[2]),
+ .Q(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [2]),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[8]),
+ .D(s_axi_wdata[1]),
+ .Q(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[8]),
+ .D(s_axi_wdata[0]),
+ .Q(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [0]),
+ .R(Bus2IIC_Reset));
+ FDRE \RD_FIFO_CNTRL.ro_prev_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\RD_FIFO_CNTRL.ro_prev_i_reg_0 ),
+ .Q(D),
+ .R(1'b0));
+ FDRE \adr_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[7]),
+ .Q(\adr_i_reg[0]_0 [6]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[6]),
+ .Q(\adr_i_reg[0]_0 [5]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[5]),
+ .Q(\adr_i_reg[0]_0 [4]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[4]),
+ .Q(\adr_i_reg[0]_0 [3]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[3]),
+ .Q(\adr_i_reg[0]_0 [2]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[2]),
+ .Q(\adr_i_reg[0]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDRE \adr_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[9]),
+ .D(s_axi_wdata[1]),
+ .Q(\adr_i_reg[0]_0 [0]),
+ .R(Bus2IIC_Reset));
+ (* SOFT_HLUTNM = "soft_lutpair33" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ callingReadAccess_i_1
+ (.I0(Tx_fifo_rd),
+ .I1(Tx_fifo_rd_d),
+ .I2(Tx_data_exists),
+ .I3(dynamic_MSMS),
+ .O(p_3_in));
+ LUT2 #(
+ .INIT(4'h9))
+ clk_cnt_en1_carry_i_1
+ (.I0(Timing_param_thigh[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(S[3]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en1_carry_i_2
+ (.I0(Timing_param_thigh[8]),
+ .I1(\next_scl_state1_inferred__1/i__carry [8]),
+ .I2(\next_scl_state1_inferred__1/i__carry [6]),
+ .I3(\timing_param_thigh_i_reg[7]_0 [6]),
+ .I4(\next_scl_state1_inferred__1/i__carry [7]),
+ .I5(\timing_param_thigh_i_reg[7]_0 [7]),
+ .O(S[2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en1_carry_i_3
+ (.I0(\timing_param_thigh_i_reg[7]_0 [4]),
+ .I1(\next_scl_state1_inferred__1/i__carry [4]),
+ .I2(\next_scl_state1_inferred__1/i__carry [5]),
+ .I3(\timing_param_thigh_i_reg[7]_0 [5]),
+ .I4(\next_scl_state1_inferred__1/i__carry [3]),
+ .I5(\timing_param_thigh_i_reg[7]_0 [3]),
+ .O(S[1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en1_carry_i_4
+ (.I0(\timing_param_thigh_i_reg[7]_0 [2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [2]),
+ .I2(\next_scl_state1_inferred__1/i__carry [0]),
+ .I3(\timing_param_thigh_i_reg[7]_0 [0]),
+ .I4(\next_scl_state1_inferred__1/i__carry [1]),
+ .I5(\timing_param_thigh_i_reg[7]_0 [1]),
+ .O(S[0]));
+ LUT2 #(
+ .INIT(4'h9))
+ clk_cnt_en2_carry_i_1
+ (.I0(Timing_param_thddat[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_thddat_i_reg[9]_0 [3]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en2_carry_i_2
+ (.I0(Timing_param_thddat[8]),
+ .I1(\next_scl_state1_inferred__1/i__carry [8]),
+ .I2(\next_scl_state1_inferred__1/i__carry [6]),
+ .I3(Timing_param_thddat[6]),
+ .I4(\next_scl_state1_inferred__1/i__carry [7]),
+ .I5(Timing_param_thddat[7]),
+ .O(\timing_param_thddat_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en2_carry_i_3
+ (.I0(Timing_param_thddat[5]),
+ .I1(\next_scl_state1_inferred__1/i__carry [5]),
+ .I2(\next_scl_state1_inferred__1/i__carry [3]),
+ .I3(Timing_param_thddat[3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [4]),
+ .I5(Timing_param_thddat[4]),
+ .O(\timing_param_thddat_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ clk_cnt_en2_carry_i_4
+ (.I0(Timing_param_thddat[2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [2]),
+ .I2(\next_scl_state1_inferred__1/i__carry [1]),
+ .I3(Timing_param_thddat[1]),
+ .I4(\next_scl_state1_inferred__1/i__carry [0]),
+ .I5(Timing_param_thddat[0]),
+ .O(\timing_param_thddat_i_reg[9]_0 [0]));
+ (* SOFT_HLUTNM = "soft_lutpair33" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \cr_i[5]_i_4
+ (.I0(Tx_fifo_rd),
+ .I1(Tx_fifo_rd_d),
+ .O(\FIFO_GEN_DTR.Tx_fifo_rd_reg_0 ));
+ FDRE \cr_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[11]),
+ .D(s_axi_wdata[7]),
+ .Q(Q[6]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[11]),
+ .D(s_axi_wdata[6]),
+ .Q(Q[5]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\cr_i_reg[2]_2 [2]),
+ .Q(Q[4]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[11]),
+ .D(s_axi_wdata[4]),
+ .Q(Q[3]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\cr_i_reg[2]_2 [1]),
+ .Q(Q[2]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\cr_i_reg[2]_2 [0]),
+ .Q(Q[1]),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[11]),
+ .D(s_axi_wdata[1]),
+ .Q(Cr),
+ .R(Bus2IIC_Reset));
+ FDRE \cr_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[11]),
+ .D(s_axi_wdata[0]),
+ .Q(Q[0]),
+ .R(Bus2IIC_Reset));
+ LUT4 #(
+ .INIT(16'h00B0))
+ firstDynStartSeen_i_1
+ (.I0(firstDynStartSeen),
+ .I1(firstDynStartSeen_reg_0),
+ .I2(Q[1]),
+ .I3(Tx_fifo_rst),
+ .O(firstDynStartSeen_reg));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1
+ (.I0(Timing_param_tsusto[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_tsusto_i_reg[9]_0 [3]));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1__0
+ (.I0(Timing_param_tsusta[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_tsusta_i_reg[9]_0 [3]));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1__1
+ (.I0(Timing_param_tbuf[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_tbuf_i_reg[9]_0 [3]));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1__2
+ (.I0(Timing_param_thdsta[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_thdsta_i_reg[9]_0 [3]));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1__3
+ (.I0(Timing_param_tlow[9]),
+ .I1(\next_scl_state1_inferred__1/i__carry [9]),
+ .O(\timing_param_tlow_i_reg[9]_0 [3]));
+ LUT2 #(
+ .INIT(4'h9))
+ i__carry_i_1__4
+ (.I0(Timing_param_tsudat[9]),
+ .I1(\sda_setup0_inferred__0/i__carry [9]),
+ .O(\timing_param_tsudat_i_reg[9]_0 [3]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2
+ (.I0(Timing_param_tsusto[8]),
+ .I1(\next_scl_state1_inferred__1/i__carry [8]),
+ .I2(\next_scl_state1_inferred__1/i__carry [7]),
+ .I3(\timing_param_tsusto_i_reg[7]_0 [7]),
+ .I4(\next_scl_state1_inferred__1/i__carry [6]),
+ .I5(\timing_param_tsusto_i_reg[7]_0 [6]),
+ .O(\timing_param_tsusto_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2__0
+ (.I0(\timing_param_tsusta_i_reg[7]_0 [5]),
+ .I1(\next_scl_state1_inferred__1/i__carry [7]),
+ .I2(\next_scl_state1_inferred__1/i__carry [8]),
+ .I3(Timing_param_tsusta[8]),
+ .I4(\next_scl_state1_inferred__1/i__carry [6]),
+ .I5(\timing_param_tsusta_i_reg[7]_0 [4]),
+ .O(\timing_param_tsusta_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2__1
+ (.I0(\timing_param_tbuf_i_reg[7]_0 [5]),
+ .I1(\next_scl_state1_inferred__1/i__carry [7]),
+ .I2(\next_scl_state1_inferred__1/i__carry [8]),
+ .I3(Timing_param_tbuf[8]),
+ .I4(\next_scl_state1_inferred__1/i__carry [6]),
+ .I5(\timing_param_tbuf_i_reg[7]_0 [4]),
+ .O(\timing_param_tbuf_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2__2
+ (.I0(Timing_param_thdsta[8]),
+ .I1(\next_scl_state1_inferred__1/i__carry [8]),
+ .I2(\next_scl_state1_inferred__1/i__carry [6]),
+ .I3(\timing_param_thdsta_i_reg[7]_0 [3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [7]),
+ .I5(\timing_param_thdsta_i_reg[7]_0 [4]),
+ .O(\timing_param_thdsta_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2__3
+ (.I0(Timing_param_tlow[8]),
+ .I1(\next_scl_state1_inferred__1/i__carry [8]),
+ .I2(\next_scl_state1_inferred__1/i__carry [6]),
+ .I3(\timing_param_tlow_i_reg[7]_0 [3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [7]),
+ .I5(\timing_param_tlow_i_reg[7]_0 [4]),
+ .O(\timing_param_tlow_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_2__4
+ (.I0(Timing_param_tsudat[8]),
+ .I1(\sda_setup0_inferred__0/i__carry [8]),
+ .I2(\sda_setup0_inferred__0/i__carry [6]),
+ .I3(Timing_param_tsudat[6]),
+ .I4(\sda_setup0_inferred__0/i__carry [7]),
+ .I5(Timing_param_tsudat[7]),
+ .O(\timing_param_tsudat_i_reg[9]_0 [2]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3
+ (.I0(\timing_param_tsusto_i_reg[7]_0 [5]),
+ .I1(\next_scl_state1_inferred__1/i__carry [5]),
+ .I2(\next_scl_state1_inferred__1/i__carry [3]),
+ .I3(\timing_param_tsusto_i_reg[7]_0 [3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [4]),
+ .I5(\timing_param_tsusto_i_reg[7]_0 [4]),
+ .O(\timing_param_tsusto_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3__0
+ (.I0(\timing_param_tsusta_i_reg[7]_0 [2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [4]),
+ .I2(\next_scl_state1_inferred__1/i__carry [5]),
+ .I3(\timing_param_tsusta_i_reg[7]_0 [3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [3]),
+ .I5(Timing_param_tsusta[3]),
+ .O(\timing_param_tsusta_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3__1
+ (.I0(\timing_param_tbuf_i_reg[7]_0 [3]),
+ .I1(\next_scl_state1_inferred__1/i__carry [5]),
+ .I2(\next_scl_state1_inferred__1/i__carry [4]),
+ .I3(\timing_param_tbuf_i_reg[7]_0 [2]),
+ .I4(\next_scl_state1_inferred__1/i__carry [3]),
+ .I5(Timing_param_tbuf[3]),
+ .O(\timing_param_tbuf_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3__2
+ (.I0(\timing_param_thdsta_i_reg[7]_0 [2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [5]),
+ .I2(\next_scl_state1_inferred__1/i__carry [4]),
+ .I3(\timing_param_thdsta_i_reg[7]_0 [1]),
+ .I4(\next_scl_state1_inferred__1/i__carry [3]),
+ .I5(Timing_param_thdsta[3]),
+ .O(\timing_param_thdsta_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3__3
+ (.I0(\timing_param_tlow_i_reg[7]_0 [2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [5]),
+ .I2(\next_scl_state1_inferred__1/i__carry [3]),
+ .I3(Timing_param_tlow[3]),
+ .I4(\next_scl_state1_inferred__1/i__carry [4]),
+ .I5(\timing_param_tlow_i_reg[7]_0 [1]),
+ .O(\timing_param_tlow_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_3__4
+ (.I0(Timing_param_tsudat[5]),
+ .I1(\sda_setup0_inferred__0/i__carry [5]),
+ .I2(\sda_setup0_inferred__0/i__carry [3]),
+ .I3(\timing_param_tsudat_i_reg[3]_0 [3]),
+ .I4(\sda_setup0_inferred__0/i__carry [4]),
+ .I5(Timing_param_tsudat[4]),
+ .O(\timing_param_tsudat_i_reg[9]_0 [1]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4
+ (.I0(\timing_param_tsusto_i_reg[7]_0 [2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [2]),
+ .I2(\next_scl_state1_inferred__1/i__carry [1]),
+ .I3(\timing_param_tsusto_i_reg[7]_0 [1]),
+ .I4(\next_scl_state1_inferred__1/i__carry [0]),
+ .I5(\timing_param_tsusto_i_reg[7]_0 [0]),
+ .O(\timing_param_tsusto_i_reg[9]_0 [0]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4__0
+ (.I0(\timing_param_tsusta_i_reg[7]_0 [1]),
+ .I1(\next_scl_state1_inferred__1/i__carry [1]),
+ .I2(\next_scl_state1_inferred__1/i__carry [2]),
+ .I3(Timing_param_tsusta[2]),
+ .I4(\next_scl_state1_inferred__1/i__carry [0]),
+ .I5(\timing_param_tsusta_i_reg[7]_0 [0]),
+ .O(\timing_param_tsusta_i_reg[9]_0 [0]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4__1
+ (.I0(Timing_param_tbuf[2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [2]),
+ .I2(\next_scl_state1_inferred__1/i__carry [0]),
+ .I3(\timing_param_tbuf_i_reg[7]_0 [0]),
+ .I4(\next_scl_state1_inferred__1/i__carry [1]),
+ .I5(\timing_param_tbuf_i_reg[7]_0 [1]),
+ .O(\timing_param_tbuf_i_reg[9]_0 [0]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4__2
+ (.I0(Timing_param_thdsta[1]),
+ .I1(\next_scl_state1_inferred__1/i__carry [1]),
+ .I2(\next_scl_state1_inferred__1/i__carry [2]),
+ .I3(Timing_param_thdsta[2]),
+ .I4(\next_scl_state1_inferred__1/i__carry [0]),
+ .I5(\timing_param_thdsta_i_reg[7]_0 [0]),
+ .O(\timing_param_thdsta_i_reg[9]_0 [0]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4__3
+ (.I0(Timing_param_tlow[2]),
+ .I1(\next_scl_state1_inferred__1/i__carry [2]),
+ .I2(\next_scl_state1_inferred__1/i__carry [0]),
+ .I3(\timing_param_tlow_i_reg[7]_0 [0]),
+ .I4(\next_scl_state1_inferred__1/i__carry [1]),
+ .I5(Timing_param_tlow[1]),
+ .O(\timing_param_tlow_i_reg[9]_0 [0]));
+ LUT6 #(
+ .INIT(64'h9009000000009009))
+ i__carry_i_4__4
+ (.I0(\timing_param_tsudat_i_reg[3]_0 [2]),
+ .I1(\sda_setup0_inferred__0/i__carry [2]),
+ .I2(\sda_setup0_inferred__0/i__carry [1]),
+ .I3(\timing_param_tsudat_i_reg[3]_0 [1]),
+ .I4(\sda_setup0_inferred__0/i__carry [0]),
+ .I5(\timing_param_tsudat_i_reg[3]_0 [0]),
+ .O(\timing_param_tsudat_i_reg[9]_0 [0]));
+ FDRE msms_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(Q[1]),
+ .Q(msms_d1),
+ .R(Bus2IIC_Reset));
+ LUT5 #(
+ .INIT(32'hCE0C0A00))
+ msms_set_i_i_1
+ (.I0(D),
+ .I1(\sr_i_reg[1]_0 [1]),
+ .I2(Q[1]),
+ .I3(msms_d1),
+ .I4(Msms_set),
+ .O(msms_set_i_i_1_n_0));
+ FDRE msms_set_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(msms_set_i_i_1_n_0),
+ .Q(Msms_set),
+ .R(Bus2IIC_Reset));
+ FDRE new_rcv_dta_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(New_rcv_dta),
+ .Q(new_rcv_dta_d1),
+ .R(Bus2IIC_Reset));
+ LUT6 #(
+ .INIT(64'h001DFF1DFFFFFFFF))
+ \q_int[1]_i_2
+ (.I0(CO),
+ .I1(stop_scl_reg),
+ .I2(\q_int_reg[1] ),
+ .I3(Q[4]),
+ .I4(\q_int_reg[1]_0 ),
+ .I5(\q_int_reg[1]_1 ),
+ .O(stop_scl_reg_reg));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \s_axi_rdata_i[0]_i_10
+ (.I0(gpo),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_thddat[0]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .I4(sr_i[7]),
+ .O(\GPO_GEN.gpo_i_reg[31]_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[1]_i_10
+ (.I0(IIC2Bus_IntrEvent[5]),
+ .I1(\s_axi_rdata_i[0]_i_7 [4]),
+ .I2(Timing_param_thddat[1]),
+ .I3(\s_axi_rdata_i[0]_i_7 [3]),
+ .O(\IIC2Bus_IntrEvent_reg[5]_0 ));
+ LUT6 #(
+ .INIT(64'h00E2FFFF00E20000))
+ \s_axi_rdata_i[1]_i_5
+ (.I0(\adr_i_reg[0]_0 [0]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_thdsta[1]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(\s_axi_rdata_i[1]_i_9_n_0 ),
+ .O(\adr_i_reg[6]_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \s_axi_rdata_i[1]_i_9
+ (.I0(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [1]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_tlow[1]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .I4(Cr),
+ .O(\s_axi_rdata_i[1]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'h2F202F2F2F202020))
+ \s_axi_rdata_i[2]_i_5
+ (.I0(\s_axi_rdata_i[2]_i_7_n_0 ),
+ .I1(\s_axi_rdata_i[0]_i_7 [4]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(\s_axi_rdata_i[2]_i_8_n_0 ),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(\s_axi_rdata_i[2]_i_9_n_0 ),
+ .O(\bus2ip_addr_i_reg[6]_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[2]_i_6
+ (.I0(sr_i[5]),
+ .I1(\s_axi_rdata_i[0]_i_7 [4]),
+ .I2(Timing_param_thddat[2]),
+ .I3(\s_axi_rdata_i[0]_i_7 [3]),
+ .O(\sr_i_reg[5]_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[2]_i_7
+ (.I0(Timing_param_tbuf[2]),
+ .I1(Rc_addr[1]),
+ .I2(\s_axi_rdata_i[0]_i_7 [2]),
+ .I3(Timing_param_tsusta[2]),
+ .I4(\s_axi_rdata_i[0]_i_7 [3]),
+ .I5(Tx_fifo_data[0]),
+ .O(\s_axi_rdata_i[2]_i_7_n_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[2]_i_8
+ (.I0(\adr_i_reg[0]_0 [1]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_thdsta[2]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .O(\s_axi_rdata_i[2]_i_8_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \s_axi_rdata_i[2]_i_9
+ (.I0(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [2]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_tlow[2]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .I4(Q[1]),
+ .O(\s_axi_rdata_i[2]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'h2F202F2F2F202020))
+ \s_axi_rdata_i[3]_i_5
+ (.I0(\s_axi_rdata_i[3]_i_7_n_0 ),
+ .I1(\s_axi_rdata_i[0]_i_7 [4]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(\s_axi_rdata_i[3]_i_8_n_0 ),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(\s_axi_rdata_i[3]_i_9_n_0 ),
+ .O(\bus2ip_addr_i_reg[6] ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[3]_i_6
+ (.I0(sr_i[4]),
+ .I1(\s_axi_rdata_i[0]_i_7 [4]),
+ .I2(Timing_param_thddat[3]),
+ .I3(\s_axi_rdata_i[0]_i_7 [3]),
+ .O(\sr_i_reg[4]_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[3]_i_7
+ (.I0(Timing_param_tbuf[3]),
+ .I1(Rc_addr[0]),
+ .I2(\s_axi_rdata_i[0]_i_7 [2]),
+ .I3(Timing_param_tsusta[3]),
+ .I4(\s_axi_rdata_i[0]_i_7 [3]),
+ .I5(Tx_fifo_data[1]),
+ .O(\s_axi_rdata_i[3]_i_7_n_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[3]_i_8
+ (.I0(\adr_i_reg[0]_0 [2]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_thdsta[3]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .O(\s_axi_rdata_i[3]_i_8_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \s_axi_rdata_i[3]_i_9
+ (.I0(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0 [3]),
+ .I1(\s_axi_rdata_i[0]_i_7 [3]),
+ .I2(Timing_param_tlow[3]),
+ .I3(\s_axi_rdata_i[0]_i_7 [4]),
+ .I4(Q[2]),
+ .O(\s_axi_rdata_i[3]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'hFCFC7C7FFFFF7C7F))
+ \s_axi_rdata_i[4]_i_7
+ (.I0(Timing_param_tsudat[4]),
+ .I1(\s_axi_rdata_i[0]_i_7 [2]),
+ .I2(\s_axi_rdata_i[0]_i_7 [3]),
+ .I3(sr_i[3]),
+ .I4(\s_axi_rdata_i[0]_i_7 [4]),
+ .I5(Timing_param_thddat[4]),
+ .O(\timing_param_tsudat_i_reg[4]_0 ));
+ LUT6 #(
+ .INIT(64'hFCFC7C7FFFFF7C7F))
+ \s_axi_rdata_i[5]_i_7
+ (.I0(Timing_param_tsudat[5]),
+ .I1(\s_axi_rdata_i[0]_i_7 [2]),
+ .I2(\s_axi_rdata_i[0]_i_7 [3]),
+ .I3(sr_i[2]),
+ .I4(\s_axi_rdata_i[0]_i_7 [4]),
+ .I5(Timing_param_thddat[5]),
+ .O(\timing_param_tsudat_i_reg[5]_0 ));
+ LUT6 #(
+ .INIT(64'hFCFC7C7FFFFF7C7F))
+ \s_axi_rdata_i[6]_i_7
+ (.I0(Timing_param_tsudat[6]),
+ .I1(\s_axi_rdata_i[0]_i_7 [2]),
+ .I2(\s_axi_rdata_i[0]_i_7 [3]),
+ .I3(sr_i[1]),
+ .I4(\s_axi_rdata_i[0]_i_7 [4]),
+ .I5(Timing_param_thddat[6]),
+ .O(\timing_param_tsudat_i_reg[6]_0 ));
+ LUT6 #(
+ .INIT(64'hFCFC7C7FFFFF7C7F))
+ \s_axi_rdata_i[7]_i_10
+ (.I0(Timing_param_tsudat[7]),
+ .I1(\s_axi_rdata_i[0]_i_7 [2]),
+ .I2(\s_axi_rdata_i[0]_i_7 [3]),
+ .I3(\sr_i_reg[0]_0 ),
+ .I4(\s_axi_rdata_i[0]_i_7 [4]),
+ .I5(Timing_param_thddat[7]),
+ .O(\timing_param_tsudat_i_reg[7]_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[8]_i_1
+ (.I0(\s_axi_rdata_i[8]_i_2_n_0 ),
+ .I1(\s_axi_rdata_i[0]_i_7 [0]),
+ .I2(\s_axi_rdata_i[8]_i_3_n_0 ),
+ .I3(\s_axi_rdata_i_reg[8] ),
+ .O(\bus2ip_addr_i_reg[2] [0]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[8]_i_2
+ (.I0(Timing_param_tbuf[8]),
+ .I1(Timing_param_tsusta[8]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(Timing_param_thdsta[8]),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(Timing_param_tlow[8]),
+ .O(\s_axi_rdata_i[8]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[8]_i_3
+ (.I0(Timing_param_thigh[8]),
+ .I1(Timing_param_tsusto[8]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(Timing_param_tsudat[8]),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(Timing_param_thddat[8]),
+ .O(\s_axi_rdata_i[8]_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \s_axi_rdata_i[9]_i_1
+ (.I0(\s_axi_rdata_i[9]_i_2_n_0 ),
+ .I1(\s_axi_rdata_i[0]_i_7 [0]),
+ .I2(\s_axi_rdata_i[9]_i_3_n_0 ),
+ .I3(\s_axi_rdata_i_reg[8] ),
+ .O(\bus2ip_addr_i_reg[2] [1]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[9]_i_2
+ (.I0(Timing_param_tbuf[9]),
+ .I1(Timing_param_tsusta[9]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(Timing_param_thdsta[9]),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(Timing_param_tlow[9]),
+ .O(\s_axi_rdata_i[9]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \s_axi_rdata_i[9]_i_3
+ (.I0(Timing_param_thigh[9]),
+ .I1(Timing_param_tsusto[9]),
+ .I2(\s_axi_rdata_i[0]_i_7 [1]),
+ .I3(Timing_param_tsudat[9]),
+ .I4(\s_axi_rdata_i[0]_i_7 [2]),
+ .I5(Timing_param_thddat[9]),
+ .O(\s_axi_rdata_i[9]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT2 #(
+ .INIT(4'hB))
+ sda_cout_reg_i_5
+ (.I0(Q[4]),
+ .I1(stop_scl_reg),
+ .O(\cr_i_reg[2]_1 ));
+ FDRE \sr_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[0]_1 ),
+ .Q(\sr_i_reg[0]_0 ),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [5]),
+ .Q(sr_i[1]),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [4]),
+ .Q(sr_i[2]),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [3]),
+ .Q(sr_i[3]),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [2]),
+ .Q(sr_i[4]),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [1]),
+ .Q(sr_i[5]),
+ .R(Bus2IIC_Reset));
+ FDRE \sr_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\sr_i_reg[1]_0 [0]),
+ .Q(sr_i[7]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tbuf_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [0]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tbuf_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[1]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[2]),
+ .Q(Timing_param_tbuf[2]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tbuf_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[3]),
+ .Q(Timing_param_tbuf[3]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [3]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [4]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_tbuf_i_reg[7]_0 [5]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tbuf_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_tbuf[8]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tbuf_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[3]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_tbuf[9]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thddat_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[0]),
+ .Q(Timing_param_thddat[0]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[1]),
+ .Q(Timing_param_thddat[1]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[2]),
+ .Q(Timing_param_thddat[2]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[3]),
+ .Q(Timing_param_thddat[3]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[4]),
+ .Q(Timing_param_thddat[4]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[5]),
+ .Q(Timing_param_thddat[5]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[6]),
+ .Q(Timing_param_thddat[6]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[7]),
+ .Q(Timing_param_thddat[7]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_thddat[8]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thddat_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[0]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_thddat[9]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_thdsta_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_thdsta_i_reg[7]_0 [0]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[1]),
+ .Q(Timing_param_thdsta[1]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[2]),
+ .Q(Timing_param_thdsta[2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[3]),
+ .Q(Timing_param_thdsta[3]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thdsta_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_thdsta_i_reg[7]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_thdsta_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thdsta_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_thdsta_i_reg[7]_0 [3]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_thdsta_i_reg[7]_0 [4]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thdsta_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_thdsta[8]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thdsta_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[5]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_thdsta[9]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [0]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thigh_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[1]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[2]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[3]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [3]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thigh_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [4]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [5]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [6]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_thigh_i_reg[7]_0 [7]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_thigh_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_thigh[8]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_thigh_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[2]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_thigh[9]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_tlow_i_reg[7]_0 [0]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tlow_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[1]),
+ .Q(Timing_param_tlow[1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[2]),
+ .Q(Timing_param_tlow[2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[3]),
+ .Q(Timing_param_tlow[3]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tlow_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_tlow_i_reg[7]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_tlow_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_tlow_i_reg[7]_0 [3]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_tlow_i_reg[7]_0 [4]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tlow_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_tlow[8]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tlow_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[1]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_tlow[9]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsudat_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_tsudat_i_reg[3]_0 [0]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsudat_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[1]),
+ .Q(\timing_param_tsudat_i_reg[3]_0 [1]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsudat_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[2]),
+ .Q(\timing_param_tsudat_i_reg[3]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsudat_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[3]),
+ .Q(\timing_param_tsudat_i_reg[3]_0 [3]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsudat_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[4]),
+ .Q(Timing_param_tsudat[4]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsudat_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[5]),
+ .Q(Timing_param_tsudat[5]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsudat_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[6]),
+ .Q(Timing_param_tsudat[6]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsudat_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[7]),
+ .Q(Timing_param_tsudat[7]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsudat_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_tsudat[8]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsudat_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[4]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_tsudat[9]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsusta_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [0]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsusta_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[1]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [1]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsusta_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[2]),
+ .Q(Timing_param_tsusta[2]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsusta_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[3]),
+ .Q(Timing_param_tsusta[3]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusta_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusta_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [3]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsusta_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [4]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsusta_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_tsusta_i_reg[7]_0 [5]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsusta_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_tsusta[8]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsusta_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[7]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_tsusta[9]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsusto_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[0]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [0]),
+ .R(Bus2IIC_Reset));
+ FDRE \timing_param_tsusto_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[1]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [1]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[2]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [2]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsusto_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[3]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [3]),
+ .R(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[4]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [4]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[5]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [5]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[6]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [6]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[7]),
+ .Q(\timing_param_tsusto_i_reg[7]_0 [7]),
+ .S(Bus2IIC_Reset));
+ FDSE \timing_param_tsusto_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[8]),
+ .Q(Timing_param_tsusto[8]),
+ .S(Bus2IIC_Reset));
+ FDRE \timing_param_tsusto_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(Bus2IIC_WrCE[6]),
+ .D(s_axi_wdata[9]),
+ .Q(Timing_param_tsusto[9]),
+ .R(Bus2IIC_Reset));
+endmodule
+
+module TopLevel_axi_iic_0_0_shift8
+ (\data_int_reg[7]_0 ,
+ Q,
+ tx_under_prev_i_reg,
+ shift_reg_en,
+ \data_int_reg[1]_0 ,
+ \LEVEL_1_GEN.master_sda_reg ,
+ slave_sda_reg,
+ state__0,
+ \LEVEL_1_GEN.master_sda_reg_0 ,
+ Tx_fifo_data,
+ \data_int_reg[7]_1 ,
+ s_axi_aclk,
+ \data_int_reg[0]_0 );
+ output \data_int_reg[7]_0 ;
+ output [7:0]Q;
+ output tx_under_prev_i_reg;
+ input shift_reg_en;
+ input \data_int_reg[1]_0 ;
+ input \LEVEL_1_GEN.master_sda_reg ;
+ input slave_sda_reg;
+ input [2:0]state__0;
+ input \LEVEL_1_GEN.master_sda_reg_0 ;
+ input [6:0]Tx_fifo_data;
+ input \data_int_reg[7]_1 ;
+ input s_axi_aclk;
+ input [0:0]\data_int_reg[0]_0 ;
+
+ wire \LEVEL_1_GEN.master_sda_reg ;
+ wire \LEVEL_1_GEN.master_sda_reg_0 ;
+ wire [7:0]Q;
+ wire [6:0]Tx_fifo_data;
+ wire \data_int[7]_i_1_n_0 ;
+ wire [0:0]\data_int_reg[0]_0 ;
+ wire \data_int_reg[1]_0 ;
+ wire \data_int_reg[7]_0 ;
+ wire \data_int_reg[7]_1 ;
+ wire [7:1]p_2_in__0;
+ wire s_axi_aclk;
+ wire shift_reg_en;
+ wire slave_sda_reg;
+ wire [2:0]state__0;
+ wire tx_under_prev_i_reg;
+
+ LUT6 #(
+ .INIT(64'hFFAFFFFFF0AFFFCF))
+ \LEVEL_1_GEN.master_sda_i_1
+ (.I0(\LEVEL_1_GEN.master_sda_reg ),
+ .I1(\LEVEL_1_GEN.master_sda_reg_0 ),
+ .I2(state__0[1]),
+ .I3(state__0[2]),
+ .I4(state__0[0]),
+ .I5(Q[7]),
+ .O(tx_under_prev_i_reg));
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[1]_i_1
+ (.I0(Tx_fifo_data[0]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[0]),
+ .O(p_2_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[2]_i_1
+ (.I0(Tx_fifo_data[1]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[1]),
+ .O(p_2_in__0[2]));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[3]_i_1
+ (.I0(Tx_fifo_data[2]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[2]),
+ .O(p_2_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[4]_i_1
+ (.I0(Tx_fifo_data[3]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[3]),
+ .O(p_2_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[5]_i_1
+ (.I0(Tx_fifo_data[4]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[4]),
+ .O(p_2_in__0[5]));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[6]_i_1
+ (.I0(Tx_fifo_data[5]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[5]),
+ .O(p_2_in__0[6]));
+ LUT2 #(
+ .INIT(4'hE))
+ \data_int[7]_i_1
+ (.I0(shift_reg_en),
+ .I1(\data_int_reg[1]_0 ),
+ .O(\data_int[7]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \data_int[7]_i_2
+ (.I0(Tx_fifo_data[6]),
+ .I1(\data_int_reg[1]_0 ),
+ .I2(Q[6]),
+ .O(p_2_in__0[7]));
+ FDRE \data_int_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(\data_int_reg[0]_0 ),
+ .Q(Q[0]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[1]),
+ .Q(Q[1]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[2]),
+ .Q(Q[2]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[3]),
+ .Q(Q[3]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[4]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[4]),
+ .Q(Q[4]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[5]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[5]),
+ .Q(Q[5]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[6]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[6]),
+ .Q(Q[6]),
+ .R(\data_int_reg[7]_1 ));
+ FDRE \data_int_reg[7]
+ (.C(s_axi_aclk),
+ .CE(\data_int[7]_i_1_n_0 ),
+ .D(p_2_in__0[7]),
+ .Q(Q[7]),
+ .R(\data_int_reg[7]_1 ));
+ LUT6 #(
+ .INIT(64'hFFCFCCAAFFFFFFFF))
+ slave_sda_i_1
+ (.I0(Q[7]),
+ .I1(\LEVEL_1_GEN.master_sda_reg ),
+ .I2(slave_sda_reg),
+ .I3(state__0[0]),
+ .I4(state__0[2]),
+ .I5(state__0[1]),
+ .O(\data_int_reg[7]_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "shift8" *)
+module TopLevel_axi_iic_0_0_shift8_1
+ (shift_reg_ld0,
+ \cr_i_reg[4] ,
+ abgc_i_reg,
+ aas_i_reg,
+ detect_start_reg,
+ \FSM_sequential_state_reg[2] ,
+ detect_start_reg_0,
+ \data_int_reg[0]_0 ,
+ shift_reg_ld_reg,
+ shift_reg_ld_reg_0,
+ state__0,
+ Q,
+ \FSM_sequential_state_reg[1] ,
+ master_slave,
+ \FSM_sequential_state_reg[1]_0 ,
+ aas_i_reg_0,
+ aas_i_reg_1,
+ aas_i_reg_2,
+ detect_start,
+ abgc_i_reg_0,
+ sda_sample,
+ arb_lost,
+ \FSM_sequential_state_reg[2]_0 ,
+ Ro_prev,
+ aas_i_reg_3,
+ srw_i_reg,
+ \data_int_reg[0]_1 ,
+ E,
+ s_axi_aclk,
+ \data_int_reg[0]_2 );
+ output shift_reg_ld0;
+ output \cr_i_reg[4] ;
+ output abgc_i_reg;
+ output aas_i_reg;
+ output detect_start_reg;
+ output \FSM_sequential_state_reg[2] ;
+ output detect_start_reg_0;
+ output \data_int_reg[0]_0 ;
+ input shift_reg_ld_reg;
+ input shift_reg_ld_reg_0;
+ input [2:0]state__0;
+ input [2:0]Q;
+ input \FSM_sequential_state_reg[1] ;
+ input master_slave;
+ input \FSM_sequential_state_reg[1]_0 ;
+ input aas_i_reg_0;
+ input aas_i_reg_1;
+ input aas_i_reg_2;
+ input detect_start;
+ input abgc_i_reg_0;
+ input sda_sample;
+ input arb_lost;
+ input \FSM_sequential_state_reg[2]_0 ;
+ input Ro_prev;
+ input [6:0]aas_i_reg_3;
+ input [0:0]srw_i_reg;
+ input \data_int_reg[0]_1 ;
+ input [0:0]E;
+ input s_axi_aclk;
+ input \data_int_reg[0]_2 ;
+
+ wire [0:0]E;
+ wire \FSM_sequential_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_state[2]_i_10_n_0 ;
+ wire \FSM_sequential_state[2]_i_8_n_0 ;
+ wire \FSM_sequential_state_reg[1] ;
+ wire \FSM_sequential_state_reg[1]_0 ;
+ wire \FSM_sequential_state_reg[2] ;
+ wire \FSM_sequential_state_reg[2]_0 ;
+ wire [2:0]Q;
+ wire Ro_prev;
+ wire aas_i_reg;
+ wire aas_i_reg_0;
+ wire aas_i_reg_1;
+ wire aas_i_reg_2;
+ wire [6:0]aas_i_reg_3;
+ wire abgc_i_i_2_n_0;
+ wire abgc_i_i_3_n_0;
+ wire abgc_i_reg;
+ wire abgc_i_reg_0;
+ wire arb_lost;
+ wire \cr_i_reg[4] ;
+ wire \data_int_reg[0]_0 ;
+ wire \data_int_reg[0]_1 ;
+ wire \data_int_reg[0]_2 ;
+ wire detect_start;
+ wire detect_start_reg;
+ wire detect_start_reg_0;
+ wire [7:0]i2c_header;
+ wire master_slave;
+ wire s_axi_aclk;
+ wire sda_sample;
+ wire shift_reg_ld0;
+ wire shift_reg_ld_i_3_n_0;
+ wire shift_reg_ld_reg;
+ wire shift_reg_ld_reg_0;
+ wire slave_sda_i_3_n_0;
+ wire slave_sda_i_4_n_0;
+ wire [0:0]srw_i_reg;
+ wire [2:0]state__0;
+
+ LUT6 #(
+ .INIT(64'h000E000EFF0F0F0F))
+ \FSM_sequential_state[0]_i_2
+ (.I0(detect_start),
+ .I1(\FSM_sequential_state[2]_i_10_n_0 ),
+ .I2(state__0[0]),
+ .I3(state__0[1]),
+ .I4(Ro_prev),
+ .I5(state__0[2]),
+ .O(detect_start_reg_0));
+ LUT6 #(
+ .INIT(64'hF5F4F5F0FFFFFFF0))
+ \FSM_sequential_state[1]_i_2
+ (.I0(\FSM_sequential_state[1]_i_3_n_0 ),
+ .I1(Q[1]),
+ .I2(\FSM_sequential_state_reg[1] ),
+ .I3(abgc_i_reg),
+ .I4(master_slave),
+ .I5(\FSM_sequential_state_reg[1]_0 ),
+ .O(\cr_i_reg[4] ));
+ LUT6 #(
+ .INIT(64'hEEFFEFEFFFFFFFFF))
+ \FSM_sequential_state[1]_i_3
+ (.I0(sda_sample),
+ .I1(arb_lost),
+ .I2(i2c_header[0]),
+ .I3(Q[1]),
+ .I4(master_slave),
+ .I5(aas_i_reg_0),
+ .O(\FSM_sequential_state[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFABAAAAAB))
+ \FSM_sequential_state[2]_i_10
+ (.I0(master_slave),
+ .I1(slave_sda_i_4_n_0),
+ .I2(slave_sda_i_3_n_0),
+ .I3(i2c_header[7]),
+ .I4(aas_i_reg_3[6]),
+ .I5(abgc_i_reg_0),
+ .O(\FSM_sequential_state[2]_i_10_n_0 ));
+ LUT6 #(
+ .INIT(64'h20FF2000FFFF00FF))
+ \FSM_sequential_state[2]_i_3
+ (.I0(\FSM_sequential_state[2]_i_8_n_0 ),
+ .I1(\FSM_sequential_state_reg[2]_0 ),
+ .I2(\FSM_sequential_state[2]_i_10_n_0 ),
+ .I3(state__0[2]),
+ .I4(detect_start),
+ .I5(state__0[1]),
+ .O(\FSM_sequential_state_reg[2] ));
+ LUT3 #(
+ .INIT(8'h35))
+ \FSM_sequential_state[2]_i_8
+ (.I0(i2c_header[0]),
+ .I1(Q[1]),
+ .I2(master_slave),
+ .O(\FSM_sequential_state[2]_i_8_n_0 ));
+ LUT5 #(
+ .INIT(32'h00A80000))
+ aas_i_i_1
+ (.I0(abgc_i_reg),
+ .I1(aas_i_reg_0),
+ .I2(aas_i_reg_1),
+ .I3(aas_i_reg_2),
+ .I4(Q[0]),
+ .O(aas_i_reg));
+ LUT6 #(
+ .INIT(64'h0000000044440400))
+ abgc_i_i_1
+ (.I0(detect_start),
+ .I1(Q[0]),
+ .I2(abgc_i_i_2_n_0),
+ .I3(abgc_i_i_3_n_0),
+ .I4(abgc_i_reg_0),
+ .I5(aas_i_reg_2),
+ .O(detect_start_reg));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFF7))
+ abgc_i_i_2
+ (.I0(state__0[1]),
+ .I1(state__0[2]),
+ .I2(state__0[0]),
+ .I3(i2c_header[2]),
+ .I4(i2c_header[3]),
+ .I5(i2c_header[4]),
+ .O(abgc_i_i_2_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ abgc_i_i_3
+ (.I0(i2c_header[6]),
+ .I1(i2c_header[0]),
+ .I2(i2c_header[1]),
+ .I3(Q[2]),
+ .I4(i2c_header[5]),
+ .I5(i2c_header[7]),
+ .O(abgc_i_i_3_n_0));
+ FDRE \data_int_reg[0]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(\data_int_reg[0]_2 ),
+ .Q(i2c_header[0]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[1]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[0]),
+ .Q(i2c_header[1]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[2]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[1]),
+ .Q(i2c_header[2]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[3]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[2]),
+ .Q(i2c_header[3]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[4]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[3]),
+ .Q(i2c_header[4]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[5]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[4]),
+ .Q(i2c_header[5]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[6]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[5]),
+ .Q(i2c_header[6]),
+ .R(\data_int_reg[0]_1 ));
+ FDRE \data_int_reg[7]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(i2c_header[6]),
+ .Q(i2c_header[7]),
+ .R(\data_int_reg[0]_1 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFEEEEEFEE))
+ shift_reg_ld_i_1
+ (.I0(shift_reg_ld_reg),
+ .I1(shift_reg_ld_reg_0),
+ .I2(state__0[2]),
+ .I3(state__0[0]),
+ .I4(state__0[1]),
+ .I5(shift_reg_ld_i_3_n_0),
+ .O(shift_reg_ld0));
+ LUT6 #(
+ .INIT(64'h0808000808000000))
+ shift_reg_ld_i_3
+ (.I0(state__0[1]),
+ .I1(state__0[2]),
+ .I2(state__0[0]),
+ .I3(master_slave),
+ .I4(Q[1]),
+ .I5(i2c_header[0]),
+ .O(shift_reg_ld_i_3_n_0));
+ LUT5 #(
+ .INIT(32'hAAAAAAEB))
+ slave_sda_i_2
+ (.I0(abgc_i_reg_0),
+ .I1(aas_i_reg_3[6]),
+ .I2(i2c_header[7]),
+ .I3(slave_sda_i_3_n_0),
+ .I4(slave_sda_i_4_n_0),
+ .O(abgc_i_reg));
+ LUT6 #(
+ .INIT(64'h6FF6FFFFFFFF6FF6))
+ slave_sda_i_3
+ (.I0(i2c_header[4]),
+ .I1(aas_i_reg_3[3]),
+ .I2(aas_i_reg_3[5]),
+ .I3(i2c_header[6]),
+ .I4(aas_i_reg_3[4]),
+ .I5(i2c_header[5]),
+ .O(slave_sda_i_3_n_0));
+ LUT6 #(
+ .INIT(64'h6FF6FFFFFFFF6FF6))
+ slave_sda_i_4
+ (.I0(i2c_header[1]),
+ .I1(aas_i_reg_3[0]),
+ .I2(aas_i_reg_3[1]),
+ .I3(i2c_header[2]),
+ .I4(aas_i_reg_3[2]),
+ .I5(i2c_header[3]),
+ .O(slave_sda_i_4_n_0));
+ LUT5 #(
+ .INIT(32'hEFFF2000))
+ srw_i_i_1
+ (.I0(i2c_header[0]),
+ .I1(state__0[0]),
+ .I2(state__0[2]),
+ .I3(state__0[1]),
+ .I4(srw_i_reg),
+ .O(\data_int_reg[0]_0 ));
+endmodule
+
+module TopLevel_axi_iic_0_0_slave_attachment
+ (\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ,
+ s_axi_rresp,
+ Bus_RNW_reg_reg,
+ s_axi_rvalid_i_reg_0,
+ s_axi_bvalid_i_reg_0,
+ s_axi_bresp,
+ Q,
+ is_write_reg_0,
+ is_read_reg_0,
+ irpt_wrack,
+ E,
+ reset_trig0,
+ sw_rst_cond,
+ \s_axi_wdata[5] ,
+ Bus2IIC_WrCE,
+ \bus2ip_addr_i_reg[3]_0 ,
+ Bus2IIC_RdCE,
+ \s_axi_wdata[31] ,
+ s_axi_wdata_0_sp_1,
+ s_axi_rdata,
+ AXI_IP2Bus_WrAck20,
+ AXI_IP2Bus_RdAck20,
+ AXI_Bus2IP_Reset,
+ s_axi_aclk,
+ s_axi_arvalid,
+ Rc_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_7_0 ,
+ \s_axi_rdata_i_reg[7]_i_7_1 ,
+ Tx_fifo_data,
+ \s_axi_rdata_i_reg[7]_i_6_0 ,
+ \s_axi_rdata_i_reg[7]_i_6_1 ,
+ \s_axi_rdata_i[7]_i_8_0 ,
+ \s_axi_rdata_i[7]_i_8_1 ,
+ \s_axi_rdata_i[0]_i_2_0 ,
+ s_axi_aresetn,
+ AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2,
+ s_axi_wvalid,
+ s_axi_awvalid,
+ AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2,
+ sw_rst_cond_d1,
+ s_axi_wdata,
+ \cr_i_reg[2] ,
+ firstDynStartSeen,
+ \cr_i_reg[2]_0 ,
+ Rc_addr,
+ \s_axi_rdata_i_reg[7]_i_6_2 ,
+ \s_axi_rdata_i_reg[1]_0 ,
+ \s_axi_rdata_i_reg[7]_0 ,
+ p_1_in8_in,
+ \s_axi_rdata_i_reg[4]_i_2_0 ,
+ p_1_in5_in,
+ \s_axi_rdata_i_reg[5]_i_2_0 ,
+ p_1_in2_in,
+ \s_axi_rdata_i_reg[6]_i_2_0 ,
+ p_1_in,
+ \s_axi_rdata_i_reg[7]_i_2_0 ,
+ cr_txModeSelect_set,
+ cr_txModeSelect_clr,
+ s_axi_rready,
+ s_axi_bready,
+ \s_axi_rdata_i_reg[0]_0 ,
+ p_1_in17_in,
+ p_1_in14_in,
+ p_1_in11_in,
+ ipif_glbl_irpt_enable_reg,
+ \s_axi_rdata_i_reg[7]_i_6_3 ,
+ \s_axi_rdata_i_reg[3]_0 ,
+ Tx_addr,
+ \s_axi_rdata_i[3]_i_2_0 ,
+ \s_axi_rdata_i[3]_i_2_1 ,
+ \s_axi_rdata_i_reg[2]_0 ,
+ \s_axi_rdata_i[2]_i_2_0 ,
+ \s_axi_rdata_i[1]_i_2_0 ,
+ \s_axi_rdata_i[0]_i_2_1 ,
+ s_axi_araddr,
+ s_axi_awaddr,
+ gpo,
+ D);
+ output \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ;
+ output [0:0]s_axi_rresp;
+ output Bus_RNW_reg_reg;
+ output s_axi_rvalid_i_reg_0;
+ output s_axi_bvalid_i_reg_0;
+ output [0:0]s_axi_bresp;
+ output [4:0]Q;
+ output is_write_reg_0;
+ output is_read_reg_0;
+ output irpt_wrack;
+ output [0:0]E;
+ output reset_trig0;
+ output sw_rst_cond;
+ output [1:0]\s_axi_wdata[5] ;
+ output [11:0]Bus2IIC_WrCE;
+ output \bus2ip_addr_i_reg[3]_0 ;
+ output [0:0]Bus2IIC_RdCE;
+ output \s_axi_wdata[31] ;
+ output s_axi_wdata_0_sp_1;
+ output [10:0]s_axi_rdata;
+ output AXI_IP2Bus_WrAck20;
+ output AXI_IP2Bus_RdAck20;
+ input AXI_Bus2IP_Reset;
+ input s_axi_aclk;
+ input s_axi_arvalid;
+ input [0:7]Rc_fifo_data;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ input [7:0]\s_axi_rdata_i_reg[7]_i_7_1 ;
+ input [5:0]Tx_fifo_data;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ input [5:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ input [5:0]\s_axi_rdata_i[7]_i_8_0 ;
+ input [4:0]\s_axi_rdata_i[7]_i_8_1 ;
+ input [0:0]\s_axi_rdata_i[0]_i_2_0 ;
+ input s_axi_aresetn;
+ input AXI_IP2Bus_RdAck1;
+ input AXI_IP2Bus_RdAck2;
+ input s_axi_wvalid;
+ input s_axi_awvalid;
+ input AXI_IP2Bus_WrAck1;
+ input AXI_IP2Bus_WrAck2;
+ input sw_rst_cond_d1;
+ input [5:0]s_axi_wdata;
+ input \cr_i_reg[2] ;
+ input firstDynStartSeen;
+ input \cr_i_reg[2]_0 ;
+ input [1:0]Rc_addr;
+ input [4:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ input \s_axi_rdata_i_reg[1]_0 ;
+ input [7:0]\s_axi_rdata_i_reg[7]_0 ;
+ input p_1_in8_in;
+ input \s_axi_rdata_i_reg[4]_i_2_0 ;
+ input p_1_in5_in;
+ input \s_axi_rdata_i_reg[5]_i_2_0 ;
+ input p_1_in2_in;
+ input \s_axi_rdata_i_reg[6]_i_2_0 ;
+ input p_1_in;
+ input \s_axi_rdata_i_reg[7]_i_2_0 ;
+ input cr_txModeSelect_set;
+ input cr_txModeSelect_clr;
+ input s_axi_rready;
+ input s_axi_bready;
+ input \s_axi_rdata_i_reg[0]_0 ;
+ input p_1_in17_in;
+ input p_1_in14_in;
+ input p_1_in11_in;
+ input ipif_glbl_irpt_enable_reg;
+ input [3:0]\s_axi_rdata_i_reg[7]_i_6_3 ;
+ input \s_axi_rdata_i_reg[3]_0 ;
+ input [0:3]Tx_addr;
+ input [3:0]\s_axi_rdata_i[3]_i_2_0 ;
+ input \s_axi_rdata_i[3]_i_2_1 ;
+ input \s_axi_rdata_i_reg[2]_0 ;
+ input \s_axi_rdata_i[2]_i_2_0 ;
+ input \s_axi_rdata_i[1]_i_2_0 ;
+ input \s_axi_rdata_i[0]_i_2_1 ;
+ input [8:0]s_axi_araddr;
+ input [8:0]s_axi_awaddr;
+ input [0:0]gpo;
+ input [1:0]D;
+
+ wire AXI_Bus2IP_Reset;
+ wire [24:31]AXI_IP2Bus_Data;
+ wire AXI_IP2Bus_Error;
+ wire AXI_IP2Bus_RdAck1;
+ wire AXI_IP2Bus_RdAck2;
+ wire AXI_IP2Bus_RdAck20;
+ wire AXI_IP2Bus_WrAck1;
+ wire AXI_IP2Bus_WrAck2;
+ wire AXI_IP2Bus_WrAck20;
+ wire [0:8]Bus2IIC_Addr;
+ wire [0:0]Bus2IIC_RdCE;
+ wire [11:0]Bus2IIC_WrCE;
+ wire Bus_RNW_reg_reg;
+ wire [1:0]D;
+ wire [0:0]E;
+ wire \FSM_onehot_state[0]_i_1_n_0 ;
+ wire \FSM_onehot_state[1]_i_1_n_0 ;
+ wire \FSM_onehot_state[2]_i_1_n_0 ;
+ wire \FSM_onehot_state[3]_i_1_n_0 ;
+ wire \FSM_onehot_state[3]_i_2_n_0 ;
+ wire \FSM_onehot_state_reg_n_0_[0] ;
+ wire \FSM_onehot_state_reg_n_0_[3] ;
+ wire \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ;
+ wire \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
+ wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ;
+ wire I_DECODER_n_34;
+ wire [0:0]Intr2Bus_DBus;
+ wire [4:0]Q;
+ wire [1:0]Rc_addr;
+ wire [0:7]Rc_fifo_data;
+ wire [0:3]Tx_addr;
+ wire [5:0]Tx_fifo_data;
+ wire \bus2ip_addr_i[0]_i_1_n_0 ;
+ wire \bus2ip_addr_i[1]_i_1_n_0 ;
+ wire \bus2ip_addr_i[2]_i_1_n_0 ;
+ wire \bus2ip_addr_i[3]_i_1_n_0 ;
+ wire \bus2ip_addr_i[4]_i_1_n_0 ;
+ wire \bus2ip_addr_i[5]_i_1_n_0 ;
+ wire \bus2ip_addr_i[6]_i_1_n_0 ;
+ wire \bus2ip_addr_i[7]_i_1_n_0 ;
+ wire \bus2ip_addr_i[8]_i_1_n_0 ;
+ wire \bus2ip_addr_i[8]_i_2_n_0 ;
+ wire \bus2ip_addr_i_reg[3]_0 ;
+ wire bus2ip_rnw_i_reg_n_0;
+ wire \cr_i_reg[2] ;
+ wire \cr_i_reg[2]_0 ;
+ wire cr_txModeSelect_clr;
+ wire cr_txModeSelect_set;
+ wire firstDynStartSeen;
+ wire [0:0]gpo;
+ wire ipif_glbl_irpt_enable_reg;
+ wire irpt_wrack;
+ wire is_read_i_1_n_0;
+ wire is_read_reg_0;
+ wire is_read_reg_n_0;
+ wire is_write_i_1_n_0;
+ wire is_write_i_2_n_0;
+ wire is_write_reg_0;
+ wire is_write_reg_n_0;
+ wire [1:0]p_0_out;
+ wire p_1_in;
+ wire p_1_in11_in;
+ wire p_1_in14_in;
+ wire p_1_in17_in;
+ wire p_1_in2_in;
+ wire p_1_in5_in;
+ wire p_1_in8_in;
+ wire [3:0]plusOp;
+ wire reset_trig0;
+ wire rst;
+ wire s_axi_aclk;
+ wire [8:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arvalid;
+ wire [8:0]s_axi_awaddr;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire [0:0]s_axi_bresp;
+ wire s_axi_bresp_i;
+ wire s_axi_bvalid_i_i_1_n_0;
+ wire s_axi_bvalid_i_reg_0;
+ wire [10:0]s_axi_rdata;
+ wire \s_axi_rdata_i[0]_i_11_n_0 ;
+ wire [0:0]\s_axi_rdata_i[0]_i_2_0 ;
+ wire \s_axi_rdata_i[0]_i_2_1 ;
+ wire \s_axi_rdata_i[0]_i_2_n_0 ;
+ wire \s_axi_rdata_i[0]_i_3_n_0 ;
+ wire \s_axi_rdata_i[0]_i_5_n_0 ;
+ wire \s_axi_rdata_i[0]_i_6_n_0 ;
+ wire \s_axi_rdata_i[0]_i_7_n_0 ;
+ wire \s_axi_rdata_i[0]_i_8_n_0 ;
+ wire \s_axi_rdata_i[0]_i_9_n_0 ;
+ wire \s_axi_rdata_i[1]_i_11_n_0 ;
+ wire \s_axi_rdata_i[1]_i_2_0 ;
+ wire \s_axi_rdata_i[1]_i_2_n_0 ;
+ wire \s_axi_rdata_i[1]_i_3_n_0 ;
+ wire \s_axi_rdata_i[1]_i_6_n_0 ;
+ wire \s_axi_rdata_i[1]_i_7_n_0 ;
+ wire \s_axi_rdata_i[1]_i_8_n_0 ;
+ wire \s_axi_rdata_i[2]_i_2_0 ;
+ wire \s_axi_rdata_i[2]_i_2_n_0 ;
+ wire \s_axi_rdata_i[2]_i_3_n_0 ;
+ wire \s_axi_rdata_i[2]_i_4_n_0 ;
+ wire [3:0]\s_axi_rdata_i[3]_i_2_0 ;
+ wire \s_axi_rdata_i[3]_i_2_1 ;
+ wire \s_axi_rdata_i[3]_i_2_n_0 ;
+ wire \s_axi_rdata_i[3]_i_3_n_0 ;
+ wire \s_axi_rdata_i[3]_i_4_n_0 ;
+ wire \s_axi_rdata_i[4]_i_5_n_0 ;
+ wire \s_axi_rdata_i[4]_i_6_n_0 ;
+ wire \s_axi_rdata_i[4]_i_8_n_0 ;
+ wire \s_axi_rdata_i[4]_i_9_n_0 ;
+ wire \s_axi_rdata_i[5]_i_5_n_0 ;
+ wire \s_axi_rdata_i[5]_i_6_n_0 ;
+ wire \s_axi_rdata_i[5]_i_8_n_0 ;
+ wire \s_axi_rdata_i[5]_i_9_n_0 ;
+ wire \s_axi_rdata_i[6]_i_5_n_0 ;
+ wire \s_axi_rdata_i[6]_i_6_n_0 ;
+ wire \s_axi_rdata_i[6]_i_8_n_0 ;
+ wire \s_axi_rdata_i[6]_i_9_n_0 ;
+ wire \s_axi_rdata_i[7]_i_11_n_0 ;
+ wire \s_axi_rdata_i[7]_i_12_n_0 ;
+ wire [5:0]\s_axi_rdata_i[7]_i_8_0 ;
+ wire [4:0]\s_axi_rdata_i[7]_i_8_1 ;
+ wire \s_axi_rdata_i[7]_i_8_n_0 ;
+ wire \s_axi_rdata_i[7]_i_9_n_0 ;
+ wire \s_axi_rdata_i[9]_i_6_n_0 ;
+ wire \s_axi_rdata_i_reg[0]_0 ;
+ wire \s_axi_rdata_i_reg[1]_0 ;
+ wire \s_axi_rdata_i_reg[2]_0 ;
+ wire \s_axi_rdata_i_reg[3]_0 ;
+ wire \s_axi_rdata_i_reg[4]_i_2_0 ;
+ wire \s_axi_rdata_i_reg[4]_i_2_n_0 ;
+ wire \s_axi_rdata_i_reg[4]_i_3_n_0 ;
+ wire \s_axi_rdata_i_reg[4]_i_4_n_0 ;
+ wire \s_axi_rdata_i_reg[5]_i_2_0 ;
+ wire \s_axi_rdata_i_reg[5]_i_2_n_0 ;
+ wire \s_axi_rdata_i_reg[5]_i_3_n_0 ;
+ wire \s_axi_rdata_i_reg[5]_i_4_n_0 ;
+ wire \s_axi_rdata_i_reg[6]_i_2_0 ;
+ wire \s_axi_rdata_i_reg[6]_i_2_n_0 ;
+ wire \s_axi_rdata_i_reg[6]_i_3_n_0 ;
+ wire \s_axi_rdata_i_reg[6]_i_4_n_0 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_0 ;
+ wire \s_axi_rdata_i_reg[7]_i_2_0 ;
+ wire \s_axi_rdata_i_reg[7]_i_2_n_0 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6_0 ;
+ wire [5:0]\s_axi_rdata_i_reg[7]_i_6_1 ;
+ wire [4:0]\s_axi_rdata_i_reg[7]_i_6_2 ;
+ wire [3:0]\s_axi_rdata_i_reg[7]_i_6_3 ;
+ wire \s_axi_rdata_i_reg[7]_i_6_n_0 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7_0 ;
+ wire [7:0]\s_axi_rdata_i_reg[7]_i_7_1 ;
+ wire \s_axi_rdata_i_reg[7]_i_7_n_0 ;
+ wire s_axi_rready;
+ wire [0:0]s_axi_rresp;
+ wire s_axi_rresp_i;
+ wire s_axi_rvalid_i_i_1_n_0;
+ wire s_axi_rvalid_i_reg_0;
+ wire [5:0]s_axi_wdata;
+ wire \s_axi_wdata[31] ;
+ wire [1:0]\s_axi_wdata[5] ;
+ wire s_axi_wdata_0_sn_1;
+ wire s_axi_wvalid;
+ wire start2;
+ wire start2_i_1_n_0;
+ wire [1:0]state;
+ wire \state[1]_i_2_n_0 ;
+ wire sw_rst_cond;
+ wire sw_rst_cond_d1;
+
+ assign s_axi_wdata_0_sp_1 = s_axi_wdata_0_sn_1;
+ LUT6 #(
+ .INIT(64'h44444F444F444F44))
+ \FSM_onehot_state[0]_i_1
+ (.I0(\FSM_onehot_state[3]_i_2_n_0 ),
+ .I1(\FSM_onehot_state_reg_n_0_[3] ),
+ .I2(s_axi_arvalid),
+ .I3(\FSM_onehot_state_reg_n_0_[0] ),
+ .I4(s_axi_wvalid),
+ .I5(s_axi_awvalid),
+ .O(\FSM_onehot_state[0]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h8F88))
+ \FSM_onehot_state[1]_i_1
+ (.I0(\FSM_onehot_state_reg_n_0_[0] ),
+ .I1(s_axi_arvalid),
+ .I2(is_read_reg_0),
+ .I3(s_axi_rresp_i),
+ .O(\FSM_onehot_state[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h4000FFFF40004000))
+ \FSM_onehot_state[2]_i_1
+ (.I0(s_axi_arvalid),
+ .I1(\FSM_onehot_state_reg_n_0_[0] ),
+ .I2(s_axi_wvalid),
+ .I3(s_axi_awvalid),
+ .I4(is_write_reg_0),
+ .I5(s_axi_bresp_i),
+ .O(\FSM_onehot_state[2]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFF888F888F888))
+ \FSM_onehot_state[3]_i_1
+ (.I0(is_read_reg_0),
+ .I1(s_axi_rresp_i),
+ .I2(s_axi_bresp_i),
+ .I3(is_write_reg_0),
+ .I4(\FSM_onehot_state_reg_n_0_[3] ),
+ .I5(\FSM_onehot_state[3]_i_2_n_0 ),
+ .O(\FSM_onehot_state[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h0777))
+ \FSM_onehot_state[3]_i_2
+ (.I0(s_axi_rvalid_i_reg_0),
+ .I1(s_axi_rready),
+ .I2(s_axi_bvalid_i_reg_0),
+ .I3(s_axi_bready),
+ .O(\FSM_onehot_state[3]_i_2_n_0 ));
+ (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
+ FDSE #(
+ .INIT(1'b1))
+ \FSM_onehot_state_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_onehot_state[0]_i_1_n_0 ),
+ .Q(\FSM_onehot_state_reg_n_0_[0] ),
+ .S(rst));
+ (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_onehot_state_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_onehot_state[1]_i_1_n_0 ),
+ .Q(s_axi_rresp_i),
+ .R(rst));
+ (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_onehot_state_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_onehot_state[2]_i_1_n_0 ),
+ .Q(s_axi_bresp_i),
+ .R(rst));
+ (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_onehot_state_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_onehot_state[3]_i_1_n_0 ),
+ .Q(\FSM_onehot_state_reg_n_0_[3] ),
+ .R(rst));
+ (* SOFT_HLUTNM = "soft_lutpair61" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
+ (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
+ .O(plusOp[0]));
+ (* SOFT_HLUTNM = "soft_lutpair61" *)
+ LUT2 #(
+ .INIT(4'h6))
+ \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
+ (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
+ .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
+ .O(plusOp[1]));
+ (* SOFT_HLUTNM = "soft_lutpair56" *)
+ LUT3 #(
+ .INIT(8'h6A))
+ \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
+ (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
+ .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
+ .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
+ .O(plusOp[2]));
+ LUT2 #(
+ .INIT(4'h9))
+ \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
+ (.I0(state[0]),
+ .I1(state[1]),
+ .O(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair56" *)
+ LUT4 #(
+ .INIT(16'h6AAA))
+ \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
+ (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
+ .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
+ .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
+ .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
+ .O(plusOp[3]));
+ FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(plusOp[0]),
+ .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
+ .R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+ FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(plusOp[1]),
+ .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
+ .R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+ FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(plusOp[2]),
+ .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
+ .R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+ FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(plusOp[3]),
+ .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
+ .R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+ TopLevel_axi_iic_0_0_address_decoder I_DECODER
+ (.AXI_IP2Bus_Error(AXI_IP2Bus_Error),
+ .AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
+ .AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
+ .AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
+ .AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
+ .AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
+ .AXI_IP2Bus_WrAck20(AXI_IP2Bus_WrAck20),
+ .AXI_IP2Bus_WrAck2_reg(bus2ip_rnw_i_reg_n_0),
+ .Bus2IIC_RdCE(Bus2IIC_RdCE),
+ .Bus2IIC_WrCE(Bus2IIC_WrCE),
+ .Bus_RNW_reg_reg_0(Bus_RNW_reg_reg),
+ .D({Intr2Bus_DBus,AXI_IP2Bus_Data[24],AXI_IP2Bus_Data[25],AXI_IP2Bus_Data[26],AXI_IP2Bus_Data[27],AXI_IP2Bus_Data[28],AXI_IP2Bus_Data[29],AXI_IP2Bus_Data[30],AXI_IP2Bus_Data[31]}),
+ .E(E),
+ .\FSM_onehot_state_reg[2] (I_DECODER_n_34),
+ .\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 (\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ),
+ .\MEM_DECODE_GEN[2].cs_out_i_reg[2]_0 ({Bus2IIC_Addr[0],Bus2IIC_Addr[1],Q,Bus2IIC_Addr[7],Bus2IIC_Addr[8]}),
+ .Q(start2),
+ .\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3]_0 ),
+ .\cr_i_reg[2] (\cr_i_reg[2] ),
+ .\cr_i_reg[2]_0 ({\s_axi_rdata_i[7]_i_8_0 [3],\s_axi_rdata_i[7]_i_8_0 [1]}),
+ .\cr_i_reg[2]_1 (\cr_i_reg[2]_0 ),
+ .cr_txModeSelect_clr(cr_txModeSelect_clr),
+ .cr_txModeSelect_set(cr_txModeSelect_set),
+ .firstDynStartSeen(firstDynStartSeen),
+ .gpo(gpo),
+ .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+ .irpt_wrack(irpt_wrack),
+ .is_read_reg(is_read_reg_0),
+ .is_write_reg(is_write_reg_0),
+ .p_1_in(p_1_in),
+ .p_1_in11_in(p_1_in11_in),
+ .p_1_in14_in(p_1_in14_in),
+ .p_1_in17_in(p_1_in17_in),
+ .p_1_in2_in(p_1_in2_in),
+ .p_1_in5_in(p_1_in5_in),
+ .p_1_in8_in(p_1_in8_in),
+ .reset_trig0(reset_trig0),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arready(is_read_reg_n_0),
+ .s_axi_awready(is_write_reg_n_0),
+ .s_axi_awready_0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ),
+ .s_axi_bresp(s_axi_bresp),
+ .\s_axi_bresp_i_reg[1] (s_axi_bresp_i),
+ .\s_axi_rdata_i_reg[0] (\s_axi_rdata_i[0]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i[0]_i_3_n_0 ),
+ .\s_axi_rdata_i_reg[0]_1 (\s_axi_rdata_i_reg[0]_0 ),
+ .\s_axi_rdata_i_reg[1] (\s_axi_rdata_i[1]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[1]_0 (\s_axi_rdata_i[1]_i_3_n_0 ),
+ .\s_axi_rdata_i_reg[2] (\s_axi_rdata_i[2]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[3] (\s_axi_rdata_i[3]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[4] (\s_axi_rdata_i_reg[4]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[5] (\s_axi_rdata_i_reg[5]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[6] (\s_axi_rdata_i_reg[6]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[7] (\s_axi_rdata_i_reg[7]_0 ),
+ .\s_axi_rdata_i_reg[7]_0 (\s_axi_rdata_i_reg[7]_i_2_n_0 ),
+ .\s_axi_rdata_i_reg[8] (\s_axi_rdata_i[9]_i_6_n_0 ),
+ .s_axi_wdata(s_axi_wdata),
+ .\s_axi_wdata[31] (\s_axi_wdata[31] ),
+ .\s_axi_wdata[5] (\s_axi_wdata[5] ),
+ .s_axi_wdata_0_sp_1(s_axi_wdata_0_sn_1),
+ .sw_rst_cond(sw_rst_cond),
+ .sw_rst_cond_d1(sw_rst_cond_d1));
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[0]_i_1
+ (.I0(s_axi_araddr[0]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[0]),
+ .O(\bus2ip_addr_i[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair60" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[1]_i_1
+ (.I0(s_axi_araddr[1]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[1]),
+ .O(\bus2ip_addr_i[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair60" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[2]_i_1
+ (.I0(s_axi_araddr[2]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[2]),
+ .O(\bus2ip_addr_i[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair59" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[3]_i_1
+ (.I0(s_axi_araddr[3]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[3]),
+ .O(\bus2ip_addr_i[3]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair59" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[4]_i_1
+ (.I0(s_axi_araddr[4]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[4]),
+ .O(\bus2ip_addr_i[4]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair58" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[5]_i_1
+ (.I0(s_axi_araddr[5]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[5]),
+ .O(\bus2ip_addr_i[5]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair58" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[6]_i_1
+ (.I0(s_axi_araddr[6]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[6]),
+ .O(\bus2ip_addr_i[6]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair57" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[7]_i_1
+ (.I0(s_axi_araddr[7]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[7]),
+ .O(\bus2ip_addr_i[7]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h03020202))
+ \bus2ip_addr_i[8]_i_1
+ (.I0(s_axi_arvalid),
+ .I1(state[0]),
+ .I2(state[1]),
+ .I3(s_axi_wvalid),
+ .I4(s_axi_awvalid),
+ .O(\bus2ip_addr_i[8]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair57" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \bus2ip_addr_i[8]_i_2
+ (.I0(s_axi_araddr[8]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_awaddr[8]),
+ .O(\bus2ip_addr_i[8]_i_2_n_0 ));
+ FDRE \bus2ip_addr_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[0]_i_1_n_0 ),
+ .Q(Bus2IIC_Addr[8]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[1]_i_1_n_0 ),
+ .Q(Bus2IIC_Addr[7]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[2]_i_1_n_0 ),
+ .Q(Q[0]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[3]_i_1_n_0 ),
+ .Q(Q[1]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[4]_i_1_n_0 ),
+ .Q(Q[2]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[5]_i_1_n_0 ),
+ .Q(Q[3]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[6]_i_1_n_0 ),
+ .Q(Q[4]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[7]_i_1_n_0 ),
+ .Q(Bus2IIC_Addr[1]),
+ .R(rst));
+ FDRE \bus2ip_addr_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(\bus2ip_addr_i[8]_i_2_n_0 ),
+ .Q(Bus2IIC_Addr[0]),
+ .R(rst));
+ FDRE bus2ip_rnw_i_reg
+ (.C(s_axi_aclk),
+ .CE(\bus2ip_addr_i[8]_i_1_n_0 ),
+ .D(s_axi_arvalid),
+ .Q(bus2ip_rnw_i_reg_n_0),
+ .R(rst));
+ LUT5 #(
+ .INIT(32'hB8BB8888))
+ is_read_i_1
+ (.I0(s_axi_arvalid),
+ .I1(\FSM_onehot_state_reg_n_0_[0] ),
+ .I2(\FSM_onehot_state[3]_i_2_n_0 ),
+ .I3(\FSM_onehot_state_reg_n_0_[3] ),
+ .I4(is_read_reg_n_0),
+ .O(is_read_i_1_n_0));
+ FDRE is_read_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(is_read_i_1_n_0),
+ .Q(is_read_reg_n_0),
+ .R(rst));
+ LUT6 #(
+ .INIT(64'h0080FFFF00800000))
+ is_write_i_1
+ (.I0(s_axi_awvalid),
+ .I1(s_axi_wvalid),
+ .I2(\FSM_onehot_state_reg_n_0_[0] ),
+ .I3(s_axi_arvalid),
+ .I4(is_write_i_2_n_0),
+ .I5(is_write_reg_n_0),
+ .O(is_write_i_1_n_0));
+ LUT6 #(
+ .INIT(64'hFFEAEAEAAAAAAAAA))
+ is_write_i_2
+ (.I0(\FSM_onehot_state_reg_n_0_[0] ),
+ .I1(s_axi_rvalid_i_reg_0),
+ .I2(s_axi_rready),
+ .I3(s_axi_bvalid_i_reg_0),
+ .I4(s_axi_bready),
+ .I5(\FSM_onehot_state_reg_n_0_[3] ),
+ .O(is_write_i_2_n_0));
+ FDRE is_write_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(is_write_i_1_n_0),
+ .Q(is_write_reg_n_0),
+ .R(rst));
+ FDRE rst_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(AXI_Bus2IP_Reset),
+ .Q(rst),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_bresp_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(I_DECODER_n_34),
+ .Q(s_axi_bresp),
+ .R(rst));
+ LUT5 #(
+ .INIT(32'h75553000))
+ s_axi_bvalid_i_i_1
+ (.I0(s_axi_bready),
+ .I1(state[0]),
+ .I2(state[1]),
+ .I3(is_write_reg_0),
+ .I4(s_axi_bvalid_i_reg_0),
+ .O(s_axi_bvalid_i_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_bvalid_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_bvalid_i_i_1_n_0),
+ .Q(s_axi_bvalid_i_reg_0),
+ .R(rst));
+ LUT5 #(
+ .INIT(32'h00011101))
+ \s_axi_rdata_i[0]_i_11
+ (.I0(Q[2]),
+ .I1(Q[0]),
+ .I2(Tx_fifo_data[0]),
+ .I3(Q[3]),
+ .I4(\s_axi_rdata_i_reg[7]_i_6_0 [0]),
+ .O(\s_axi_rdata_i[0]_i_11_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000FFB0B0))
+ \s_axi_rdata_i[0]_i_2
+ (.I0(\s_axi_rdata_i[0]_i_5_n_0 ),
+ .I1(\s_axi_rdata_i_reg[7]_i_6_2 [0]),
+ .I2(\s_axi_rdata_i[0]_i_6_n_0 ),
+ .I3(\s_axi_rdata_i[0]_i_7_n_0 ),
+ .I4(Q[0]),
+ .I5(Q[1]),
+ .O(\s_axi_rdata_i[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000AAEAAAAA))
+ \s_axi_rdata_i[0]_i_3
+ (.I0(\s_axi_rdata_i[0]_i_8_n_0 ),
+ .I1(\s_axi_rdata_i_reg[7]_i_7_1 [0]),
+ .I2(Q[2]),
+ .I3(Q[4]),
+ .I4(Q[3]),
+ .I5(\s_axi_rdata_i[0]_i_9_n_0 ),
+ .O(\s_axi_rdata_i[0]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair55" *)
+ LUT3 #(
+ .INIT(8'hDF))
+ \s_axi_rdata_i[0]_i_5
+ (.I0(Q[3]),
+ .I1(Q[4]),
+ .I2(Q[2]),
+ .O(\s_axi_rdata_i[0]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFAABFBFFFFABFB))
+ \s_axi_rdata_i[0]_i_6
+ (.I0(Q[2]),
+ .I1(\s_axi_rdata_i[7]_i_8_0 [0]),
+ .I2(Q[4]),
+ .I3(\s_axi_rdata_i[7]_i_8_1 [0]),
+ .I4(Q[3]),
+ .I5(\s_axi_rdata_i[0]_i_2_0 ),
+ .O(\s_axi_rdata_i[0]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'h00E2FFFF00E20000))
+ \s_axi_rdata_i[0]_i_7
+ (.I0(Tx_addr[0]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i[3]_i_2_0 [0]),
+ .I3(Q[4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[0]_i_2_1 ),
+ .O(\s_axi_rdata_i[0]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'h1311131313111111))
+ \s_axi_rdata_i[0]_i_8
+ (.I0(Q[0]),
+ .I1(Q[4]),
+ .I2(Q[2]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [0]),
+ .I4(Q[3]),
+ .I5(Rc_fifo_data[7]),
+ .O(\s_axi_rdata_i[0]_i_8_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF00200222))
+ \s_axi_rdata_i[0]_i_9
+ (.I0(Q[2]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_1 [0]),
+ .I4(Rc_addr[1]),
+ .I5(\s_axi_rdata_i[0]_i_11_n_0 ),
+ .O(\s_axi_rdata_i[0]_i_9_n_0 ));
+ LUT5 #(
+ .INIT(32'h00011101))
+ \s_axi_rdata_i[1]_i_11
+ (.I0(Q[2]),
+ .I1(Q[0]),
+ .I2(Tx_fifo_data[1]),
+ .I3(Q[3]),
+ .I4(\s_axi_rdata_i_reg[7]_i_6_0 [1]),
+ .O(\s_axi_rdata_i[1]_i_11_n_0 ));
+ LUT4 #(
+ .INIT(16'h0035))
+ \s_axi_rdata_i[1]_i_2
+ (.I0(\s_axi_rdata_i_reg[1]_0 ),
+ .I1(\s_axi_rdata_i[1]_i_6_n_0 ),
+ .I2(Q[0]),
+ .I3(Q[1]),
+ .O(\s_axi_rdata_i[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000AAEAAAAA))
+ \s_axi_rdata_i[1]_i_3
+ (.I0(\s_axi_rdata_i[1]_i_7_n_0 ),
+ .I1(\s_axi_rdata_i_reg[7]_i_7_1 [1]),
+ .I2(Q[2]),
+ .I3(Q[4]),
+ .I4(Q[3]),
+ .I5(\s_axi_rdata_i[1]_i_8_n_0 ),
+ .O(\s_axi_rdata_i[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h00E2FFFF00E20000))
+ \s_axi_rdata_i[1]_i_6
+ (.I0(Tx_addr[1]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i[3]_i_2_0 [1]),
+ .I3(Q[4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[1]_i_2_0 ),
+ .O(\s_axi_rdata_i[1]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'h1311131313111111))
+ \s_axi_rdata_i[1]_i_7
+ (.I0(Q[0]),
+ .I1(Q[4]),
+ .I2(Q[2]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [1]),
+ .I4(Q[3]),
+ .I5(Rc_fifo_data[6]),
+ .O(\s_axi_rdata_i[1]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF00200222))
+ \s_axi_rdata_i[1]_i_8
+ (.I0(Q[2]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_1 [1]),
+ .I4(Rc_addr[0]),
+ .I5(\s_axi_rdata_i[1]_i_11_n_0 ),
+ .O(\s_axi_rdata_i[1]_i_8_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8FFB800))
+ \s_axi_rdata_i[2]_i_2
+ (.I0(\s_axi_rdata_i[2]_i_3_n_0 ),
+ .I1(Q[1]),
+ .I2(\s_axi_rdata_i[2]_i_4_n_0 ),
+ .I3(Q[0]),
+ .I4(\s_axi_rdata_i_reg[2]_0 ),
+ .O(\s_axi_rdata_i[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000CCE200E2))
+ \s_axi_rdata_i[2]_i_3
+ (.I0(Rc_fifo_data[5]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i_reg[7]_i_7_0 [2]),
+ .I3(Q[2]),
+ .I4(\s_axi_rdata_i_reg[7]_i_7_1 [2]),
+ .I5(Q[4]),
+ .O(\s_axi_rdata_i[2]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h00E2FFFF00E20000))
+ \s_axi_rdata_i[2]_i_4
+ (.I0(Tx_addr[2]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i[3]_i_2_0 [2]),
+ .I3(Q[4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[2]_i_2_0 ),
+ .O(\s_axi_rdata_i[2]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8FFB800))
+ \s_axi_rdata_i[3]_i_2
+ (.I0(\s_axi_rdata_i[3]_i_3_n_0 ),
+ .I1(Q[1]),
+ .I2(\s_axi_rdata_i[3]_i_4_n_0 ),
+ .I3(Q[0]),
+ .I4(\s_axi_rdata_i_reg[3]_0 ),
+ .O(\s_axi_rdata_i[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000CCE200E2))
+ \s_axi_rdata_i[3]_i_3
+ (.I0(Rc_fifo_data[4]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i_reg[7]_i_7_0 [3]),
+ .I3(Q[2]),
+ .I4(\s_axi_rdata_i_reg[7]_i_7_1 [3]),
+ .I5(Q[4]),
+ .O(\s_axi_rdata_i[3]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h00E2FFFF00E20000))
+ \s_axi_rdata_i[3]_i_4
+ (.I0(Tx_addr[3]),
+ .I1(Q[3]),
+ .I2(\s_axi_rdata_i[3]_i_2_0 [3]),
+ .I3(Q[4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[3]_i_2_1 ),
+ .O(\s_axi_rdata_i[3]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hABFBFFFFABFB0000))
+ \s_axi_rdata_i[4]_i_5
+ (.I0(Q[4]),
+ .I1(\s_axi_rdata_i_reg[7]_i_6_3 [0]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_2 [1]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[4]_i_9_n_0 ),
+ .O(\s_axi_rdata_i[4]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[4]_i_6
+ (.I0(Q[4]),
+ .I1(Tx_fifo_data[2]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_0 [2]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_6_1 [2]),
+ .O(\s_axi_rdata_i[4]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[4]_i_8
+ (.I0(Q[4]),
+ .I1(Rc_fifo_data[3]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_7_1 [4]),
+ .O(\s_axi_rdata_i[4]_i_8_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair55" *)
+ LUT4 #(
+ .INIT(16'hABFB))
+ \s_axi_rdata_i[4]_i_9
+ (.I0(Q[3]),
+ .I1(\s_axi_rdata_i[7]_i_8_0 [2]),
+ .I2(Q[4]),
+ .I3(\s_axi_rdata_i[7]_i_8_1 [1]),
+ .O(\s_axi_rdata_i[4]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'hABFBFFFFABFB0000))
+ \s_axi_rdata_i[5]_i_5
+ (.I0(Q[4]),
+ .I1(\s_axi_rdata_i_reg[7]_i_6_3 [1]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_2 [2]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[5]_i_9_n_0 ),
+ .O(\s_axi_rdata_i[5]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[5]_i_6
+ (.I0(Q[4]),
+ .I1(Tx_fifo_data[3]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_0 [3]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_6_1 [3]),
+ .O(\s_axi_rdata_i[5]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[5]_i_8
+ (.I0(Q[4]),
+ .I1(Rc_fifo_data[2]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [5]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_7_1 [5]),
+ .O(\s_axi_rdata_i[5]_i_8_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \s_axi_rdata_i[5]_i_9
+ (.I0(Q[3]),
+ .I1(\s_axi_rdata_i[7]_i_8_0 [3]),
+ .I2(Q[4]),
+ .I3(\s_axi_rdata_i[7]_i_8_1 [2]),
+ .O(\s_axi_rdata_i[5]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'hABFBFFFFABFB0000))
+ \s_axi_rdata_i[6]_i_5
+ (.I0(Q[4]),
+ .I1(\s_axi_rdata_i_reg[7]_i_6_3 [2]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_2 [3]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[6]_i_9_n_0 ),
+ .O(\s_axi_rdata_i[6]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[6]_i_6
+ (.I0(Q[4]),
+ .I1(Tx_fifo_data[4]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_0 [4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_6_1 [4]),
+ .O(\s_axi_rdata_i[6]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[6]_i_8
+ (.I0(Q[4]),
+ .I1(Rc_fifo_data[1]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [6]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_7_1 [6]),
+ .O(\s_axi_rdata_i[6]_i_8_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \s_axi_rdata_i[6]_i_9
+ (.I0(Q[3]),
+ .I1(\s_axi_rdata_i[7]_i_8_0 [4]),
+ .I2(Q[4]),
+ .I3(\s_axi_rdata_i[7]_i_8_1 [3]),
+ .O(\s_axi_rdata_i[6]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[7]_i_11
+ (.I0(Q[4]),
+ .I1(Rc_fifo_data[0]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_7_0 [7]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_7_1 [7]),
+ .O(\s_axi_rdata_i[7]_i_11_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \s_axi_rdata_i[7]_i_12
+ (.I0(Q[3]),
+ .I1(\s_axi_rdata_i[7]_i_8_0 [5]),
+ .I2(Q[4]),
+ .I3(\s_axi_rdata_i[7]_i_8_1 [4]),
+ .O(\s_axi_rdata_i[7]_i_12_n_0 ));
+ LUT6 #(
+ .INIT(64'hABFBFFFFABFB0000))
+ \s_axi_rdata_i[7]_i_8
+ (.I0(Q[4]),
+ .I1(\s_axi_rdata_i_reg[7]_i_6_3 [3]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_2 [4]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i[7]_i_12_n_0 ),
+ .O(\s_axi_rdata_i[7]_i_8_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFABFBFFFFABFB))
+ \s_axi_rdata_i[7]_i_9
+ (.I0(Q[4]),
+ .I1(Tx_fifo_data[5]),
+ .I2(Q[3]),
+ .I3(\s_axi_rdata_i_reg[7]_i_6_0 [5]),
+ .I4(Q[2]),
+ .I5(\s_axi_rdata_i_reg[7]_i_6_1 [5]),
+ .O(\s_axi_rdata_i[7]_i_9_n_0 ));
+ LUT3 #(
+ .INIT(8'hFE))
+ \s_axi_rdata_i[9]_i_6
+ (.I0(Bus2IIC_Addr[7]),
+ .I1(Bus2IIC_Addr[8]),
+ .I2(Bus2IIC_Addr[1]),
+ .O(\s_axi_rdata_i[9]_i_6_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[0]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[31]),
+ .Q(s_axi_rdata[0]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[30]),
+ .Q(s_axi_rdata[1]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[2]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[29]),
+ .Q(s_axi_rdata[2]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[31]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(Intr2Bus_DBus),
+ .Q(s_axi_rdata[10]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[3]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[28]),
+ .Q(s_axi_rdata[3]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[4]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[27]),
+ .Q(s_axi_rdata[4]),
+ .R(rst));
+ MUXF8 \s_axi_rdata_i_reg[4]_i_2
+ (.I0(\s_axi_rdata_i_reg[4]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[4]_i_4_n_0 ),
+ .O(\s_axi_rdata_i_reg[4]_i_2_n_0 ),
+ .S(Q[0]));
+ MUXF7 \s_axi_rdata_i_reg[4]_i_3
+ (.I0(\s_axi_rdata_i[4]_i_5_n_0 ),
+ .I1(\s_axi_rdata_i[4]_i_6_n_0 ),
+ .O(\s_axi_rdata_i_reg[4]_i_3_n_0 ),
+ .S(Q[1]));
+ MUXF7 \s_axi_rdata_i_reg[4]_i_4
+ (.I0(\s_axi_rdata_i_reg[4]_i_2_0 ),
+ .I1(\s_axi_rdata_i[4]_i_8_n_0 ),
+ .O(\s_axi_rdata_i_reg[4]_i_4_n_0 ),
+ .S(Q[1]));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[5]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[26]),
+ .Q(s_axi_rdata[5]),
+ .R(rst));
+ MUXF8 \s_axi_rdata_i_reg[5]_i_2
+ (.I0(\s_axi_rdata_i_reg[5]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[5]_i_4_n_0 ),
+ .O(\s_axi_rdata_i_reg[5]_i_2_n_0 ),
+ .S(Q[0]));
+ MUXF7 \s_axi_rdata_i_reg[5]_i_3
+ (.I0(\s_axi_rdata_i[5]_i_5_n_0 ),
+ .I1(\s_axi_rdata_i[5]_i_6_n_0 ),
+ .O(\s_axi_rdata_i_reg[5]_i_3_n_0 ),
+ .S(Q[1]));
+ MUXF7 \s_axi_rdata_i_reg[5]_i_4
+ (.I0(\s_axi_rdata_i_reg[5]_i_2_0 ),
+ .I1(\s_axi_rdata_i[5]_i_8_n_0 ),
+ .O(\s_axi_rdata_i_reg[5]_i_4_n_0 ),
+ .S(Q[1]));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[6]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[25]),
+ .Q(s_axi_rdata[6]),
+ .R(rst));
+ MUXF8 \s_axi_rdata_i_reg[6]_i_2
+ (.I0(\s_axi_rdata_i_reg[6]_i_3_n_0 ),
+ .I1(\s_axi_rdata_i_reg[6]_i_4_n_0 ),
+ .O(\s_axi_rdata_i_reg[6]_i_2_n_0 ),
+ .S(Q[0]));
+ MUXF7 \s_axi_rdata_i_reg[6]_i_3
+ (.I0(\s_axi_rdata_i[6]_i_5_n_0 ),
+ .I1(\s_axi_rdata_i[6]_i_6_n_0 ),
+ .O(\s_axi_rdata_i_reg[6]_i_3_n_0 ),
+ .S(Q[1]));
+ MUXF7 \s_axi_rdata_i_reg[6]_i_4
+ (.I0(\s_axi_rdata_i_reg[6]_i_2_0 ),
+ .I1(\s_axi_rdata_i[6]_i_8_n_0 ),
+ .O(\s_axi_rdata_i_reg[6]_i_4_n_0 ),
+ .S(Q[1]));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[7]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Data[24]),
+ .Q(s_axi_rdata[7]),
+ .R(rst));
+ MUXF8 \s_axi_rdata_i_reg[7]_i_2
+ (.I0(\s_axi_rdata_i_reg[7]_i_6_n_0 ),
+ .I1(\s_axi_rdata_i_reg[7]_i_7_n_0 ),
+ .O(\s_axi_rdata_i_reg[7]_i_2_n_0 ),
+ .S(Q[0]));
+ MUXF7 \s_axi_rdata_i_reg[7]_i_6
+ (.I0(\s_axi_rdata_i[7]_i_8_n_0 ),
+ .I1(\s_axi_rdata_i[7]_i_9_n_0 ),
+ .O(\s_axi_rdata_i_reg[7]_i_6_n_0 ),
+ .S(Q[1]));
+ MUXF7 \s_axi_rdata_i_reg[7]_i_7
+ (.I0(\s_axi_rdata_i_reg[7]_i_2_0 ),
+ .I1(\s_axi_rdata_i[7]_i_11_n_0 ),
+ .O(\s_axi_rdata_i_reg[7]_i_7_n_0 ),
+ .S(Q[1]));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[8]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(D[0]),
+ .Q(s_axi_rdata[8]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rdata_i_reg[9]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(D[1]),
+ .Q(s_axi_rdata[9]),
+ .R(rst));
+ FDRE #(
+ .INIT(1'b0))
+ \s_axi_rresp_i_reg[1]
+ (.C(s_axi_aclk),
+ .CE(s_axi_rresp_i),
+ .D(AXI_IP2Bus_Error),
+ .Q(s_axi_rresp),
+ .R(rst));
+ LUT5 #(
+ .INIT(32'h75553000))
+ s_axi_rvalid_i_i_1
+ (.I0(s_axi_rready),
+ .I1(state[1]),
+ .I2(state[0]),
+ .I3(is_read_reg_0),
+ .I4(s_axi_rvalid_i_reg_0),
+ .O(s_axi_rvalid_i_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_rvalid_i_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_rvalid_i_i_1_n_0),
+ .Q(s_axi_rvalid_i_reg_0),
+ .R(rst));
+ (* SOFT_HLUTNM = "soft_lutpair54" *)
+ LUT5 #(
+ .INIT(32'h000F0008))
+ start2_i_1
+ (.I0(s_axi_wvalid),
+ .I1(s_axi_awvalid),
+ .I2(state[0]),
+ .I3(state[1]),
+ .I4(s_axi_arvalid),
+ .O(start2_i_1_n_0));
+ FDRE start2_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(start2_i_1_n_0),
+ .Q(start2),
+ .R(rst));
+ LUT5 #(
+ .INIT(32'hFBF83B38))
+ \state[0]_i_1
+ (.I0(is_write_reg_0),
+ .I1(state[1]),
+ .I2(state[0]),
+ .I3(s_axi_arvalid),
+ .I4(\FSM_onehot_state[3]_i_2_n_0 ),
+ .O(p_0_out[0]));
+ LUT6 #(
+ .INIT(64'hEECFEECC22CF22CC))
+ \state[1]_i_1
+ (.I0(is_read_reg_0),
+ .I1(state[1]),
+ .I2(s_axi_arvalid),
+ .I3(state[0]),
+ .I4(\state[1]_i_2_n_0 ),
+ .I5(\FSM_onehot_state[3]_i_2_n_0 ),
+ .O(p_0_out[1]));
+ (* SOFT_HLUTNM = "soft_lutpair54" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \state[1]_i_2
+ (.I0(s_axi_wvalid),
+ .I1(s_axi_awvalid),
+ .O(\state[1]_i_2_n_0 ));
+ FDRE \state_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(p_0_out[0]),
+ .Q(state[0]),
+ .R(rst));
+ FDRE \state_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(p_0_out[1]),
+ .Q(state[1]),
+ .R(rst));
+endmodule
+
+module TopLevel_axi_iic_0_0_soft_reset
+ (sw_rst_cond_d1,
+ AXI_Bus2IP_Reset,
+ ctrlFifoDin,
+ SR,
+ sw_rst_cond,
+ s_axi_aclk,
+ reset_trig0,
+ s_axi_aresetn,
+ s_axi_wdata,
+ Tx_fifo_rst);
+ output sw_rst_cond_d1;
+ output AXI_Bus2IP_Reset;
+ output [0:1]ctrlFifoDin;
+ output [0:0]SR;
+ input sw_rst_cond;
+ input s_axi_aclk;
+ input reset_trig0;
+ input s_axi_aresetn;
+ input [1:0]s_axi_wdata;
+ input Tx_fifo_rst;
+
+ wire AXI_Bus2IP_Reset;
+ wire \RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ;
+ wire \RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ;
+ wire \RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ;
+ wire \RESET_FLOPS[3].RST_FLOPS_n_0 ;
+ wire S;
+ wire [0:0]SR;
+ wire Tx_fifo_rst;
+ wire [0:1]ctrlFifoDin;
+ wire [1:3]flop_q_chain;
+ wire reset_trig0;
+ wire s_axi_aclk;
+ wire s_axi_aresetn;
+ wire [1:0]s_axi_wdata;
+ wire sw_rst_cond;
+ wire sw_rst_cond_d1;
+
+ (* SOFT_HLUTNM = "soft_lutpair62" *)
+ LUT3 #(
+ .INIT(8'h02))
+ \FIFO_RAM[0].SRL16E_I_i_1
+ (.I0(s_axi_wdata[1]),
+ .I1(SR),
+ .I2(Tx_fifo_rst),
+ .O(ctrlFifoDin[0]));
+ (* SOFT_HLUTNM = "soft_lutpair62" *)
+ LUT3 #(
+ .INIT(8'h02))
+ \FIFO_RAM[1].SRL16E_I_i_1
+ (.I0(s_axi_wdata[0]),
+ .I1(SR),
+ .I2(Tx_fifo_rst),
+ .O(ctrlFifoDin[1]));
+ LUT2 #(
+ .INIT(4'hB))
+ \GPO_GEN.gpo_i[31]_i_1
+ (.I0(\RESET_FLOPS[3].RST_FLOPS_n_0 ),
+ .I1(s_axi_aresetn),
+ .O(SR));
+ (* IS_CE_INVERTED = "1'b0" *)
+ (* IS_S_INVERTED = "1'b0" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \RESET_FLOPS[0].RST_FLOPS
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(S),
+ .Q(flop_q_chain[1]),
+ .R(AXI_Bus2IP_Reset));
+ (* IS_CE_INVERTED = "1'b0" *)
+ (* IS_S_INVERTED = "1'b0" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \RESET_FLOPS[1].RST_FLOPS
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ),
+ .Q(flop_q_chain[2]),
+ .R(AXI_Bus2IP_Reset));
+ (* SOFT_HLUTNM = "soft_lutpair63" *)
+ LUT2 #(
+ .INIT(4'hE))
+ \RESET_FLOPS[1].RST_FLOPS_i_1
+ (.I0(S),
+ .I1(flop_q_chain[1]),
+ .O(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ));
+ (* IS_CE_INVERTED = "1'b0" *)
+ (* IS_S_INVERTED = "1'b0" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \RESET_FLOPS[2].RST_FLOPS
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ),
+ .Q(flop_q_chain[3]),
+ .R(AXI_Bus2IP_Reset));
+ (* SOFT_HLUTNM = "soft_lutpair63" *)
+ LUT2 #(
+ .INIT(4'hE))
+ \RESET_FLOPS[2].RST_FLOPS_i_1
+ (.I0(S),
+ .I1(flop_q_chain[2]),
+ .O(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ));
+ (* IS_CE_INVERTED = "1'b0" *)
+ (* IS_S_INVERTED = "1'b0" *)
+ (* box_type = "PRIMITIVE" *)
+ FDRE #(
+ .INIT(1'b0),
+ .IS_C_INVERTED(1'b0),
+ .IS_D_INVERTED(1'b0),
+ .IS_R_INVERTED(1'b0))
+ \RESET_FLOPS[3].RST_FLOPS
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ),
+ .Q(\RESET_FLOPS[3].RST_FLOPS_n_0 ),
+ .R(AXI_Bus2IP_Reset));
+ LUT2 #(
+ .INIT(4'hE))
+ \RESET_FLOPS[3].RST_FLOPS_i_1
+ (.I0(S),
+ .I1(flop_q_chain[3]),
+ .O(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ));
+ FDRE reset_trig_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(reset_trig0),
+ .Q(S),
+ .R(AXI_Bus2IP_Reset));
+ LUT1 #(
+ .INIT(2'h1))
+ rst_i_1
+ (.I0(s_axi_aresetn),
+ .O(AXI_Bus2IP_Reset));
+ FDRE sw_rst_cond_d1_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(sw_rst_cond),
+ .Q(sw_rst_cond_d1),
+ .R(AXI_Bus2IP_Reset));
+endmodule
+
+module TopLevel_axi_iic_0_0_upcnt_n
+ (\FSM_sequential_scl_state_reg[1] ,
+ \q_int_reg[0]_0 ,
+ Q,
+ \q_int_reg[4]_0 ,
+ CO,
+ scndry_out,
+ \q_int_reg[1]_0 ,
+ \q_int_reg[1]_1 ,
+ \q_int_reg[1]_2 ,
+ arb_lost,
+ \q_int_reg[9]_0 ,
+ s_axi_aclk);
+ output \FSM_sequential_scl_state_reg[1] ;
+ output [9:0]\q_int_reg[0]_0 ;
+ input [3:0]Q;
+ input \q_int_reg[4]_0 ;
+ input [0:0]CO;
+ input scndry_out;
+ input \q_int_reg[1]_0 ;
+ input \q_int_reg[1]_1 ;
+ input [0:0]\q_int_reg[1]_2 ;
+ input arb_lost;
+ input \q_int_reg[9]_0 ;
+ input s_axi_aclk;
+
+ wire [0:0]CO;
+ wire \FSM_sequential_scl_state_reg[1] ;
+ wire [3:0]Q;
+ wire arb_lost;
+ wire [8:0]p_0_in;
+ wire \q_int[0]_i_1__1_n_0 ;
+ wire \q_int[0]_i_2__1_n_0 ;
+ wire \q_int[0]_i_3__1_n_0 ;
+ wire \q_int[0]_i_4_n_0 ;
+ wire \q_int[0]_i_5__0_n_0 ;
+ wire \q_int[0]_i_7_n_0 ;
+ wire \q_int[1]_i_3_n_0 ;
+ wire \q_int[2]_i_2_n_0 ;
+ wire \q_int[3]_i_2_n_0 ;
+ wire \q_int[4]_i_2_n_0 ;
+ wire \q_int[5]_i_2_n_0 ;
+ wire \q_int[6]_i_2_n_0 ;
+ wire \q_int[7]_i_2_n_0 ;
+ wire [9:0]\q_int_reg[0]_0 ;
+ wire \q_int_reg[1]_0 ;
+ wire \q_int_reg[1]_1 ;
+ wire [0:0]\q_int_reg[1]_2 ;
+ wire \q_int_reg[4]_0 ;
+ wire \q_int_reg[9]_0 ;
+ wire s_axi_aclk;
+ wire scndry_out;
+
+ LUT3 #(
+ .INIT(8'h1F))
+ \q_int[0]_i_1__1
+ (.I0(Q[2]),
+ .I1(Q[1]),
+ .I2(Q[3]),
+ .O(\q_int[0]_i_1__1_n_0 ));
+ LUT6 #(
+ .INIT(64'h2020202020222222))
+ \q_int[0]_i_2__1
+ (.I0(\q_int[0]_i_3__1_n_0 ),
+ .I1(\q_int[0]_i_4_n_0 ),
+ .I2(\q_int[0]_i_5__0_n_0 ),
+ .I3(\q_int_reg[4]_0 ),
+ .I4(\FSM_sequential_scl_state_reg[1] ),
+ .I5(\q_int[0]_i_7_n_0 ),
+ .O(\q_int[0]_i_2__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT5 #(
+ .INIT(32'hAAAA6AAA))
+ \q_int[0]_i_3__1
+ (.I0(\q_int_reg[0]_0 [9]),
+ .I1(\q_int_reg[0]_0 [8]),
+ .I2(\q_int_reg[0]_0 [7]),
+ .I3(\q_int_reg[0]_0 [6]),
+ .I4(\q_int[3]_i_2_n_0 ),
+ .O(\q_int[0]_i_3__1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000005500FF0051))
+ \q_int[0]_i_4
+ (.I0(Q[2]),
+ .I1(\q_int_reg[1]_1 ),
+ .I2(\q_int_reg[1]_2 ),
+ .I3(Q[0]),
+ .I4(Q[1]),
+ .I5(Q[3]),
+ .O(\q_int[0]_i_4_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \q_int[0]_i_5__0
+ (.I0(Q[3]),
+ .I1(Q[2]),
+ .O(\q_int[0]_i_5__0_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \q_int[0]_i_6
+ (.I0(Q[1]),
+ .I1(arb_lost),
+ .O(\FSM_sequential_scl_state_reg[1] ));
+ LUT3 #(
+ .INIT(8'h54))
+ \q_int[0]_i_7
+ (.I0(Q[0]),
+ .I1(CO),
+ .I2(scndry_out),
+ .O(\q_int[0]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000445444540000))
+ \q_int[1]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[1]_0 ),
+ .I3(\q_int[0]_i_7_n_0 ),
+ .I4(\q_int[1]_i_3_n_0 ),
+ .I5(\q_int_reg[0]_0 [8]),
+ .O(p_0_in[8]));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \q_int[1]_i_3
+ (.I0(\q_int_reg[0]_0 [7]),
+ .I1(\q_int_reg[0]_0 [6]),
+ .I2(\q_int[3]_i_2_n_0 ),
+ .O(\q_int[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h4454000000004454))
+ \q_int[2]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[1]_0 ),
+ .I3(\q_int[0]_i_7_n_0 ),
+ .I4(\q_int[2]_i_2_n_0 ),
+ .I5(\q_int_reg[0]_0 [7]),
+ .O(p_0_in[7]));
+ LUT2 #(
+ .INIT(4'hB))
+ \q_int[2]_i_2
+ (.I0(\q_int[3]_i_2_n_0 ),
+ .I1(\q_int_reg[0]_0 [6]),
+ .O(\q_int[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h4454000000004454))
+ \q_int[3]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[1]_0 ),
+ .I3(\q_int[0]_i_7_n_0 ),
+ .I4(\q_int[3]_i_2_n_0 ),
+ .I5(\q_int_reg[0]_0 [6]),
+ .O(p_0_in[6]));
+ LUT6 #(
+ .INIT(64'h7FFFFFFFFFFFFFFF))
+ \q_int[3]_i_2
+ (.I0(\q_int_reg[0]_0 [4]),
+ .I1(\q_int_reg[0]_0 [2]),
+ .I2(\q_int_reg[0]_0 [0]),
+ .I3(\q_int_reg[0]_0 [1]),
+ .I4(\q_int_reg[0]_0 [3]),
+ .I5(\q_int_reg[0]_0 [5]),
+ .O(\q_int[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000044444555))
+ \q_int[4]_i_1
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[4]_0 ),
+ .I3(\FSM_sequential_scl_state_reg[1] ),
+ .I4(\q_int[0]_i_7_n_0 ),
+ .I5(\q_int[4]_i_2_n_0 ),
+ .O(p_0_in[5]));
+ LUT6 #(
+ .INIT(64'h9555555555555555))
+ \q_int[4]_i_2
+ (.I0(\q_int_reg[0]_0 [5]),
+ .I1(\q_int_reg[0]_0 [4]),
+ .I2(\q_int_reg[0]_0 [2]),
+ .I3(\q_int_reg[0]_0 [0]),
+ .I4(\q_int_reg[0]_0 [1]),
+ .I5(\q_int_reg[0]_0 [3]),
+ .O(\q_int[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000044444555))
+ \q_int[5]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[4]_0 ),
+ .I3(\FSM_sequential_scl_state_reg[1] ),
+ .I4(\q_int[0]_i_7_n_0 ),
+ .I5(\q_int[5]_i_2_n_0 ),
+ .O(p_0_in[4]));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT5 #(
+ .INIT(32'h95555555))
+ \q_int[5]_i_2
+ (.I0(\q_int_reg[0]_0 [4]),
+ .I1(\q_int_reg[0]_0 [3]),
+ .I2(\q_int_reg[0]_0 [1]),
+ .I3(\q_int_reg[0]_0 [0]),
+ .I4(\q_int_reg[0]_0 [2]),
+ .O(\q_int[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000044444555))
+ \q_int[6]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[4]_0 ),
+ .I3(\FSM_sequential_scl_state_reg[1] ),
+ .I4(\q_int[0]_i_7_n_0 ),
+ .I5(\q_int[6]_i_2_n_0 ),
+ .O(p_0_in[3]));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h9555))
+ \q_int[6]_i_2
+ (.I0(\q_int_reg[0]_0 [3]),
+ .I1(\q_int_reg[0]_0 [2]),
+ .I2(\q_int_reg[0]_0 [0]),
+ .I3(\q_int_reg[0]_0 [1]),
+ .O(\q_int[6]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000044444555))
+ \q_int[7]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[4]_0 ),
+ .I3(\FSM_sequential_scl_state_reg[1] ),
+ .I4(\q_int[0]_i_7_n_0 ),
+ .I5(\q_int[7]_i_2_n_0 ),
+ .O(p_0_in[2]));
+ LUT3 #(
+ .INIT(8'h95))
+ \q_int[7]_i_2
+ (.I0(\q_int_reg[0]_0 [2]),
+ .I1(\q_int_reg[0]_0 [1]),
+ .I2(\q_int_reg[0]_0 [0]),
+ .O(\q_int[7]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000445444540000))
+ \q_int[8]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[1]_0 ),
+ .I3(\q_int[0]_i_7_n_0 ),
+ .I4(\q_int_reg[0]_0 [1]),
+ .I5(\q_int_reg[0]_0 [0]),
+ .O(p_0_in[1]));
+ LUT6 #(
+ .INIT(64'h0000000044444555))
+ \q_int[9]_i_1__0
+ (.I0(\q_int[0]_i_4_n_0 ),
+ .I1(\q_int[0]_i_5__0_n_0 ),
+ .I2(\q_int_reg[4]_0 ),
+ .I3(\FSM_sequential_scl_state_reg[1] ),
+ .I4(\q_int[0]_i_7_n_0 ),
+ .I5(\q_int_reg[0]_0 [0]),
+ .O(p_0_in[0]));
+ FDRE \q_int_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(\q_int[0]_i_2__1_n_0 ),
+ .Q(\q_int_reg[0]_0 [9]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[8]),
+ .Q(\q_int_reg[0]_0 [8]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[7]),
+ .Q(\q_int_reg[0]_0 [7]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[6]),
+ .Q(\q_int_reg[0]_0 [6]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[4]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[5]),
+ .Q(\q_int_reg[0]_0 [5]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[5]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[4]),
+ .Q(\q_int_reg[0]_0 [4]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[6]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[3]),
+ .Q(\q_int_reg[0]_0 [3]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[7]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[2]),
+ .Q(\q_int_reg[0]_0 [2]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[8]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[1]),
+ .Q(\q_int_reg[0]_0 [1]),
+ .R(\q_int_reg[9]_0 ));
+ FDRE \q_int_reg[9]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__1_n_0 ),
+ .D(p_0_in[0]),
+ .Q(\q_int_reg[0]_0 [0]),
+ .R(\q_int_reg[9]_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "upcnt_n" *)
+module TopLevel_axi_iic_0_0_upcnt_n_2
+ (gen_stop_d1_reg,
+ Q,
+ sda_setup,
+ gen_stop_d1,
+ gen_stop,
+ \q_int[0]_i_3_0 ,
+ rsta_d1,
+ tx_under_prev_d1,
+ \q_int[0]_i_3_1 ,
+ \q_int[0]_i_3_2 ,
+ \q_int[0]_i_3_3 ,
+ \q_int_reg[0]_0 ,
+ s_axi_aclk);
+ output gen_stop_d1_reg;
+ output [9:0]Q;
+ input sda_setup;
+ input gen_stop_d1;
+ input gen_stop;
+ input [0:0]\q_int[0]_i_3_0 ;
+ input rsta_d1;
+ input tx_under_prev_d1;
+ input \q_int[0]_i_3_1 ;
+ input \q_int[0]_i_3_2 ;
+ input \q_int[0]_i_3_3 ;
+ input \q_int_reg[0]_0 ;
+ input s_axi_aclk;
+
+ wire [9:0]Q;
+ wire gen_stop;
+ wire gen_stop_d1;
+ wire gen_stop_d1_reg;
+ wire [9:0]p_0_in__0;
+ wire \q_int[0]_i_1_n_0 ;
+ wire [0:0]\q_int[0]_i_3_0 ;
+ wire \q_int[0]_i_3_1 ;
+ wire \q_int[0]_i_3_2 ;
+ wire \q_int[0]_i_3_3 ;
+ wire \q_int[0]_i_4__0_n_0 ;
+ wire \q_int[0]_i_5_n_0 ;
+ wire \q_int[1]_i_1__1_n_0 ;
+ wire \q_int[2]_i_1__1_n_0 ;
+ wire \q_int[3]_i_1__1_n_0 ;
+ wire \q_int[4]_i_1__0_n_0 ;
+ wire \q_int[4]_i_2__0_n_0 ;
+ wire \q_int_reg[0]_0 ;
+ wire rsta_d1;
+ wire s_axi_aclk;
+ wire sda_setup;
+ wire tx_under_prev_d1;
+
+ LUT2 #(
+ .INIT(4'hE))
+ \q_int[0]_i_1
+ (.I0(sda_setup),
+ .I1(gen_stop_d1_reg),
+ .O(\q_int[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000BFFF4000))
+ \q_int[0]_i_2
+ (.I0(\q_int[0]_i_4__0_n_0 ),
+ .I1(Q[6]),
+ .I2(Q[7]),
+ .I3(Q[8]),
+ .I4(Q[9]),
+ .I5(gen_stop_d1_reg),
+ .O(p_0_in__0[9]));
+ LUT3 #(
+ .INIT(8'hF4))
+ \q_int[0]_i_3
+ (.I0(gen_stop_d1),
+ .I1(gen_stop),
+ .I2(\q_int[0]_i_5_n_0 ),
+ .O(gen_stop_d1_reg));
+ LUT6 #(
+ .INIT(64'h7FFFFFFFFFFFFFFF))
+ \q_int[0]_i_4__0
+ (.I0(Q[4]),
+ .I1(Q[2]),
+ .I2(Q[0]),
+ .I3(Q[1]),
+ .I4(Q[3]),
+ .I5(Q[5]),
+ .O(\q_int[0]_i_4__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h22F2FFFFFFFF22F2))
+ \q_int[0]_i_5
+ (.I0(\q_int[0]_i_3_0 ),
+ .I1(rsta_d1),
+ .I2(tx_under_prev_d1),
+ .I3(\q_int[0]_i_3_1 ),
+ .I4(\q_int[0]_i_3_2 ),
+ .I5(\q_int[0]_i_3_3 ),
+ .O(\q_int[0]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT5 #(
+ .INIT(32'h55150040))
+ \q_int[1]_i_1__1
+ (.I0(gen_stop_d1_reg),
+ .I1(Q[7]),
+ .I2(Q[6]),
+ .I3(\q_int[0]_i_4__0_n_0 ),
+ .I4(Q[8]),
+ .O(\q_int[1]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT4 #(
+ .INIT(16'h4510))
+ \q_int[2]_i_1__1
+ (.I0(gen_stop_d1_reg),
+ .I1(\q_int[0]_i_4__0_n_0 ),
+ .I2(Q[6]),
+ .I3(Q[7]),
+ .O(\q_int[2]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'h41))
+ \q_int[3]_i_1__1
+ (.I0(gen_stop_d1_reg),
+ .I1(\q_int[0]_i_4__0_n_0 ),
+ .I2(Q[6]),
+ .O(\q_int[3]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'h41))
+ \q_int[4]_i_1__0
+ (.I0(gen_stop_d1_reg),
+ .I1(\q_int[4]_i_2__0_n_0 ),
+ .I2(Q[5]),
+ .O(\q_int[4]_i_1__0_n_0 ));
+ LUT5 #(
+ .INIT(32'h7FFFFFFF))
+ \q_int[4]_i_2__0
+ (.I0(Q[3]),
+ .I1(Q[1]),
+ .I2(Q[0]),
+ .I3(Q[2]),
+ .I4(Q[4]),
+ .O(\q_int[4]_i_2__0_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000007FFF8000))
+ \q_int[5]_i_1
+ (.I0(Q[2]),
+ .I1(Q[0]),
+ .I2(Q[1]),
+ .I3(Q[3]),
+ .I4(Q[4]),
+ .I5(gen_stop_d1_reg),
+ .O(p_0_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT5 #(
+ .INIT(32'h00007F80))
+ \q_int[6]_i_1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(Q[2]),
+ .I3(Q[3]),
+ .I4(gen_stop_d1_reg),
+ .O(p_0_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT4 #(
+ .INIT(16'h0078))
+ \q_int[7]_i_1
+ (.I0(Q[0]),
+ .I1(Q[1]),
+ .I2(Q[2]),
+ .I3(gen_stop_d1_reg),
+ .O(p_0_in__0[2]));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'h06))
+ \q_int[8]_i_1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(gen_stop_d1_reg),
+ .O(p_0_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT2 #(
+ .INIT(4'h1))
+ \q_int[9]_i_1
+ (.I0(Q[0]),
+ .I1(gen_stop_d1_reg),
+ .O(p_0_in__0[0]));
+ FDRE \q_int_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[9]),
+ .Q(Q[9]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(\q_int[1]_i_1__1_n_0 ),
+ .Q(Q[8]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(\q_int[2]_i_1__1_n_0 ),
+ .Q(Q[7]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(\q_int[3]_i_1__1_n_0 ),
+ .Q(Q[6]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[4]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(\q_int[4]_i_1__0_n_0 ),
+ .Q(Q[5]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[5]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[4]),
+ .Q(Q[4]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[6]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[3]),
+ .Q(Q[3]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[7]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[2]),
+ .Q(Q[2]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[8]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[1]),
+ .Q(Q[1]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[9]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1_n_0 ),
+ .D(p_0_in__0[0]),
+ .Q(Q[0]),
+ .R(\q_int_reg[0]_0 ));
+endmodule
+
+(* ORIG_REF_NAME = "upcnt_n" *)
+module TopLevel_axi_iic_0_0_upcnt_n__parameterized0
+ (EarlyAckDataState0,
+ \q_int_reg[1]_0 ,
+ \FSM_sequential_state_reg[2] ,
+ \FSM_sequential_state_reg[1] ,
+ \FSM_sequential_state_reg[0] ,
+ detect_start,
+ state__0,
+ bit_cnt_en,
+ \FSM_sequential_state_reg[0]_0 ,
+ EarlyAckDataState_reg,
+ EarlyAckDataState_reg_0,
+ scl_falling_edge,
+ dtc_i_reg,
+ \FSM_sequential_state_reg[2]_0 ,
+ \FSM_sequential_state_reg[2]_1 ,
+ state0,
+ \FSM_sequential_state_reg[1]_0 ,
+ Q,
+ \FSM_sequential_state_reg[1]_1 ,
+ \FSM_sequential_state_reg[0]_1 ,
+ \q_int_reg[0]_0 ,
+ s_axi_aclk);
+ output EarlyAckDataState0;
+ output \q_int_reg[1]_0 ;
+ output \FSM_sequential_state_reg[2] ;
+ output \FSM_sequential_state_reg[1] ;
+ output \FSM_sequential_state_reg[0] ;
+ input detect_start;
+ input [2:0]state__0;
+ input bit_cnt_en;
+ input \FSM_sequential_state_reg[0]_0 ;
+ input EarlyAckDataState_reg;
+ input EarlyAckDataState_reg_0;
+ input scl_falling_edge;
+ input dtc_i_reg;
+ input \FSM_sequential_state_reg[2]_0 ;
+ input \FSM_sequential_state_reg[2]_1 ;
+ input state0;
+ input \FSM_sequential_state_reg[1]_0 ;
+ input [0:0]Q;
+ input \FSM_sequential_state_reg[1]_1 ;
+ input \FSM_sequential_state_reg[0]_1 ;
+ input \q_int_reg[0]_0 ;
+ input s_axi_aclk;
+
+ wire EarlyAckDataState0;
+ wire EarlyAckDataState_reg;
+ wire EarlyAckDataState_reg_0;
+ wire \FSM_sequential_state[2]_i_2_n_0 ;
+ wire \FSM_sequential_state[2]_i_6_n_0 ;
+ wire \FSM_sequential_state_reg[0] ;
+ wire \FSM_sequential_state_reg[0]_0 ;
+ wire \FSM_sequential_state_reg[0]_1 ;
+ wire \FSM_sequential_state_reg[1] ;
+ wire \FSM_sequential_state_reg[1]_0 ;
+ wire \FSM_sequential_state_reg[1]_1 ;
+ wire \FSM_sequential_state_reg[2] ;
+ wire \FSM_sequential_state_reg[2]_0 ;
+ wire \FSM_sequential_state_reg[2]_1 ;
+ wire [0:0]Q;
+ wire [3:0]bit_cnt;
+ wire bit_cnt_en;
+ wire detect_start;
+ wire dtc_i_reg;
+ wire \q_int[0]_i_1__0_n_0 ;
+ wire \q_int[0]_i_2__0_n_0 ;
+ wire \q_int[0]_i_3__0_n_0 ;
+ wire \q_int[1]_i_1_n_0 ;
+ wire \q_int[2]_i_1_n_0 ;
+ wire \q_int[3]_i_1_n_0 ;
+ wire \q_int_reg[0]_0 ;
+ wire \q_int_reg[1]_0 ;
+ wire s_axi_aclk;
+ wire scl_falling_edge;
+ wire state0;
+ wire [2:0]state__0;
+
+ LUT6 #(
+ .INIT(64'hAAAAAAAABAAAAAAE))
+ EarlyAckDataState_i_1
+ (.I0(EarlyAckDataState_reg),
+ .I1(bit_cnt[3]),
+ .I2(bit_cnt[1]),
+ .I3(bit_cnt[0]),
+ .I4(bit_cnt[2]),
+ .I5(EarlyAckDataState_reg_0),
+ .O(EarlyAckDataState0));
+ LUT5 #(
+ .INIT(32'h0000E200))
+ \FSM_sequential_state[0]_i_1
+ (.I0(state__0[0]),
+ .I1(\FSM_sequential_state[2]_i_2_n_0 ),
+ .I2(\FSM_sequential_state_reg[0]_1 ),
+ .I3(Q),
+ .I4(\FSM_sequential_state_reg[1]_1 ),
+ .O(\FSM_sequential_state_reg[0] ));
+ LUT5 #(
+ .INIT(32'h0000E200))
+ \FSM_sequential_state[1]_i_1
+ (.I0(state__0[1]),
+ .I1(\FSM_sequential_state[2]_i_2_n_0 ),
+ .I2(\FSM_sequential_state_reg[1]_0 ),
+ .I3(Q),
+ .I4(\FSM_sequential_state_reg[1]_1 ),
+ .O(\FSM_sequential_state_reg[1] ));
+ LUT6 #(
+ .INIT(64'h00000000EEE222E2))
+ \FSM_sequential_state[2]_i_1
+ (.I0(state__0[2]),
+ .I1(\FSM_sequential_state[2]_i_2_n_0 ),
+ .I2(\FSM_sequential_state_reg[2]_0 ),
+ .I3(state__0[0]),
+ .I4(\FSM_sequential_state_reg[2]_1 ),
+ .I5(state0),
+ .O(\FSM_sequential_state_reg[2] ));
+ LUT6 #(
+ .INIT(64'h0000000033FEBAFC))
+ \FSM_sequential_state[2]_i_2
+ (.I0(\FSM_sequential_state[2]_i_6_n_0 ),
+ .I1(state__0[0]),
+ .I2(detect_start),
+ .I3(state__0[2]),
+ .I4(state__0[1]),
+ .I5(\FSM_sequential_state_reg[0]_0 ),
+ .O(\FSM_sequential_state[2]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'h0010))
+ \FSM_sequential_state[2]_i_6
+ (.I0(bit_cnt[1]),
+ .I1(bit_cnt[0]),
+ .I2(bit_cnt[3]),
+ .I3(bit_cnt[2]),
+ .O(\FSM_sequential_state[2]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'h0080FFFF00800000))
+ dtc_i_i_1
+ (.I0(bit_cnt[2]),
+ .I1(bit_cnt[0]),
+ .I2(bit_cnt[1]),
+ .I3(bit_cnt[3]),
+ .I4(scl_falling_edge),
+ .I5(dtc_i_reg),
+ .O(\q_int_reg[1]_0 ));
+ LUT5 #(
+ .INIT(32'hEFEFFEEF))
+ \q_int[0]_i_1__0
+ (.I0(bit_cnt_en),
+ .I1(detect_start),
+ .I2(state__0[2]),
+ .I3(state__0[1]),
+ .I4(state__0[0]),
+ .O(\q_int[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'h2AAA8000))
+ \q_int[0]_i_2__0
+ (.I0(\q_int[0]_i_3__0_n_0 ),
+ .I1(bit_cnt[1]),
+ .I2(bit_cnt[0]),
+ .I3(bit_cnt[2]),
+ .I4(bit_cnt[3]),
+ .O(\q_int[0]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h00B4))
+ \q_int[0]_i_3__0
+ (.I0(state__0[0]),
+ .I1(state__0[1]),
+ .I2(state__0[2]),
+ .I3(detect_start),
+ .O(\q_int[0]_i_3__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT4 #(
+ .INIT(16'h2A80))
+ \q_int[1]_i_1
+ (.I0(\q_int[0]_i_3__0_n_0 ),
+ .I1(bit_cnt[0]),
+ .I2(bit_cnt[1]),
+ .I3(bit_cnt[2]),
+ .O(\q_int[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000441444140000))
+ \q_int[2]_i_1
+ (.I0(detect_start),
+ .I1(state__0[2]),
+ .I2(state__0[1]),
+ .I3(state__0[0]),
+ .I4(bit_cnt[0]),
+ .I5(bit_cnt[1]),
+ .O(\q_int[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT5 #(
+ .INIT(32'h00004414))
+ \q_int[3]_i_1
+ (.I0(detect_start),
+ .I1(state__0[2]),
+ .I2(state__0[1]),
+ .I3(state__0[0]),
+ .I4(bit_cnt[0]),
+ .O(\q_int[3]_i_1_n_0 ));
+ FDRE \q_int_reg[0]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__0_n_0 ),
+ .D(\q_int[0]_i_2__0_n_0 ),
+ .Q(bit_cnt[3]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[1]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__0_n_0 ),
+ .D(\q_int[1]_i_1_n_0 ),
+ .Q(bit_cnt[2]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[2]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__0_n_0 ),
+ .D(\q_int[2]_i_1_n_0 ),
+ .Q(bit_cnt[1]),
+ .R(\q_int_reg[0]_0 ));
+ FDRE \q_int_reg[3]
+ (.C(s_axi_aclk),
+ .CE(\q_int[0]_i_1__0_n_0 ),
+ .D(\q_int[3]_i_1_n_0 ),
+ .Q(bit_cnt[0]),
+ .R(\q_int_reg[0]_0 ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.vhdl
new file mode 100644
index 0000000..40f49ea
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_sim_netlist.vhdl
@@ -0,0 +1,12192 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Mon Oct 14 17:13:30 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim -rename_top TopLevel_axi_iic_0_0 -prefix
+-- TopLevel_axi_iic_0_0_ TopLevel_axi_iic_0_0_sim_netlist.vhdl
+-- Design : TopLevel_axi_iic_0_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_SRL_FIFO is
+ port (
+ Rc_Data_Exists : out STD_LOGIC;
+ Rc_addr : out STD_LOGIC_VECTOR ( 0 to 3 );
+ Rc_fifo_data : out STD_LOGIC_VECTOR ( 0 to 7 );
+ msms_set_i_reg : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \Addr_Counters[1].FDRE_I_0\ : out STD_LOGIC;
+ Bus2IIC_Reset : in STD_LOGIC;
+ D_0 : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ \s_axi_rdata_i[7]_i_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ Msms_set : in STD_LOGIC;
+ \Addr_Counters[0].FDRE_I_0\ : in STD_LOGIC;
+ \Addr_Counters[0].FDRE_I_1\ : in STD_LOGIC;
+ Rc_fifo_rd : in STD_LOGIC;
+ Rc_fifo_rd_d : in STD_LOGIC;
+ Rc_fifo_wr_d : in STD_LOGIC;
+ Rc_fifo_wr : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_SRL_FIFO;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_SRL_FIFO is
+ signal \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[3].XORCY_I_i_1__1_n_0\ : STD_LOGIC;
+ signal CI : STD_LOGIC;
+ signal \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\ : STD_LOGIC;
+ signal \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\ : STD_LOGIC;
+ signal \^rc_data_exists\ : STD_LOGIC;
+ signal \^rc_addr\ : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal S : STD_LOGIC;
+ signal S0_out : STD_LOGIC;
+ signal S1_out : STD_LOGIC;
+ signal addr_cy_1 : STD_LOGIC;
+ signal addr_cy_2 : STD_LOGIC;
+ signal addr_cy_3 : STD_LOGIC;
+ signal sum_A_0 : STD_LOGIC;
+ signal sum_A_1 : STD_LOGIC;
+ signal sum_A_2 : STD_LOGIC;
+ signal sum_A_3 : STD_LOGIC;
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute box_type : string;
+ attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
+ attribute OPT_MODIFIED : string;
+ attribute OPT_MODIFIED of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "MLO";
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
+ attribute XILINX_TRANSFORM_PINMAP : string;
+ attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
+ attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
+ attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
+ attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \Data_Exists_DFF_i_2__0\ : label is "soft_lutpair30";
+ attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name : string;
+ attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[0].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[1].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[2].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[3].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[4].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[5].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[6].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[7].SRL16E_I ";
+ attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.ro_prev_i_i_3\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \sr_i[1]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \sr_i[2]_i_1\ : label is "soft_lutpair30";
+begin
+ Rc_Data_Exists <= \^rc_data_exists\;
+ Rc_addr(0 to 3) <= \^rc_addr\(0 to 3);
+\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^rc_data_exists\,
+ D => sum_A_3,
+ Q => \^rc_addr\(0),
+ R => Bus2IIC_Reset
+ );
+\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
+ CO(2) => addr_cy_1,
+ CO(1) => addr_cy_2,
+ CO(0) => addr_cy_3,
+ CYINIT => CI,
+ DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
+ DI(2) => \^rc_addr\(2),
+ DI(1) => \^rc_addr\(1),
+ DI(0) => \^rc_addr\(0),
+ O(3) => sum_A_0,
+ O(2) => sum_A_1,
+ O(1) => sum_A_2,
+ O(0) => sum_A_3,
+ S(3) => \Addr_Counters[3].XORCY_I_i_1__1_n_0\,
+ S(2) => S0_out,
+ S(1) => S1_out,
+ S(0) => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A208"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
+ I1 => Rc_fifo_rd,
+ I2 => Rc_fifo_rd_d,
+ I3 => \^rc_addr\(0),
+ O => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF7FFF00000000"
+ )
+ port map (
+ I0 => \^rc_addr\(1),
+ I1 => \^rc_addr\(2),
+ I2 => \^rc_addr\(3),
+ I3 => \^rc_addr\(0),
+ I4 => \Addr_Counters[0].FDRE_I_0\,
+ I5 => \Addr_Counters[0].FDRE_I_1\,
+ O => CI
+ );
+\Addr_Counters[0].MUXCY_L_I_i_3__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFF4"
+ )
+ port map (
+ I0 => Rc_fifo_wr_d,
+ I1 => Rc_fifo_wr,
+ I2 => \^rc_addr\(0),
+ I3 => \^rc_addr\(3),
+ I4 => \^rc_addr\(2),
+ I5 => \^rc_addr\(1),
+ O => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\
+ );
+\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^rc_data_exists\,
+ D => sum_A_2,
+ Q => \^rc_addr\(1),
+ R => Bus2IIC_Reset
+ );
+\Addr_Counters[1].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A208"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
+ I1 => Rc_fifo_rd,
+ I2 => Rc_fifo_rd_d,
+ I3 => \^rc_addr\(1),
+ O => S1_out
+ );
+\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^rc_data_exists\,
+ D => sum_A_1,
+ Q => \^rc_addr\(2),
+ R => Bus2IIC_Reset
+ );
+\Addr_Counters[2].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A208"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
+ I1 => Rc_fifo_rd,
+ I2 => Rc_fifo_rd_d,
+ I3 => \^rc_addr\(2),
+ O => S0_out
+ );
+\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^rc_data_exists\,
+ D => sum_A_0,
+ Q => \^rc_addr\(3),
+ R => Bus2IIC_Reset
+ );
+\Addr_Counters[3].XORCY_I_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A208"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
+ I1 => Rc_fifo_rd,
+ I2 => Rc_fifo_rd_d,
+ I3 => \^rc_addr\(3),
+ O => \Addr_Counters[3].XORCY_I_i_1__1_n_0\
+ );
+Data_Exists_DFF: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => D_0,
+ Q => \^rc_data_exists\,
+ R => Bus2IIC_Reset
+ );
+\Data_Exists_DFF_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \^rc_addr\(1),
+ I1 => \^rc_addr\(2),
+ I2 => \^rc_addr\(3),
+ I3 => \^rc_addr\(0),
+ O => \Addr_Counters[1].FDRE_I_0\
+ );
+\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(7),
+ Q => Rc_fifo_data(0)
+ );
+\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(6),
+ Q => Rc_fifo_data(1)
+ );
+\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(5),
+ Q => Rc_fifo_data(2)
+ );
+\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(4),
+ Q => Rc_fifo_data(3)
+ );
+\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(3),
+ Q => Rc_fifo_data(4)
+ );
+\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(2),
+ Q => Rc_fifo_data(5)
+ );
+\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(1),
+ Q => Rc_fifo_data(6)
+ );
+\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^rc_addr\(0),
+ A1 => \^rc_addr\(1),
+ A2 => \^rc_addr\(2),
+ A3 => \^rc_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => \s_axi_rdata_i[7]_i_11\(0),
+ Q => Rc_fifo_data(7)
+ );
+\RD_FIFO_CNTRL.ro_prev_i_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0001000000000001"
+ )
+ port map (
+ I0 => Bus2IIC_Reset,
+ I1 => Msms_set,
+ I2 => \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\,
+ I3 => \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\,
+ I4 => Q(3),
+ I5 => \^rc_addr\(3),
+ O => msms_set_i_reg
+ );
+\RD_FIFO_CNTRL.ro_prev_i_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6FF6"
+ )
+ port map (
+ I0 => \^rc_addr\(1),
+ I1 => Q(1),
+ I2 => \^rc_addr\(2),
+ I3 => Q(2),
+ O => \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\
+ );
+\RD_FIFO_CNTRL.ro_prev_i_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6F"
+ )
+ port map (
+ I0 => \^rc_addr\(0),
+ I1 => Q(0),
+ I2 => \^rc_data_exists\,
+ O => \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\
+ );
+\sr_i[1]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^rc_data_exists\,
+ O => D(1)
+ );
+\sr_i[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^rc_addr\(1),
+ I1 => \^rc_addr\(2),
+ I2 => \^rc_addr\(3),
+ I3 => \^rc_addr\(0),
+ O => D(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_SRL_FIFO_0 is
+ port (
+ Tx_data_exists : out STD_LOGIC;
+ Tx_addr : out STD_LOGIC_VECTOR ( 0 to 3 );
+ Tx_fifo_data : out STD_LOGIC_VECTOR ( 0 to 7 );
+ \Addr_Counters[0].FDRE_I_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Data_Exists_DFF_0 : out STD_LOGIC;
+ p_0_in : out STD_LOGIC;
+ Data_Exists_DFF_1 : out STD_LOGIC;
+ shift_reg_ld_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Tx_fifo_rst : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ Data_Exists_DFF_2 : in STD_LOGIC;
+ \Addr_Counters[0].FDRE_I_1\ : in STD_LOGIC;
+ Tx_fifo_wr : in STD_LOGIC;
+ Tx_fifo_wr_d : in STD_LOGIC;
+ rdCntrFrmTxFifo : in STD_LOGIC;
+ Tx_fifo_rd_d : in STD_LOGIC;
+ Tx_fifo_rd : in STD_LOGIC;
+ dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
+ shift_reg_ld : in STD_LOGIC;
+ \data_int_reg[0]\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_axi_iic_0_0_SRL_FIFO_0 : entity is "SRL_FIFO";
+end TopLevel_axi_iic_0_0_SRL_FIFO_0;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_SRL_FIFO_0 is
+ signal \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[3].XORCY_I_i_1__0_n_0\ : STD_LOGIC;
+ signal CI : STD_LOGIC;
+ signal D : STD_LOGIC;
+ signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
+ signal S : STD_LOGIC;
+ signal S0_out : STD_LOGIC;
+ signal S1_out : STD_LOGIC;
+ signal \^tx_addr\ : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal \^tx_data_exists\ : STD_LOGIC;
+ signal \^tx_fifo_data\ : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal addr_cy_1 : STD_LOGIC;
+ signal addr_cy_2 : STD_LOGIC;
+ signal addr_cy_3 : STD_LOGIC;
+ signal sum_A_0 : STD_LOGIC;
+ signal sum_A_1 : STD_LOGIC;
+ signal sum_A_2 : STD_LOGIC;
+ signal sum_A_3 : STD_LOGIC;
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute box_type : string;
+ attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
+ attribute OPT_MODIFIED : string;
+ attribute OPT_MODIFIED of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "MLO";
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
+ attribute XILINX_TRANSFORM_PINMAP : string;
+ attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
+ attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
+ attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
+ attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \Data_Exists_DFF_i_1__0\ : label is "soft_lutpair36";
+ attribute SOFT_HLUTNM of Data_Exists_DFF_i_3 : label is "soft_lutpair37";
+ attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name : string;
+ attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[0].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[1].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[2].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[3].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[4].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[5].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[6].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[7].SRL16E_I ";
+ attribute SOFT_HLUTNM of \sr_i[0]_i_1\ : label is "soft_lutpair36";
+ attribute SOFT_HLUTNM of \sr_i[3]_i_1\ : label is "soft_lutpair37";
+begin
+ Tx_addr(0 to 3) <= \^tx_addr\(0 to 3);
+ Tx_data_exists <= \^tx_data_exists\;
+ Tx_fifo_data(0 to 7) <= \^tx_fifo_data\(0 to 7);
+\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^tx_data_exists\,
+ D => sum_A_3,
+ Q => \^tx_addr\(0),
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
+ CO(2) => addr_cy_1,
+ CO(1) => addr_cy_2,
+ CO(0) => addr_cy_3,
+ CYINIT => CI,
+ DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
+ DI(2) => \^tx_addr\(2),
+ DI(1) => \^tx_addr\(1),
+ DI(0) => \^tx_addr\(0),
+ O(3) => sum_A_0,
+ O(2) => sum_A_1,
+ O(1) => sum_A_2,
+ O(0) => sum_A_3,
+ S(3) => \Addr_Counters[3].XORCY_I_i_1__0_n_0\,
+ S(2) => S0_out,
+ S(1) => S1_out,
+ S(0) => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \^tx_addr\(0),
+ O => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_2__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF00000000"
+ )
+ port map (
+ I0 => Data_Exists_DFF_2,
+ I1 => \^tx_addr\(0),
+ I2 => \^tx_addr\(3),
+ I3 => \^tx_addr\(2),
+ I4 => \^tx_addr\(1),
+ I5 => \Addr_Counters[0].FDRE_I_1\,
+ O => CI
+ );
+\Addr_Counters[0].MUXCY_L_I_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFF4"
+ )
+ port map (
+ I0 => Tx_fifo_wr_d,
+ I1 => Tx_fifo_wr,
+ I2 => \^tx_addr\(1),
+ I3 => \^tx_addr\(2),
+ I4 => \^tx_addr\(3),
+ I5 => \^tx_addr\(0),
+ O => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\
+ );
+\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^tx_data_exists\,
+ D => sum_A_2,
+ Q => \^tx_addr\(1),
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[1].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \^tx_addr\(1),
+ O => S1_out
+ );
+\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^tx_data_exists\,
+ D => sum_A_1,
+ Q => \^tx_addr\(2),
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[2].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \^tx_addr\(2),
+ O => S0_out
+ );
+\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^tx_data_exists\,
+ D => sum_A_0,
+ Q => \^tx_addr\(3),
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[3].XORCY_I_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \^tx_addr\(3),
+ O => \Addr_Counters[3].XORCY_I_i_1__0_n_0\
+ );
+Data_Exists_DFF: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => D,
+ Q => \^tx_data_exists\,
+ R => Tx_fifo_rst
+ );
+\Data_Exists_DFF_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFF20022"
+ )
+ port map (
+ I0 => Tx_fifo_wr,
+ I1 => Tx_fifo_wr_d,
+ I2 => Data_Exists_DFF_2,
+ I3 => Data_Exists_DFF_i_3_n_0,
+ I4 => \^tx_data_exists\,
+ O => D
+ );
+Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \^tx_addr\(0),
+ I1 => \^tx_addr\(3),
+ I2 => \^tx_addr\(2),
+ I3 => \^tx_addr\(1),
+ O => Data_Exists_DFF_i_3_n_0
+ );
+\FIFO_GEN_DTR.IIC2Bus_IntrEvent[7]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^tx_addr\(3),
+ O => p_0_in
+ );
+\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(7),
+ Q => \^tx_fifo_data\(0)
+ );
+\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(6),
+ Q => \^tx_fifo_data\(1)
+ );
+\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(5),
+ Q => \^tx_fifo_data\(2)
+ );
+\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(4),
+ Q => \^tx_fifo_data\(3)
+ );
+\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(3),
+ Q => \^tx_fifo_data\(4)
+ );
+\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(2),
+ Q => \^tx_fifo_data\(5)
+ );
+\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(1),
+ Q => \^tx_fifo_data\(6)
+ );
+\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \^tx_addr\(0),
+ A1 => \^tx_addr\(1),
+ A2 => \^tx_addr\(2),
+ A3 => \^tx_addr\(3),
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => s_axi_wdata(0),
+ Q => \^tx_fifo_data\(7)
+ );
+\cr_i[5]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \^tx_data_exists\,
+ I1 => dynamic_MSMS(0),
+ O => Data_Exists_DFF_1
+ );
+\data_int[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^tx_fifo_data\(7),
+ I1 => shift_reg_ld,
+ I2 => \data_int_reg[0]\,
+ O => shift_reg_ld_reg(0)
+ );
+\sr_i[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^tx_data_exists\,
+ O => Data_Exists_DFF_0
+ );
+\sr_i[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^tx_addr\(0),
+ I1 => \^tx_addr\(3),
+ I2 => \^tx_addr\(2),
+ I3 => \^tx_addr\(1),
+ O => \Addr_Counters[0].FDRE_I_0\(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0\ is
+ port (
+ Data_Exists_DFF_0 : out STD_LOGIC;
+ dynamic_MSMS : out STD_LOGIC_VECTOR ( 0 to 1 );
+ Data_Exists_DFF_1 : out STD_LOGIC;
+ \Addr_Counters[1].FDRE_I_0\ : out STD_LOGIC;
+ Tx_fifo_rst : in STD_LOGIC;
+ D : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ ctrlFifoDin : in STD_LOGIC_VECTOR ( 0 to 1 );
+ rdCntrFrmTxFifo : in STD_LOGIC;
+ Tx_fifo_rd_d : in STD_LOGIC;
+ Tx_fifo_rd : in STD_LOGIC;
+ \Addr_Counters[0].FDRE_I_0\ : in STD_LOGIC;
+ \Addr_Counters[0].FDRE_I_1\ : in STD_LOGIC;
+ Tx_data_exists : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0\ : entity is "SRL_FIFO";
+end \TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0\;
+
+architecture STRUCTURE of \TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0\ is
+ signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[0].MUXCY_L_I_i_3_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
+ signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
+ signal CI : STD_LOGIC;
+ signal \^data_exists_dff_0\ : STD_LOGIC;
+ signal S : STD_LOGIC;
+ signal S0_out : STD_LOGIC;
+ signal S1_out : STD_LOGIC;
+ signal addr_cy_1 : STD_LOGIC;
+ signal addr_cy_2 : STD_LOGIC;
+ signal addr_cy_3 : STD_LOGIC;
+ signal \^dynamic_msms\ : STD_LOGIC_VECTOR ( 0 to 1 );
+ signal sum_A_0 : STD_LOGIC;
+ signal sum_A_1 : STD_LOGIC;
+ signal sum_A_2 : STD_LOGIC;
+ signal sum_A_3 : STD_LOGIC;
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ attribute box_type : string;
+ attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
+ attribute OPT_MODIFIED : string;
+ attribute OPT_MODIFIED of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "MLO";
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
+ attribute XILINX_TRANSFORM_PINMAP : string;
+ attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
+ attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \Addr_Counters[0].MUXCY_L_I_i_3\ : label is "soft_lutpair35";
+ attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
+ attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
+ attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
+ attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM of \Data_Exists_DFF_i_3__0\ : label is "soft_lutpair35";
+ attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name : string;
+ attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM ";
+ attribute srl_name : string;
+ attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[0].SRL16E_I ";
+ attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
+ attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM ";
+ attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[1].SRL16E_I ";
+begin
+ Data_Exists_DFF_0 <= \^data_exists_dff_0\;
+ dynamic_MSMS(0 to 1) <= \^dynamic_msms\(0 to 1);
+\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^data_exists_dff_0\,
+ D => sum_A_3,
+ Q => \Addr_Counters[0].FDRE_I_n_0\,
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
+ CO(2) => addr_cy_1,
+ CO(1) => addr_cy_2,
+ CO(0) => addr_cy_3,
+ CYINIT => CI,
+ DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
+ DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
+ DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
+ DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
+ O(3) => sum_A_0,
+ O(2) => sum_A_1,
+ O(1) => sum_A_2,
+ O(0) => sum_A_3,
+ S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
+ S(2) => S0_out,
+ S(1) => S1_out,
+ S(0) => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \Addr_Counters[0].FDRE_I_n_0\,
+ O => S
+ );
+\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2AAAAAAAAAAAAAAA"
+ )
+ port map (
+ I0 => \Addr_Counters[0].FDRE_I_0\,
+ I1 => \Addr_Counters[2].FDRE_I_n_0\,
+ I2 => \Addr_Counters[3].FDRE_I_n_0\,
+ I3 => \Addr_Counters[1].FDRE_I_n_0\,
+ I4 => \Addr_Counters[0].FDRE_I_n_0\,
+ I5 => \Addr_Counters[0].FDRE_I_1\,
+ O => CI
+ );
+\Addr_Counters[0].MUXCY_L_I_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFFE"
+ )
+ port map (
+ I0 => \Addr_Counters[0].FDRE_I_0\,
+ I1 => \Addr_Counters[2].FDRE_I_n_0\,
+ I2 => \Addr_Counters[0].FDRE_I_n_0\,
+ I3 => \Addr_Counters[3].FDRE_I_n_0\,
+ I4 => \Addr_Counters[1].FDRE_I_n_0\,
+ O => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\
+ );
+\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^data_exists_dff_0\,
+ D => sum_A_2,
+ Q => \Addr_Counters[1].FDRE_I_n_0\,
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \Addr_Counters[1].FDRE_I_n_0\,
+ O => S1_out
+ );
+\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^data_exists_dff_0\,
+ D => sum_A_1,
+ Q => \Addr_Counters[2].FDRE_I_n_0\,
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \Addr_Counters[2].FDRE_I_n_0\,
+ O => S0_out
+ );
+\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => \^data_exists_dff_0\,
+ D => sum_A_0,
+ Q => \Addr_Counters[3].FDRE_I_n_0\,
+ R => Tx_fifo_rst
+ );
+\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20228A88"
+ )
+ port map (
+ I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
+ I1 => rdCntrFrmTxFifo,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ I4 => \Addr_Counters[3].FDRE_I_n_0\,
+ O => \Addr_Counters[3].XORCY_I_i_1_n_0\
+ );
+Data_Exists_DFF: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => D,
+ Q => \^data_exists_dff_0\,
+ R => Tx_fifo_rst
+ );
+\Data_Exists_DFF_i_3__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \Addr_Counters[1].FDRE_I_n_0\,
+ I1 => \Addr_Counters[3].FDRE_I_n_0\,
+ I2 => \Addr_Counters[0].FDRE_I_n_0\,
+ I3 => \Addr_Counters[2].FDRE_I_n_0\,
+ O => \Addr_Counters[1].FDRE_I_0\
+ );
+\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \Addr_Counters[0].FDRE_I_n_0\,
+ A1 => \Addr_Counters[1].FDRE_I_n_0\,
+ A2 => \Addr_Counters[2].FDRE_I_n_0\,
+ A3 => \Addr_Counters[3].FDRE_I_n_0\,
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => ctrlFifoDin(0),
+ Q => \^dynamic_msms\(0)
+ );
+\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
+ generic map(
+ INIT => X"0000",
+ IS_CLK_INVERTED => '0'
+ )
+ port map (
+ A0 => \Addr_Counters[0].FDRE_I_n_0\,
+ A1 => \Addr_Counters[1].FDRE_I_n_0\,
+ A2 => \Addr_Counters[2].FDRE_I_n_0\,
+ A3 => \Addr_Counters[3].FDRE_I_n_0\,
+ CE => CI,
+ CLK => s_axi_aclk,
+ D => ctrlFifoDin(1),
+ Q => \^dynamic_msms\(1)
+ );
+\cr_i[2]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F7FF"
+ )
+ port map (
+ I0 => \^dynamic_msms\(1),
+ I1 => Tx_data_exists,
+ I2 => Tx_fifo_rd_d,
+ I3 => Tx_fifo_rd,
+ O => Data_Exists_DFF_1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_address_decoder is
+ port (
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\ : out STD_LOGIC;
+ Bus_RNW_reg_reg_0 : out STD_LOGIC;
+ is_write_reg : out STD_LOGIC;
+ is_read_reg : out STD_LOGIC;
+ irpt_wrack : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ reset_trig0 : out STD_LOGIC;
+ sw_rst_cond : out STD_LOGIC;
+ AXI_IP2Bus_Error : out STD_LOGIC;
+ \s_axi_wdata[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \bus2ip_addr_i_reg[3]\ : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 8 downto 0 );
+ Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_onehot_state_reg[2]\ : out STD_LOGIC;
+ \s_axi_wdata[31]\ : out STD_LOGIC;
+ s_axi_wdata_0_sp_1 : out STD_LOGIC;
+ AXI_IP2Bus_WrAck20 : out STD_LOGIC;
+ AXI_IP2Bus_RdAck20 : out STD_LOGIC;
+ Q : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_arready : in STD_LOGIC;
+ AXI_IP2Bus_RdAck1 : in STD_LOGIC;
+ AXI_IP2Bus_RdAck2 : in STD_LOGIC;
+ s_axi_awready : in STD_LOGIC;
+ AXI_IP2Bus_WrAck1 : in STD_LOGIC;
+ AXI_IP2Bus_WrAck2 : in STD_LOGIC;
+ s_axi_awready_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ sw_rst_cond_d1 : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \cr_i_reg[2]\ : in STD_LOGIC;
+ \cr_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ firstDynStartSeen : in STD_LOGIC;
+ \cr_i_reg[2]_1\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[8]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[0]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[0]_0\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[1]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[1]_0\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ p_1_in8_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[4]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[5]\ : in STD_LOGIC;
+ p_1_in5_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[6]\ : in STD_LOGIC;
+ p_1_in2_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_0\ : in STD_LOGIC;
+ p_1_in : in STD_LOGIC;
+ cr_txModeSelect_set : in STD_LOGIC;
+ cr_txModeSelect_clr : in STD_LOGIC;
+ \s_axi_rdata_i_reg[0]_1\ : in STD_LOGIC;
+ p_1_in17_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[2]\ : in STD_LOGIC;
+ p_1_in14_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[3]\ : in STD_LOGIC;
+ p_1_in11_in : in STD_LOGIC;
+ ipif_glbl_irpt_enable_reg : in STD_LOGIC;
+ \s_axi_bresp_i_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_bresp : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gpo : in STD_LOGIC_VECTOR ( 0 to 0 );
+ AXI_IP2Bus_WrAck2_reg : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_address_decoder;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_address_decoder is
+ signal AXI_Bus2IP_CS : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^axi_ip2bus_error\ : STD_LOGIC;
+ signal \^bus2iic_wrce\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
+ signal \^bus_rnw_reg_reg_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\ : STD_LOGIC;
+ signal \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\ : STD_LOGIC;
+ signal \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\ : STD_LOGIC;
+ signal \MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0\ : STD_LOGIC;
+ signal cs_ce_clr : STD_LOGIC;
+ signal \^is_read_reg\ : STD_LOGIC;
+ signal \^is_write_reg\ : STD_LOGIC;
+ signal p_10_in : STD_LOGIC;
+ signal p_11_in : STD_LOGIC;
+ signal p_12_in : STD_LOGIC;
+ signal p_13_in : STD_LOGIC;
+ signal p_14_in : STD_LOGIC;
+ signal p_15_in : STD_LOGIC;
+ signal p_16_in : STD_LOGIC;
+ signal p_16_out : STD_LOGIC;
+ signal p_17_in : STD_LOGIC;
+ signal p_17_out : STD_LOGIC;
+ signal p_18_in : STD_LOGIC;
+ signal p_25_in : STD_LOGIC;
+ signal p_28_in : STD_LOGIC;
+ signal p_2_in : STD_LOGIC;
+ signal p_3_in : STD_LOGIC;
+ signal p_4_in : STD_LOGIC;
+ signal p_5_in : STD_LOGIC;
+ signal p_5_out : STD_LOGIC;
+ signal p_6_in : STD_LOGIC;
+ signal p_7_in : STD_LOGIC;
+ signal p_7_out : STD_LOGIC;
+ signal p_8_in : STD_LOGIC;
+ signal p_8_out : STD_LOGIC;
+ signal p_9_in : STD_LOGIC;
+ signal pselect_hit_i_0 : STD_LOGIC;
+ signal pselect_hit_i_2 : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_10_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_7_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_9_n_0\ : STD_LOGIC;
+ signal s_axi_wdata_0_sn_1 : STD_LOGIC;
+ signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
+ signal \^sw_rst_cond\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of AXI_IP2Bus_RdAck2_i_1 : label is "soft_lutpair42";
+ attribute SOFT_HLUTNM of AXI_IP2Bus_WrAck2_i_1 : label is "soft_lutpair42";
+ attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair49";
+ attribute SOFT_HLUTNM of \FIFO_GEN_DTR.Tx_fifo_wr_i_1\ : label is "soft_lutpair53";
+ attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\ : label is "soft_lutpair41";
+ attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_3\ : label is "soft_lutpair48";
+ attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\ : label is "soft_lutpair41";
+ attribute SOFT_HLUTNM of \GPO_GEN.gpo_i[31]_i_2\ : label is "soft_lutpair43";
+ attribute SOFT_HLUTNM of \MEM_DECODE_GEN[0].cs_out_i[0]_i_1\ : label is "soft_lutpair48";
+ attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.Rc_fifo_rd_i_1\ : label is "soft_lutpair46";
+ attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1\ : label is "soft_lutpair47";
+ attribute SOFT_HLUTNM of \adr_i[0]_i_1\ : label is "soft_lutpair44";
+ attribute SOFT_HLUTNM of \cr_i[0]_i_1\ : label is "soft_lutpair43";
+ attribute SOFT_HLUTNM of \ip_irpt_enable_reg[7]_i_1\ : label is "soft_lutpair40";
+ attribute SOFT_HLUTNM of ipif_glbl_irpt_enable_reg_i_1 : label is "soft_lutpair44";
+ attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair38";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair40";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[1]_i_4\ : label is "soft_lutpair39";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_1\ : label is "soft_lutpair38";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[7]_i_4\ : label is "soft_lutpair53";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[7]_i_5\ : label is "soft_lutpair39";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[9]_i_7\ : label is "soft_lutpair47";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[9]_i_8\ : label is "soft_lutpair45";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[9]_i_9\ : label is "soft_lutpair46";
+ attribute SOFT_HLUTNM of \timing_param_tbuf_i[9]_i_1\ : label is "soft_lutpair51";
+ attribute SOFT_HLUTNM of \timing_param_thddat_i[9]_i_1\ : label is "soft_lutpair52";
+ attribute SOFT_HLUTNM of \timing_param_thdsta_i[9]_i_1\ : label is "soft_lutpair45";
+ attribute SOFT_HLUTNM of \timing_param_thigh_i[9]_i_1\ : label is "soft_lutpair52";
+ attribute SOFT_HLUTNM of \timing_param_tlow_i[9]_i_1\ : label is "soft_lutpair50";
+ attribute SOFT_HLUTNM of \timing_param_tsudat_i[9]_i_1\ : label is "soft_lutpair51";
+ attribute SOFT_HLUTNM of \timing_param_tsusta_i[9]_i_1\ : label is "soft_lutpair49";
+ attribute SOFT_HLUTNM of \timing_param_tsusto_i[9]_i_1\ : label is "soft_lutpair50";
+begin
+ AXI_IP2Bus_Error <= \^axi_ip2bus_error\;
+ Bus2IIC_WrCE(11 downto 0) <= \^bus2iic_wrce\(11 downto 0);
+ Bus_RNW_reg_reg_0 <= \^bus_rnw_reg_reg_0\;
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\ <= \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\;
+ is_read_reg <= \^is_read_reg\;
+ is_write_reg <= \^is_write_reg\;
+ s_axi_wdata_0_sp_1 <= s_axi_wdata_0_sn_1;
+ sw_rst_cond <= \^sw_rst_cond\;
+AXI_IP2Bus_RdAck2_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE00"
+ )
+ port map (
+ I0 => AXI_Bus2IP_CS(1),
+ I1 => AXI_Bus2IP_CS(2),
+ I2 => AXI_Bus2IP_CS(0),
+ I3 => AXI_IP2Bus_WrAck2_reg,
+ O => AXI_IP2Bus_RdAck20
+ );
+AXI_IP2Bus_WrAck2_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00FE"
+ )
+ port map (
+ I0 => AXI_Bus2IP_CS(1),
+ I1 => AXI_Bus2IP_CS(2),
+ I2 => AXI_Bus2IP_CS(0),
+ I3 => AXI_IP2Bus_WrAck2_reg,
+ O => AXI_IP2Bus_WrAck20
+ );
+Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => AXI_IP2Bus_WrAck2_reg,
+ I1 => Q,
+ I2 => \^bus_rnw_reg_reg_0\,
+ O => Bus_RNW_reg_i_1_n_0
+ );
+Bus_RNW_reg_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Bus_RNW_reg_i_1_n_0,
+ Q => \^bus_rnw_reg_reg_0\,
+ R => '0'
+ );
+\FIFO_GEN_DTR.Tx_fifo_wr_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_16_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(10)
+ );
+\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"02000000"
+ )
+ port map (
+ I0 => pselect_hit_i_2,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => p_5_out
+ );
+\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => p_5_out,
+ Q => p_25_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000004"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I1 => pselect_hit_i_0,
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
+ Q => p_18_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000020"
+ )
+ port map (
+ I0 => pselect_hit_i_0,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ O => p_16_out
+ );
+\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => p_16_out,
+ Q => p_17_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0001000000000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I5 => pselect_hit_i_0,
+ O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\,
+ Q => p_16_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000080"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I2 => pselect_hit_i_0,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ O => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\,
+ Q => p_15_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000001000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => pselect_hit_i_0,
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\,
+ Q => p_14_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000010000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => pselect_hit_i_0,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\,
+ Q => p_13_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000010000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => pselect_hit_i_0,
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\,
+ Q => p_12_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0008000000000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I5 => pselect_hit_i_0,
+ O => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\,
+ Q => p_11_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000040000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\,
+ Q => p_10_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000004000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I1 => pselect_hit_i_0,
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\,
+ Q => p_9_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0100000000000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I3 => pselect_hit_i_0,
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\,
+ Q => p_8_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000040000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\,
+ Q => p_7_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000004000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\,
+ Q => p_6_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000040000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\,
+ Q => p_5_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0008000000000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I1 => pselect_hit_i_0,
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\,
+ Q => p_4_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4000000000000000"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ O => \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[32].ce_out_i_reg[32]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\,
+ Q => p_3_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000400"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I1 => pselect_hit_i_0,
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\
+ );
+\GEN_BKEND_CE_REGISTERS[33].ce_out_i_reg[33]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\,
+ Q => p_2_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FB"
+ )
+ port map (
+ I0 => \^is_write_reg\,
+ I1 => s_axi_aresetn,
+ I2 => \^is_read_reg\,
+ O => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000200000"
+ )
+ port map (
+ I0 => pselect_hit_i_0,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ O => p_17_out
+ );
+\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => Q,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ O => pselect_hit_i_0
+ );
+\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg[34]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => p_17_out,
+ Q => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"08000000"
+ )
+ port map (
+ I0 => pselect_hit_i_2,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ O => p_8_out
+ );
+\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => p_8_out,
+ Q => p_28_in,
+ R => cs_ce_clr
+ );
+\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00020000"
+ )
+ port map (
+ I0 => pselect_hit_i_2,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ O => p_7_out
+ );
+\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => p_7_out,
+ Q => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ R => cs_ce_clr
+ );
+\GPO_GEN.gpo_i[31]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB08"
+ )
+ port map (
+ I0 => s_axi_wdata(0),
+ I1 => p_9_in,
+ I2 => \^bus_rnw_reg_reg_0\,
+ I3 => gpo(0),
+ O => s_axi_wdata_0_sn_1
+ );
+\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0010"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(7),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I2 => Q,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ O => pselect_hit_i_2
+ );
+\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => pselect_hit_i_2,
+ Q => AXI_Bus2IP_CS(2),
+ R => cs_ce_clr
+ );
+\MEM_DECODE_GEN[1].cs_out_i[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(2),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I2 => \MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0\,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ I5 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(7),
+ O => \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\
+ );
+\MEM_DECODE_GEN[1].cs_out_i[1]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ O => \MEM_DECODE_GEN[1].cs_out_i[1]_i_2_n_0\
+ );
+\MEM_DECODE_GEN[1].cs_out_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\,
+ Q => AXI_Bus2IP_CS(1),
+ R => cs_ce_clr
+ );
+\MEM_DECODE_GEN[2].cs_out_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Q,
+ D => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8),
+ Q => AXI_Bus2IP_CS(0),
+ R => cs_ce_clr
+ );
+\RD_FIFO_CNTRL.Rc_fifo_rd_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \^bus_rnw_reg_reg_0\,
+ I1 => p_15_in,
+ O => Bus2IIC_RdCE(0)
+ );
+\RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_10_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(8)
+ );
+\adr_i[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_14_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(9)
+ );
+\cr_i[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_18_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(11)
+ );
+\cr_i[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"B888B888B8BBB888"
+ )
+ port map (
+ I0 => s_axi_wdata(4),
+ I1 => \^bus2iic_wrce\(11),
+ I2 => \cr_i_reg[2]\,
+ I3 => \cr_i_reg[2]_0\(1),
+ I4 => firstDynStartSeen,
+ I5 => \cr_i_reg[2]_1\,
+ O => \s_axi_wdata[5]\(1)
+ );
+\cr_i[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"08080808FBFBFB08"
+ )
+ port map (
+ I0 => s_axi_wdata(3),
+ I1 => p_18_in,
+ I2 => \^bus_rnw_reg_reg_0\,
+ I3 => \cr_i_reg[2]_0\(0),
+ I4 => cr_txModeSelect_set,
+ I5 => cr_txModeSelect_clr,
+ O => \s_axi_wdata[5]\(0)
+ );
+\ip_irpt_enable_reg[7]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_25_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => E(0)
+ );
+ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB08"
+ )
+ port map (
+ I0 => s_axi_wdata(5),
+ I1 => p_28_in,
+ I2 => \^bus_rnw_reg_reg_0\,
+ I3 => ipif_glbl_irpt_enable_reg,
+ O => \s_axi_wdata[31]\
+ );
+irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F0E"
+ )
+ port map (
+ I0 => p_25_in,
+ I1 => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ I2 => \^bus_rnw_reg_reg_0\,
+ I3 => p_28_in,
+ O => irpt_wrack
+ );
+reset_trig_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^sw_rst_cond\,
+ I1 => sw_rst_cond_d1,
+ O => reset_trig0
+ );
+s_axi_arready_INST_0: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4F44"
+ )
+ port map (
+ I0 => s_axi_wready_INST_0_i_1_n_0,
+ I1 => s_axi_arready,
+ I2 => AXI_IP2Bus_RdAck1,
+ I3 => AXI_IP2Bus_RdAck2,
+ O => \^is_read_reg\
+ );
+\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \^axi_ip2bus_error\,
+ I1 => \s_axi_bresp_i_reg[1]\(0),
+ I2 => s_axi_bresp(0),
+ O => \FSM_onehot_state_reg[2]\
+ );
+\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFF1011"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[0]\,
+ I2 => \s_axi_rdata_i_reg[0]_0\,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I4 => \s_axi_rdata_i[0]_i_4_n_0\,
+ O => D(0)
+ );
+\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"8C808080"
+ )
+ port map (
+ I0 => \s_axi_rdata_i_reg[0]_1\,
+ I1 => \^bus_rnw_reg_reg_0\,
+ I2 => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(0),
+ I4 => p_25_in,
+ O => \s_axi_rdata_i[0]_i_4_n_0\
+ );
+\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFF1011"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[1]\,
+ I2 => \s_axi_rdata_i_reg[1]_0\,
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I4 => \s_axi_rdata_i[1]_i_4_n_0\,
+ O => D(1)
+ );
+\s_axi_rdata_i[1]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"8C808080"
+ )
+ port map (
+ I0 => p_1_in17_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ I2 => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(1),
+ I4 => p_25_in,
+ O => \s_axi_rdata_i[1]_i_4_n_0\
+ );
+\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF4444444F444"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[2]\,
+ I2 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(2),
+ I4 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I5 => p_1_in14_in,
+ O => D(2)
+ );
+\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000080"
+ )
+ port map (
+ I0 => p_28_in,
+ I1 => ipif_glbl_irpt_enable_reg,
+ I2 => \^bus_rnw_reg_reg_0\,
+ I3 => p_25_in,
+ I4 => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ O => D(8)
+ );
+\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF4444444F444"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[3]\,
+ I2 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(3),
+ I4 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I5 => p_1_in11_in,
+ O => D(3)
+ );
+\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F808F808F808FFFF"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I1 => \s_axi_rdata_i_reg[7]\(4),
+ I2 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I3 => p_1_in8_in,
+ I4 => \s_axi_rdata_i_reg[4]\,
+ I5 => \s_axi_rdata_i[7]_i_3_n_0\,
+ O => D(4)
+ );
+\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF1111111F111"
+ )
+ port map (
+ I0 => \s_axi_rdata_i_reg[5]\,
+ I1 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I2 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(5),
+ I4 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I5 => p_1_in5_in,
+ O => D(5)
+ );
+\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF1111111F111"
+ )
+ port map (
+ I0 => \s_axi_rdata_i_reg[6]\,
+ I1 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I2 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(6),
+ I4 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I5 => p_1_in2_in,
+ O => D(6)
+ );
+\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF1111111F111"
+ )
+ port map (
+ I0 => \s_axi_rdata_i_reg[7]_0\,
+ I1 => \s_axi_rdata_i[7]_i_3_n_0\,
+ I2 => \s_axi_rdata_i[7]_i_4_n_0\,
+ I3 => \s_axi_rdata_i_reg[7]\(7),
+ I4 => \s_axi_rdata_i[7]_i_5_n_0\,
+ I5 => p_1_in,
+ O => D(7)
+ );
+\s_axi_rdata_i[7]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[9]_i_5_n_0\,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(7),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(0),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(1),
+ O => \s_axi_rdata_i[7]_i_3_n_0\
+ );
+\s_axi_rdata_i[7]_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \^bus_rnw_reg_reg_0\,
+ I1 => p_25_in,
+ O => \s_axi_rdata_i[7]_i_4_n_0\
+ );
+\s_axi_rdata_i[7]_i_5\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \^bus_rnw_reg_reg_0\,
+ I1 => \^gen_bkend_ce_registers[8].ce_out_i_reg[8]_0\,
+ O => \s_axi_rdata_i[7]_i_5_n_0\
+ );
+\s_axi_rdata_i[9]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => p_8_in,
+ I1 => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
+ I2 => p_5_in,
+ I3 => p_18_in,
+ I4 => p_16_in,
+ I5 => p_17_in,
+ O => \s_axi_rdata_i[9]_i_10_n_0\
+ );
+\s_axi_rdata_i[9]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFEABFF"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[9]_i_5_n_0\,
+ I1 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(3),
+ I2 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(4),
+ I3 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(5),
+ I4 => \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6),
+ I5 => \s_axi_rdata_i_reg[8]\,
+ O => \bus2ip_addr_i_reg[3]\
+ );
+\s_axi_rdata_i[9]_i_5\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0100FFFF"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[9]_i_7_n_0\,
+ I1 => \s_axi_rdata_i[9]_i_8_n_0\,
+ I2 => \s_axi_rdata_i[9]_i_9_n_0\,
+ I3 => \s_axi_rdata_i[9]_i_10_n_0\,
+ I4 => \^bus_rnw_reg_reg_0\,
+ O => \s_axi_rdata_i[9]_i_5_n_0\
+ );
+\s_axi_rdata_i[9]_i_7\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => p_11_in,
+ I1 => p_9_in,
+ I2 => p_10_in,
+ I3 => p_3_in,
+ O => \s_axi_rdata_i[9]_i_7_n_0\
+ );
+\s_axi_rdata_i[9]_i_8\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => p_14_in,
+ I1 => p_6_in,
+ I2 => p_13_in,
+ I3 => p_2_in,
+ O => \s_axi_rdata_i[9]_i_8_n_0\
+ );
+\s_axi_rdata_i[9]_i_9\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => p_15_in,
+ I1 => p_4_in,
+ I2 => p_12_in,
+ I3 => p_7_in,
+ O => \s_axi_rdata_i[9]_i_9_n_0\
+ );
+\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4444404444444444"
+ )
+ port map (
+ I0 => \^bus_rnw_reg_reg_0\,
+ I1 => AXI_Bus2IP_CS(1),
+ I2 => s_axi_wdata(0),
+ I3 => s_axi_wdata(1),
+ I4 => s_axi_wdata(2),
+ I5 => s_axi_wdata(3),
+ O => \^axi_ip2bus_error\
+ );
+s_axi_wready_INST_0: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4F44"
+ )
+ port map (
+ I0 => s_axi_wready_INST_0_i_1_n_0,
+ I1 => s_axi_awready,
+ I2 => AXI_IP2Bus_WrAck1,
+ I3 => AXI_IP2Bus_WrAck2,
+ O => \^is_write_reg\
+ );
+s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFEF"
+ )
+ port map (
+ I0 => s_axi_awready_0(1),
+ I1 => s_axi_awready_0(0),
+ I2 => s_axi_awready_0(3),
+ I3 => s_axi_awready_0(2),
+ O => s_axi_wready_INST_0_i_1_n_0
+ );
+sw_rst_cond_d1_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000040000000000"
+ )
+ port map (
+ I0 => \^bus_rnw_reg_reg_0\,
+ I1 => AXI_Bus2IP_CS(1),
+ I2 => s_axi_wdata(0),
+ I3 => s_axi_wdata(1),
+ I4 => s_axi_wdata(2),
+ I5 => s_axi_wdata(3),
+ O => \^sw_rst_cond\
+ );
+\timing_param_tbuf_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_4_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(3)
+ );
+\timing_param_thddat_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(0)
+ );
+\timing_param_thdsta_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_6_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(5)
+ );
+\timing_param_thigh_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_3_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(2)
+ );
+\timing_param_tlow_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_2_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(1)
+ );
+\timing_param_tsudat_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_5_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(4)
+ );
+\timing_param_tsusta_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_8_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(7)
+ );
+\timing_param_tsusto_i[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_7_in,
+ I1 => \^bus_rnw_reg_reg_0\,
+ O => \^bus2iic_wrce\(6)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_cdc_sync is
+ port (
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : out STD_LOGIC;
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1\ : out STD_LOGIC;
+ sda_rin_d1 : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_cdc_sync;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_cdc_sync is
+ signal \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_s_level_out_d4_1\ : STD_LOGIC;
+ signal s_level_out_d1_cdc_to : STD_LOGIC;
+ signal s_level_out_d2 : STD_LOGIC;
+ signal s_level_out_d3 : STD_LOGIC;
+ attribute ASYNC_REG : boolean;
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
+ attribute box_type : string;
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
+begin
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1\ <= \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_s_level_out_d4_1\;
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sda_i,
+ Q => s_level_out_d1_cdc_to,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d1_cdc_to,
+ Q => s_level_out_d2,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d2,
+ Q => s_level_out_d3,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d3,
+ Q => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_s_level_out_d4_1\,
+ R => '0'
+ );
+detect_stop_b_i_3: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_s_level_out_d4_1\,
+ I1 => sda_rin_d1,
+ O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_cdc_sync_4 is
+ port (
+ scl_rising_edge0 : out STD_LOGIC;
+ scndry_out : out STD_LOGIC;
+ scl_rin_d1 : in STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_axi_iic_0_0_cdc_sync_4 : entity is "cdc_sync";
+end TopLevel_axi_iic_0_0_cdc_sync_4;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_cdc_sync_4 is
+ signal s_level_out_d1_cdc_to : STD_LOGIC;
+ signal s_level_out_d2 : STD_LOGIC;
+ signal s_level_out_d3 : STD_LOGIC;
+ signal \^scndry_out\ : STD_LOGIC;
+ attribute ASYNC_REG : boolean;
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
+ attribute box_type : string;
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
+ attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
+ attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
+ attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
+begin
+ scndry_out <= \^scndry_out\;
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_i,
+ Q => s_level_out_d1_cdc_to,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d1_cdc_to,
+ Q => s_level_out_d2,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d2,
+ Q => s_level_out_d3,
+ R => '0'
+ );
+\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_level_out_d3,
+ Q => \^scndry_out\,
+ R => '0'
+ );
+scl_rising_edge_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^scndry_out\,
+ I1 => scl_rin_d1,
+ O => scl_rising_edge0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_dynamic_master is
+ port (
+ rdCntrFrmTxFifo : out STD_LOGIC;
+ rxCntDone : out STD_LOGIC;
+ firstDynStartSeen : out STD_LOGIC;
+ cr_txModeSelect_set : out STD_LOGIC;
+ cr_txModeSelect_clr : out STD_LOGIC;
+ \rdByteCntr_reg[2]_0\ : out STD_LOGIC;
+ rdCntrFrmTxFifo_reg_0 : out STD_LOGIC;
+ Tx_fifo_rst : in STD_LOGIC;
+ ackDataState : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ p_3_in : in STD_LOGIC;
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
+ earlyAckDataState : in STD_LOGIC;
+ firstDynStartSeen_reg_0 : in STD_LOGIC;
+ Tx_fifo_rd_d : in STD_LOGIC;
+ Tx_fifo_rd : in STD_LOGIC;
+ earlyAckHdr : in STD_LOGIC;
+ Tx_data_exists : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_dynamic_master;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_dynamic_master is
+ signal Cr_txModeSelect_clr_i_1_n_0 : STD_LOGIC;
+ signal Cr_txModeSelect_set_i_1_n_0 : STD_LOGIC;
+ signal ackDataState_d1 : STD_LOGIC;
+ signal callingReadAccess : STD_LOGIC;
+ signal earlyAckDataState_d1 : STD_LOGIC;
+ signal \^firstdynstartseen\ : STD_LOGIC;
+ signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \rdByteCntr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \rdByteCntr[0]_i_3_n_0\ : STD_LOGIC;
+ signal \rdByteCntr[0]_i_4_n_0\ : STD_LOGIC;
+ signal \rdByteCntr[1]_i_2_n_0\ : STD_LOGIC;
+ signal rdByteCntr_reg : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal \^rdbytecntr_reg[2]_0\ : STD_LOGIC;
+ signal \^rdcntrfrmtxfifo\ : STD_LOGIC;
+ signal rdCntrFrmTxFifo0 : STD_LOGIC;
+ signal rxCntDone0 : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of Cr_txModeSelect_clr_i_1 : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of Cr_txModeSelect_set_i_1 : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \rdByteCntr[6]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \rdByteCntr[7]_i_1\ : label is "soft_lutpair0";
+begin
+ firstDynStartSeen <= \^firstdynstartseen\;
+ \rdByteCntr_reg[2]_0\ <= \^rdbytecntr_reg[2]_0\;
+ rdCntrFrmTxFifo <= \^rdcntrfrmtxfifo\;
+Cr_txModeSelect_clr_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0080"
+ )
+ port map (
+ I0 => callingReadAccess,
+ I1 => \^firstdynstartseen\,
+ I2 => earlyAckHdr,
+ I3 => Tx_fifo_rst,
+ O => Cr_txModeSelect_clr_i_1_n_0
+ );
+Cr_txModeSelect_clr_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Cr_txModeSelect_clr_i_1_n_0,
+ Q => cr_txModeSelect_clr,
+ R => '0'
+ );
+Cr_txModeSelect_set_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0040"
+ )
+ port map (
+ I0 => callingReadAccess,
+ I1 => \^firstdynstartseen\,
+ I2 => earlyAckHdr,
+ I3 => Tx_fifo_rst,
+ O => Cr_txModeSelect_set_i_1_n_0
+ );
+Cr_txModeSelect_set_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Cr_txModeSelect_set_i_1_n_0,
+ Q => cr_txModeSelect_set,
+ R => '0'
+ );
+\Data_Exists_DFF_i_2__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"45"
+ )
+ port map (
+ I0 => \^rdcntrfrmtxfifo\,
+ I1 => Tx_fifo_rd_d,
+ I2 => Tx_fifo_rd,
+ O => rdCntrFrmTxFifo_reg_0
+ );
+ackDataState_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => ackDataState,
+ Q => ackDataState_d1,
+ R => Tx_fifo_rst
+ );
+callingReadAccess_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => p_3_in,
+ D => Tx_fifo_data(7),
+ Q => callingReadAccess,
+ R => Tx_fifo_rst
+ );
+earlyAckDataState_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => earlyAckDataState,
+ Q => earlyAckDataState_d1,
+ R => Tx_fifo_rst
+ );
+firstDynStartSeen_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => firstDynStartSeen_reg_0,
+ Q => \^firstdynstartseen\,
+ R => '0'
+ );
+\rdByteCntr[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BAAA"
+ )
+ port map (
+ I0 => \^rdcntrfrmtxfifo\,
+ I1 => earlyAckDataState_d1,
+ I2 => earlyAckDataState,
+ I3 => \rdByteCntr[0]_i_3_n_0\,
+ O => \rdByteCntr[0]_i_1_n_0\
+ );
+\rdByteCntr[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B88BB8B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(0),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(0),
+ I3 => rdByteCntr_reg(1),
+ I4 => \rdByteCntr[0]_i_4_n_0\,
+ O => \p_0_in__1\(7)
+ );
+\rdByteCntr[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFFE"
+ )
+ port map (
+ I0 => \rdByteCntr[1]_i_2_n_0\,
+ I1 => rdByteCntr_reg(1),
+ I2 => rdByteCntr_reg(0),
+ I3 => rdByteCntr_reg(3),
+ I4 => rdByteCntr_reg(2),
+ O => \rdByteCntr[0]_i_3_n_0\
+ );
+\rdByteCntr[0]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => rdByteCntr_reg(4),
+ I1 => rdByteCntr_reg(7),
+ I2 => rdByteCntr_reg(6),
+ I3 => rdByteCntr_reg(5),
+ I4 => rdByteCntr_reg(3),
+ I5 => rdByteCntr_reg(2),
+ O => \rdByteCntr[0]_i_4_n_0\
+ );
+\rdByteCntr[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"B8B8B8B8B8B8B88B"
+ )
+ port map (
+ I0 => Tx_fifo_data(1),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(1),
+ I3 => rdByteCntr_reg(2),
+ I4 => rdByteCntr_reg(3),
+ I5 => \rdByteCntr[1]_i_2_n_0\,
+ O => \p_0_in__1\(6)
+ );
+\rdByteCntr[1]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => rdByteCntr_reg(4),
+ I1 => rdByteCntr_reg(7),
+ I2 => rdByteCntr_reg(6),
+ I3 => rdByteCntr_reg(5),
+ O => \rdByteCntr[1]_i_2_n_0\
+ );
+\rdByteCntr[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8B8B88B"
+ )
+ port map (
+ I0 => Tx_fifo_data(2),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(2),
+ I3 => \rdByteCntr[1]_i_2_n_0\,
+ I4 => rdByteCntr_reg(3),
+ O => \p_0_in__1\(5)
+ );
+\rdByteCntr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"B88B"
+ )
+ port map (
+ I0 => Tx_fifo_data(3),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(3),
+ I3 => \rdByteCntr[1]_i_2_n_0\,
+ O => \p_0_in__1\(4)
+ );
+\rdByteCntr[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BBBBBBB88888888B"
+ )
+ port map (
+ I0 => Tx_fifo_data(4),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(5),
+ I3 => rdByteCntr_reg(6),
+ I4 => rdByteCntr_reg(7),
+ I5 => rdByteCntr_reg(4),
+ O => \p_0_in__1\(3)
+ );
+\rdByteCntr[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"BBB8888B"
+ )
+ port map (
+ I0 => Tx_fifo_data(5),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(7),
+ I3 => rdByteCntr_reg(6),
+ I4 => rdByteCntr_reg(5),
+ O => \p_0_in__1\(2)
+ );
+\rdByteCntr[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"B88B"
+ )
+ port map (
+ I0 => Tx_fifo_data(6),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(7),
+ I3 => rdByteCntr_reg(6),
+ O => \p_0_in__1\(1)
+ );
+\rdByteCntr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"8B"
+ )
+ port map (
+ I0 => Tx_fifo_data(7),
+ I1 => \^rdcntrfrmtxfifo\,
+ I2 => rdByteCntr_reg(7),
+ O => \p_0_in__1\(0)
+ );
+\rdByteCntr_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(7),
+ Q => rdByteCntr_reg(0),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(6),
+ Q => rdByteCntr_reg(1),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(5),
+ Q => rdByteCntr_reg(2),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(4),
+ Q => rdByteCntr_reg(3),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(3),
+ Q => rdByteCntr_reg(4),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(2),
+ Q => rdByteCntr_reg(5),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(1),
+ Q => rdByteCntr_reg(6),
+ R => Tx_fifo_rst
+ );
+\rdByteCntr_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \rdByteCntr[0]_i_1_n_0\,
+ D => \p_0_in__1\(0),
+ Q => rdByteCntr_reg(7),
+ R => Tx_fifo_rst
+ );
+rdCntrFrmTxFifo_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 => callingReadAccess,
+ I1 => earlyAckHdr,
+ I2 => Tx_data_exists,
+ O => rdCntrFrmTxFifo0
+ );
+rdCntrFrmTxFifo_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => rdCntrFrmTxFifo0,
+ Q => \^rdcntrfrmtxfifo\,
+ R => Tx_fifo_rst
+ );
+rxCntDone_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => ackDataState_d1,
+ I1 => ackDataState,
+ I2 => \^rdbytecntr_reg[2]_0\,
+ O => rxCntDone0
+ );
+rxCntDone_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFEFFFFFFFF"
+ )
+ port map (
+ I0 => rdByteCntr_reg(2),
+ I1 => rdByteCntr_reg(3),
+ I2 => rdByteCntr_reg(0),
+ I3 => rdByteCntr_reg(1),
+ I4 => \rdByteCntr[1]_i_2_n_0\,
+ I5 => callingReadAccess,
+ O => \^rdbytecntr_reg[2]_0\
+ );
+rxCntDone_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => rxCntDone0,
+ Q => rxCntDone,
+ R => Tx_fifo_rst
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_interrupt_control is
+ port (
+ \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
+ p_1_in17_in : out STD_LOGIC;
+ p_1_in14_in : out STD_LOGIC;
+ p_1_in11_in : out STD_LOGIC;
+ p_1_in8_in : out STD_LOGIC;
+ p_1_in5_in : out STD_LOGIC;
+ p_1_in2_in : out STD_LOGIC;
+ p_1_in : out STD_LOGIC;
+ ipif_glbl_irpt_enable_reg : out STD_LOGIC;
+ iic2intc_irpt : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+ irpt_wrack : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ ipif_glbl_irpt_enable_reg_reg_0 : in STD_LOGIC;
+ Bus_RNW_reg : in STD_LOGIC;
+ p_27_in : in STD_LOGIC;
+ IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ E : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end TopLevel_axi_iic_0_0_interrupt_control;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_interrupt_control is
+ signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
+ signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\ : STD_LOGIC;
+ signal \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\ : STD_LOGIC;
+ signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal iic2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
+ signal iic2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
+ signal iic2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
+ signal iic2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
+ signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
+ signal irpt_wrack_d1 : STD_LOGIC;
+ signal \^p_1_in\ : STD_LOGIC;
+ signal \^p_1_in11_in\ : STD_LOGIC;
+ signal \^p_1_in14_in\ : STD_LOGIC;
+ signal \^p_1_in17_in\ : STD_LOGIC;
+ signal \^p_1_in2_in\ : STD_LOGIC;
+ signal \^p_1_in5_in\ : STD_LOGIC;
+ signal \^p_1_in8_in\ : STD_LOGIC;
+begin
+ \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
+ Q(7 downto 0) <= \^q\(7 downto 0);
+ ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\;
+ p_1_in <= \^p_1_in\;
+ p_1_in11_in <= \^p_1_in11_in\;
+ p_1_in14_in <= \^p_1_in14_in\;
+ p_1_in17_in <= \^p_1_in17_in\;
+ p_1_in2_in <= \^p_1_in2_in\;
+ p_1_in5_in <= \^p_1_in5_in\;
+ p_1_in8_in <= \^p_1_in8_in\;
+\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(0),
+ I4 => s_axi_wdata(0),
+ I5 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
+ O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
+ Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(1),
+ I4 => s_axi_wdata(1),
+ I5 => \^p_1_in17_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\,
+ Q => \^p_1_in17_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(2),
+ I4 => s_axi_wdata(2),
+ I5 => \^p_1_in14_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\,
+ Q => \^p_1_in14_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(3),
+ I4 => s_axi_wdata(3),
+ I5 => \^p_1_in11_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\,
+ Q => \^p_1_in11_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(4),
+ I4 => s_axi_wdata(4),
+ I5 => \^p_1_in8_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\,
+ Q => \^p_1_in8_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(5),
+ I4 => s_axi_wdata(5),
+ I5 => \^p_1_in5_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\,
+ Q => \^p_1_in5_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(6),
+ I4 => s_axi_wdata(6),
+ I5 => \^p_1_in2_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\,
+ Q => \^p_1_in2_in\,
+ R => SR(0)
+ );
+\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEFFFFFFF10FF00"
+ )
+ port map (
+ I0 => irpt_wrack_d1,
+ I1 => Bus_RNW_reg,
+ I2 => p_27_in,
+ I3 => IIC2Bus_IntrEvent(7),
+ I4 => s_axi_wdata(7),
+ I5 => \^p_1_in\,
+ O => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\
+ );
+\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\,
+ Q => \^p_1_in\,
+ R => SR(0)
+ );
+iic2intc_irpt_INST_0: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAA8AA"
+ )
+ port map (
+ I0 => \^ipif_glbl_irpt_enable_reg\,
+ I1 => iic2intc_irpt_INST_0_i_1_n_0,
+ I2 => iic2intc_irpt_INST_0_i_2_n_0,
+ I3 => iic2intc_irpt_INST_0_i_3_n_0,
+ I4 => iic2intc_irpt_INST_0_i_4_n_0,
+ O => iic2intc_irpt
+ );
+iic2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F888"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
+ I2 => \^q\(7),
+ I3 => \^p_1_in\,
+ O => iic2intc_irpt_INST_0_i_1_n_0
+ );
+iic2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F888"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \^p_1_in8_in\,
+ I2 => \^q\(1),
+ I3 => \^p_1_in17_in\,
+ O => iic2intc_irpt_INST_0_i_2_n_0
+ );
+iic2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0777"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \^p_1_in5_in\,
+ I2 => \^q\(3),
+ I3 => \^p_1_in11_in\,
+ O => iic2intc_irpt_INST_0_i_3_n_0
+ );
+iic2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F888"
+ )
+ port map (
+ I0 => \^q\(6),
+ I1 => \^p_1_in2_in\,
+ I2 => \^q\(2),
+ I3 => \^p_1_in14_in\,
+ O => iic2intc_irpt_INST_0_i_4_n_0
+ );
+\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(0),
+ Q => \^q\(0),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(1),
+ Q => \^q\(1),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(2),
+ Q => \^q\(2),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(3),
+ Q => \^q\(3),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(4),
+ Q => \^q\(4),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(5),
+ Q => \^q\(5),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(6),
+ Q => \^q\(6),
+ R => SR(0)
+ );
+\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => s_axi_wdata(7),
+ Q => \^q\(7),
+ R => SR(0)
+ );
+ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => ipif_glbl_irpt_enable_reg_reg_0,
+ Q => \^ipif_glbl_irpt_enable_reg\,
+ R => SR(0)
+ );
+irpt_wrack_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => irpt_wrack,
+ Q => irpt_wrack_d1,
+ R => SR(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_reg_interface is
+ port (
+ IIC2Bus_IntrEvent : out STD_LOGIC_VECTOR ( 0 to 7 );
+ Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ Tx_fifo_wr : out STD_LOGIC;
+ Tx_fifo_rd : out STD_LOGIC;
+ Tx_fifo_rst : out STD_LOGIC;
+ new_rcv_dta_d1 : out STD_LOGIC;
+ Rc_fifo_wr : out STD_LOGIC;
+ Rc_fifo_rd : out STD_LOGIC;
+ \sr_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gpo : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Msms_set : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 0 to 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_thigh_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ \timing_param_tsusto_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_tsusto_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ \timing_param_tsusta_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_tsusta_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ \timing_param_tbuf_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_tbuf_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ \timing_param_thddat_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_thdsta_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_thdsta_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ \timing_param_tlow_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_tlow_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ \timing_param_tsudat_i_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \timing_param_tsudat_i_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ D_0 : out STD_LOGIC;
+ Tx_fifo_wr_d_reg : out STD_LOGIC;
+ \cr_i_reg[7]_0\ : out STD_LOGIC;
+ \cr_i_reg[3]_0\ : out STD_LOGIC;
+ stop_scl_reg_reg : out STD_LOGIC;
+ \cr_i_reg[2]_0\ : out STD_LOGIC;
+ firstDynStartSeen_reg : out STD_LOGIC;
+ p_3_in : out STD_LOGIC;
+ \FIFO_GEN_DTR.Tx_fifo_rd_reg_0\ : out STD_LOGIC;
+ \bus2ip_addr_i_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \timing_param_tsudat_i_reg[4]_0\ : out STD_LOGIC;
+ \timing_param_tsudat_i_reg[5]_0\ : out STD_LOGIC;
+ \timing_param_tsudat_i_reg[6]_0\ : out STD_LOGIC;
+ \timing_param_tsudat_i_reg[7]_0\ : out STD_LOGIC;
+ \sr_i_reg[4]_0\ : out STD_LOGIC;
+ \bus2ip_addr_i_reg[6]\ : out STD_LOGIC;
+ \adr_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \sr_i_reg[5]_0\ : out STD_LOGIC;
+ \bus2ip_addr_i_reg[6]_0\ : out STD_LOGIC;
+ \IIC2Bus_IntrEvent_reg[5]_0\ : out STD_LOGIC;
+ \adr_i_reg[6]_0\ : out STD_LOGIC;
+ \GPO_GEN.gpo_i_reg[31]_0\ : out STD_LOGIC;
+ \cr_i_reg[2]_1\ : out STD_LOGIC;
+ \FIFO_GEN_DTR.Tx_fifo_wr_reg_0\ : out STD_LOGIC;
+ D_1 : out STD_LOGIC;
+ \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0\ : out STD_LOGIC;
+ \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0\ : out STD_LOGIC;
+ Bus2IIC_Reset : in STD_LOGIC;
+ p_0_in : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ Bus2IIC_WrCE : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ Rdy_new_xmt : in STD_LOGIC;
+ New_rcv_dta : in STD_LOGIC;
+ p_6_out : in STD_LOGIC;
+ Bus2IIC_RdCE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \sr_i_reg[0]_1\ : in STD_LOGIC;
+ Aas : in STD_LOGIC;
+ \GPO_GEN.gpo_i_reg[31]_1\ : in STD_LOGIC;
+ \RD_FIFO_CNTRL.ro_prev_i_reg_0\ : in STD_LOGIC;
+ \next_scl_state1_inferred__1/i__carry\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ \sda_setup0_inferred__0/i__carry\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ Tx_fifo_rd_d : in STD_LOGIC;
+ rdCntrFrmTxFifo : in STD_LOGIC;
+ Data_Exists_DFF : in STD_LOGIC;
+ Data_Exists_DFF_0 : in STD_LOGIC;
+ Tx_fifo_wr_d : in STD_LOGIC;
+ \LEVEL_1_GEN.master_sda_reg\ : in STD_LOGIC;
+ earlyAckDataState : in STD_LOGIC;
+ CO : in STD_LOGIC_VECTOR ( 0 to 0 );
+ stop_scl_reg : in STD_LOGIC;
+ \q_int_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \q_int_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \q_int_reg[1]_1\ : in STD_LOGIC;
+ firstDynStartSeen : in STD_LOGIC;
+ firstDynStartSeen_reg_0 : in STD_LOGIC;
+ Tx_data_exists : in STD_LOGIC;
+ dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \s_axi_rdata_i[0]_i_7\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i_reg[8]\ : in STD_LOGIC;
+ Rc_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ Rc_fifo_wr_d : in STD_LOGIC;
+ Rc_fifo_rd_d : in STD_LOGIC;
+ Data_Exists_DFF_1 : in STD_LOGIC;
+ Rc_Data_Exists : in STD_LOGIC;
+ \sr_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ \cr_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \IIC2Bus_IntrEvent_reg[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
+ );
+end TopLevel_axi_iic_0_0_reg_interface;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_reg_interface is
+ signal Cr : STD_LOGIC_VECTOR ( 6 to 6 );
+ signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^iic2bus_intrevent\ : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal \^msms_set\ : STD_LOGIC;
+ signal \^q\ : STD_LOGIC_VECTOR ( 6 downto 0 );
+ signal \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^rc_fifo_rd\ : STD_LOGIC;
+ signal \^rc_fifo_wr\ : STD_LOGIC;
+ signal Timing_param_tbuf : STD_LOGIC_VECTOR ( 9 downto 2 );
+ signal Timing_param_thddat : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal Timing_param_thdsta : STD_LOGIC_VECTOR ( 9 downto 1 );
+ signal Timing_param_thigh : STD_LOGIC_VECTOR ( 9 downto 8 );
+ signal Timing_param_tlow : STD_LOGIC_VECTOR ( 9 downto 1 );
+ signal Timing_param_tsudat : STD_LOGIC_VECTOR ( 9 downto 4 );
+ signal Timing_param_tsusta : STD_LOGIC_VECTOR ( 9 downto 2 );
+ signal Timing_param_tsusto : STD_LOGIC_VECTOR ( 9 downto 8 );
+ signal \^tx_fifo_rd\ : STD_LOGIC;
+ signal \^tx_fifo_rst\ : STD_LOGIC;
+ signal \^tx_fifo_wr\ : STD_LOGIC;
+ signal \^tx_fifo_wr_d_reg\ : STD_LOGIC;
+ signal \^adr_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
+ signal \^gpo\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal msms_d1 : STD_LOGIC;
+ signal msms_set_i_i_1_n_0 : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_7_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_7_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[8]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_3_n_0\ : STD_LOGIC;
+ signal sr_i : STD_LOGIC_VECTOR ( 1 to 7 );
+ signal \^sr_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^timing_param_tbuf_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal \^timing_param_thdsta_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \^timing_param_thigh_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \^timing_param_tlow_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \^timing_param_tsudat_i_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^timing_param_tsusta_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal \^timing_param_tsusto_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \Addr_Counters[0].MUXCY_L_I_i_4\ : label is "soft_lutpair34";
+ attribute SOFT_HLUTNM of Data_Exists_DFF_i_2 : label is "soft_lutpair34";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[3]_i_4\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of callingReadAccess_i_1 : label is "soft_lutpair33";
+ attribute SOFT_HLUTNM of \cr_i[5]_i_4\ : label is "soft_lutpair33";
+ attribute SOFT_HLUTNM of sda_cout_reg_i_5 : label is "soft_lutpair32";
+begin
+ D(0) <= \^d\(0);
+ IIC2Bus_IntrEvent(0 to 7) <= \^iic2bus_intrevent\(0 to 7);
+ Msms_set <= \^msms_set\;
+ Q(6 downto 0) <= \^q\(6 downto 0);
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\(3 downto 0) <= \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(3 downto 0);
+ Rc_fifo_rd <= \^rc_fifo_rd\;
+ Rc_fifo_wr <= \^rc_fifo_wr\;
+ Tx_fifo_rd <= \^tx_fifo_rd\;
+ Tx_fifo_rst <= \^tx_fifo_rst\;
+ Tx_fifo_wr <= \^tx_fifo_wr\;
+ Tx_fifo_wr_d_reg <= \^tx_fifo_wr_d_reg\;
+ \adr_i_reg[0]_0\(6 downto 0) <= \^adr_i_reg[0]_0\(6 downto 0);
+ gpo(0) <= \^gpo\(0);
+ \sr_i_reg[0]_0\(0) <= \^sr_i_reg[0]_0\(0);
+ \timing_param_tbuf_i_reg[7]_0\(5 downto 0) <= \^timing_param_tbuf_i_reg[7]_0\(5 downto 0);
+ \timing_param_thdsta_i_reg[7]_0\(4 downto 0) <= \^timing_param_thdsta_i_reg[7]_0\(4 downto 0);
+ \timing_param_thigh_i_reg[7]_0\(7 downto 0) <= \^timing_param_thigh_i_reg[7]_0\(7 downto 0);
+ \timing_param_tlow_i_reg[7]_0\(4 downto 0) <= \^timing_param_tlow_i_reg[7]_0\(4 downto 0);
+ \timing_param_tsudat_i_reg[3]_0\(3 downto 0) <= \^timing_param_tsudat_i_reg[3]_0\(3 downto 0);
+ \timing_param_tsusta_i_reg[7]_0\(5 downto 0) <= \^timing_param_tsusta_i_reg[7]_0\(5 downto 0);
+ \timing_param_tsusto_i_reg[7]_0\(7 downto 0) <= \^timing_param_tsusto_i_reg[7]_0\(7 downto 0);
+\Addr_Counters[0].MUXCY_L_I_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^tx_fifo_wr\,
+ I1 => Tx_fifo_wr_d,
+ O => \FIFO_GEN_DTR.Tx_fifo_wr_reg_0\
+ );
+\Addr_Counters[0].MUXCY_L_I_i_4__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^rc_fifo_rd\,
+ I1 => Rc_fifo_rd_d,
+ O => \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0\
+ );
+\Addr_Counters[0].MUXCY_L_I_i_5\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^rc_fifo_wr\,
+ I1 => Rc_fifo_wr_d,
+ O => \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0\
+ );
+Data_Exists_DFF_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFAAFB0000AAAA"
+ )
+ port map (
+ I0 => \^tx_fifo_wr_d_reg\,
+ I1 => \^tx_fifo_rd\,
+ I2 => Tx_fifo_rd_d,
+ I3 => rdCntrFrmTxFifo,
+ I4 => Data_Exists_DFF,
+ I5 => Data_Exists_DFF_0,
+ O => D_0
+ );
+\Data_Exists_DFF_i_1__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF2FF00002222"
+ )
+ port map (
+ I0 => \^rc_fifo_wr\,
+ I1 => Rc_fifo_wr_d,
+ I2 => Rc_fifo_rd_d,
+ I3 => \^rc_fifo_rd\,
+ I4 => Data_Exists_DFF_1,
+ I5 => Rc_Data_Exists,
+ O => D_1
+ );
+Data_Exists_DFF_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFF4"
+ )
+ port map (
+ I0 => Tx_fifo_wr_d,
+ I1 => \^tx_fifo_wr\,
+ I2 => Bus2IIC_Reset,
+ I3 => \^tx_fifo_rst\,
+ O => \^tx_fifo_wr_d_reg\
+ );
+\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => p_0_in,
+ Q => \^iic2bus_intrevent\(7),
+ R => Bus2IIC_Reset
+ );
+\FIFO_GEN_DTR.Tx_fifo_rd_reg\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Rdy_new_xmt,
+ Q => \^tx_fifo_rd\,
+ R => Bus2IIC_Reset
+ );
+\FIFO_GEN_DTR.Tx_fifo_rst_reg\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Cr(6),
+ Q => \^tx_fifo_rst\,
+ S => Bus2IIC_Reset
+ );
+\FIFO_GEN_DTR.Tx_fifo_wr_reg\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Bus2IIC_WrCE(10),
+ Q => \^tx_fifo_wr\,
+ R => Bus2IIC_Reset
+ );
+\FSM_sequential_scl_state[3]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(0),
+ O => \cr_i_reg[7]_0\
+ );
+\FSM_sequential_scl_state[3]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \q_int_reg[1]_0\(0),
+ I1 => \^q\(4),
+ I2 => \q_int_reg[1]\(0),
+ I3 => stop_scl_reg,
+ I4 => CO(0),
+ O => \cr_i_reg[2]_0\
+ );
+\GPO_GEN.gpo_i_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \GPO_GEN.gpo_i_reg[31]_1\,
+ Q => \^gpo\(0),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \IIC2Bus_IntrEvent_reg[0]_0\(4),
+ Q => \^iic2bus_intrevent\(0),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \IIC2Bus_IntrEvent_reg[0]_0\(3),
+ Q => \^iic2bus_intrevent\(1),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \IIC2Bus_IntrEvent_reg[0]_0\(2),
+ Q => \^iic2bus_intrevent\(2),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \^d\(0),
+ Q => \^iic2bus_intrevent\(3),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \IIC2Bus_IntrEvent_reg[0]_0\(1),
+ Q => \^iic2bus_intrevent\(4),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Aas,
+ Q => \^iic2bus_intrevent\(5),
+ R => Bus2IIC_Reset
+ );
+\IIC2Bus_IntrEvent_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \IIC2Bus_IntrEvent_reg[0]_0\(0),
+ Q => \^iic2bus_intrevent\(6),
+ R => Bus2IIC_Reset
+ );
+\LEVEL_1_GEN.master_sda_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"BA"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \LEVEL_1_GEN.master_sda_reg\,
+ I2 => earlyAckDataState,
+ O => \cr_i_reg[3]_0\
+ );
+\RD_FIFO_CNTRL.Rc_fifo_rd_reg\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Bus2IIC_RdCE(0),
+ Q => \^rc_fifo_rd\,
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.Rc_fifo_wr_reg\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => p_6_out,
+ Q => \^rc_fifo_wr\,
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(8),
+ D => s_axi_wdata(3),
+ Q => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(3),
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(8),
+ D => s_axi_wdata(2),
+ Q => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(2),
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(8),
+ D => s_axi_wdata(1),
+ Q => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(8),
+ D => s_axi_wdata(0),
+ Q => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\RD_FIFO_CNTRL.ro_prev_i_reg\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \RD_FIFO_CNTRL.ro_prev_i_reg_0\,
+ Q => \^d\(0),
+ R => '0'
+ );
+\adr_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(7),
+ Q => \^adr_i_reg[0]_0\(6),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(6),
+ Q => \^adr_i_reg[0]_0\(5),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(5),
+ Q => \^adr_i_reg[0]_0\(4),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(4),
+ Q => \^adr_i_reg[0]_0\(3),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(3),
+ Q => \^adr_i_reg[0]_0\(2),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(2),
+ Q => \^adr_i_reg[0]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\adr_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(9),
+ D => s_axi_wdata(1),
+ Q => \^adr_i_reg[0]_0\(0),
+ R => Bus2IIC_Reset
+ );
+callingReadAccess_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2000"
+ )
+ port map (
+ I0 => \^tx_fifo_rd\,
+ I1 => Tx_fifo_rd_d,
+ I2 => Tx_data_exists,
+ I3 => dynamic_MSMS(0),
+ O => p_3_in
+ );
+clk_cnt_en1_carry_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_thigh(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => S(3)
+ );
+clk_cnt_en1_carry_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thigh(8),
+ I1 => \next_scl_state1_inferred__1/i__carry\(8),
+ I2 => \next_scl_state1_inferred__1/i__carry\(6),
+ I3 => \^timing_param_thigh_i_reg[7]_0\(6),
+ I4 => \next_scl_state1_inferred__1/i__carry\(7),
+ I5 => \^timing_param_thigh_i_reg[7]_0\(7),
+ O => S(2)
+ );
+clk_cnt_en1_carry_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_thigh_i_reg[7]_0\(4),
+ I1 => \next_scl_state1_inferred__1/i__carry\(4),
+ I2 => \next_scl_state1_inferred__1/i__carry\(5),
+ I3 => \^timing_param_thigh_i_reg[7]_0\(5),
+ I4 => \next_scl_state1_inferred__1/i__carry\(3),
+ I5 => \^timing_param_thigh_i_reg[7]_0\(3),
+ O => S(1)
+ );
+clk_cnt_en1_carry_i_4: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_thigh_i_reg[7]_0\(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(2),
+ I2 => \next_scl_state1_inferred__1/i__carry\(0),
+ I3 => \^timing_param_thigh_i_reg[7]_0\(0),
+ I4 => \next_scl_state1_inferred__1/i__carry\(1),
+ I5 => \^timing_param_thigh_i_reg[7]_0\(1),
+ O => S(0)
+ );
+clk_cnt_en2_carry_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_thddat(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_thddat_i_reg[9]_0\(3)
+ );
+clk_cnt_en2_carry_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thddat(8),
+ I1 => \next_scl_state1_inferred__1/i__carry\(8),
+ I2 => \next_scl_state1_inferred__1/i__carry\(6),
+ I3 => Timing_param_thddat(6),
+ I4 => \next_scl_state1_inferred__1/i__carry\(7),
+ I5 => Timing_param_thddat(7),
+ O => \timing_param_thddat_i_reg[9]_0\(2)
+ );
+clk_cnt_en2_carry_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thddat(5),
+ I1 => \next_scl_state1_inferred__1/i__carry\(5),
+ I2 => \next_scl_state1_inferred__1/i__carry\(3),
+ I3 => Timing_param_thddat(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(4),
+ I5 => Timing_param_thddat(4),
+ O => \timing_param_thddat_i_reg[9]_0\(1)
+ );
+clk_cnt_en2_carry_i_4: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thddat(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(2),
+ I2 => \next_scl_state1_inferred__1/i__carry\(1),
+ I3 => Timing_param_thddat(1),
+ I4 => \next_scl_state1_inferred__1/i__carry\(0),
+ I5 => Timing_param_thddat(0),
+ O => \timing_param_thddat_i_reg[9]_0\(0)
+ );
+\cr_i[5]_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^tx_fifo_rd\,
+ I1 => Tx_fifo_rd_d,
+ O => \FIFO_GEN_DTR.Tx_fifo_rd_reg_0\
+ );
+\cr_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(11),
+ D => s_axi_wdata(7),
+ Q => \^q\(6),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(11),
+ D => s_axi_wdata(6),
+ Q => \^q\(5),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \cr_i_reg[2]_2\(2),
+ Q => \^q\(4),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(11),
+ D => s_axi_wdata(4),
+ Q => \^q\(3),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \cr_i_reg[2]_2\(1),
+ Q => \^q\(2),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \cr_i_reg[2]_2\(0),
+ Q => \^q\(1),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(11),
+ D => s_axi_wdata(1),
+ Q => Cr(6),
+ R => Bus2IIC_Reset
+ );
+\cr_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(11),
+ D => s_axi_wdata(0),
+ Q => \^q\(0),
+ R => Bus2IIC_Reset
+ );
+firstDynStartSeen_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00B0"
+ )
+ port map (
+ I0 => firstDynStartSeen,
+ I1 => firstDynStartSeen_reg_0,
+ I2 => \^q\(1),
+ I3 => \^tx_fifo_rst\,
+ O => firstDynStartSeen_reg
+ );
+\i__carry_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_tsusto(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_tsusto_i_reg[9]_0\(3)
+ );
+\i__carry_i_1__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_tsusta(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_tsusta_i_reg[9]_0\(3)
+ );
+\i__carry_i_1__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_tbuf(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_tbuf_i_reg[9]_0\(3)
+ );
+\i__carry_i_1__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_thdsta(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_thdsta_i_reg[9]_0\(3)
+ );
+\i__carry_i_1__3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_tlow(9),
+ I1 => \next_scl_state1_inferred__1/i__carry\(9),
+ O => \timing_param_tlow_i_reg[9]_0\(3)
+ );
+\i__carry_i_1__4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => Timing_param_tsudat(9),
+ I1 => \sda_setup0_inferred__0/i__carry\(9),
+ O => \timing_param_tsudat_i_reg[9]_0\(3)
+ );
+\i__carry_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tsusto(8),
+ I1 => \next_scl_state1_inferred__1/i__carry\(8),
+ I2 => \next_scl_state1_inferred__1/i__carry\(7),
+ I3 => \^timing_param_tsusto_i_reg[7]_0\(7),
+ I4 => \next_scl_state1_inferred__1/i__carry\(6),
+ I5 => \^timing_param_tsusto_i_reg[7]_0\(6),
+ O => \timing_param_tsusto_i_reg[9]_0\(2)
+ );
+\i__carry_i_2__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsusta_i_reg[7]_0\(5),
+ I1 => \next_scl_state1_inferred__1/i__carry\(7),
+ I2 => \next_scl_state1_inferred__1/i__carry\(8),
+ I3 => Timing_param_tsusta(8),
+ I4 => \next_scl_state1_inferred__1/i__carry\(6),
+ I5 => \^timing_param_tsusta_i_reg[7]_0\(4),
+ O => \timing_param_tsusta_i_reg[9]_0\(2)
+ );
+\i__carry_i_2__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tbuf_i_reg[7]_0\(5),
+ I1 => \next_scl_state1_inferred__1/i__carry\(7),
+ I2 => \next_scl_state1_inferred__1/i__carry\(8),
+ I3 => Timing_param_tbuf(8),
+ I4 => \next_scl_state1_inferred__1/i__carry\(6),
+ I5 => \^timing_param_tbuf_i_reg[7]_0\(4),
+ O => \timing_param_tbuf_i_reg[9]_0\(2)
+ );
+\i__carry_i_2__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thdsta(8),
+ I1 => \next_scl_state1_inferred__1/i__carry\(8),
+ I2 => \next_scl_state1_inferred__1/i__carry\(6),
+ I3 => \^timing_param_thdsta_i_reg[7]_0\(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(7),
+ I5 => \^timing_param_thdsta_i_reg[7]_0\(4),
+ O => \timing_param_thdsta_i_reg[9]_0\(2)
+ );
+\i__carry_i_2__3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tlow(8),
+ I1 => \next_scl_state1_inferred__1/i__carry\(8),
+ I2 => \next_scl_state1_inferred__1/i__carry\(6),
+ I3 => \^timing_param_tlow_i_reg[7]_0\(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(7),
+ I5 => \^timing_param_tlow_i_reg[7]_0\(4),
+ O => \timing_param_tlow_i_reg[9]_0\(2)
+ );
+\i__carry_i_2__4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tsudat(8),
+ I1 => \sda_setup0_inferred__0/i__carry\(8),
+ I2 => \sda_setup0_inferred__0/i__carry\(6),
+ I3 => Timing_param_tsudat(6),
+ I4 => \sda_setup0_inferred__0/i__carry\(7),
+ I5 => Timing_param_tsudat(7),
+ O => \timing_param_tsudat_i_reg[9]_0\(2)
+ );
+\i__carry_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsusto_i_reg[7]_0\(5),
+ I1 => \next_scl_state1_inferred__1/i__carry\(5),
+ I2 => \next_scl_state1_inferred__1/i__carry\(3),
+ I3 => \^timing_param_tsusto_i_reg[7]_0\(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(4),
+ I5 => \^timing_param_tsusto_i_reg[7]_0\(4),
+ O => \timing_param_tsusto_i_reg[9]_0\(1)
+ );
+\i__carry_i_3__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsusta_i_reg[7]_0\(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(4),
+ I2 => \next_scl_state1_inferred__1/i__carry\(5),
+ I3 => \^timing_param_tsusta_i_reg[7]_0\(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(3),
+ I5 => Timing_param_tsusta(3),
+ O => \timing_param_tsusta_i_reg[9]_0\(1)
+ );
+\i__carry_i_3__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tbuf_i_reg[7]_0\(3),
+ I1 => \next_scl_state1_inferred__1/i__carry\(5),
+ I2 => \next_scl_state1_inferred__1/i__carry\(4),
+ I3 => \^timing_param_tbuf_i_reg[7]_0\(2),
+ I4 => \next_scl_state1_inferred__1/i__carry\(3),
+ I5 => Timing_param_tbuf(3),
+ O => \timing_param_tbuf_i_reg[9]_0\(1)
+ );
+\i__carry_i_3__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_thdsta_i_reg[7]_0\(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(5),
+ I2 => \next_scl_state1_inferred__1/i__carry\(4),
+ I3 => \^timing_param_thdsta_i_reg[7]_0\(1),
+ I4 => \next_scl_state1_inferred__1/i__carry\(3),
+ I5 => Timing_param_thdsta(3),
+ O => \timing_param_thdsta_i_reg[9]_0\(1)
+ );
+\i__carry_i_3__3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tlow_i_reg[7]_0\(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(5),
+ I2 => \next_scl_state1_inferred__1/i__carry\(3),
+ I3 => Timing_param_tlow(3),
+ I4 => \next_scl_state1_inferred__1/i__carry\(4),
+ I5 => \^timing_param_tlow_i_reg[7]_0\(1),
+ O => \timing_param_tlow_i_reg[9]_0\(1)
+ );
+\i__carry_i_3__4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tsudat(5),
+ I1 => \sda_setup0_inferred__0/i__carry\(5),
+ I2 => \sda_setup0_inferred__0/i__carry\(3),
+ I3 => \^timing_param_tsudat_i_reg[3]_0\(3),
+ I4 => \sda_setup0_inferred__0/i__carry\(4),
+ I5 => Timing_param_tsudat(4),
+ O => \timing_param_tsudat_i_reg[9]_0\(1)
+ );
+\i__carry_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsusto_i_reg[7]_0\(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(2),
+ I2 => \next_scl_state1_inferred__1/i__carry\(1),
+ I3 => \^timing_param_tsusto_i_reg[7]_0\(1),
+ I4 => \next_scl_state1_inferred__1/i__carry\(0),
+ I5 => \^timing_param_tsusto_i_reg[7]_0\(0),
+ O => \timing_param_tsusto_i_reg[9]_0\(0)
+ );
+\i__carry_i_4__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsusta_i_reg[7]_0\(1),
+ I1 => \next_scl_state1_inferred__1/i__carry\(1),
+ I2 => \next_scl_state1_inferred__1/i__carry\(2),
+ I3 => Timing_param_tsusta(2),
+ I4 => \next_scl_state1_inferred__1/i__carry\(0),
+ I5 => \^timing_param_tsusta_i_reg[7]_0\(0),
+ O => \timing_param_tsusta_i_reg[9]_0\(0)
+ );
+\i__carry_i_4__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tbuf(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(2),
+ I2 => \next_scl_state1_inferred__1/i__carry\(0),
+ I3 => \^timing_param_tbuf_i_reg[7]_0\(0),
+ I4 => \next_scl_state1_inferred__1/i__carry\(1),
+ I5 => \^timing_param_tbuf_i_reg[7]_0\(1),
+ O => \timing_param_tbuf_i_reg[9]_0\(0)
+ );
+\i__carry_i_4__2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_thdsta(1),
+ I1 => \next_scl_state1_inferred__1/i__carry\(1),
+ I2 => \next_scl_state1_inferred__1/i__carry\(2),
+ I3 => Timing_param_thdsta(2),
+ I4 => \next_scl_state1_inferred__1/i__carry\(0),
+ I5 => \^timing_param_thdsta_i_reg[7]_0\(0),
+ O => \timing_param_thdsta_i_reg[9]_0\(0)
+ );
+\i__carry_i_4__3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => Timing_param_tlow(2),
+ I1 => \next_scl_state1_inferred__1/i__carry\(2),
+ I2 => \next_scl_state1_inferred__1/i__carry\(0),
+ I3 => \^timing_param_tlow_i_reg[7]_0\(0),
+ I4 => \next_scl_state1_inferred__1/i__carry\(1),
+ I5 => Timing_param_tlow(1),
+ O => \timing_param_tlow_i_reg[9]_0\(0)
+ );
+\i__carry_i_4__4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => \^timing_param_tsudat_i_reg[3]_0\(2),
+ I1 => \sda_setup0_inferred__0/i__carry\(2),
+ I2 => \sda_setup0_inferred__0/i__carry\(1),
+ I3 => \^timing_param_tsudat_i_reg[3]_0\(1),
+ I4 => \sda_setup0_inferred__0/i__carry\(0),
+ I5 => \^timing_param_tsudat_i_reg[3]_0\(0),
+ O => \timing_param_tsudat_i_reg[9]_0\(0)
+ );
+msms_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \^q\(1),
+ Q => msms_d1,
+ R => Bus2IIC_Reset
+ );
+msms_set_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"CE0C0A00"
+ )
+ port map (
+ I0 => \^d\(0),
+ I1 => \sr_i_reg[1]_0\(1),
+ I2 => \^q\(1),
+ I3 => msms_d1,
+ I4 => \^msms_set\,
+ O => msms_set_i_i_1_n_0
+ );
+msms_set_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => msms_set_i_i_1_n_0,
+ Q => \^msms_set\,
+ R => Bus2IIC_Reset
+ );
+new_rcv_dta_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => New_rcv_dta,
+ Q => new_rcv_dta_d1,
+ R => Bus2IIC_Reset
+ );
+\q_int[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"001DFF1DFFFFFFFF"
+ )
+ port map (
+ I0 => CO(0),
+ I1 => stop_scl_reg,
+ I2 => \q_int_reg[1]\(0),
+ I3 => \^q\(4),
+ I4 => \q_int_reg[1]_0\(0),
+ I5 => \q_int_reg[1]_1\,
+ O => stop_scl_reg_reg
+ );
+\s_axi_rdata_i[0]_i_10\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \^gpo\(0),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_thddat(0),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ I4 => sr_i(7),
+ O => \GPO_GEN.gpo_i_reg[31]_0\
+ );
+\s_axi_rdata_i[1]_i_10\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => \^iic2bus_intrevent\(5),
+ I1 => \s_axi_rdata_i[0]_i_7\(4),
+ I2 => Timing_param_thddat(1),
+ I3 => \s_axi_rdata_i[0]_i_7\(3),
+ O => \IIC2Bus_IntrEvent_reg[5]_0\
+ );
+\s_axi_rdata_i[1]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00E2FFFF00E20000"
+ )
+ port map (
+ I0 => \^adr_i_reg[0]_0\(0),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_thdsta(1),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => \s_axi_rdata_i[1]_i_9_n_0\,
+ O => \adr_i_reg[6]_0\
+ );
+\s_axi_rdata_i[1]_i_9\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(1),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_tlow(1),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ I4 => Cr(6),
+ O => \s_axi_rdata_i[1]_i_9_n_0\
+ );
+\s_axi_rdata_i[2]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2F202F2F2F202020"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[2]_i_7_n_0\,
+ I1 => \s_axi_rdata_i[0]_i_7\(4),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => \s_axi_rdata_i[2]_i_8_n_0\,
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => \s_axi_rdata_i[2]_i_9_n_0\,
+ O => \bus2ip_addr_i_reg[6]_0\
+ );
+\s_axi_rdata_i[2]_i_6\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => sr_i(5),
+ I1 => \s_axi_rdata_i[0]_i_7\(4),
+ I2 => Timing_param_thddat(2),
+ I3 => \s_axi_rdata_i[0]_i_7\(3),
+ O => \sr_i_reg[5]_0\
+ );
+\s_axi_rdata_i[2]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_tbuf(2),
+ I1 => Rc_addr(1),
+ I2 => \s_axi_rdata_i[0]_i_7\(2),
+ I3 => Timing_param_tsusta(2),
+ I4 => \s_axi_rdata_i[0]_i_7\(3),
+ I5 => Tx_fifo_data(0),
+ O => \s_axi_rdata_i[2]_i_7_n_0\
+ );
+\s_axi_rdata_i[2]_i_8\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => \^adr_i_reg[0]_0\(1),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_thdsta(2),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ O => \s_axi_rdata_i[2]_i_8_n_0\
+ );
+\s_axi_rdata_i[2]_i_9\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(2),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_tlow(2),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ I4 => \^q\(1),
+ O => \s_axi_rdata_i[2]_i_9_n_0\
+ );
+\s_axi_rdata_i[3]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2F202F2F2F202020"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[3]_i_7_n_0\,
+ I1 => \s_axi_rdata_i[0]_i_7\(4),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => \s_axi_rdata_i[3]_i_8_n_0\,
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => \s_axi_rdata_i[3]_i_9_n_0\,
+ O => \bus2ip_addr_i_reg[6]\
+ );
+\s_axi_rdata_i[3]_i_6\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => sr_i(4),
+ I1 => \s_axi_rdata_i[0]_i_7\(4),
+ I2 => Timing_param_thddat(3),
+ I3 => \s_axi_rdata_i[0]_i_7\(3),
+ O => \sr_i_reg[4]_0\
+ );
+\s_axi_rdata_i[3]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_tbuf(3),
+ I1 => Rc_addr(0),
+ I2 => \s_axi_rdata_i[0]_i_7\(2),
+ I3 => Timing_param_tsusta(3),
+ I4 => \s_axi_rdata_i[0]_i_7\(3),
+ I5 => Tx_fifo_data(1),
+ O => \s_axi_rdata_i[3]_i_7_n_0\
+ );
+\s_axi_rdata_i[3]_i_8\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => \^adr_i_reg[0]_0\(2),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_thdsta(3),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ O => \s_axi_rdata_i[3]_i_8_n_0\
+ );
+\s_axi_rdata_i[3]_i_9\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \^rd_fifo_cntrl.rc_fifo_pirq_i_reg[4]_0\(3),
+ I1 => \s_axi_rdata_i[0]_i_7\(3),
+ I2 => Timing_param_tlow(3),
+ I3 => \s_axi_rdata_i[0]_i_7\(4),
+ I4 => \^q\(2),
+ O => \s_axi_rdata_i[3]_i_9_n_0\
+ );
+\s_axi_rdata_i[4]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FCFC7C7FFFFF7C7F"
+ )
+ port map (
+ I0 => Timing_param_tsudat(4),
+ I1 => \s_axi_rdata_i[0]_i_7\(2),
+ I2 => \s_axi_rdata_i[0]_i_7\(3),
+ I3 => sr_i(3),
+ I4 => \s_axi_rdata_i[0]_i_7\(4),
+ I5 => Timing_param_thddat(4),
+ O => \timing_param_tsudat_i_reg[4]_0\
+ );
+\s_axi_rdata_i[5]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FCFC7C7FFFFF7C7F"
+ )
+ port map (
+ I0 => Timing_param_tsudat(5),
+ I1 => \s_axi_rdata_i[0]_i_7\(2),
+ I2 => \s_axi_rdata_i[0]_i_7\(3),
+ I3 => sr_i(2),
+ I4 => \s_axi_rdata_i[0]_i_7\(4),
+ I5 => Timing_param_thddat(5),
+ O => \timing_param_tsudat_i_reg[5]_0\
+ );
+\s_axi_rdata_i[6]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FCFC7C7FFFFF7C7F"
+ )
+ port map (
+ I0 => Timing_param_tsudat(6),
+ I1 => \s_axi_rdata_i[0]_i_7\(2),
+ I2 => \s_axi_rdata_i[0]_i_7\(3),
+ I3 => sr_i(1),
+ I4 => \s_axi_rdata_i[0]_i_7\(4),
+ I5 => Timing_param_thddat(6),
+ O => \timing_param_tsudat_i_reg[6]_0\
+ );
+\s_axi_rdata_i[7]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FCFC7C7FFFFF7C7F"
+ )
+ port map (
+ I0 => Timing_param_tsudat(7),
+ I1 => \s_axi_rdata_i[0]_i_7\(2),
+ I2 => \s_axi_rdata_i[0]_i_7\(3),
+ I3 => \^sr_i_reg[0]_0\(0),
+ I4 => \s_axi_rdata_i[0]_i_7\(4),
+ I5 => Timing_param_thddat(7),
+ O => \timing_param_tsudat_i_reg[7]_0\
+ );
+\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[8]_i_2_n_0\,
+ I1 => \s_axi_rdata_i[0]_i_7\(0),
+ I2 => \s_axi_rdata_i[8]_i_3_n_0\,
+ I3 => \s_axi_rdata_i_reg[8]\,
+ O => \bus2ip_addr_i_reg[2]\(0)
+ );
+\s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_tbuf(8),
+ I1 => Timing_param_tsusta(8),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => Timing_param_thdsta(8),
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => Timing_param_tlow(8),
+ O => \s_axi_rdata_i[8]_i_2_n_0\
+ );
+\s_axi_rdata_i[8]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_thigh(8),
+ I1 => Timing_param_tsusto(8),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => Timing_param_tsudat(8),
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => Timing_param_thddat(8),
+ O => \s_axi_rdata_i[8]_i_3_n_0\
+ );
+\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E2"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[9]_i_2_n_0\,
+ I1 => \s_axi_rdata_i[0]_i_7\(0),
+ I2 => \s_axi_rdata_i[9]_i_3_n_0\,
+ I3 => \s_axi_rdata_i_reg[8]\,
+ O => \bus2ip_addr_i_reg[2]\(1)
+ );
+\s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_tbuf(9),
+ I1 => Timing_param_tsusta(9),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => Timing_param_thdsta(9),
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => Timing_param_tlow(9),
+ O => \s_axi_rdata_i[9]_i_2_n_0\
+ );
+\s_axi_rdata_i[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => Timing_param_thigh(9),
+ I1 => Timing_param_tsusto(9),
+ I2 => \s_axi_rdata_i[0]_i_7\(1),
+ I3 => Timing_param_tsudat(9),
+ I4 => \s_axi_rdata_i[0]_i_7\(2),
+ I5 => Timing_param_thddat(9),
+ O => \s_axi_rdata_i[9]_i_3_n_0\
+ );
+sda_cout_reg_i_5: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => stop_scl_reg,
+ O => \cr_i_reg[2]_1\
+ );
+\sr_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[0]_1\,
+ Q => \^sr_i_reg[0]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(5),
+ Q => sr_i(1),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(4),
+ Q => sr_i(2),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(3),
+ Q => sr_i(3),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(2),
+ Q => sr_i(4),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(1),
+ Q => sr_i(5),
+ R => Bus2IIC_Reset
+ );
+\sr_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \sr_i_reg[1]_0\(0),
+ Q => sr_i(7),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(1),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(2),
+ Q => Timing_param_tbuf(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(3),
+ Q => Timing_param_tbuf(3),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[6]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(4),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[7]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_tbuf_i_reg[7]_0\(5),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(8),
+ Q => Timing_param_tbuf(8),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tbuf_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(3),
+ D => s_axi_wdata(9),
+ Q => Timing_param_tbuf(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(0),
+ Q => Timing_param_thddat(0),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(1),
+ Q => Timing_param_thddat(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(2),
+ Q => Timing_param_thddat(2),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(3),
+ Q => Timing_param_thddat(3),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(4),
+ Q => Timing_param_thddat(4),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(5),
+ Q => Timing_param_thddat(5),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(6),
+ Q => Timing_param_thddat(6),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(7),
+ Q => Timing_param_thddat(7),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(8),
+ Q => Timing_param_thddat(8),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thddat_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(0),
+ D => s_axi_wdata(9),
+ Q => Timing_param_thddat(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_thdsta_i_reg[7]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[1]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(1),
+ Q => Timing_param_thdsta(1),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(2),
+ Q => Timing_param_thdsta(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(3),
+ Q => Timing_param_thdsta(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_thdsta_i_reg[7]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_thdsta_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_thdsta_i_reg[7]_0\(3),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[7]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_thdsta_i_reg[7]_0\(4),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(8),
+ Q => Timing_param_thdsta(8),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thdsta_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(5),
+ D => s_axi_wdata(9),
+ Q => Timing_param_thdsta(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_thigh_i_reg[7]_0\(0),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(1),
+ Q => \^timing_param_thigh_i_reg[7]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(2),
+ Q => \^timing_param_thigh_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(3),
+ Q => \^timing_param_thigh_i_reg[7]_0\(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_thigh_i_reg[7]_0\(4),
+ R => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_thigh_i_reg[7]_0\(5),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[6]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_thigh_i_reg[7]_0\(6),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[7]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_thigh_i_reg[7]_0\(7),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(8),
+ Q => Timing_param_thigh(8),
+ S => Bus2IIC_Reset
+ );
+\timing_param_thigh_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(2),
+ D => s_axi_wdata(9),
+ Q => Timing_param_thigh(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_tlow_i_reg[7]_0\(0),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(1),
+ Q => Timing_param_tlow(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(2),
+ Q => Timing_param_tlow(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(3),
+ Q => Timing_param_tlow(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_tlow_i_reg[7]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_tlow_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[6]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_tlow_i_reg[7]_0\(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[7]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_tlow_i_reg[7]_0\(4),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(8),
+ Q => Timing_param_tlow(8),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tlow_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(1),
+ D => s_axi_wdata(9),
+ Q => Timing_param_tlow(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_tsudat_i_reg[3]_0\(0),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[1]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(1),
+ Q => \^timing_param_tsudat_i_reg[3]_0\(1),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(2),
+ Q => \^timing_param_tsudat_i_reg[3]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(3),
+ Q => \^timing_param_tsudat_i_reg[3]_0\(3),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(4),
+ Q => Timing_param_tsudat(4),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(5),
+ Q => Timing_param_tsudat(5),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(6),
+ Q => Timing_param_tsudat(6),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(7),
+ Q => Timing_param_tsudat(7),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(8),
+ Q => Timing_param_tsudat(8),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsudat_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(4),
+ D => s_axi_wdata(9),
+ Q => Timing_param_tsudat(9),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[1]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(1),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(1),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(2),
+ Q => Timing_param_tsusta(2),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(3),
+ Q => Timing_param_tsusta(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(3),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(4),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_tsusta_i_reg[7]_0\(5),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(8),
+ Q => Timing_param_tsusta(8),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusta_i_reg[9]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(7),
+ D => s_axi_wdata(9),
+ Q => Timing_param_tsusta(9),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(0),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(0),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(1),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(1),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(2),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(2),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(3),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(3),
+ R => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(4),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(4),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(5),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(5),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[6]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(6),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(6),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[7]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(7),
+ Q => \^timing_param_tsusto_i_reg[7]_0\(7),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(8),
+ Q => Timing_param_tsusto(8),
+ S => Bus2IIC_Reset
+ );
+\timing_param_tsusto_i_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => Bus2IIC_WrCE(6),
+ D => s_axi_wdata(9),
+ Q => Timing_param_tsusto(9),
+ R => Bus2IIC_Reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_shift8 is
+ port (
+ \data_int_reg[7]_0\ : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ tx_under_prev_i_reg : out STD_LOGIC;
+ shift_reg_en : in STD_LOGIC;
+ \data_int_reg[1]_0\ : in STD_LOGIC;
+ \LEVEL_1_GEN.master_sda_reg\ : in STD_LOGIC;
+ slave_sda_reg : in STD_LOGIC;
+ \state__0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \LEVEL_1_GEN.master_sda_reg_0\ : in STD_LOGIC;
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ \data_int_reg[7]_1\ : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ \data_int_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end TopLevel_axi_iic_0_0_shift8;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_shift8 is
+ signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \data_int[7]_i_1_n_0\ : STD_LOGIC;
+ signal \p_2_in__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \data_int[2]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \data_int[3]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \data_int[4]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \data_int[5]_i_1\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \data_int[6]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \data_int[7]_i_2\ : label is "soft_lutpair6";
+begin
+ Q(7 downto 0) <= \^q\(7 downto 0);
+\LEVEL_1_GEN.master_sda_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFAFFFFFF0AFFFCF"
+ )
+ port map (
+ I0 => \LEVEL_1_GEN.master_sda_reg\,
+ I1 => \LEVEL_1_GEN.master_sda_reg_0\,
+ I2 => \state__0\(1),
+ I3 => \state__0\(2),
+ I4 => \state__0\(0),
+ I5 => \^q\(7),
+ O => tx_under_prev_i_reg
+ );
+\data_int[1]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(0),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(0),
+ O => \p_2_in__0\(1)
+ );
+\data_int[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(1),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(1),
+ O => \p_2_in__0\(2)
+ );
+\data_int[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(2),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(2),
+ O => \p_2_in__0\(3)
+ );
+\data_int[4]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(3),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(3),
+ O => \p_2_in__0\(4)
+ );
+\data_int[5]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(4),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(4),
+ O => \p_2_in__0\(5)
+ );
+\data_int[6]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(5),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(5),
+ O => \p_2_in__0\(6)
+ );
+\data_int[7]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => shift_reg_en,
+ I1 => \data_int_reg[1]_0\,
+ O => \data_int[7]_i_1_n_0\
+ );
+\data_int[7]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Tx_fifo_data(6),
+ I1 => \data_int_reg[1]_0\,
+ I2 => \^q\(6),
+ O => \p_2_in__0\(7)
+ );
+\data_int_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \data_int_reg[0]_0\(0),
+ Q => \^q\(0),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(1),
+ Q => \^q\(1),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(2),
+ Q => \^q\(2),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(3),
+ Q => \^q\(3),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(4),
+ Q => \^q\(4),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(5),
+ Q => \^q\(5),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(6),
+ Q => \^q\(6),
+ R => \data_int_reg[7]_1\
+ );
+\data_int_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \data_int[7]_i_1_n_0\,
+ D => \p_2_in__0\(7),
+ Q => \^q\(7),
+ R => \data_int_reg[7]_1\
+ );
+slave_sda_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFCFCCAAFFFFFFFF"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \LEVEL_1_GEN.master_sda_reg\,
+ I2 => slave_sda_reg,
+ I3 => \state__0\(0),
+ I4 => \state__0\(2),
+ I5 => \state__0\(1),
+ O => \data_int_reg[7]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_shift8_1 is
+ port (
+ shift_reg_ld0 : out STD_LOGIC;
+ \cr_i_reg[4]\ : out STD_LOGIC;
+ abgc_i_reg : out STD_LOGIC;
+ aas_i_reg : out STD_LOGIC;
+ detect_start_reg : out STD_LOGIC;
+ \FSM_sequential_state_reg[2]\ : out STD_LOGIC;
+ detect_start_reg_0 : out STD_LOGIC;
+ \data_int_reg[0]_0\ : out STD_LOGIC;
+ shift_reg_ld_reg : in STD_LOGIC;
+ shift_reg_ld_reg_0 : in STD_LOGIC;
+ \state__0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \FSM_sequential_state_reg[1]\ : in STD_LOGIC;
+ master_slave : in STD_LOGIC;
+ \FSM_sequential_state_reg[1]_0\ : in STD_LOGIC;
+ aas_i_reg_0 : in STD_LOGIC;
+ aas_i_reg_1 : in STD_LOGIC;
+ aas_i_reg_2 : in STD_LOGIC;
+ detect_start : in STD_LOGIC;
+ abgc_i_reg_0 : in STD_LOGIC;
+ sda_sample : in STD_LOGIC;
+ arb_lost : in STD_LOGIC;
+ \FSM_sequential_state_reg[2]_0\ : in STD_LOGIC;
+ Ro_prev : in STD_LOGIC;
+ aas_i_reg_3 : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ srw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \data_int_reg[0]_1\ : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aclk : in STD_LOGIC;
+ \data_int_reg[0]_2\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_axi_iic_0_0_shift8_1 : entity is "shift8";
+end TopLevel_axi_iic_0_0_shift8_1;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_shift8_1 is
+ signal \FSM_sequential_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_10_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_8_n_0\ : STD_LOGIC;
+ signal abgc_i_i_2_n_0 : STD_LOGIC;
+ signal abgc_i_i_3_n_0 : STD_LOGIC;
+ signal \^abgc_i_reg\ : STD_LOGIC;
+ signal i2c_header : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal shift_reg_ld_i_3_n_0 : STD_LOGIC;
+ signal slave_sda_i_3_n_0 : STD_LOGIC;
+ signal slave_sda_i_4_n_0 : STD_LOGIC;
+begin
+ abgc_i_reg <= \^abgc_i_reg\;
+\FSM_sequential_state[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000E000EFF0F0F0F"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => \FSM_sequential_state[2]_i_10_n_0\,
+ I2 => \state__0\(0),
+ I3 => \state__0\(1),
+ I4 => Ro_prev,
+ I5 => \state__0\(2),
+ O => detect_start_reg_0
+ );
+\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F5F4F5F0FFFFFFF0"
+ )
+ port map (
+ I0 => \FSM_sequential_state[1]_i_3_n_0\,
+ I1 => Q(1),
+ I2 => \FSM_sequential_state_reg[1]\,
+ I3 => \^abgc_i_reg\,
+ I4 => master_slave,
+ I5 => \FSM_sequential_state_reg[1]_0\,
+ O => \cr_i_reg[4]\
+ );
+\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EEFFEFEFFFFFFFFF"
+ )
+ port map (
+ I0 => sda_sample,
+ I1 => arb_lost,
+ I2 => i2c_header(0),
+ I3 => Q(1),
+ I4 => master_slave,
+ I5 => aas_i_reg_0,
+ O => \FSM_sequential_state[1]_i_3_n_0\
+ );
+\FSM_sequential_state[2]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFABAAAAAB"
+ )
+ port map (
+ I0 => master_slave,
+ I1 => slave_sda_i_4_n_0,
+ I2 => slave_sda_i_3_n_0,
+ I3 => i2c_header(7),
+ I4 => aas_i_reg_3(6),
+ I5 => abgc_i_reg_0,
+ O => \FSM_sequential_state[2]_i_10_n_0\
+ );
+\FSM_sequential_state[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"20FF2000FFFF00FF"
+ )
+ port map (
+ I0 => \FSM_sequential_state[2]_i_8_n_0\,
+ I1 => \FSM_sequential_state_reg[2]_0\,
+ I2 => \FSM_sequential_state[2]_i_10_n_0\,
+ I3 => \state__0\(2),
+ I4 => detect_start,
+ I5 => \state__0\(1),
+ O => \FSM_sequential_state_reg[2]\
+ );
+\FSM_sequential_state[2]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"35"
+ )
+ port map (
+ I0 => i2c_header(0),
+ I1 => Q(1),
+ I2 => master_slave,
+ O => \FSM_sequential_state[2]_i_8_n_0\
+ );
+aas_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00A80000"
+ )
+ port map (
+ I0 => \^abgc_i_reg\,
+ I1 => aas_i_reg_0,
+ I2 => aas_i_reg_1,
+ I3 => aas_i_reg_2,
+ I4 => Q(0),
+ O => aas_i_reg
+ );
+abgc_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044440400"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => Q(0),
+ I2 => abgc_i_i_2_n_0,
+ I3 => abgc_i_i_3_n_0,
+ I4 => abgc_i_reg_0,
+ I5 => aas_i_reg_2,
+ O => detect_start_reg
+ );
+abgc_i_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFF7"
+ )
+ port map (
+ I0 => \state__0\(1),
+ I1 => \state__0\(2),
+ I2 => \state__0\(0),
+ I3 => i2c_header(2),
+ I4 => i2c_header(3),
+ I5 => i2c_header(4),
+ O => abgc_i_i_2_n_0
+ );
+abgc_i_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => i2c_header(6),
+ I1 => i2c_header(0),
+ I2 => i2c_header(1),
+ I3 => Q(2),
+ I4 => i2c_header(5),
+ I5 => i2c_header(7),
+ O => abgc_i_i_3_n_0
+ );
+\data_int_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => \data_int_reg[0]_2\,
+ Q => i2c_header(0),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(0),
+ Q => i2c_header(1),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(1),
+ Q => i2c_header(2),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(2),
+ Q => i2c_header(3),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(3),
+ Q => i2c_header(4),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(4),
+ Q => i2c_header(5),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(5),
+ Q => i2c_header(6),
+ R => \data_int_reg[0]_1\
+ );
+\data_int_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => i2c_header(6),
+ Q => i2c_header(7),
+ R => \data_int_reg[0]_1\
+ );
+shift_reg_ld_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFEEEEEFEE"
+ )
+ port map (
+ I0 => shift_reg_ld_reg,
+ I1 => shift_reg_ld_reg_0,
+ I2 => \state__0\(2),
+ I3 => \state__0\(0),
+ I4 => \state__0\(1),
+ I5 => shift_reg_ld_i_3_n_0,
+ O => shift_reg_ld0
+ );
+shift_reg_ld_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0808000808000000"
+ )
+ port map (
+ I0 => \state__0\(1),
+ I1 => \state__0\(2),
+ I2 => \state__0\(0),
+ I3 => master_slave,
+ I4 => Q(1),
+ I5 => i2c_header(0),
+ O => shift_reg_ld_i_3_n_0
+ );
+slave_sda_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAAEB"
+ )
+ port map (
+ I0 => abgc_i_reg_0,
+ I1 => aas_i_reg_3(6),
+ I2 => i2c_header(7),
+ I3 => slave_sda_i_3_n_0,
+ I4 => slave_sda_i_4_n_0,
+ O => \^abgc_i_reg\
+ );
+slave_sda_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6FF6FFFFFFFF6FF6"
+ )
+ port map (
+ I0 => i2c_header(4),
+ I1 => aas_i_reg_3(3),
+ I2 => aas_i_reg_3(5),
+ I3 => i2c_header(6),
+ I4 => aas_i_reg_3(4),
+ I5 => i2c_header(5),
+ O => slave_sda_i_3_n_0
+ );
+slave_sda_i_4: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6FF6FFFFFFFF6FF6"
+ )
+ port map (
+ I0 => i2c_header(1),
+ I1 => aas_i_reg_3(0),
+ I2 => aas_i_reg_3(1),
+ I3 => i2c_header(2),
+ I4 => aas_i_reg_3(2),
+ I5 => i2c_header(3),
+ O => slave_sda_i_4_n_0
+ );
+srw_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EFFF2000"
+ )
+ port map (
+ I0 => i2c_header(0),
+ I1 => \state__0\(0),
+ I2 => \state__0\(2),
+ I3 => \state__0\(1),
+ I4 => srw_i_reg(0),
+ O => \data_int_reg[0]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_soft_reset is
+ port (
+ sw_rst_cond_d1 : out STD_LOGIC;
+ AXI_Bus2IP_Reset : out STD_LOGIC;
+ ctrlFifoDin : out STD_LOGIC_VECTOR ( 0 to 1 );
+ SR : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sw_rst_cond : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ reset_trig0 : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ Tx_fifo_rst : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_soft_reset;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_soft_reset is
+ signal \^axi_bus2ip_reset\ : STD_LOGIC;
+ signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
+ signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
+ signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
+ signal \RESET_FLOPS[3].RST_FLOPS_n_0\ : STD_LOGIC;
+ signal S : STD_LOGIC;
+ signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal flop_q_chain : STD_LOGIC_VECTOR ( 1 to 3 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair62";
+ attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair62";
+ attribute IS_CE_INVERTED : string;
+ attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
+ attribute IS_S_INVERTED : string;
+ attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
+ attribute box_type : string;
+ attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
+ attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
+ attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
+ attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair63";
+ attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
+ attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
+ attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
+ attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair63";
+ attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
+ attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
+ attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
+begin
+ AXI_Bus2IP_Reset <= \^axi_bus2ip_reset\;
+ SR(0) <= \^sr\(0);
+\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => s_axi_wdata(1),
+ I1 => \^sr\(0),
+ I2 => Tx_fifo_rst,
+ O => ctrlFifoDin(0)
+ );
+\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => s_axi_wdata(0),
+ I1 => \^sr\(0),
+ I2 => Tx_fifo_rst,
+ O => ctrlFifoDin(1)
+ );
+\GPO_GEN.gpo_i[31]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \RESET_FLOPS[3].RST_FLOPS_n_0\,
+ I1 => s_axi_aresetn,
+ O => \^sr\(0)
+ );
+\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => S,
+ Q => flop_q_chain(1),
+ R => \^axi_bus2ip_reset\
+ );
+\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
+ Q => flop_q_chain(2),
+ R => \^axi_bus2ip_reset\
+ );
+\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => S,
+ I1 => flop_q_chain(1),
+ O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
+ );
+\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
+ Q => flop_q_chain(3),
+ R => \^axi_bus2ip_reset\
+ );
+\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => S,
+ I1 => flop_q_chain(2),
+ O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
+ );
+\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0',
+ IS_C_INVERTED => '0',
+ IS_D_INVERTED => '0',
+ IS_R_INVERTED => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
+ Q => \RESET_FLOPS[3].RST_FLOPS_n_0\,
+ R => \^axi_bus2ip_reset\
+ );
+\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => S,
+ I1 => flop_q_chain(3),
+ O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
+ );
+reset_trig_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => reset_trig0,
+ Q => S,
+ R => \^axi_bus2ip_reset\
+ );
+rst_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => s_axi_aresetn,
+ O => \^axi_bus2ip_reset\
+ );
+sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sw_rst_cond,
+ Q => sw_rst_cond_d1,
+ R => \^axi_bus2ip_reset\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_upcnt_n is
+ port (
+ \FSM_sequential_scl_state_reg[1]\ : out STD_LOGIC;
+ \q_int_reg[0]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \q_int_reg[4]_0\ : in STD_LOGIC;
+ CO : in STD_LOGIC_VECTOR ( 0 to 0 );
+ scndry_out : in STD_LOGIC;
+ \q_int_reg[1]_0\ : in STD_LOGIC;
+ \q_int_reg[1]_1\ : in STD_LOGIC;
+ \q_int_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ arb_lost : in STD_LOGIC;
+ \q_int_reg[9]_0\ : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_upcnt_n;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_upcnt_n is
+ signal \^fsm_sequential_scl_state_reg[1]\ : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 8 downto 0 );
+ signal \q_int[0]_i_1__1_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_2__1_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_3__1_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_4_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_5__0_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_7_n_0\ : STD_LOGIC;
+ signal \q_int[1]_i_3_n_0\ : STD_LOGIC;
+ signal \q_int[2]_i_2_n_0\ : STD_LOGIC;
+ signal \q_int[3]_i_2_n_0\ : STD_LOGIC;
+ signal \q_int[4]_i_2_n_0\ : STD_LOGIC;
+ signal \q_int[5]_i_2_n_0\ : STD_LOGIC;
+ signal \q_int[6]_i_2_n_0\ : STD_LOGIC;
+ signal \q_int[7]_i_2_n_0\ : STD_LOGIC;
+ signal \^q_int_reg[0]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \q_int[0]_i_3__1\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \q_int[1]_i_3\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \q_int[5]_i_2\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \q_int[6]_i_2\ : label is "soft_lutpair4";
+begin
+ \FSM_sequential_scl_state_reg[1]\ <= \^fsm_sequential_scl_state_reg[1]\;
+ \q_int_reg[0]_0\(9 downto 0) <= \^q_int_reg[0]_0\(9 downto 0);
+\q_int[0]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"1F"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => Q(1),
+ I2 => Q(3),
+ O => \q_int[0]_i_1__1_n_0\
+ );
+\q_int[0]_i_2__1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2020202020222222"
+ )
+ port map (
+ I0 => \q_int[0]_i_3__1_n_0\,
+ I1 => \q_int[0]_i_4_n_0\,
+ I2 => \q_int[0]_i_5__0_n_0\,
+ I3 => \q_int_reg[4]_0\,
+ I4 => \^fsm_sequential_scl_state_reg[1]\,
+ I5 => \q_int[0]_i_7_n_0\,
+ O => \q_int[0]_i_2__1_n_0\
+ );
+\q_int[0]_i_3__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAA6AAA"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(9),
+ I1 => \^q_int_reg[0]_0\(8),
+ I2 => \^q_int_reg[0]_0\(7),
+ I3 => \^q_int_reg[0]_0\(6),
+ I4 => \q_int[3]_i_2_n_0\,
+ O => \q_int[0]_i_3__1_n_0\
+ );
+\q_int[0]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000005500FF0051"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \q_int_reg[1]_1\,
+ I2 => \q_int_reg[1]_2\(0),
+ I3 => Q(0),
+ I4 => Q(1),
+ I5 => Q(3),
+ O => \q_int[0]_i_4_n_0\
+ );
+\q_int[0]_i_5__0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => Q(2),
+ O => \q_int[0]_i_5__0_n_0\
+ );
+\q_int[0]_i_6\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => arb_lost,
+ O => \^fsm_sequential_scl_state_reg[1]\
+ );
+\q_int[0]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"54"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => CO(0),
+ I2 => scndry_out,
+ O => \q_int[0]_i_7_n_0\
+ );
+\q_int[1]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000445444540000"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[1]_0\,
+ I3 => \q_int[0]_i_7_n_0\,
+ I4 => \q_int[1]_i_3_n_0\,
+ I5 => \^q_int_reg[0]_0\(8),
+ O => p_0_in(8)
+ );
+\q_int[1]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(7),
+ I1 => \^q_int_reg[0]_0\(6),
+ I2 => \q_int[3]_i_2_n_0\,
+ O => \q_int[1]_i_3_n_0\
+ );
+\q_int[2]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4454000000004454"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[1]_0\,
+ I3 => \q_int[0]_i_7_n_0\,
+ I4 => \q_int[2]_i_2_n_0\,
+ I5 => \^q_int_reg[0]_0\(7),
+ O => p_0_in(7)
+ );
+\q_int[2]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \q_int[3]_i_2_n_0\,
+ I1 => \^q_int_reg[0]_0\(6),
+ O => \q_int[2]_i_2_n_0\
+ );
+\q_int[3]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4454000000004454"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[1]_0\,
+ I3 => \q_int[0]_i_7_n_0\,
+ I4 => \q_int[3]_i_2_n_0\,
+ I5 => \^q_int_reg[0]_0\(6),
+ O => p_0_in(6)
+ );
+\q_int[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFFFFFFFFFF"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(4),
+ I1 => \^q_int_reg[0]_0\(2),
+ I2 => \^q_int_reg[0]_0\(0),
+ I3 => \^q_int_reg[0]_0\(1),
+ I4 => \^q_int_reg[0]_0\(3),
+ I5 => \^q_int_reg[0]_0\(5),
+ O => \q_int[3]_i_2_n_0\
+ );
+\q_int[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044444555"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[4]_0\,
+ I3 => \^fsm_sequential_scl_state_reg[1]\,
+ I4 => \q_int[0]_i_7_n_0\,
+ I5 => \q_int[4]_i_2_n_0\,
+ O => p_0_in(5)
+ );
+\q_int[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"9555555555555555"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(5),
+ I1 => \^q_int_reg[0]_0\(4),
+ I2 => \^q_int_reg[0]_0\(2),
+ I3 => \^q_int_reg[0]_0\(0),
+ I4 => \^q_int_reg[0]_0\(1),
+ I5 => \^q_int_reg[0]_0\(3),
+ O => \q_int[4]_i_2_n_0\
+ );
+\q_int[5]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044444555"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[4]_0\,
+ I3 => \^fsm_sequential_scl_state_reg[1]\,
+ I4 => \q_int[0]_i_7_n_0\,
+ I5 => \q_int[5]_i_2_n_0\,
+ O => p_0_in(4)
+ );
+\q_int[5]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"95555555"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(4),
+ I1 => \^q_int_reg[0]_0\(3),
+ I2 => \^q_int_reg[0]_0\(1),
+ I3 => \^q_int_reg[0]_0\(0),
+ I4 => \^q_int_reg[0]_0\(2),
+ O => \q_int[5]_i_2_n_0\
+ );
+\q_int[6]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044444555"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[4]_0\,
+ I3 => \^fsm_sequential_scl_state_reg[1]\,
+ I4 => \q_int[0]_i_7_n_0\,
+ I5 => \q_int[6]_i_2_n_0\,
+ O => p_0_in(3)
+ );
+\q_int[6]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9555"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(3),
+ I1 => \^q_int_reg[0]_0\(2),
+ I2 => \^q_int_reg[0]_0\(0),
+ I3 => \^q_int_reg[0]_0\(1),
+ O => \q_int[6]_i_2_n_0\
+ );
+\q_int[7]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044444555"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[4]_0\,
+ I3 => \^fsm_sequential_scl_state_reg[1]\,
+ I4 => \q_int[0]_i_7_n_0\,
+ I5 => \q_int[7]_i_2_n_0\,
+ O => p_0_in(2)
+ );
+\q_int[7]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"95"
+ )
+ port map (
+ I0 => \^q_int_reg[0]_0\(2),
+ I1 => \^q_int_reg[0]_0\(1),
+ I2 => \^q_int_reg[0]_0\(0),
+ O => \q_int[7]_i_2_n_0\
+ );
+\q_int[8]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000445444540000"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[1]_0\,
+ I3 => \q_int[0]_i_7_n_0\,
+ I4 => \^q_int_reg[0]_0\(1),
+ I5 => \^q_int_reg[0]_0\(0),
+ O => p_0_in(1)
+ );
+\q_int[9]_i_1__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000044444555"
+ )
+ port map (
+ I0 => \q_int[0]_i_4_n_0\,
+ I1 => \q_int[0]_i_5__0_n_0\,
+ I2 => \q_int_reg[4]_0\,
+ I3 => \^fsm_sequential_scl_state_reg[1]\,
+ I4 => \q_int[0]_i_7_n_0\,
+ I5 => \^q_int_reg[0]_0\(0),
+ O => p_0_in(0)
+ );
+\q_int_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => \q_int[0]_i_2__1_n_0\,
+ Q => \^q_int_reg[0]_0\(9),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(8),
+ Q => \^q_int_reg[0]_0\(8),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(7),
+ Q => \^q_int_reg[0]_0\(7),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(6),
+ Q => \^q_int_reg[0]_0\(6),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(5),
+ Q => \^q_int_reg[0]_0\(5),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(4),
+ Q => \^q_int_reg[0]_0\(4),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(3),
+ Q => \^q_int_reg[0]_0\(3),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(2),
+ Q => \^q_int_reg[0]_0\(2),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(1),
+ Q => \^q_int_reg[0]_0\(1),
+ R => \q_int_reg[9]_0\
+ );
+\q_int_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__1_n_0\,
+ D => p_0_in(0),
+ Q => \^q_int_reg[0]_0\(0),
+ R => \q_int_reg[9]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_upcnt_n_2 is
+ port (
+ gen_stop_d1_reg : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ sda_setup : in STD_LOGIC;
+ gen_stop_d1 : in STD_LOGIC;
+ gen_stop : in STD_LOGIC;
+ \q_int[0]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rsta_d1 : in STD_LOGIC;
+ tx_under_prev_d1 : in STD_LOGIC;
+ \q_int[0]_i_3_1\ : in STD_LOGIC;
+ \q_int[0]_i_3_2\ : in STD_LOGIC;
+ \q_int[0]_i_3_3\ : in STD_LOGIC;
+ \q_int_reg[0]_0\ : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_axi_iic_0_0_upcnt_n_2 : entity is "upcnt_n";
+end TopLevel_axi_iic_0_0_upcnt_n_2;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_upcnt_n_2 is
+ signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal \^gen_stop_d1_reg\ : STD_LOGIC;
+ signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal \q_int[0]_i_1_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_4__0_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_5_n_0\ : STD_LOGIC;
+ signal \q_int[1]_i_1__1_n_0\ : STD_LOGIC;
+ signal \q_int[2]_i_1__1_n_0\ : STD_LOGIC;
+ signal \q_int[3]_i_1__1_n_0\ : STD_LOGIC;
+ signal \q_int[4]_i_1__0_n_0\ : STD_LOGIC;
+ signal \q_int[4]_i_2__0_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \q_int[1]_i_1__1\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \q_int[2]_i_1__1\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \q_int[3]_i_1__1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \q_int[4]_i_1__0\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \q_int[6]_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \q_int[7]_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \q_int[8]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \q_int[9]_i_1\ : label is "soft_lutpair12";
+begin
+ Q(9 downto 0) <= \^q\(9 downto 0);
+ gen_stop_d1_reg <= \^gen_stop_d1_reg\;
+\q_int[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => sda_setup,
+ I1 => \^gen_stop_d1_reg\,
+ O => \q_int[0]_i_1_n_0\
+ );
+\q_int[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000BFFF4000"
+ )
+ port map (
+ I0 => \q_int[0]_i_4__0_n_0\,
+ I1 => \^q\(6),
+ I2 => \^q\(7),
+ I3 => \^q\(8),
+ I4 => \^q\(9),
+ I5 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(9)
+ );
+\q_int[0]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"F4"
+ )
+ port map (
+ I0 => gen_stop_d1,
+ I1 => gen_stop,
+ I2 => \q_int[0]_i_5_n_0\,
+ O => \^gen_stop_d1_reg\
+ );
+\q_int[0]_i_4__0\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFFFFFFFFFF"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \^q\(2),
+ I2 => \^q\(0),
+ I3 => \^q\(1),
+ I4 => \^q\(3),
+ I5 => \^q\(5),
+ O => \q_int[0]_i_4__0_n_0\
+ );
+\q_int[0]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"22F2FFFFFFFF22F2"
+ )
+ port map (
+ I0 => \q_int[0]_i_3_0\(0),
+ I1 => rsta_d1,
+ I2 => tx_under_prev_d1,
+ I3 => \q_int[0]_i_3_1\,
+ I4 => \q_int[0]_i_3_2\,
+ I5 => \q_int[0]_i_3_3\,
+ O => \q_int[0]_i_5_n_0\
+ );
+\q_int[1]_i_1__1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55150040"
+ )
+ port map (
+ I0 => \^gen_stop_d1_reg\,
+ I1 => \^q\(7),
+ I2 => \^q\(6),
+ I3 => \q_int[0]_i_4__0_n_0\,
+ I4 => \^q\(8),
+ O => \q_int[1]_i_1__1_n_0\
+ );
+\q_int[2]_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4510"
+ )
+ port map (
+ I0 => \^gen_stop_d1_reg\,
+ I1 => \q_int[0]_i_4__0_n_0\,
+ I2 => \^q\(6),
+ I3 => \^q\(7),
+ O => \q_int[2]_i_1__1_n_0\
+ );
+\q_int[3]_i_1__1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"41"
+ )
+ port map (
+ I0 => \^gen_stop_d1_reg\,
+ I1 => \q_int[0]_i_4__0_n_0\,
+ I2 => \^q\(6),
+ O => \q_int[3]_i_1__1_n_0\
+ );
+\q_int[4]_i_1__0\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"41"
+ )
+ port map (
+ I0 => \^gen_stop_d1_reg\,
+ I1 => \q_int[4]_i_2__0_n_0\,
+ I2 => \^q\(5),
+ O => \q_int[4]_i_1__0_n_0\
+ );
+\q_int[4]_i_2__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFFFFFF"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \^q\(1),
+ I2 => \^q\(0),
+ I3 => \^q\(2),
+ I4 => \^q\(4),
+ O => \q_int[4]_i_2__0_n_0\
+ );
+\q_int[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000007FFF8000"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(0),
+ I2 => \^q\(1),
+ I3 => \^q\(3),
+ I4 => \^q\(4),
+ I5 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(4)
+ );
+\q_int[6]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00007F80"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => \^q\(2),
+ I3 => \^q\(3),
+ I4 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(3)
+ );
+\q_int[7]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0078"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(1),
+ I2 => \^q\(2),
+ I3 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(2)
+ );
+\q_int[8]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"06"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \^q\(0),
+ I2 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(1)
+ );
+\q_int[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^gen_stop_d1_reg\,
+ O => \p_0_in__0\(0)
+ );
+\q_int_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(9),
+ Q => \^q\(9),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \q_int[1]_i_1__1_n_0\,
+ Q => \^q\(8),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \q_int[2]_i_1__1_n_0\,
+ Q => \^q\(7),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \q_int[3]_i_1__1_n_0\,
+ Q => \^q\(6),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \q_int[4]_i_1__0_n_0\,
+ Q => \^q\(5),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(4),
+ Q => \^q\(4),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(3),
+ Q => \^q\(3),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(2),
+ Q => \^q\(2),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(1),
+ Q => \^q\(1),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1_n_0\,
+ D => \p_0_in__0\(0),
+ Q => \^q\(0),
+ R => \q_int_reg[0]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \TopLevel_axi_iic_0_0_upcnt_n__parameterized0\ is
+ port (
+ EarlyAckDataState0 : out STD_LOGIC;
+ \q_int_reg[1]_0\ : out STD_LOGIC;
+ \FSM_sequential_state_reg[2]\ : out STD_LOGIC;
+ \FSM_sequential_state_reg[1]\ : out STD_LOGIC;
+ \FSM_sequential_state_reg[0]\ : out STD_LOGIC;
+ detect_start : in STD_LOGIC;
+ \state__0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ bit_cnt_en : in STD_LOGIC;
+ \FSM_sequential_state_reg[0]_0\ : in STD_LOGIC;
+ EarlyAckDataState_reg : in STD_LOGIC;
+ EarlyAckDataState_reg_0 : in STD_LOGIC;
+ scl_falling_edge : in STD_LOGIC;
+ dtc_i_reg : in STD_LOGIC;
+ \FSM_sequential_state_reg[2]_0\ : in STD_LOGIC;
+ \FSM_sequential_state_reg[2]_1\ : in STD_LOGIC;
+ state0 : in STD_LOGIC;
+ \FSM_sequential_state_reg[1]_0\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_state_reg[1]_1\ : in STD_LOGIC;
+ \FSM_sequential_state_reg[0]_1\ : in STD_LOGIC;
+ \q_int_reg[0]_0\ : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \TopLevel_axi_iic_0_0_upcnt_n__parameterized0\ : entity is "upcnt_n";
+end \TopLevel_axi_iic_0_0_upcnt_n__parameterized0\;
+
+architecture STRUCTURE of \TopLevel_axi_iic_0_0_upcnt_n__parameterized0\ is
+ signal \FSM_sequential_state[2]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_6_n_0\ : STD_LOGIC;
+ signal bit_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \q_int[0]_i_1__0_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_2__0_n_0\ : STD_LOGIC;
+ signal \q_int[0]_i_3__0_n_0\ : STD_LOGIC;
+ signal \q_int[1]_i_1_n_0\ : STD_LOGIC;
+ signal \q_int[2]_i_1_n_0\ : STD_LOGIC;
+ signal \q_int[3]_i_1_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \q_int[0]_i_2__0\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \q_int[0]_i_3__0\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair3";
+begin
+EarlyAckDataState_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAAAAABAAAAAAE"
+ )
+ port map (
+ I0 => EarlyAckDataState_reg,
+ I1 => bit_cnt(3),
+ I2 => bit_cnt(1),
+ I3 => bit_cnt(0),
+ I4 => bit_cnt(2),
+ I5 => EarlyAckDataState_reg_0,
+ O => EarlyAckDataState0
+ );
+\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000E200"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \FSM_sequential_state[2]_i_2_n_0\,
+ I2 => \FSM_sequential_state_reg[0]_1\,
+ I3 => Q(0),
+ I4 => \FSM_sequential_state_reg[1]_1\,
+ O => \FSM_sequential_state_reg[0]\
+ );
+\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000E200"
+ )
+ port map (
+ I0 => \state__0\(1),
+ I1 => \FSM_sequential_state[2]_i_2_n_0\,
+ I2 => \FSM_sequential_state_reg[1]_0\,
+ I3 => Q(0),
+ I4 => \FSM_sequential_state_reg[1]_1\,
+ O => \FSM_sequential_state_reg[1]\
+ );
+\FSM_sequential_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000EEE222E2"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => \FSM_sequential_state[2]_i_2_n_0\,
+ I2 => \FSM_sequential_state_reg[2]_0\,
+ I3 => \state__0\(0),
+ I4 => \FSM_sequential_state_reg[2]_1\,
+ I5 => state0,
+ O => \FSM_sequential_state_reg[2]\
+ );
+\FSM_sequential_state[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033FEBAFC"
+ )
+ port map (
+ I0 => \FSM_sequential_state[2]_i_6_n_0\,
+ I1 => \state__0\(0),
+ I2 => detect_start,
+ I3 => \state__0\(2),
+ I4 => \state__0\(1),
+ I5 => \FSM_sequential_state_reg[0]_0\,
+ O => \FSM_sequential_state[2]_i_2_n_0\
+ );
+\FSM_sequential_state[2]_i_6\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0010"
+ )
+ port map (
+ I0 => bit_cnt(1),
+ I1 => bit_cnt(0),
+ I2 => bit_cnt(3),
+ I3 => bit_cnt(2),
+ O => \FSM_sequential_state[2]_i_6_n_0\
+ );
+dtc_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0080FFFF00800000"
+ )
+ port map (
+ I0 => bit_cnt(2),
+ I1 => bit_cnt(0),
+ I2 => bit_cnt(1),
+ I3 => bit_cnt(3),
+ I4 => scl_falling_edge,
+ I5 => dtc_i_reg,
+ O => \q_int_reg[1]_0\
+ );
+\q_int[0]_i_1__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EFEFFEEF"
+ )
+ port map (
+ I0 => bit_cnt_en,
+ I1 => detect_start,
+ I2 => \state__0\(2),
+ I3 => \state__0\(1),
+ I4 => \state__0\(0),
+ O => \q_int[0]_i_1__0_n_0\
+ );
+\q_int[0]_i_2__0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"2AAA8000"
+ )
+ port map (
+ I0 => \q_int[0]_i_3__0_n_0\,
+ I1 => bit_cnt(1),
+ I2 => bit_cnt(0),
+ I3 => bit_cnt(2),
+ I4 => bit_cnt(3),
+ O => \q_int[0]_i_2__0_n_0\
+ );
+\q_int[0]_i_3__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00B4"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ I3 => detect_start,
+ O => \q_int[0]_i_3__0_n_0\
+ );
+\q_int[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2A80"
+ )
+ port map (
+ I0 => \q_int[0]_i_3__0_n_0\,
+ I1 => bit_cnt(0),
+ I2 => bit_cnt(1),
+ I3 => bit_cnt(2),
+ O => \q_int[1]_i_1_n_0\
+ );
+\q_int[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000441444140000"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => \state__0\(2),
+ I2 => \state__0\(1),
+ I3 => \state__0\(0),
+ I4 => bit_cnt(0),
+ I5 => bit_cnt(1),
+ O => \q_int[2]_i_1_n_0\
+ );
+\q_int[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00004414"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => \state__0\(2),
+ I2 => \state__0\(1),
+ I3 => \state__0\(0),
+ I4 => bit_cnt(0),
+ O => \q_int[3]_i_1_n_0\
+ );
+\q_int_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__0_n_0\,
+ D => \q_int[0]_i_2__0_n_0\,
+ Q => bit_cnt(3),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__0_n_0\,
+ D => \q_int[1]_i_1_n_0\,
+ Q => bit_cnt(2),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__0_n_0\,
+ D => \q_int[2]_i_1_n_0\,
+ Q => bit_cnt(1),
+ R => \q_int_reg[0]_0\
+ );
+\q_int_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \q_int[0]_i_1__0_n_0\,
+ D => \q_int[3]_i_1_n_0\,
+ Q => bit_cnt(0),
+ R => \q_int_reg[0]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_debounce is
+ port (
+ scl_rising_edge0 : out STD_LOGIC;
+ scndry_out : out STD_LOGIC;
+ scl_rin_d1 : in STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_debounce;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_debounce is
+begin
+INPUT_DOUBLE_REGS: entity work.TopLevel_axi_iic_0_0_cdc_sync_4
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ scl_i => scl_i,
+ scl_rin_d1 => scl_rin_d1,
+ scl_rising_edge0 => scl_rising_edge0,
+ scndry_out => scndry_out
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_debounce_3 is
+ port (
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : out STD_LOGIC;
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : out STD_LOGIC;
+ sda_rin_d1 : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_axi_iic_0_0_debounce_3 : entity is "debounce";
+end TopLevel_axi_iic_0_0_debounce_3;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_debounce_3 is
+begin
+INPUT_DOUBLE_REGS: entity work.TopLevel_axi_iic_0_0_cdc_sync
+ port map (
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\,
+ s_axi_aclk => s_axi_aclk,
+ sda_i => sda_i,
+ sda_rin_d1 => sda_rin_d1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_iic_control is
+ port (
+ shift_reg_ld : out STD_LOGIC;
+ sda_rin_d1 : out STD_LOGIC;
+ scl_rin_d1 : out STD_LOGIC;
+ Tx_under_prev : out STD_LOGIC;
+ Bb : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ New_rcv_dta : out STD_LOGIC;
+ earlyAckHdr : out STD_LOGIC;
+ earlyAckDataState : out STD_LOGIC;
+ ackDataState : out STD_LOGIC;
+ CO : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \timing_param_tsusto_i_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \timing_param_tsusta_i_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ stop_scl_reg : out STD_LOGIC;
+ Aas : out STD_LOGIC;
+ srw_i_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ Rdy_new_xmt : out STD_LOGIC;
+ \q_int_reg[0]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ \FSM_sequential_scl_state_reg[1]_0\ : out STD_LOGIC;
+ \q_int_reg[0]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ sda_t : out STD_LOGIC;
+ \FSM_sequential_scl_state_reg[2]_0\ : out STD_LOGIC;
+ \s_axi_wdata[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ scl_t : out STD_LOGIC;
+ p_6_out : out STD_LOGIC;
+ \data_i2c_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ \q_int_reg[0]_1\ : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ \data_int_reg[0]\ : in STD_LOGIC;
+ scndry_out : in STD_LOGIC;
+ scl_rising_edge0 : in STD_LOGIC;
+ Ro_prev : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ sr_i : in STD_LOGIC_VECTOR ( 0 to 0 );
+ S : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state[3]_i_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state[3]_i_4_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state[0]_i_6_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state_reg[2]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \FSM_sequential_scl_state[1]_i_2_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ sda_setup_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \q_int_reg[4]\ : in STD_LOGIC;
+ \LEVEL_1_GEN.master_sda_reg_0\ : in STD_LOGIC;
+ \q_int_reg[1]\ : in STD_LOGIC;
+ aas_i_reg_0 : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \cr_i_reg[5]\ : in STD_LOGIC;
+ Tx_data_exists : in STD_LOGIC;
+ dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \cr_i_reg[5]_0\ : in STD_LOGIC;
+ rxCntDone : in STD_LOGIC;
+ sda_cout_reg_reg_0 : in STD_LOGIC;
+ Msms_set : in STD_LOGIC;
+ \data_int_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 6 downto 0 );
+ new_rcv_dta_d1 : in STD_LOGIC;
+ detect_stop_b_reg_0 : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_iic_control;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_iic_control is
+ signal \^aas\ : STD_LOGIC;
+ signal AckDataState_i_1_n_0 : STD_LOGIC;
+ signal BITCNT_n_1 : STD_LOGIC;
+ signal BITCNT_n_2 : STD_LOGIC;
+ signal BITCNT_n_3 : STD_LOGIC;
+ signal BITCNT_n_4 : STD_LOGIC;
+ signal \^bb\ : STD_LOGIC;
+ signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal EarlyAckDataState0 : STD_LOGIC;
+ signal EarlyAckDataState_i_2_n_0 : STD_LOGIC;
+ signal EarlyAckHdr0 : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_4_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_5_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_6_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[0]_i_7_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_4_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_5_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_6_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[1]_i_7_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[2]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[3]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_scl_state[3]_i_5_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[1]_i_4_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[1]_i_5_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_4_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_7_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_state[2]_i_9_n_0\ : STD_LOGIC;
+ signal I2CDATA_REG_n_0 : STD_LOGIC;
+ signal I2CDATA_REG_n_2 : STD_LOGIC;
+ signal I2CDATA_REG_n_3 : STD_LOGIC;
+ signal I2CDATA_REG_n_4 : STD_LOGIC;
+ signal I2CDATA_REG_n_5 : STD_LOGIC;
+ signal I2CDATA_REG_n_6 : STD_LOGIC;
+ signal I2CDATA_REG_n_7 : STD_LOGIC;
+ signal I2CDATA_REG_n_8 : STD_LOGIC;
+ signal I2CDATA_REG_n_9 : STD_LOGIC;
+ signal I2CHEADER_REG_n_1 : STD_LOGIC;
+ signal I2CHEADER_REG_n_2 : STD_LOGIC;
+ signal I2CHEADER_REG_n_3 : STD_LOGIC;
+ signal I2CHEADER_REG_n_4 : STD_LOGIC;
+ signal I2CHEADER_REG_n_5 : STD_LOGIC;
+ signal I2CHEADER_REG_n_6 : STD_LOGIC;
+ signal I2CHEADER_REG_n_7 : STD_LOGIC;
+ signal \LEVEL_1_GEN.master_sda_reg_n_0\ : STD_LOGIC;
+ signal \^new_rcv_dta\ : STD_LOGIC;
+ signal \^rdy_new_xmt\ : STD_LOGIC;
+ signal SETUP_CNT_n_0 : STD_LOGIC;
+ signal \^tx_under_prev\ : STD_LOGIC;
+ signal aas_i_i_2_n_0 : STD_LOGIC;
+ signal al_i_i_1_n_0 : STD_LOGIC;
+ signal al_i_i_2_n_0 : STD_LOGIC;
+ signal al_prevent : STD_LOGIC;
+ signal al_prevent_i_1_n_0 : STD_LOGIC;
+ signal arb_lost : STD_LOGIC;
+ signal arb_lost_i_1_n_0 : STD_LOGIC;
+ signal arb_lost_i_2_n_0 : STD_LOGIC;
+ signal arb_lost_i_3_n_0 : STD_LOGIC;
+ signal bit_cnt_en : STD_LOGIC;
+ signal bit_cnt_en0 : STD_LOGIC;
+ signal bus_busy_d1 : STD_LOGIC;
+ signal bus_busy_i_1_n_0 : STD_LOGIC;
+ signal clk_cnt_en13_out : STD_LOGIC;
+ signal clk_cnt_en1_carry_n_1 : STD_LOGIC;
+ signal clk_cnt_en1_carry_n_2 : STD_LOGIC;
+ signal clk_cnt_en1_carry_n_3 : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__0/i__carry_n_1\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__0/i__carry_n_2\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__0/i__carry_n_3\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__1/i__carry_n_1\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__1/i__carry_n_2\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__1/i__carry_n_3\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__2/i__carry_n_1\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__2/i__carry_n_2\ : STD_LOGIC;
+ signal \clk_cnt_en1_inferred__2/i__carry_n_3\ : STD_LOGIC;
+ signal clk_cnt_en2 : STD_LOGIC;
+ signal clk_cnt_en2_carry_n_1 : STD_LOGIC;
+ signal clk_cnt_en2_carry_n_2 : STD_LOGIC;
+ signal clk_cnt_en2_carry_n_3 : STD_LOGIC;
+ signal \cr_i[5]_i_3_n_0\ : STD_LOGIC;
+ signal data_i2c_i0 : STD_LOGIC;
+ signal detect_start : STD_LOGIC;
+ signal detect_start_i_1_n_0 : STD_LOGIC;
+ signal detect_start_i_2_n_0 : STD_LOGIC;
+ signal detect_stop0 : STD_LOGIC;
+ signal detect_stop_b_i_1_n_0 : STD_LOGIC;
+ signal detect_stop_b_i_2_n_0 : STD_LOGIC;
+ signal detect_stop_b_reg_n_0 : STD_LOGIC;
+ signal detect_stop_i_1_n_0 : STD_LOGIC;
+ signal detect_stop_reg_n_0 : STD_LOGIC;
+ signal dtc_i_d1 : STD_LOGIC;
+ signal dtc_i_d2 : STD_LOGIC;
+ signal dtc_i_reg_n_0 : STD_LOGIC;
+ signal dtre_d1 : STD_LOGIC;
+ signal gen_start : STD_LOGIC;
+ signal gen_start_i_1_n_0 : STD_LOGIC;
+ signal gen_stop : STD_LOGIC;
+ signal gen_stop_d1 : STD_LOGIC;
+ signal gen_stop_i_1_n_0 : STD_LOGIC;
+ signal i2c_header_en : STD_LOGIC;
+ signal i2c_header_en0 : STD_LOGIC;
+ signal master_slave : STD_LOGIC;
+ signal master_slave_i_1_n_0 : STD_LOGIC;
+ signal msms_d1 : STD_LOGIC;
+ signal msms_d10 : STD_LOGIC;
+ signal msms_d1_i_2_n_0 : STD_LOGIC;
+ signal msms_d2 : STD_LOGIC;
+ signal msms_rst_i : STD_LOGIC;
+ signal msms_rst_i_i_1_n_0 : STD_LOGIC;
+ signal next_scl_state : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal next_scl_state10_out : STD_LOGIC;
+ signal \next_scl_state1_inferred__0/i__carry_n_1\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__0/i__carry_n_2\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__0/i__carry_n_3\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__1/i__carry_n_0\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__1/i__carry_n_1\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__1/i__carry_n_2\ : STD_LOGIC;
+ signal \next_scl_state1_inferred__1/i__carry_n_3\ : STD_LOGIC;
+ signal rdy_new_xmt_i_i_1_n_0 : STD_LOGIC;
+ signal rdy_new_xmt_i_i_2_n_0 : STD_LOGIC;
+ signal ro_prev_d1 : STD_LOGIC;
+ signal rsta_d1 : STD_LOGIC;
+ signal rsta_tx_under_prev : STD_LOGIC;
+ signal rsta_tx_under_prev_i_1_n_0 : STD_LOGIC;
+ signal scl_cout_reg : STD_LOGIC;
+ signal scl_cout_reg0 : STD_LOGIC;
+ signal scl_f_edg_d1 : STD_LOGIC;
+ signal scl_f_edg_d2 : STD_LOGIC;
+ signal scl_f_edg_d3 : STD_LOGIC;
+ signal scl_falling_edge : STD_LOGIC;
+ signal scl_falling_edge0 : STD_LOGIC;
+ signal \^scl_rin_d1\ : STD_LOGIC;
+ signal scl_rising_edge : STD_LOGIC;
+ signal scl_state : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal sda_cout_reg : STD_LOGIC;
+ signal sda_cout_reg_i_1_n_0 : STD_LOGIC;
+ signal sda_cout_reg_i_2_n_0 : STD_LOGIC;
+ signal sda_cout_reg_i_3_n_0 : STD_LOGIC;
+ signal sda_cout_reg_i_4_n_0 : STD_LOGIC;
+ signal \^sda_rin_d1\ : STD_LOGIC;
+ signal sda_sample : STD_LOGIC;
+ signal sda_sample_i_1_n_0 : STD_LOGIC;
+ signal sda_setup : STD_LOGIC;
+ signal \sda_setup0_inferred__0/i__carry_n_0\ : STD_LOGIC;
+ signal \sda_setup0_inferred__0/i__carry_n_1\ : STD_LOGIC;
+ signal \sda_setup0_inferred__0/i__carry_n_2\ : STD_LOGIC;
+ signal \sda_setup0_inferred__0/i__carry_n_3\ : STD_LOGIC;
+ signal sda_setup_i_1_n_0 : STD_LOGIC;
+ signal shift_reg : STD_LOGIC_VECTOR ( 7 to 7 );
+ signal shift_reg_en : STD_LOGIC;
+ signal shift_reg_en0 : STD_LOGIC;
+ signal shift_reg_en_i_2_n_0 : STD_LOGIC;
+ signal \^shift_reg_ld\ : STD_LOGIC;
+ signal shift_reg_ld0 : STD_LOGIC;
+ signal shift_reg_ld_d1 : STD_LOGIC;
+ signal shift_reg_ld_i_2_n_0 : STD_LOGIC;
+ signal slave_sda_reg_n_0 : STD_LOGIC;
+ signal sm_stop_i_1_n_0 : STD_LOGIC;
+ signal sm_stop_i_2_n_0 : STD_LOGIC;
+ signal sm_stop_i_3_n_0 : STD_LOGIC;
+ signal sm_stop_reg_n_0 : STD_LOGIC;
+ signal \^srw_i_reg_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal state0 : STD_LOGIC;
+ signal \state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^stop_scl_reg\ : STD_LOGIC;
+ signal stop_scl_reg_i_1_n_0 : STD_LOGIC;
+ signal stop_scl_reg_i_2_n_0 : STD_LOGIC;
+ signal stop_scl_reg_i_3_n_0 : STD_LOGIC;
+ signal stop_scl_reg_i_4_n_0 : STD_LOGIC;
+ signal stop_scl_reg_i_5_n_0 : STD_LOGIC;
+ signal stop_scl_reg_i_6_n_0 : STD_LOGIC;
+ signal \^timing_param_tsusto_i_reg[9]\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal tx_under_prev_d1 : STD_LOGIC;
+ signal tx_under_prev_i0 : STD_LOGIC;
+ signal tx_under_prev_i_i_1_n_0 : STD_LOGIC;
+ signal txer_edge_i_1_n_0 : STD_LOGIC;
+ signal txer_edge_i_2_n_0 : STD_LOGIC;
+ signal txer_i_i_1_n_0 : STD_LOGIC;
+ signal txer_i_reg_n_0 : STD_LOGIC;
+ signal NLW_clk_cnt_en1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_clk_cnt_en2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of AckDataState_i_1 : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of EarlyAckDataState_i_2 : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of EarlyAckHdr_i_1 : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[0]_i_7\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[1]_i_3\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[1]_i_4\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[1]_i_6\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[1]_i_7\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \FSM_sequential_scl_state[3]_i_5\ : label is "soft_lutpair26";
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_scl_state_reg[0]\ : label is "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_scl_state_reg[1]\ : label is "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_scl_state_reg[2]\ : label is "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_scl_state_reg[3]\ : label is "start_edge:0011,scl_low_edge:0100,start:0010,start_wait:0001,scl_idle:0000,scl_high:0111,stop_wait:1001,scl_high_edge:0110,stop_edge:1000,scl_low:0101";
+ attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_4\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_4\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_5\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_9\ : label is "soft_lutpair29";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[2]\ : label is "ack_header:110,wait_ack:001,header:101,ack_data:011,rcv_data:100,xmit_data:010,idle:000";
+ attribute SOFT_HLUTNM of \IIC2Bus_IntrEvent[4]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of aas_i_i_2 : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of al_i_i_2 : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of arb_lost_i_2 : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of arb_lost_i_3 : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of bit_cnt_en_i_1 : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of bus_busy_i_1 : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \cr_i[2]_i_2\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of detect_stop_i_2 : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of gen_stop_i_1 : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of i2c_header_en_i_1 : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of master_slave_i_1 : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of rdy_new_xmt_i_i_2 : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of sda_sample_i_1 : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of shift_reg_ld_i_2 : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of sm_stop_i_3 : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of stop_scl_reg_i_2 : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of stop_scl_reg_i_4 : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of stop_scl_reg_i_5 : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of stop_scl_reg_i_6 : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of txer_edge_i_2 : label is "soft_lutpair18";
+begin
+ Aas <= \^aas\;
+ Bb <= \^bb\;
+ D(3 downto 0) <= \^d\(3 downto 0);
+ New_rcv_dta <= \^new_rcv_dta\;
+ Rdy_new_xmt <= \^rdy_new_xmt\;
+ Tx_under_prev <= \^tx_under_prev\;
+ scl_rin_d1 <= \^scl_rin_d1\;
+ sda_rin_d1 <= \^sda_rin_d1\;
+ shift_reg_ld <= \^shift_reg_ld\;
+ srw_i_reg_0(1 downto 0) <= \^srw_i_reg_0\(1 downto 0);
+ stop_scl_reg <= \^stop_scl_reg\;
+ \timing_param_tsusto_i_reg[9]\(0) <= \^timing_param_tsusto_i_reg[9]\(0);
+AckDataState_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ O => AckDataState_i_1_n_0
+ );
+AckDataState_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AckDataState_i_1_n_0,
+ Q => ackDataState,
+ R => \q_int_reg[0]_1\
+ );
+BITCNT: entity work.\TopLevel_axi_iic_0_0_upcnt_n__parameterized0\
+ port map (
+ EarlyAckDataState0 => EarlyAckDataState0,
+ EarlyAckDataState_reg => AckDataState_i_1_n_0,
+ EarlyAckDataState_reg_0 => EarlyAckDataState_i_2_n_0,
+ \FSM_sequential_state_reg[0]\ => BITCNT_n_4,
+ \FSM_sequential_state_reg[0]_0\ => \FSM_sequential_state[2]_i_7_n_0\,
+ \FSM_sequential_state_reg[0]_1\ => I2CHEADER_REG_n_6,
+ \FSM_sequential_state_reg[1]\ => BITCNT_n_3,
+ \FSM_sequential_state_reg[1]_0\ => I2CHEADER_REG_n_1,
+ \FSM_sequential_state_reg[1]_1\ => detect_stop_reg_n_0,
+ \FSM_sequential_state_reg[2]\ => BITCNT_n_2,
+ \FSM_sequential_state_reg[2]_0\ => I2CHEADER_REG_n_5,
+ \FSM_sequential_state_reg[2]_1\ => \FSM_sequential_state[2]_i_4_n_0\,
+ Q(0) => Q(0),
+ bit_cnt_en => bit_cnt_en,
+ detect_start => detect_start,
+ dtc_i_reg => dtc_i_reg_n_0,
+ \q_int_reg[0]_0\ => \q_int_reg[0]_1\,
+ \q_int_reg[1]_0\ => BITCNT_n_1,
+ s_axi_aclk => s_axi_aclk,
+ scl_falling_edge => scl_falling_edge,
+ state0 => state0,
+ \state__0\(2 downto 0) => \state__0\(2 downto 0)
+ );
+CLKCNT: entity work.TopLevel_axi_iic_0_0_upcnt_n
+ port map (
+ CO(0) => clk_cnt_en2,
+ \FSM_sequential_scl_state_reg[1]\ => \FSM_sequential_scl_state_reg[1]_0\,
+ Q(3 downto 0) => scl_state(3 downto 0),
+ arb_lost => arb_lost,
+ \q_int_reg[0]_0\(9 downto 0) => \q_int_reg[0]_0\(9 downto 0),
+ \q_int_reg[1]_0\ => \q_int_reg[1]\,
+ \q_int_reg[1]_1\ => detect_stop_b_reg_n_0,
+ \q_int_reg[1]_2\(0) => clk_cnt_en13_out,
+ \q_int_reg[4]_0\ => \q_int_reg[4]\,
+ \q_int_reg[9]_0\ => \q_int_reg[0]_1\,
+ s_axi_aclk => s_axi_aclk,
+ scndry_out => scndry_out
+ );
+EarlyAckDataState_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FB"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(2),
+ I2 => \state__0\(1),
+ O => EarlyAckDataState_i_2_n_0
+ );
+EarlyAckDataState_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => EarlyAckDataState0,
+ Q => earlyAckDataState,
+ R => \q_int_reg[0]_1\
+ );
+EarlyAckHdr_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0080"
+ )
+ port map (
+ I0 => scl_f_edg_d3,
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ I3 => \state__0\(0),
+ O => EarlyAckHdr0
+ );
+EarlyAckHdr_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => EarlyAckHdr0,
+ Q => earlyAckHdr,
+ R => \q_int_reg[0]_1\
+ );
+\FSM_sequential_scl_state[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000ABABAFAA"
+ )
+ port map (
+ I0 => \FSM_sequential_scl_state[0]_i_4_n_0\,
+ I1 => clk_cnt_en13_out,
+ I2 => scl_state(1),
+ I3 => \FSM_sequential_scl_state[0]_i_5_n_0\,
+ I4 => scl_state(0),
+ I5 => \FSM_sequential_scl_state[0]_i_6_n_0\,
+ O => \FSM_sequential_scl_state[0]_i_2_n_0\
+ );
+\FSM_sequential_scl_state[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0A22FAEE"
+ )
+ port map (
+ I0 => \data_int_reg[0]\,
+ I1 => scl_state(2),
+ I2 => scl_state(0),
+ I3 => scl_state(3),
+ I4 => clk_cnt_en13_out,
+ O => \FSM_sequential_scl_state[0]_i_3_n_0\
+ );
+\FSM_sequential_scl_state[0]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EEFE4444EEFEF4F4"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => scl_state(2),
+ I2 => scl_state(1),
+ I3 => next_scl_state10_out,
+ I4 => scl_state(0),
+ I5 => \data_int_reg[0]\,
+ O => \FSM_sequential_scl_state[0]_i_4_n_0\
+ );
+\FSM_sequential_scl_state[0]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000002228222A"
+ )
+ port map (
+ I0 => detect_stop_b_reg_n_0,
+ I1 => scl_state(3),
+ I2 => scl_state(2),
+ I3 => scl_state(1),
+ I4 => clk_cnt_en13_out,
+ I5 => \FSM_sequential_scl_state[0]_i_7_n_0\,
+ O => \FSM_sequential_scl_state[0]_i_5_n_0\
+ );
+\FSM_sequential_scl_state[0]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000FF55F0BB"
+ )
+ port map (
+ I0 => scndry_out,
+ I1 => clk_cnt_en2,
+ I2 => \next_scl_state1_inferred__1/i__carry_n_0\,
+ I3 => scl_state(0),
+ I4 => scl_state(1),
+ I5 => \FSM_sequential_scl_state[1]_i_7_n_0\,
+ O => \FSM_sequential_scl_state[0]_i_6_n_0\
+ );
+\FSM_sequential_scl_state[0]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"BF"
+ )
+ port map (
+ I0 => \^bb\,
+ I1 => gen_start,
+ I2 => master_slave,
+ O => \FSM_sequential_scl_state[0]_i_7_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4444444545454545"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => \FSM_sequential_scl_state[1]_i_2_n_0\,
+ I2 => \FSM_sequential_scl_state[1]_i_3_n_0\,
+ I3 => \FSM_sequential_scl_state[1]_i_4_n_0\,
+ I4 => \FSM_sequential_scl_state[1]_i_5_n_0\,
+ I5 => \FSM_sequential_scl_state[1]_i_6_n_0\,
+ O => \FSM_sequential_scl_state[1]_i_1_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000006262EA62"
+ )
+ port map (
+ I0 => scl_state(1),
+ I1 => scl_state(0),
+ I2 => \next_scl_state1_inferred__1/i__carry_n_0\,
+ I3 => Q(3),
+ I4 => arb_lost,
+ I5 => \FSM_sequential_scl_state[1]_i_7_n_0\,
+ O => \FSM_sequential_scl_state[1]_i_2_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FE44EE44"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => scl_state(2),
+ I2 => scl_state(1),
+ I3 => scl_state(0),
+ I4 => next_scl_state10_out,
+ O => \FSM_sequential_scl_state[1]_i_3_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"03FD0000"
+ )
+ port map (
+ I0 => clk_cnt_en13_out,
+ I1 => scl_state(1),
+ I2 => scl_state(2),
+ I3 => scl_state(3),
+ I4 => detect_stop_b_reg_n_0,
+ O => \FSM_sequential_scl_state[1]_i_4_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_5\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFBF"
+ )
+ port map (
+ I0 => scl_state(0),
+ I1 => master_slave,
+ I2 => gen_start,
+ I3 => \^bb\,
+ O => \FSM_sequential_scl_state[1]_i_5_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"15"
+ )
+ port map (
+ I0 => scl_state(1),
+ I1 => scl_state(0),
+ I2 => clk_cnt_en13_out,
+ O => \FSM_sequential_scl_state[1]_i_6_n_0\
+ );
+\FSM_sequential_scl_state[1]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"35"
+ )
+ port map (
+ I0 => scl_state(2),
+ I1 => scl_state(0),
+ I2 => scl_state(3),
+ O => \FSM_sequential_scl_state[1]_i_7_n_0\
+ );
+\FSM_sequential_scl_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000000000FF80"
+ )
+ port map (
+ I0 => next_scl_state10_out,
+ I1 => scl_state(0),
+ I2 => scl_state(1),
+ I3 => scl_state(2),
+ I4 => \FSM_sequential_scl_state[2]_i_2_n_0\,
+ I5 => scl_state(3),
+ O => next_scl_state(2)
+ );
+\FSM_sequential_scl_state[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FE00000000000000"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => \^stop_scl_reg\,
+ I2 => arb_lost,
+ I3 => scl_state(1),
+ I4 => scl_state(0),
+ I5 => scl_state(2),
+ O => \FSM_sequential_scl_state[2]_i_2_n_0\
+ );
+\FSM_sequential_scl_state[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"545555FF555555FF"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => \q_int_reg[4]\,
+ I2 => arb_lost,
+ I3 => scl_state(1),
+ I4 => scl_state(2),
+ I5 => scl_state(0),
+ O => \FSM_sequential_scl_state[3]_i_2_n_0\
+ );
+\FSM_sequential_scl_state[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"77777777000F0000"
+ )
+ port map (
+ I0 => clk_cnt_en13_out,
+ I1 => scl_state(0),
+ I2 => \FSM_sequential_scl_state[3]_i_5_n_0\,
+ I3 => arb_lost,
+ I4 => scl_state(2),
+ I5 => scl_state(3),
+ O => next_scl_state(3)
+ );
+\FSM_sequential_scl_state[3]_i_5\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"DFFF"
+ )
+ port map (
+ I0 => \^stop_scl_reg\,
+ I1 => Q(3),
+ I2 => scl_state(0),
+ I3 => scl_state(1),
+ O => \FSM_sequential_scl_state[3]_i_5_n_0\
+ );
+\FSM_sequential_scl_state_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
+ D => next_scl_state(0),
+ Q => scl_state(0),
+ R => \q_int_reg[0]_1\
+ );
+\FSM_sequential_scl_state_reg[0]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \FSM_sequential_scl_state[0]_i_2_n_0\,
+ I1 => \FSM_sequential_scl_state[0]_i_3_n_0\,
+ O => next_scl_state(0),
+ S => scl_state(3)
+ );
+\FSM_sequential_scl_state_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
+ D => \FSM_sequential_scl_state[1]_i_1_n_0\,
+ Q => scl_state(1),
+ R => \q_int_reg[0]_1\
+ );
+\FSM_sequential_scl_state_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
+ D => next_scl_state(2),
+ Q => scl_state(2),
+ R => \q_int_reg[0]_1\
+ );
+\FSM_sequential_scl_state_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
+ D => next_scl_state(3),
+ Q => scl_state(3),
+ R => \q_int_reg[0]_1\
+ );
+\FSM_sequential_state[1]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4088"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => \state__0\(0),
+ I2 => Ro_prev,
+ I3 => \state__0\(1),
+ O => \FSM_sequential_state[1]_i_4_n_0\
+ );
+\FSM_sequential_state[1]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFBAAAAFFFBFFFB"
+ )
+ port map (
+ I0 => \state__0\(1),
+ I1 => \state__0\(0),
+ I2 => sda_sample,
+ I3 => arb_lost,
+ I4 => detect_start,
+ I5 => \state__0\(2),
+ O => \FSM_sequential_state[1]_i_5_n_0\
+ );
+\FSM_sequential_state[2]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"34"
+ )
+ port map (
+ I0 => Ro_prev,
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ O => \FSM_sequential_state[2]_i_4_n_0\
+ );
+\FSM_sequential_state[2]_i_5\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => detect_stop_reg_n_0,
+ I1 => Q(0),
+ O => state0
+ );
+\FSM_sequential_state[2]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"0D"
+ )
+ port map (
+ I0 => ro_prev_d1,
+ I1 => Ro_prev,
+ I2 => scl_f_edg_d2,
+ O => \FSM_sequential_state[2]_i_7_n_0\
+ );
+\FSM_sequential_state[2]_i_9\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => arb_lost,
+ I1 => sda_sample,
+ O => \FSM_sequential_state[2]_i_9_n_0\
+ );
+\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => BITCNT_n_4,
+ Q => \state__0\(0),
+ R => '0'
+ );
+\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => BITCNT_n_3,
+ Q => \state__0\(1),
+ R => '0'
+ );
+\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => BITCNT_n_2,
+ Q => \state__0\(2),
+ R => '0'
+ );
+I2CDATA_REG: entity work.TopLevel_axi_iic_0_0_shift8
+ port map (
+ \LEVEL_1_GEN.master_sda_reg\ => \LEVEL_1_GEN.master_sda_reg_0\,
+ \LEVEL_1_GEN.master_sda_reg_0\ => \^tx_under_prev\,
+ Q(7) => shift_reg(7),
+ Q(6) => I2CDATA_REG_n_2,
+ Q(5) => I2CDATA_REG_n_3,
+ Q(4) => I2CDATA_REG_n_4,
+ Q(3) => I2CDATA_REG_n_5,
+ Q(2) => I2CDATA_REG_n_6,
+ Q(1) => I2CDATA_REG_n_7,
+ Q(0) => I2CDATA_REG_n_8,
+ Tx_fifo_data(6 downto 0) => Tx_fifo_data(6 downto 0),
+ \data_int_reg[0]_0\(0) => \data_int_reg[0]_0\(0),
+ \data_int_reg[1]_0\ => \^shift_reg_ld\,
+ \data_int_reg[7]_0\ => I2CDATA_REG_n_0,
+ \data_int_reg[7]_1\ => \q_int_reg[0]_1\,
+ s_axi_aclk => s_axi_aclk,
+ shift_reg_en => shift_reg_en,
+ slave_sda_reg => I2CHEADER_REG_n_2,
+ \state__0\(2 downto 0) => \state__0\(2 downto 0),
+ tx_under_prev_i_reg => I2CDATA_REG_n_9
+ );
+I2CHEADER_REG: entity work.TopLevel_axi_iic_0_0_shift8_1
+ port map (
+ E(0) => i2c_header_en,
+ \FSM_sequential_state_reg[1]\ => \FSM_sequential_state[1]_i_4_n_0\,
+ \FSM_sequential_state_reg[1]_0\ => \FSM_sequential_state[1]_i_5_n_0\,
+ \FSM_sequential_state_reg[2]\ => I2CHEADER_REG_n_5,
+ \FSM_sequential_state_reg[2]_0\ => \FSM_sequential_state[2]_i_9_n_0\,
+ Q(2) => Q(4),
+ Q(1) => Q(2),
+ Q(0) => Q(0),
+ Ro_prev => Ro_prev,
+ aas_i_reg => I2CHEADER_REG_n_3,
+ aas_i_reg_0 => aas_i_i_2_n_0,
+ aas_i_reg_1 => \^aas\,
+ aas_i_reg_2 => detect_stop_reg_n_0,
+ aas_i_reg_3(6 downto 0) => aas_i_reg_0(6 downto 0),
+ abgc_i_reg => I2CHEADER_REG_n_2,
+ abgc_i_reg_0 => \^srw_i_reg_0\(0),
+ arb_lost => arb_lost,
+ \cr_i_reg[4]\ => I2CHEADER_REG_n_1,
+ \data_int_reg[0]_0\ => I2CHEADER_REG_n_7,
+ \data_int_reg[0]_1\ => \q_int_reg[0]_1\,
+ \data_int_reg[0]_2\ => \data_int_reg[0]\,
+ detect_start => detect_start,
+ detect_start_reg => I2CHEADER_REG_n_4,
+ detect_start_reg_0 => I2CHEADER_REG_n_6,
+ master_slave => master_slave,
+ s_axi_aclk => s_axi_aclk,
+ sda_sample => sda_sample,
+ shift_reg_ld0 => shift_reg_ld0,
+ shift_reg_ld_reg => shift_reg_ld_i_2_n_0,
+ shift_reg_ld_reg_0 => \^tx_under_prev\,
+ srw_i_reg(0) => \^srw_i_reg_0\(1),
+ \state__0\(2 downto 0) => \state__0\(2 downto 0)
+ );
+\IIC2Bus_IntrEvent[4]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^bb\,
+ O => \^d\(1)
+ );
+\IIC2Bus_IntrEvent[6]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^aas\,
+ O => \^d\(0)
+ );
+\LEVEL_1_GEN.master_sda_reg\: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I2CDATA_REG_n_9,
+ Q => \LEVEL_1_GEN.master_sda_reg_n_0\,
+ S => \q_int_reg[0]_1\
+ );
+\RD_FIFO_CNTRL.Rc_fifo_wr_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^new_rcv_dta\,
+ I1 => new_rcv_dta_d1,
+ O => p_6_out
+ );
+SETUP_CNT: entity work.TopLevel_axi_iic_0_0_upcnt_n_2
+ port map (
+ Q(9 downto 0) => \q_int_reg[0]\(9 downto 0),
+ gen_stop => gen_stop,
+ gen_stop_d1 => gen_stop_d1,
+ gen_stop_d1_reg => SETUP_CNT_n_0,
+ \q_int[0]_i_3_0\(0) => Q(3),
+ \q_int[0]_i_3_1\ => \^tx_under_prev\,
+ \q_int[0]_i_3_2\ => \^sda_rin_d1\,
+ \q_int[0]_i_3_3\ => \data_int_reg[0]\,
+ \q_int_reg[0]_0\ => \q_int_reg[0]_1\,
+ rsta_d1 => rsta_d1,
+ s_axi_aclk => s_axi_aclk,
+ sda_setup => sda_setup,
+ tx_under_prev_d1 => tx_under_prev_d1
+ );
+aas_i_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(2),
+ I2 => \state__0\(1),
+ O => aas_i_i_2_n_0
+ );
+aas_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I2CHEADER_REG_n_3,
+ Q => \^aas\,
+ R => '0'
+ );
+abgc_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I2CHEADER_REG_n_4,
+ Q => \^srw_i_reg_0\(0),
+ R => '0'
+ );
+al_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"E0E0E0E0E0EEE0E0"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => master_slave,
+ I2 => al_i_i_2_n_0,
+ I3 => al_prevent,
+ I4 => detect_stop_reg_n_0,
+ I5 => sm_stop_reg_n_0,
+ O => al_i_i_1_n_0
+ );
+al_i_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FDDD"
+ )
+ port map (
+ I0 => master_slave,
+ I1 => arb_lost,
+ I2 => bus_busy_d1,
+ I3 => gen_start,
+ O => al_i_i_2_n_0
+ );
+al_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => al_i_i_1_n_0,
+ Q => \^d\(3),
+ R => \q_int_reg[0]_1\
+ );
+al_prevent_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"5554"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => gen_stop,
+ I2 => sm_stop_reg_n_0,
+ I3 => al_prevent,
+ O => al_prevent_i_1_n_0
+ );
+al_prevent_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => al_prevent_i_1_n_0,
+ Q => al_prevent,
+ R => \q_int_reg[0]_1\
+ );
+arb_lost_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000002AEA2A2A"
+ )
+ port map (
+ I0 => arb_lost,
+ I1 => master_slave,
+ I2 => arb_lost_i_2_n_0,
+ I3 => \data_int_reg[0]\,
+ I4 => sda_cout_reg,
+ I5 => arb_lost_i_3_n_0,
+ O => arb_lost_i_1_n_0
+ );
+arb_lost_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0820"
+ )
+ port map (
+ I0 => scl_rising_edge,
+ I1 => \state__0\(0),
+ I2 => \state__0\(1),
+ I3 => \state__0\(2),
+ O => arb_lost_i_2_n_0
+ );
+arb_lost_i_3: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0009FFFF"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => scl_state(0),
+ I2 => scl_state(2),
+ I3 => scl_state(1),
+ I4 => Q(0),
+ O => arb_lost_i_3_n_0
+ );
+arb_lost_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => arb_lost_i_1_n_0,
+ Q => arb_lost,
+ R => '0'
+ );
+bit_cnt_en_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0848"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => scl_falling_edge,
+ I2 => \state__0\(1),
+ I3 => \state__0\(0),
+ O => bit_cnt_en0
+ );
+bit_cnt_en_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => bit_cnt_en0,
+ Q => bit_cnt_en,
+ R => \q_int_reg[0]_1\
+ );
+bus_busy_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \^bb\,
+ Q => bus_busy_d1,
+ R => \q_int_reg[0]_1\
+ );
+bus_busy_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E0"
+ )
+ port map (
+ I0 => \^bb\,
+ I1 => detect_start,
+ I2 => Q(0),
+ I3 => detect_stop_reg_n_0,
+ O => bus_busy_i_1_n_0
+ );
+bus_busy_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => bus_busy_i_1_n_0,
+ Q => \^bb\,
+ R => '0'
+ );
+clk_cnt_en1_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => CO(0),
+ CO(2) => clk_cnt_en1_carry_n_1,
+ CO(1) => clk_cnt_en1_carry_n_2,
+ CO(0) => clk_cnt_en1_carry_n_3,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => NLW_clk_cnt_en1_carry_O_UNCONNECTED(3 downto 0),
+ S(3 downto 0) => S(3 downto 0)
+ );
+\clk_cnt_en1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \^timing_param_tsusto_i_reg[9]\(0),
+ CO(2) => \clk_cnt_en1_inferred__0/i__carry_n_1\,
+ CO(1) => \clk_cnt_en1_inferred__0/i__carry_n_2\,
+ CO(0) => \clk_cnt_en1_inferred__0/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state[3]_i_4\(3 downto 0)
+ );
+\clk_cnt_en1_inferred__1/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \timing_param_tsusta_i_reg[9]\(0),
+ CO(2) => \clk_cnt_en1_inferred__1/i__carry_n_1\,
+ CO(1) => \clk_cnt_en1_inferred__1/i__carry_n_2\,
+ CO(0) => \clk_cnt_en1_inferred__1/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state[3]_i_4_0\(3 downto 0)
+ );
+\clk_cnt_en1_inferred__2/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => clk_cnt_en13_out,
+ CO(2) => \clk_cnt_en1_inferred__2/i__carry_n_1\,
+ CO(1) => \clk_cnt_en1_inferred__2/i__carry_n_2\,
+ CO(0) => \clk_cnt_en1_inferred__2/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state_reg[3]_0\(3 downto 0)
+ );
+clk_cnt_en2_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => clk_cnt_en2,
+ CO(2) => clk_cnt_en2_carry_n_1,
+ CO(1) => clk_cnt_en2_carry_n_2,
+ CO(0) => clk_cnt_en2_carry_n_3,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => NLW_clk_cnt_en2_carry_O_UNCONNECTED(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state[0]_i_6_0\(3 downto 0)
+ );
+\cr_i[2]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FBFF"
+ )
+ port map (
+ I0 => scl_state(2),
+ I1 => scl_state(1),
+ I2 => scl_state(3),
+ I3 => scl_state(0),
+ O => \FSM_sequential_scl_state_reg[2]_0\
+ );
+\cr_i[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"88888888BBBB888B"
+ )
+ port map (
+ I0 => s_axi_wdata(0),
+ I1 => E(0),
+ I2 => \^bb\,
+ I3 => \cr_i_reg[5]\,
+ I4 => Q(1),
+ I5 => \cr_i[5]_i_3_n_0\,
+ O => \s_axi_wdata[2]\(0)
+ );
+\cr_i[5]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFF80"
+ )
+ port map (
+ I0 => Tx_data_exists,
+ I1 => dynamic_MSMS(0),
+ I2 => \cr_i_reg[5]_0\,
+ I3 => msms_rst_i,
+ I4 => sm_stop_reg_n_0,
+ I5 => rxCntDone,
+ O => \cr_i[5]_i_3_n_0\
+ );
+\data_i2c_i[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00004000"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => \state__0\(1),
+ I2 => \state__0\(0),
+ I3 => scl_falling_edge,
+ I4 => Ro_prev,
+ O => data_i2c_i0
+ );
+\data_i2c_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_8,
+ Q => \data_i2c_i_reg[7]_0\(0),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_7,
+ Q => \data_i2c_i_reg[7]_0\(1),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_6,
+ Q => \data_i2c_i_reg[7]_0\(2),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_5,
+ Q => \data_i2c_i_reg[7]_0\(3),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_4,
+ Q => \data_i2c_i_reg[7]_0\(4),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_3,
+ Q => \data_i2c_i_reg[7]_0\(5),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => I2CDATA_REG_n_2,
+ Q => \data_i2c_i_reg[7]_0\(6),
+ R => \q_int_reg[0]_1\
+ );
+\data_i2c_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => data_i2c_i0,
+ D => shift_reg(7),
+ Q => \data_i2c_i_reg[7]_0\(7),
+ R => \q_int_reg[0]_1\
+ );
+detect_start_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000FB080000"
+ )
+ port map (
+ I0 => scndry_out,
+ I1 => \^sda_rin_d1\,
+ I2 => \data_int_reg[0]\,
+ I3 => detect_start,
+ I4 => Q(0),
+ I5 => detect_start_i_2_n_0,
+ O => detect_start_i_1_n_0
+ );
+detect_start_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(2),
+ I2 => \state__0\(1),
+ O => detect_start_i_2_n_0
+ );
+detect_start_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => detect_start_i_1_n_0,
+ Q => detect_start,
+ R => '0'
+ );
+detect_stop_b_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000E2220000"
+ )
+ port map (
+ I0 => detect_stop_b_reg_n_0,
+ I1 => detect_stop_b_i_2_n_0,
+ I2 => scndry_out,
+ I3 => detect_stop_b_reg_0,
+ I4 => Q(0),
+ I5 => detect_start,
+ O => detect_stop_b_i_1_n_0
+ );
+detect_stop_b_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4444444444444F44"
+ )
+ port map (
+ I0 => \^sda_rin_d1\,
+ I1 => \data_int_reg[0]\,
+ I2 => scl_state(0),
+ I3 => scl_state(1),
+ I4 => scl_state(3),
+ I5 => scl_state(2),
+ O => detect_stop_b_i_2_n_0
+ );
+detect_stop_b_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => detect_stop_b_i_1_n_0,
+ Q => detect_stop_b_reg_n_0,
+ R => '0'
+ );
+detect_stop_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000F2020000"
+ )
+ port map (
+ I0 => detect_stop_reg_n_0,
+ I1 => detect_stop0,
+ I2 => detect_stop_b_reg_0,
+ I3 => scndry_out,
+ I4 => Q(0),
+ I5 => detect_start,
+ O => detect_stop_i_1_n_0
+ );
+detect_stop_i_2: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => msms_d1,
+ I1 => msms_d2,
+ O => detect_stop0
+ );
+detect_stop_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => detect_stop_i_1_n_0,
+ Q => detect_stop_reg_n_0,
+ R => '0'
+ );
+dtc_i_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => dtc_i_reg_n_0,
+ Q => dtc_i_d1,
+ R => \q_int_reg[0]_1\
+ );
+dtc_i_d2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => dtc_i_d1,
+ Q => dtc_i_d2,
+ R => \q_int_reg[0]_1\
+ );
+dtc_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => BITCNT_n_1,
+ Q => dtc_i_reg_n_0,
+ R => \q_int_reg[0]_1\
+ );
+dtre_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sr_i(0),
+ Q => dtre_d1,
+ R => \q_int_reg[0]_1\
+ );
+gen_start_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7530"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => msms_d2,
+ I2 => msms_d1,
+ I3 => gen_start,
+ O => gen_start_i_1_n_0
+ );
+gen_start_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => gen_start_i_1_n_0,
+ Q => gen_start,
+ R => \q_int_reg[0]_1\
+ );
+gen_stop_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => gen_stop,
+ Q => gen_stop_d1,
+ R => \q_int_reg[0]_1\
+ );
+gen_stop_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55750030"
+ )
+ port map (
+ I0 => detect_stop_reg_n_0,
+ I1 => msms_d1,
+ I2 => msms_d2,
+ I3 => arb_lost,
+ I4 => gen_stop,
+ O => gen_stop_i_1_n_0
+ );
+gen_stop_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => gen_stop_i_1_n_0,
+ Q => gen_stop,
+ R => \q_int_reg[0]_1\
+ );
+i2c_header_en_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2000"
+ )
+ port map (
+ I0 => scl_rising_edge,
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ I3 => \state__0\(0),
+ O => i2c_header_en0
+ );
+i2c_header_en_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => i2c_header_en0,
+ Q => i2c_header_en,
+ R => \q_int_reg[0]_1\
+ );
+master_slave_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"4F400000"
+ )
+ port map (
+ I0 => arb_lost,
+ I1 => master_slave,
+ I2 => \^bb\,
+ I3 => msms_d1,
+ I4 => Q(0),
+ O => master_slave_i_1_n_0
+ );
+master_slave_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => master_slave_i_1_n_0,
+ Q => master_slave,
+ R => '0'
+ );
+msms_d1_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => msms_d1_i_2_n_0,
+ I1 => msms_rst_i,
+ O => msms_d10
+ );
+msms_d1_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AABAAAAAAABAAABA"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => txer_i_reg_n_0,
+ I2 => msms_d1,
+ I3 => Msms_set,
+ I4 => dtc_i_d2,
+ I5 => dtc_i_d1,
+ O => msms_d1_i_2_n_0
+ );
+msms_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => msms_d10,
+ Q => msms_d1,
+ R => \q_int_reg[0]_1\
+ );
+msms_d2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => msms_d1,
+ Q => msms_d2,
+ R => \q_int_reg[0]_1\
+ );
+msms_rst_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000008FF0800"
+ )
+ port map (
+ I0 => arb_lost_i_2_n_0,
+ I1 => sda_cout_reg,
+ I2 => \data_int_reg[0]\,
+ I3 => master_slave,
+ I4 => msms_rst_i,
+ I5 => arb_lost_i_3_n_0,
+ O => msms_rst_i_i_1_n_0
+ );
+msms_rst_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => msms_rst_i_i_1_n_0,
+ Q => msms_rst_i,
+ R => '0'
+ );
+new_rcv_dta_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => data_i2c_i0,
+ Q => \^new_rcv_dta\,
+ R => \q_int_reg[0]_1\
+ );
+\next_scl_state1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => next_scl_state10_out,
+ CO(2) => \next_scl_state1_inferred__0/i__carry_n_1\,
+ CO(1) => \next_scl_state1_inferred__0/i__carry_n_2\,
+ CO(0) => \next_scl_state1_inferred__0/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state_reg[2]_1\(3 downto 0)
+ );
+\next_scl_state1_inferred__1/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \next_scl_state1_inferred__1/i__carry_n_0\,
+ CO(2) => \next_scl_state1_inferred__1/i__carry_n_1\,
+ CO(1) => \next_scl_state1_inferred__1/i__carry_n_2\,
+ CO(0) => \next_scl_state1_inferred__1/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \FSM_sequential_scl_state[1]_i_2_0\(3 downto 0)
+ );
+rdy_new_xmt_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"222F2F2F22202020"
+ )
+ port map (
+ I0 => shift_reg_ld_d1,
+ I1 => \^shift_reg_ld\,
+ I2 => rdy_new_xmt_i_i_2_n_0,
+ I3 => Q(1),
+ I4 => detect_start_i_2_n_0,
+ I5 => \^rdy_new_xmt\,
+ O => rdy_new_xmt_i_i_1_n_0
+ );
+rdy_new_xmt_i_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ O => rdy_new_xmt_i_i_2_n_0
+ );
+rdy_new_xmt_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => rdy_new_xmt_i_i_1_n_0,
+ Q => \^rdy_new_xmt\,
+ R => \q_int_reg[0]_1\
+ );
+ro_prev_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Ro_prev,
+ Q => ro_prev_d1,
+ R => \q_int_reg[0]_1\
+ );
+rsta_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Q(3),
+ Q => rsta_d1,
+ R => \q_int_reg[0]_1\
+ );
+rsta_tx_under_prev_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"F0FF2020"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => rsta_d1,
+ I2 => sr_i(0),
+ I3 => dtre_d1,
+ I4 => rsta_tx_under_prev,
+ O => rsta_tx_under_prev_i_1_n_0
+ );
+rsta_tx_under_prev_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => rsta_tx_under_prev_i_1_n_0,
+ Q => rsta_tx_under_prev,
+ R => \q_int_reg[0]_1\
+ );
+scl_cout_reg_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0151"
+ )
+ port map (
+ I0 => Ro_prev,
+ I1 => scl_state(2),
+ I2 => scl_state(1),
+ I3 => scl_state(3),
+ O => scl_cout_reg0
+ );
+scl_cout_reg_reg: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_cout_reg0,
+ Q => scl_cout_reg,
+ S => \q_int_reg[0]_1\
+ );
+scl_f_edg_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_falling_edge,
+ Q => scl_f_edg_d1,
+ R => \q_int_reg[0]_1\
+ );
+scl_f_edg_d2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_f_edg_d1,
+ Q => scl_f_edg_d2,
+ R => \q_int_reg[0]_1\
+ );
+scl_f_edg_d3_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_f_edg_d2,
+ Q => scl_f_edg_d3,
+ R => \q_int_reg[0]_1\
+ );
+scl_falling_edge_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^scl_rin_d1\,
+ I1 => scndry_out,
+ O => scl_falling_edge0
+ );
+scl_falling_edge_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_falling_edge0,
+ Q => scl_falling_edge,
+ R => \q_int_reg[0]_1\
+ );
+scl_rin_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scndry_out,
+ Q => \^scl_rin_d1\,
+ R => '0'
+ );
+scl_rising_edge_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => scl_rising_edge0,
+ Q => scl_rising_edge,
+ R => \q_int_reg[0]_1\
+ );
+scl_t_INST_0: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0004"
+ )
+ port map (
+ I0 => sda_setup,
+ I1 => scl_cout_reg,
+ I2 => rsta_tx_under_prev,
+ I3 => Ro_prev,
+ O => scl_t
+ );
+sda_cout_reg_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FE02"
+ )
+ port map (
+ I0 => sda_cout_reg_i_2_n_0,
+ I1 => scl_state(3),
+ I2 => sda_cout_reg_i_3_n_0,
+ I3 => sda_cout_reg,
+ O => sda_cout_reg_i_1_n_0
+ );
+sda_cout_reg_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000EA2A00000F0F"
+ )
+ port map (
+ I0 => sda_cout_reg_i_4_n_0,
+ I1 => scl_state(0),
+ I2 => scl_state(1),
+ I3 => \^timing_param_tsusto_i_reg[9]\(0),
+ I4 => scl_state(3),
+ I5 => scl_state(2),
+ O => sda_cout_reg_i_2_n_0
+ );
+sda_cout_reg_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAA2AA66666666"
+ )
+ port map (
+ I0 => scl_state(0),
+ I1 => scl_state(2),
+ I2 => sda_cout_reg_reg_0,
+ I3 => \^timing_param_tsusto_i_reg[9]\(0),
+ I4 => arb_lost,
+ I5 => scl_state(1),
+ O => sda_cout_reg_i_3_n_0
+ );
+sda_cout_reg_i_4: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"1F1F1F00"
+ )
+ port map (
+ I0 => sm_stop_reg_n_0,
+ I1 => gen_stop,
+ I2 => txer_edge_i_2_n_0,
+ I3 => Q(3),
+ I4 => \LEVEL_1_GEN.master_sda_reg_n_0\,
+ O => sda_cout_reg_i_4_n_0
+ );
+sda_cout_reg_reg: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sda_cout_reg_i_1_n_0,
+ Q => sda_cout_reg,
+ S => \q_int_reg[0]_1\
+ );
+sda_rin_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \data_int_reg[0]\,
+ Q => \^sda_rin_d1\,
+ R => '0'
+ );
+sda_sample_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => \data_int_reg[0]\,
+ I1 => scl_rising_edge,
+ I2 => sda_sample,
+ O => sda_sample_i_1_n_0
+ );
+sda_sample_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sda_sample_i_1_n_0,
+ Q => sda_sample,
+ R => \q_int_reg[0]_1\
+ );
+\sda_setup0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \sda_setup0_inferred__0/i__carry_n_0\,
+ CO(2) => \sda_setup0_inferred__0/i__carry_n_1\,
+ CO(1) => \sda_setup0_inferred__0/i__carry_n_2\,
+ CO(0) => \sda_setup0_inferred__0/i__carry_n_3\,
+ CYINIT => '1',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => \NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => sda_setup_reg_0(3 downto 0)
+ );
+sda_setup_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55FD00FC"
+ )
+ port map (
+ I0 => \sda_setup0_inferred__0/i__carry_n_0\,
+ I1 => \^tx_under_prev\,
+ I2 => SETUP_CNT_n_0,
+ I3 => scndry_out,
+ I4 => sda_setup,
+ O => sda_setup_i_1_n_0
+ );
+sda_setup_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sda_setup_i_1_n_0,
+ Q => sda_setup,
+ R => \q_int_reg[0]_1\
+ );
+sda_t_INST_0: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000EFE0"
+ )
+ port map (
+ I0 => arb_lost,
+ I1 => sda_cout_reg,
+ I2 => master_slave,
+ I3 => slave_sda_reg_n_0,
+ I4 => \^stop_scl_reg\,
+ O => sda_t
+ );
+shift_reg_en_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF08000000"
+ )
+ port map (
+ I0 => master_slave,
+ I1 => scl_rising_edge,
+ I2 => \state__0\(1),
+ I3 => \state__0\(2),
+ I4 => \state__0\(0),
+ I5 => shift_reg_en_i_2_n_0,
+ O => shift_reg_en0
+ );
+shift_reg_en_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000045000000400"
+ )
+ port map (
+ I0 => detect_start,
+ I1 => scl_rising_edge,
+ I2 => \state__0\(1),
+ I3 => \state__0\(2),
+ I4 => \state__0\(0),
+ I5 => scl_f_edg_d2,
+ O => shift_reg_en_i_2_n_0
+ );
+shift_reg_en_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => shift_reg_en0,
+ Q => shift_reg_en,
+ R => \q_int_reg[0]_1\
+ );
+shift_reg_ld_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \^shift_reg_ld\,
+ Q => shift_reg_ld_d1,
+ R => \q_int_reg[0]_1\
+ );
+shift_reg_ld_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00320002"
+ )
+ port map (
+ I0 => master_slave,
+ I1 => \state__0\(0),
+ I2 => \state__0\(2),
+ I3 => \state__0\(1),
+ I4 => detect_start,
+ O => shift_reg_ld_i_2_n_0
+ );
+shift_reg_ld_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => shift_reg_ld0,
+ Q => \^shift_reg_ld\,
+ R => \q_int_reg[0]_1\
+ );
+slave_sda_reg: unisim.vcomponents.FDSE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I2CDATA_REG_n_0,
+ Q => slave_sda_reg_n_0,
+ S => \q_int_reg[0]_1\
+ );
+sm_stop_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000BA8A0000"
+ )
+ port map (
+ I0 => sm_stop_reg_n_0,
+ I1 => sm_stop_i_2_n_0,
+ I2 => sm_stop_i_3_n_0,
+ I3 => master_slave,
+ I4 => Q(0),
+ I5 => detect_stop_reg_n_0,
+ O => sm_stop_i_1_n_0
+ );
+sm_stop_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF45FFFFFFFFFF"
+ )
+ port map (
+ I0 => scl_f_edg_d2,
+ I1 => Ro_prev,
+ I2 => ro_prev_d1,
+ I3 => sda_sample,
+ I4 => arb_lost,
+ I5 => master_slave,
+ O => sm_stop_i_2_n_0
+ );
+sm_stop_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"24"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => \state__0\(0),
+ I2 => \state__0\(1),
+ O => sm_stop_i_3_n_0
+ );
+sm_stop_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => sm_stop_i_1_n_0,
+ Q => sm_stop_reg_n_0,
+ R => '0'
+ );
+srw_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I2CHEADER_REG_n_7,
+ Q => \^srw_i_reg_0\(1),
+ R => \q_int_reg[0]_1\
+ );
+stop_scl_reg_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AABABBBAAA8A888A"
+ )
+ port map (
+ I0 => stop_scl_reg_i_2_n_0,
+ I1 => stop_scl_reg_i_3_n_0,
+ I2 => scl_state(3),
+ I3 => scl_state(0),
+ I4 => stop_scl_reg_i_4_n_0,
+ I5 => \^stop_scl_reg\,
+ O => stop_scl_reg_i_1_n_0
+ );
+stop_scl_reg_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00080800"
+ )
+ port map (
+ I0 => stop_scl_reg_i_5_n_0,
+ I1 => scl_state(2),
+ I2 => scl_state(3),
+ I3 => scl_state(0),
+ I4 => scl_state(1),
+ O => stop_scl_reg_i_2_n_0
+ );
+stop_scl_reg_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000055557555"
+ )
+ port map (
+ I0 => scl_state(1),
+ I1 => arb_lost,
+ I2 => \^timing_param_tsusto_i_reg[9]\(0),
+ I3 => \^stop_scl_reg\,
+ I4 => Q(3),
+ I5 => stop_scl_reg_i_6_n_0,
+ O => stop_scl_reg_i_3_n_0
+ );
+stop_scl_reg_i_4: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => scl_state(1),
+ I1 => scl_state(2),
+ O => stop_scl_reg_i_4_n_0
+ );
+stop_scl_reg_i_5: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B5B5B500"
+ )
+ port map (
+ I0 => \state__0\(0),
+ I1 => \state__0\(1),
+ I2 => \state__0\(2),
+ I3 => gen_stop,
+ I4 => sm_stop_reg_n_0,
+ O => stop_scl_reg_i_5_n_0
+ );
+stop_scl_reg_i_6: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"BA"
+ )
+ port map (
+ I0 => scl_state(3),
+ I1 => scl_state(2),
+ I2 => scl_state(1),
+ O => stop_scl_reg_i_6_n_0
+ );
+stop_scl_reg_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => stop_scl_reg_i_1_n_0,
+ Q => \^stop_scl_reg\,
+ R => \q_int_reg[0]_1\
+ );
+tx_under_prev_d1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \^tx_under_prev\,
+ Q => tx_under_prev_d1,
+ R => \q_int_reg[0]_1\
+ );
+tx_under_prev_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EEEAAAAA"
+ )
+ port map (
+ I0 => tx_under_prev_i0,
+ I1 => sr_i(0),
+ I2 => \state__0\(1),
+ I3 => \state__0\(0),
+ I4 => \^tx_under_prev\,
+ O => tx_under_prev_i_i_1_n_0
+ );
+tx_under_prev_i_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0800000000000800"
+ )
+ port map (
+ I0 => sm_stop_i_3_n_0,
+ I1 => scl_falling_edge,
+ I2 => gen_stop,
+ I3 => sr_i(0),
+ I4 => \^aas\,
+ I5 => \^srw_i_reg_0\(1),
+ O => tx_under_prev_i0
+ );
+tx_under_prev_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => tx_under_prev_i_i_1_n_0,
+ Q => \^tx_under_prev\,
+ R => \q_int_reg[0]_1\
+ );
+txer_edge_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F5C500C000000000"
+ )
+ port map (
+ I0 => scl_f_edg_d2,
+ I1 => sda_sample,
+ I2 => scl_falling_edge,
+ I3 => txer_edge_i_2_n_0,
+ I4 => \^d\(2),
+ I5 => Q(0),
+ O => txer_edge_i_1_n_0
+ );
+txer_edge_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A7"
+ )
+ port map (
+ I0 => \state__0\(2),
+ I1 => \state__0\(1),
+ I2 => \state__0\(0),
+ O => txer_edge_i_2_n_0
+ );
+txer_edge_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => txer_edge_i_1_n_0,
+ Q => \^d\(2),
+ R => '0'
+ );
+txer_i_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FBFFBFBF08008080"
+ )
+ port map (
+ I0 => sda_sample,
+ I1 => scl_falling_edge,
+ I2 => \state__0\(0),
+ I3 => \state__0\(1),
+ I4 => \state__0\(2),
+ I5 => txer_i_reg_n_0,
+ O => txer_i_i_1_n_0
+ );
+txer_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => txer_i_i_1_n_0,
+ Q => txer_i_reg_n_0,
+ R => \q_int_reg[0]_1\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_slave_attachment is
+ port (
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : out STD_LOGIC;
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Bus_RNW_reg_reg : out STD_LOGIC;
+ s_axi_rvalid_i_reg_0 : out STD_LOGIC;
+ s_axi_bvalid_i_reg_0 : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ is_write_reg_0 : out STD_LOGIC;
+ is_read_reg_0 : out STD_LOGIC;
+ irpt_wrack : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ reset_trig0 : out STD_LOGIC;
+ sw_rst_cond : out STD_LOGIC;
+ \s_axi_wdata[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \bus2ip_addr_i_reg[3]_0\ : out STD_LOGIC;
+ Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \s_axi_wdata[31]\ : out STD_LOGIC;
+ s_axi_wdata_0_sp_1 : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ AXI_IP2Bus_WrAck20 : out STD_LOGIC;
+ AXI_IP2Bus_RdAck20 : out STD_LOGIC;
+ AXI_Bus2IP_Reset : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
+ \s_axi_rdata_i_reg[7]_i_7_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_7_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i[0]_i_2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aresetn : in STD_LOGIC;
+ AXI_IP2Bus_RdAck1 : in STD_LOGIC;
+ AXI_IP2Bus_RdAck2 : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ AXI_IP2Bus_WrAck1 : in STD_LOGIC;
+ AXI_IP2Bus_WrAck2 : in STD_LOGIC;
+ sw_rst_cond_d1 : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \cr_i_reg[2]\ : in STD_LOGIC;
+ firstDynStartSeen : in STD_LOGIC;
+ \cr_i_reg[2]_0\ : in STD_LOGIC;
+ Rc_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i_reg[1]_0\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ p_1_in8_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[4]_i_2_0\ : in STD_LOGIC;
+ p_1_in5_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[5]_i_2_0\ : in STD_LOGIC;
+ p_1_in2_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[6]_i_2_0\ : in STD_LOGIC;
+ p_1_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_2_0\ : in STD_LOGIC;
+ cr_txModeSelect_set : in STD_LOGIC;
+ cr_txModeSelect_clr : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ \s_axi_rdata_i_reg[0]_0\ : in STD_LOGIC;
+ p_1_in17_in : in STD_LOGIC;
+ p_1_in14_in : in STD_LOGIC;
+ p_1_in11_in : in STD_LOGIC;
+ ipif_glbl_irpt_enable_reg : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_6_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i_reg[3]_0\ : in STD_LOGIC;
+ Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
+ \s_axi_rdata_i[3]_i_2_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i[3]_i_2_1\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[2]_0\ : in STD_LOGIC;
+ \s_axi_rdata_i[2]_i_2_0\ : in STD_LOGIC;
+ \s_axi_rdata_i[1]_i_2_0\ : in STD_LOGIC;
+ \s_axi_rdata_i[0]_i_2_1\ : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ gpo : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 1 downto 0 )
+ );
+end TopLevel_axi_iic_0_0_slave_attachment;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_slave_attachment is
+ signal AXI_IP2Bus_Data : STD_LOGIC_VECTOR ( 24 to 31 );
+ signal AXI_IP2Bus_Error : STD_LOGIC;
+ signal Bus2IIC_Addr : STD_LOGIC_VECTOR ( 0 to 8 );
+ signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_onehot_state[3]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_onehot_state_reg_n_0_[0]\ : STD_LOGIC;
+ signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
+ signal \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\ : STD_LOGIC;
+ signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal I_DECODER_n_34 : STD_LOGIC;
+ signal Intr2Bus_DBus : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \bus2ip_addr_i[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[7]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
+ signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
+ signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
+ signal is_read_i_1_n_0 : STD_LOGIC;
+ signal \^is_read_reg_0\ : STD_LOGIC;
+ signal is_read_reg_n_0 : STD_LOGIC;
+ signal is_write_i_1_n_0 : STD_LOGIC;
+ signal is_write_i_2_n_0 : STD_LOGIC;
+ signal \^is_write_reg_0\ : STD_LOGIC;
+ signal is_write_reg_n_0 : STD_LOGIC;
+ signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal rst : STD_LOGIC;
+ signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal s_axi_bresp_i : STD_LOGIC;
+ signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
+ signal \^s_axi_bvalid_i_reg_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_11_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_7_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[0]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_11_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_7_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[1]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[2]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[3]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[4]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[4]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[4]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[4]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[5]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[5]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[5]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[5]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[6]_i_5_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[6]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[6]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[6]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_11_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_12_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_8_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[7]_i_9_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i[9]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[4]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[4]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[4]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[5]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[5]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[5]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[6]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[6]_i_3_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[6]_i_4_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[7]_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[7]_i_6_n_0\ : STD_LOGIC;
+ signal \s_axi_rdata_i_reg[7]_i_7_n_0\ : STD_LOGIC;
+ signal s_axi_rresp_i : STD_LOGIC;
+ signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
+ signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
+ signal s_axi_wdata_0_sn_1 : STD_LOGIC;
+ signal start2 : STD_LOGIC;
+ signal start2_i_1_n_0 : STD_LOGIC;
+ signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \state[1]_i_2_n_0\ : STD_LOGIC;
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[0]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
+ attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[1]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
+ attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
+ attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[3]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair61";
+ attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair61";
+ attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair56";
+ attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair56";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[1]_i_1\ : label is "soft_lutpair60";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair60";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair59";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair59";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[5]_i_1\ : label is "soft_lutpair58";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[6]_i_1\ : label is "soft_lutpair58";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[7]_i_1\ : label is "soft_lutpair57";
+ attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair57";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_5\ : label is "soft_lutpair55";
+ attribute SOFT_HLUTNM of \s_axi_rdata_i[4]_i_9\ : label is "soft_lutpair55";
+ attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair54";
+ attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair54";
+begin
+ Q(4 downto 0) <= \^q\(4 downto 0);
+ is_read_reg_0 <= \^is_read_reg_0\;
+ is_write_reg_0 <= \^is_write_reg_0\;
+ s_axi_bresp(0) <= \^s_axi_bresp\(0);
+ s_axi_bvalid_i_reg_0 <= \^s_axi_bvalid_i_reg_0\;
+ s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
+ s_axi_wdata_0_sp_1 <= s_axi_wdata_0_sn_1;
+\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"44444F444F444F44"
+ )
+ port map (
+ I0 => \FSM_onehot_state[3]_i_2_n_0\,
+ I1 => \FSM_onehot_state_reg_n_0_[3]\,
+ I2 => s_axi_arvalid,
+ I3 => \FSM_onehot_state_reg_n_0_[0]\,
+ I4 => s_axi_wvalid,
+ I5 => s_axi_awvalid,
+ O => \FSM_onehot_state[0]_i_1_n_0\
+ );
+\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8F88"
+ )
+ port map (
+ I0 => \FSM_onehot_state_reg_n_0_[0]\,
+ I1 => s_axi_arvalid,
+ I2 => \^is_read_reg_0\,
+ I3 => s_axi_rresp_i,
+ O => \FSM_onehot_state[1]_i_1_n_0\
+ );
+\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4000FFFF40004000"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => \FSM_onehot_state_reg_n_0_[0]\,
+ I2 => s_axi_wvalid,
+ I3 => s_axi_awvalid,
+ I4 => \^is_write_reg_0\,
+ I5 => s_axi_bresp_i,
+ O => \FSM_onehot_state[2]_i_1_n_0\
+ );
+\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF888F888F888"
+ )
+ port map (
+ I0 => \^is_read_reg_0\,
+ I1 => s_axi_rresp_i,
+ I2 => s_axi_bresp_i,
+ I3 => \^is_write_reg_0\,
+ I4 => \FSM_onehot_state_reg_n_0_[3]\,
+ I5 => \FSM_onehot_state[3]_i_2_n_0\,
+ O => \FSM_onehot_state[3]_i_1_n_0\
+ );
+\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0777"
+ )
+ port map (
+ I0 => \^s_axi_rvalid_i_reg_0\,
+ I1 => s_axi_rready,
+ I2 => \^s_axi_bvalid_i_reg_0\,
+ I3 => s_axi_bready,
+ O => \FSM_onehot_state[3]_i_2_n_0\
+ );
+\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \FSM_onehot_state[0]_i_1_n_0\,
+ Q => \FSM_onehot_state_reg_n_0_[0]\,
+ S => rst
+ );
+\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \FSM_onehot_state[1]_i_1_n_0\,
+ Q => s_axi_rresp_i,
+ R => rst
+ );
+\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \FSM_onehot_state[2]_i_1_n_0\,
+ Q => s_axi_bresp_i,
+ R => rst
+ );
+\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \FSM_onehot_state[3]_i_1_n_0\,
+ Q => \FSM_onehot_state_reg_n_0_[3]\,
+ R => rst
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
+ O => plusOp(0)
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
+ I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
+ O => plusOp(1)
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
+ I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
+ I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
+ O => plusOp(2)
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"9"
+ )
+ port map (
+ I0 => state(0),
+ I1 => state(1),
+ O => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6AAA"
+ )
+ port map (
+ I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
+ I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
+ I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
+ I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
+ O => plusOp(3)
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => plusOp(0),
+ Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
+ R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => plusOp(1),
+ Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
+ R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => plusOp(2),
+ Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
+ R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
+ );
+\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => plusOp(3),
+ Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
+ R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
+ );
+I_DECODER: entity work.TopLevel_axi_iic_0_0_address_decoder
+ port map (
+ AXI_IP2Bus_Error => AXI_IP2Bus_Error,
+ AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
+ AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
+ AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
+ AXI_IP2Bus_WrAck20 => AXI_IP2Bus_WrAck20,
+ AXI_IP2Bus_WrAck2_reg => bus2ip_rnw_i_reg_n_0,
+ Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
+ Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
+ Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg,
+ D(8) => Intr2Bus_DBus(0),
+ D(7) => AXI_IP2Bus_Data(24),
+ D(6) => AXI_IP2Bus_Data(25),
+ D(5) => AXI_IP2Bus_Data(26),
+ D(4) => AXI_IP2Bus_Data(27),
+ D(3) => AXI_IP2Bus_Data(28),
+ D(2) => AXI_IP2Bus_Data(29),
+ D(1) => AXI_IP2Bus_Data(30),
+ D(0) => AXI_IP2Bus_Data(31),
+ E(0) => E(0),
+ \FSM_onehot_state_reg[2]\ => I_DECODER_n_34,
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\ => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(8) => Bus2IIC_Addr(0),
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(7) => Bus2IIC_Addr(1),
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(6 downto 2) => \^q\(4 downto 0),
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(1) => Bus2IIC_Addr(7),
+ \MEM_DECODE_GEN[2].cs_out_i_reg[2]_0\(0) => Bus2IIC_Addr(8),
+ Q => start2,
+ \bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]_0\,
+ \cr_i_reg[2]\ => \cr_i_reg[2]\,
+ \cr_i_reg[2]_0\(1) => \s_axi_rdata_i[7]_i_8_0\(3),
+ \cr_i_reg[2]_0\(0) => \s_axi_rdata_i[7]_i_8_0\(1),
+ \cr_i_reg[2]_1\ => \cr_i_reg[2]_0\,
+ cr_txModeSelect_clr => cr_txModeSelect_clr,
+ cr_txModeSelect_set => cr_txModeSelect_set,
+ firstDynStartSeen => firstDynStartSeen,
+ gpo(0) => gpo(0),
+ ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
+ irpt_wrack => irpt_wrack,
+ is_read_reg => \^is_read_reg_0\,
+ is_write_reg => \^is_write_reg_0\,
+ p_1_in => p_1_in,
+ p_1_in11_in => p_1_in11_in,
+ p_1_in14_in => p_1_in14_in,
+ p_1_in17_in => p_1_in17_in,
+ p_1_in2_in => p_1_in2_in,
+ p_1_in5_in => p_1_in5_in,
+ p_1_in8_in => p_1_in8_in,
+ reset_trig0 => reset_trig0,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arready => is_read_reg_n_0,
+ s_axi_awready => is_write_reg_n_0,
+ s_axi_awready_0(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3 downto 0),
+ s_axi_bresp(0) => \^s_axi_bresp\(0),
+ \s_axi_bresp_i_reg[1]\(0) => s_axi_bresp_i,
+ \s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i[0]_i_2_n_0\,
+ \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i[0]_i_3_n_0\,
+ \s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
+ \s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i[1]_i_2_n_0\,
+ \s_axi_rdata_i_reg[1]_0\ => \s_axi_rdata_i[1]_i_3_n_0\,
+ \s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i[2]_i_2_n_0\,
+ \s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i[3]_i_2_n_0\,
+ \s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]_i_2_n_0\,
+ \s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]_i_2_n_0\,
+ \s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]_i_2_n_0\,
+ \s_axi_rdata_i_reg[7]\(7 downto 0) => \s_axi_rdata_i_reg[7]_0\(7 downto 0),
+ \s_axi_rdata_i_reg[7]_0\ => \s_axi_rdata_i_reg[7]_i_2_n_0\,
+ \s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i[9]_i_6_n_0\,
+ s_axi_wdata(5 downto 0) => s_axi_wdata(5 downto 0),
+ \s_axi_wdata[31]\ => \s_axi_wdata[31]\,
+ \s_axi_wdata[5]\(1 downto 0) => \s_axi_wdata[5]\(1 downto 0),
+ s_axi_wdata_0_sp_1 => s_axi_wdata_0_sn_1,
+ sw_rst_cond => sw_rst_cond,
+ sw_rst_cond_d1 => sw_rst_cond_d1
+ );
+\bus2ip_addr_i[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(0),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(0),
+ O => \bus2ip_addr_i[0]_i_1_n_0\
+ );
+\bus2ip_addr_i[1]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(1),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(1),
+ O => \bus2ip_addr_i[1]_i_1_n_0\
+ );
+\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(2),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(2),
+ O => \bus2ip_addr_i[2]_i_1_n_0\
+ );
+\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(3),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(3),
+ O => \bus2ip_addr_i[3]_i_1_n_0\
+ );
+\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(4),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(4),
+ O => \bus2ip_addr_i[4]_i_1_n_0\
+ );
+\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(5),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(5),
+ O => \bus2ip_addr_i[5]_i_1_n_0\
+ );
+\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(6),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(6),
+ O => \bus2ip_addr_i[6]_i_1_n_0\
+ );
+\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(7),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(7),
+ O => \bus2ip_addr_i[7]_i_1_n_0\
+ );
+\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"03020202"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => state(0),
+ I2 => state(1),
+ I3 => s_axi_wvalid,
+ I4 => s_axi_awvalid,
+ O => \bus2ip_addr_i[8]_i_1_n_0\
+ );
+\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => s_axi_araddr(8),
+ I1 => s_axi_arvalid,
+ I2 => s_axi_awaddr(8),
+ O => \bus2ip_addr_i[8]_i_2_n_0\
+ );
+\bus2ip_addr_i_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[0]_i_1_n_0\,
+ Q => Bus2IIC_Addr(8),
+ R => rst
+ );
+\bus2ip_addr_i_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[1]_i_1_n_0\,
+ Q => Bus2IIC_Addr(7),
+ R => rst
+ );
+\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[2]_i_1_n_0\,
+ Q => \^q\(0),
+ R => rst
+ );
+\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[3]_i_1_n_0\,
+ Q => \^q\(1),
+ R => rst
+ );
+\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[4]_i_1_n_0\,
+ Q => \^q\(2),
+ R => rst
+ );
+\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[5]_i_1_n_0\,
+ Q => \^q\(3),
+ R => rst
+ );
+\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[6]_i_1_n_0\,
+ Q => \^q\(4),
+ R => rst
+ );
+\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[7]_i_1_n_0\,
+ Q => Bus2IIC_Addr(1),
+ R => rst
+ );
+\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => \bus2ip_addr_i[8]_i_2_n_0\,
+ Q => Bus2IIC_Addr(0),
+ R => rst
+ );
+bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => \bus2ip_addr_i[8]_i_1_n_0\,
+ D => s_axi_arvalid,
+ Q => bus2ip_rnw_i_reg_n_0,
+ R => rst
+ );
+is_read_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BB8888"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => \FSM_onehot_state_reg_n_0_[0]\,
+ I2 => \FSM_onehot_state[3]_i_2_n_0\,
+ I3 => \FSM_onehot_state_reg_n_0_[3]\,
+ I4 => is_read_reg_n_0,
+ O => is_read_i_1_n_0
+ );
+is_read_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => is_read_i_1_n_0,
+ Q => is_read_reg_n_0,
+ R => rst
+ );
+is_write_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0080FFFF00800000"
+ )
+ port map (
+ I0 => s_axi_awvalid,
+ I1 => s_axi_wvalid,
+ I2 => \FSM_onehot_state_reg_n_0_[0]\,
+ I3 => s_axi_arvalid,
+ I4 => is_write_i_2_n_0,
+ I5 => is_write_reg_n_0,
+ O => is_write_i_1_n_0
+ );
+is_write_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFEAEAEAAAAAAAAA"
+ )
+ port map (
+ I0 => \FSM_onehot_state_reg_n_0_[0]\,
+ I1 => \^s_axi_rvalid_i_reg_0\,
+ I2 => s_axi_rready,
+ I3 => \^s_axi_bvalid_i_reg_0\,
+ I4 => s_axi_bready,
+ I5 => \FSM_onehot_state_reg_n_0_[3]\,
+ O => is_write_i_2_n_0
+ );
+is_write_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => is_write_i_1_n_0,
+ Q => is_write_reg_n_0,
+ R => rst
+ );
+rst_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AXI_Bus2IP_Reset,
+ Q => rst,
+ R => '0'
+ );
+\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => I_DECODER_n_34,
+ Q => \^s_axi_bresp\(0),
+ R => rst
+ );
+s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"75553000"
+ )
+ port map (
+ I0 => s_axi_bready,
+ I1 => state(0),
+ I2 => state(1),
+ I3 => \^is_write_reg_0\,
+ I4 => \^s_axi_bvalid_i_reg_0\,
+ O => s_axi_bvalid_i_i_1_n_0
+ );
+s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_bvalid_i_i_1_n_0,
+ Q => \^s_axi_bvalid_i_reg_0\,
+ R => rst
+ );
+\s_axi_rdata_i[0]_i_11\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00011101"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(0),
+ I2 => Tx_fifo_data(0),
+ I3 => \^q\(3),
+ I4 => \s_axi_rdata_i_reg[7]_i_6_0\(0),
+ O => \s_axi_rdata_i[0]_i_11_n_0\
+ );
+\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000FFB0B0"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[0]_i_5_n_0\,
+ I1 => \s_axi_rdata_i_reg[7]_i_6_2\(0),
+ I2 => \s_axi_rdata_i[0]_i_6_n_0\,
+ I3 => \s_axi_rdata_i[0]_i_7_n_0\,
+ I4 => \^q\(0),
+ I5 => \^q\(1),
+ O => \s_axi_rdata_i[0]_i_2_n_0\
+ );
+\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000AAEAAAAA"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[0]_i_8_n_0\,
+ I1 => \s_axi_rdata_i_reg[7]_i_7_1\(0),
+ I2 => \^q\(2),
+ I3 => \^q\(4),
+ I4 => \^q\(3),
+ I5 => \s_axi_rdata_i[0]_i_9_n_0\,
+ O => \s_axi_rdata_i[0]_i_3_n_0\
+ );
+\s_axi_rdata_i[0]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"DF"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \^q\(4),
+ I2 => \^q\(2),
+ O => \s_axi_rdata_i[0]_i_5_n_0\
+ );
+\s_axi_rdata_i[0]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFAABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \s_axi_rdata_i[7]_i_8_0\(0),
+ I2 => \^q\(4),
+ I3 => \s_axi_rdata_i[7]_i_8_1\(0),
+ I4 => \^q\(3),
+ I5 => \s_axi_rdata_i[0]_i_2_0\(0),
+ O => \s_axi_rdata_i[0]_i_6_n_0\
+ );
+\s_axi_rdata_i[0]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00E2FFFF00E20000"
+ )
+ port map (
+ I0 => Tx_addr(0),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i[3]_i_2_0\(0),
+ I3 => \^q\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[0]_i_2_1\,
+ O => \s_axi_rdata_i[0]_i_7_n_0\
+ );
+\s_axi_rdata_i[0]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"1311131313111111"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(4),
+ I2 => \^q\(2),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(0),
+ I4 => \^q\(3),
+ I5 => Rc_fifo_data(7),
+ O => \s_axi_rdata_i[0]_i_8_n_0\
+ );
+\s_axi_rdata_i[0]_i_9\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF00200222"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(0),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_1\(0),
+ I4 => Rc_addr(1),
+ I5 => \s_axi_rdata_i[0]_i_11_n_0\,
+ O => \s_axi_rdata_i[0]_i_9_n_0\
+ );
+\s_axi_rdata_i[1]_i_11\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00011101"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(0),
+ I2 => Tx_fifo_data(1),
+ I3 => \^q\(3),
+ I4 => \s_axi_rdata_i_reg[7]_i_6_0\(1),
+ O => \s_axi_rdata_i[1]_i_11_n_0\
+ );
+\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0035"
+ )
+ port map (
+ I0 => \s_axi_rdata_i_reg[1]_0\,
+ I1 => \s_axi_rdata_i[1]_i_6_n_0\,
+ I2 => \^q\(0),
+ I3 => \^q\(1),
+ O => \s_axi_rdata_i[1]_i_2_n_0\
+ );
+\s_axi_rdata_i[1]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000AAEAAAAA"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[1]_i_7_n_0\,
+ I1 => \s_axi_rdata_i_reg[7]_i_7_1\(1),
+ I2 => \^q\(2),
+ I3 => \^q\(4),
+ I4 => \^q\(3),
+ I5 => \s_axi_rdata_i[1]_i_8_n_0\,
+ O => \s_axi_rdata_i[1]_i_3_n_0\
+ );
+\s_axi_rdata_i[1]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00E2FFFF00E20000"
+ )
+ port map (
+ I0 => Tx_addr(1),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i[3]_i_2_0\(1),
+ I3 => \^q\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[1]_i_2_0\,
+ O => \s_axi_rdata_i[1]_i_6_n_0\
+ );
+\s_axi_rdata_i[1]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"1311131313111111"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => \^q\(4),
+ I2 => \^q\(2),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(1),
+ I4 => \^q\(3),
+ I5 => Rc_fifo_data(6),
+ O => \s_axi_rdata_i[1]_i_7_n_0\
+ );
+\s_axi_rdata_i[1]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF00200222"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => \^q\(0),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_1\(1),
+ I4 => Rc_addr(0),
+ I5 => \s_axi_rdata_i[1]_i_11_n_0\,
+ O => \s_axi_rdata_i[1]_i_8_n_0\
+ );
+\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8FFB800"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[2]_i_3_n_0\,
+ I1 => \^q\(1),
+ I2 => \s_axi_rdata_i[2]_i_4_n_0\,
+ I3 => \^q\(0),
+ I4 => \s_axi_rdata_i_reg[2]_0\,
+ O => \s_axi_rdata_i[2]_i_2_n_0\
+ );
+\s_axi_rdata_i[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000CCE200E2"
+ )
+ port map (
+ I0 => Rc_fifo_data(5),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i_reg[7]_i_7_0\(2),
+ I3 => \^q\(2),
+ I4 => \s_axi_rdata_i_reg[7]_i_7_1\(2),
+ I5 => \^q\(4),
+ O => \s_axi_rdata_i[2]_i_3_n_0\
+ );
+\s_axi_rdata_i[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00E2FFFF00E20000"
+ )
+ port map (
+ I0 => Tx_addr(2),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i[3]_i_2_0\(2),
+ I3 => \^q\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[2]_i_2_0\,
+ O => \s_axi_rdata_i[2]_i_4_n_0\
+ );
+\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8FFB800"
+ )
+ port map (
+ I0 => \s_axi_rdata_i[3]_i_3_n_0\,
+ I1 => \^q\(1),
+ I2 => \s_axi_rdata_i[3]_i_4_n_0\,
+ I3 => \^q\(0),
+ I4 => \s_axi_rdata_i_reg[3]_0\,
+ O => \s_axi_rdata_i[3]_i_2_n_0\
+ );
+\s_axi_rdata_i[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000CCE200E2"
+ )
+ port map (
+ I0 => Rc_fifo_data(4),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i_reg[7]_i_7_0\(3),
+ I3 => \^q\(2),
+ I4 => \s_axi_rdata_i_reg[7]_i_7_1\(3),
+ I5 => \^q\(4),
+ O => \s_axi_rdata_i[3]_i_3_n_0\
+ );
+\s_axi_rdata_i[3]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00E2FFFF00E20000"
+ )
+ port map (
+ I0 => Tx_addr(3),
+ I1 => \^q\(3),
+ I2 => \s_axi_rdata_i[3]_i_2_0\(3),
+ I3 => \^q\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[3]_i_2_1\,
+ O => \s_axi_rdata_i[3]_i_4_n_0\
+ );
+\s_axi_rdata_i[4]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"ABFBFFFFABFB0000"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \s_axi_rdata_i_reg[7]_i_6_3\(0),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_2\(1),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[4]_i_9_n_0\,
+ O => \s_axi_rdata_i[4]_i_5_n_0\
+ );
+\s_axi_rdata_i[4]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Tx_fifo_data(2),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_0\(2),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_6_1\(2),
+ O => \s_axi_rdata_i[4]_i_6_n_0\
+ );
+\s_axi_rdata_i[4]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Rc_fifo_data(3),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_7_1\(4),
+ O => \s_axi_rdata_i[4]_i_8_n_0\
+ );
+\s_axi_rdata_i[4]_i_9\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \s_axi_rdata_i[7]_i_8_0\(2),
+ I2 => \^q\(4),
+ I3 => \s_axi_rdata_i[7]_i_8_1\(1),
+ O => \s_axi_rdata_i[4]_i_9_n_0\
+ );
+\s_axi_rdata_i[5]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"ABFBFFFFABFB0000"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \s_axi_rdata_i_reg[7]_i_6_3\(1),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_2\(2),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[5]_i_9_n_0\,
+ O => \s_axi_rdata_i[5]_i_5_n_0\
+ );
+\s_axi_rdata_i[5]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Tx_fifo_data(3),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_0\(3),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_6_1\(3),
+ O => \s_axi_rdata_i[5]_i_6_n_0\
+ );
+\s_axi_rdata_i[5]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Rc_fifo_data(2),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(5),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_7_1\(5),
+ O => \s_axi_rdata_i[5]_i_8_n_0\
+ );
+\s_axi_rdata_i[5]_i_9\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \s_axi_rdata_i[7]_i_8_0\(3),
+ I2 => \^q\(4),
+ I3 => \s_axi_rdata_i[7]_i_8_1\(2),
+ O => \s_axi_rdata_i[5]_i_9_n_0\
+ );
+\s_axi_rdata_i[6]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"ABFBFFFFABFB0000"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \s_axi_rdata_i_reg[7]_i_6_3\(2),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_2\(3),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[6]_i_9_n_0\,
+ O => \s_axi_rdata_i[6]_i_5_n_0\
+ );
+\s_axi_rdata_i[6]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Tx_fifo_data(4),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_0\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_6_1\(4),
+ O => \s_axi_rdata_i[6]_i_6_n_0\
+ );
+\s_axi_rdata_i[6]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Rc_fifo_data(1),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(6),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_7_1\(6),
+ O => \s_axi_rdata_i[6]_i_8_n_0\
+ );
+\s_axi_rdata_i[6]_i_9\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \s_axi_rdata_i[7]_i_8_0\(4),
+ I2 => \^q\(4),
+ I3 => \s_axi_rdata_i[7]_i_8_1\(3),
+ O => \s_axi_rdata_i[6]_i_9_n_0\
+ );
+\s_axi_rdata_i[7]_i_11\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Rc_fifo_data(0),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_7_0\(7),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_7_1\(7),
+ O => \s_axi_rdata_i[7]_i_11_n_0\
+ );
+\s_axi_rdata_i[7]_i_12\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \s_axi_rdata_i[7]_i_8_0\(5),
+ I2 => \^q\(4),
+ I3 => \s_axi_rdata_i[7]_i_8_1\(4),
+ O => \s_axi_rdata_i[7]_i_12_n_0\
+ );
+\s_axi_rdata_i[7]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"ABFBFFFFABFB0000"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => \s_axi_rdata_i_reg[7]_i_6_3\(3),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_2\(4),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i[7]_i_12_n_0\,
+ O => \s_axi_rdata_i[7]_i_8_n_0\
+ );
+\s_axi_rdata_i[7]_i_9\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFABFBFFFFABFB"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => Tx_fifo_data(5),
+ I2 => \^q\(3),
+ I3 => \s_axi_rdata_i_reg[7]_i_6_0\(5),
+ I4 => \^q\(2),
+ I5 => \s_axi_rdata_i_reg[7]_i_6_1\(5),
+ O => \s_axi_rdata_i[7]_i_9_n_0\
+ );
+\s_axi_rdata_i[9]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FE"
+ )
+ port map (
+ I0 => Bus2IIC_Addr(7),
+ I1 => Bus2IIC_Addr(8),
+ I2 => Bus2IIC_Addr(1),
+ O => \s_axi_rdata_i[9]_i_6_n_0\
+ );
+\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(31),
+ Q => s_axi_rdata(0),
+ R => rst
+ );
+\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(30),
+ Q => s_axi_rdata(1),
+ R => rst
+ );
+\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(29),
+ Q => s_axi_rdata(2),
+ R => rst
+ );
+\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => Intr2Bus_DBus(0),
+ Q => s_axi_rdata(10),
+ R => rst
+ );
+\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(28),
+ Q => s_axi_rdata(3),
+ R => rst
+ );
+\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(27),
+ Q => s_axi_rdata(4),
+ R => rst
+ );
+\s_axi_rdata_i_reg[4]_i_2\: unisim.vcomponents.MUXF8
+ port map (
+ I0 => \s_axi_rdata_i_reg[4]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[4]_i_4_n_0\,
+ O => \s_axi_rdata_i_reg[4]_i_2_n_0\,
+ S => \^q\(0)
+ );
+\s_axi_rdata_i_reg[4]_i_3\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i[4]_i_5_n_0\,
+ I1 => \s_axi_rdata_i[4]_i_6_n_0\,
+ O => \s_axi_rdata_i_reg[4]_i_3_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[4]_i_4\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i_reg[4]_i_2_0\,
+ I1 => \s_axi_rdata_i[4]_i_8_n_0\,
+ O => \s_axi_rdata_i_reg[4]_i_4_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(26),
+ Q => s_axi_rdata(5),
+ R => rst
+ );
+\s_axi_rdata_i_reg[5]_i_2\: unisim.vcomponents.MUXF8
+ port map (
+ I0 => \s_axi_rdata_i_reg[5]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[5]_i_4_n_0\,
+ O => \s_axi_rdata_i_reg[5]_i_2_n_0\,
+ S => \^q\(0)
+ );
+\s_axi_rdata_i_reg[5]_i_3\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i[5]_i_5_n_0\,
+ I1 => \s_axi_rdata_i[5]_i_6_n_0\,
+ O => \s_axi_rdata_i_reg[5]_i_3_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[5]_i_4\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i_reg[5]_i_2_0\,
+ I1 => \s_axi_rdata_i[5]_i_8_n_0\,
+ O => \s_axi_rdata_i_reg[5]_i_4_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(25),
+ Q => s_axi_rdata(6),
+ R => rst
+ );
+\s_axi_rdata_i_reg[6]_i_2\: unisim.vcomponents.MUXF8
+ port map (
+ I0 => \s_axi_rdata_i_reg[6]_i_3_n_0\,
+ I1 => \s_axi_rdata_i_reg[6]_i_4_n_0\,
+ O => \s_axi_rdata_i_reg[6]_i_2_n_0\,
+ S => \^q\(0)
+ );
+\s_axi_rdata_i_reg[6]_i_3\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i[6]_i_5_n_0\,
+ I1 => \s_axi_rdata_i[6]_i_6_n_0\,
+ O => \s_axi_rdata_i_reg[6]_i_3_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[6]_i_4\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i_reg[6]_i_2_0\,
+ I1 => \s_axi_rdata_i[6]_i_8_n_0\,
+ O => \s_axi_rdata_i_reg[6]_i_4_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Data(24),
+ Q => s_axi_rdata(7),
+ R => rst
+ );
+\s_axi_rdata_i_reg[7]_i_2\: unisim.vcomponents.MUXF8
+ port map (
+ I0 => \s_axi_rdata_i_reg[7]_i_6_n_0\,
+ I1 => \s_axi_rdata_i_reg[7]_i_7_n_0\,
+ O => \s_axi_rdata_i_reg[7]_i_2_n_0\,
+ S => \^q\(0)
+ );
+\s_axi_rdata_i_reg[7]_i_6\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i[7]_i_8_n_0\,
+ I1 => \s_axi_rdata_i[7]_i_9_n_0\,
+ O => \s_axi_rdata_i_reg[7]_i_6_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[7]_i_7\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \s_axi_rdata_i_reg[7]_i_2_0\,
+ I1 => \s_axi_rdata_i[7]_i_11_n_0\,
+ O => \s_axi_rdata_i_reg[7]_i_7_n_0\,
+ S => \^q\(1)
+ );
+\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => D(0),
+ Q => s_axi_rdata(8),
+ R => rst
+ );
+\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => D(1),
+ Q => s_axi_rdata(9),
+ R => rst
+ );
+\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => s_axi_rresp_i,
+ D => AXI_IP2Bus_Error,
+ Q => s_axi_rresp(0),
+ R => rst
+ );
+s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"75553000"
+ )
+ port map (
+ I0 => s_axi_rready,
+ I1 => state(1),
+ I2 => state(0),
+ I3 => \^is_read_reg_0\,
+ I4 => \^s_axi_rvalid_i_reg_0\,
+ O => s_axi_rvalid_i_i_1_n_0
+ );
+s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_rvalid_i_i_1_n_0,
+ Q => \^s_axi_rvalid_i_reg_0\,
+ R => rst
+ );
+start2_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000F0008"
+ )
+ port map (
+ I0 => s_axi_wvalid,
+ I1 => s_axi_awvalid,
+ I2 => state(0),
+ I3 => state(1),
+ I4 => s_axi_arvalid,
+ O => start2_i_1_n_0
+ );
+start2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => start2_i_1_n_0,
+ Q => start2,
+ R => rst
+ );
+\state[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FBF83B38"
+ )
+ port map (
+ I0 => \^is_write_reg_0\,
+ I1 => state(1),
+ I2 => state(0),
+ I3 => s_axi_arvalid,
+ I4 => \FSM_onehot_state[3]_i_2_n_0\,
+ O => p_0_out(0)
+ );
+\state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EECFEECC22CF22CC"
+ )
+ port map (
+ I0 => \^is_read_reg_0\,
+ I1 => state(1),
+ I2 => s_axi_arvalid,
+ I3 => state(0),
+ I4 => \state[1]_i_2_n_0\,
+ I5 => \FSM_onehot_state[3]_i_2_n_0\,
+ O => p_0_out(1)
+ );
+\state[1]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s_axi_wvalid,
+ I1 => s_axi_awvalid,
+ O => \state[1]_i_2_n_0\
+ );
+\state_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => p_0_out(0),
+ Q => state(0),
+ R => rst
+ );
+\state_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => p_0_out(1),
+ Q => state(1),
+ R => rst
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_axi_lite_ipif is
+ port (
+ p_27_in : out STD_LOGIC;
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Bus_RNW_reg : out STD_LOGIC;
+ s_axi_rvalid_i_reg : out STD_LOGIC;
+ s_axi_bvalid_i_reg : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ is_write_reg : out STD_LOGIC;
+ is_read_reg : out STD_LOGIC;
+ irpt_wrack : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ reset_trig0 : out STD_LOGIC;
+ sw_rst_cond : out STD_LOGIC;
+ \s_axi_wdata[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \bus2ip_addr_i_reg[3]\ : out STD_LOGIC;
+ Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \s_axi_wdata[31]\ : out STD_LOGIC;
+ s_axi_wdata_0_sp_1 : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ AXI_IP2Bus_WrAck20 : out STD_LOGIC;
+ AXI_IP2Bus_RdAck20 : out STD_LOGIC;
+ AXI_Bus2IP_Reset : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
+ \s_axi_rdata_i_reg[7]_i_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_7_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i[0]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aresetn : in STD_LOGIC;
+ AXI_IP2Bus_RdAck1 : in STD_LOGIC;
+ AXI_IP2Bus_RdAck2 : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ AXI_IP2Bus_WrAck1 : in STD_LOGIC;
+ AXI_IP2Bus_WrAck2 : in STD_LOGIC;
+ sw_rst_cond_d1 : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \cr_i_reg[2]\ : in STD_LOGIC;
+ firstDynStartSeen : in STD_LOGIC;
+ \cr_i_reg[2]_0\ : in STD_LOGIC;
+ Rc_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i_reg[1]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ p_1_in8_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[4]_i_2\ : in STD_LOGIC;
+ p_1_in5_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[5]_i_2\ : in STD_LOGIC;
+ p_1_in2_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[6]_i_2\ : in STD_LOGIC;
+ p_1_in : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_2\ : in STD_LOGIC;
+ cr_txModeSelect_set : in STD_LOGIC;
+ cr_txModeSelect_clr : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ \s_axi_rdata_i_reg[0]\ : in STD_LOGIC;
+ p_1_in17_in : in STD_LOGIC;
+ p_1_in14_in : in STD_LOGIC;
+ p_1_in11_in : in STD_LOGIC;
+ ipif_glbl_irpt_enable_reg : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_6_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i_reg[3]\ : in STD_LOGIC;
+ Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
+ \s_axi_rdata_i[3]_i_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i[3]_i_2_0\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[2]\ : in STD_LOGIC;
+ \s_axi_rdata_i[2]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i[1]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i[0]_i_2_0\ : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ gpo : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 1 downto 0 )
+ );
+end TopLevel_axi_iic_0_0_axi_lite_ipif;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_axi_lite_ipif is
+ signal s_axi_wdata_0_sn_1 : STD_LOGIC;
+begin
+ s_axi_wdata_0_sp_1 <= s_axi_wdata_0_sn_1;
+I_SLAVE_ATTACHMENT: entity work.TopLevel_axi_iic_0_0_slave_attachment
+ port map (
+ AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
+ AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
+ AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
+ AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
+ AXI_IP2Bus_WrAck20 => AXI_IP2Bus_WrAck20,
+ Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
+ Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
+ Bus_RNW_reg_reg => Bus_RNW_reg,
+ D(1 downto 0) => D(1 downto 0),
+ E(0) => E(0),
+ \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => p_27_in,
+ Q(4 downto 0) => Q(4 downto 0),
+ Rc_addr(1 downto 0) => Rc_addr(1 downto 0),
+ Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
+ Tx_addr(0 to 3) => Tx_addr(0 to 3),
+ Tx_fifo_data(5 downto 0) => Tx_fifo_data(5 downto 0),
+ \bus2ip_addr_i_reg[3]_0\ => \bus2ip_addr_i_reg[3]\,
+ \cr_i_reg[2]\ => \cr_i_reg[2]\,
+ \cr_i_reg[2]_0\ => \cr_i_reg[2]_0\,
+ cr_txModeSelect_clr => cr_txModeSelect_clr,
+ cr_txModeSelect_set => cr_txModeSelect_set,
+ firstDynStartSeen => firstDynStartSeen,
+ gpo(0) => gpo(0),
+ ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
+ irpt_wrack => irpt_wrack,
+ is_read_reg_0 => is_read_reg,
+ is_write_reg_0 => is_write_reg,
+ p_1_in => p_1_in,
+ p_1_in11_in => p_1_in11_in,
+ p_1_in14_in => p_1_in14_in,
+ p_1_in17_in => p_1_in17_in,
+ p_1_in2_in => p_1_in2_in,
+ p_1_in5_in => p_1_in5_in,
+ p_1_in8_in => p_1_in8_in,
+ reset_trig0 => reset_trig0,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(0) => s_axi_bresp(0),
+ s_axi_bvalid_i_reg_0 => s_axi_bvalid_i_reg,
+ s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
+ \s_axi_rdata_i[0]_i_2_0\(0) => \s_axi_rdata_i[0]_i_2\(0),
+ \s_axi_rdata_i[0]_i_2_1\ => \s_axi_rdata_i[0]_i_2_0\,
+ \s_axi_rdata_i[1]_i_2_0\ => \s_axi_rdata_i[1]_i_2\,
+ \s_axi_rdata_i[2]_i_2_0\ => \s_axi_rdata_i[2]_i_2\,
+ \s_axi_rdata_i[3]_i_2_0\(3 downto 0) => \s_axi_rdata_i[3]_i_2\(3 downto 0),
+ \s_axi_rdata_i[3]_i_2_1\ => \s_axi_rdata_i[3]_i_2_0\,
+ \s_axi_rdata_i[7]_i_8_0\(5 downto 0) => \s_axi_rdata_i[7]_i_8\(5 downto 0),
+ \s_axi_rdata_i[7]_i_8_1\(4 downto 0) => \s_axi_rdata_i[7]_i_8_0\(4 downto 0),
+ \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
+ \s_axi_rdata_i_reg[1]_0\ => \s_axi_rdata_i_reg[1]\,
+ \s_axi_rdata_i_reg[2]_0\ => \s_axi_rdata_i_reg[2]\,
+ \s_axi_rdata_i_reg[3]_0\ => \s_axi_rdata_i_reg[3]\,
+ \s_axi_rdata_i_reg[4]_i_2_0\ => \s_axi_rdata_i_reg[4]_i_2\,
+ \s_axi_rdata_i_reg[5]_i_2_0\ => \s_axi_rdata_i_reg[5]_i_2\,
+ \s_axi_rdata_i_reg[6]_i_2_0\ => \s_axi_rdata_i_reg[6]_i_2\,
+ \s_axi_rdata_i_reg[7]_0\(7 downto 0) => \s_axi_rdata_i_reg[7]\(7 downto 0),
+ \s_axi_rdata_i_reg[7]_i_2_0\ => \s_axi_rdata_i_reg[7]_i_2\,
+ \s_axi_rdata_i_reg[7]_i_6_0\(5 downto 0) => \s_axi_rdata_i_reg[7]_i_6\(5 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_1\(5 downto 0) => \s_axi_rdata_i_reg[7]_i_6_0\(5 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_2\(4 downto 0) => \s_axi_rdata_i_reg[7]_i_6_1\(4 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_3\(3 downto 0) => \s_axi_rdata_i_reg[7]_i_6_2\(3 downto 0),
+ \s_axi_rdata_i_reg[7]_i_7_0\(7 downto 0) => \s_axi_rdata_i_reg[7]_i_7\(7 downto 0),
+ \s_axi_rdata_i_reg[7]_i_7_1\(7 downto 0) => \s_axi_rdata_i_reg[7]_i_7_0\(7 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(0) => s_axi_rresp(0),
+ s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
+ s_axi_wdata(5 downto 0) => s_axi_wdata(5 downto 0),
+ \s_axi_wdata[31]\ => \s_axi_wdata[31]\,
+ \s_axi_wdata[5]\(1 downto 0) => \s_axi_wdata[5]\(1 downto 0),
+ s_axi_wdata_0_sp_1 => s_axi_wdata_0_sn_1,
+ s_axi_wvalid => s_axi_wvalid,
+ sw_rst_cond => sw_rst_cond,
+ sw_rst_cond_d1 => sw_rst_cond_d1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_filter is
+ port (
+ scl_rising_edge0 : out STD_LOGIC;
+ scndry_out : out STD_LOGIC;
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : out STD_LOGIC;
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : out STD_LOGIC;
+ scl_rin_d1 : in STD_LOGIC;
+ sda_rin_d1 : in STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ sda_i : in STD_LOGIC
+ );
+end TopLevel_axi_iic_0_0_filter;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_filter is
+begin
+SCL_DEBOUNCE: entity work.TopLevel_axi_iic_0_0_debounce
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ scl_i => scl_i,
+ scl_rin_d1 => scl_rin_d1,
+ scl_rising_edge0 => scl_rising_edge0,
+ scndry_out => scndry_out
+ );
+SDA_DEBOUNCE: entity work.TopLevel_axi_iic_0_0_debounce_3
+ port map (
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\,
+ s_axi_aclk => s_axi_aclk,
+ sda_i => sda_i,
+ sda_rin_d1 => sda_rin_d1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_axi_ipif_ssp1 is
+ port (
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ Bus2IIC_Reset : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ s_axi_rvalid_i_reg : out STD_LOGIC;
+ s_axi_bvalid_i_reg : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ is_write_reg : out STD_LOGIC;
+ is_read_reg : out STD_LOGIC;
+ ctrlFifoDin : out STD_LOGIC_VECTOR ( 0 to 1 );
+ \s_axi_wdata[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \bus2ip_addr_i_reg[3]\ : out STD_LOGIC;
+ Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ iic2intc_irpt : out STD_LOGIC;
+ s_axi_wdata_0_sp_1 : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
+ \s_axi_rdata_i_reg[7]_i_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_7_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ Tx_fifo_data : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \s_axi_rdata_i[7]_i_8_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i[0]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ Tx_fifo_rst : in STD_LOGIC;
+ \cr_i_reg[2]\ : in STD_LOGIC;
+ firstDynStartSeen : in STD_LOGIC;
+ \cr_i_reg[2]_0\ : in STD_LOGIC;
+ Rc_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \s_axi_rdata_i_reg[7]_i_6_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ \s_axi_rdata_i_reg[1]\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[4]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[5]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[6]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_2\ : in STD_LOGIC;
+ cr_txModeSelect_set : in STD_LOGIC;
+ cr_txModeSelect_clr : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ \s_axi_rdata_i_reg[7]_i_6_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i_reg[3]\ : in STD_LOGIC;
+ Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
+ \s_axi_rdata_i[3]_i_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_axi_rdata_i[3]_i_2_0\ : in STD_LOGIC;
+ \s_axi_rdata_i_reg[2]\ : in STD_LOGIC;
+ \s_axi_rdata_i[2]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i[1]_i_2\ : in STD_LOGIC;
+ \s_axi_rdata_i[0]_i_2_0\ : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ gpo : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 1 downto 0 )
+ );
+end TopLevel_axi_iic_0_0_axi_ipif_ssp1;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_axi_ipif_ssp1 is
+ signal AXI_Bus2IP_Reset : STD_LOGIC;
+ signal AXI_Bus2IP_WrCE : STD_LOGIC_VECTOR ( 10 to 10 );
+ signal AXI_IP2Bus_RdAck1 : STD_LOGIC;
+ signal AXI_IP2Bus_RdAck2 : STD_LOGIC;
+ signal AXI_IP2Bus_RdAck20 : STD_LOGIC;
+ signal AXI_IP2Bus_WrAck1 : STD_LOGIC;
+ signal AXI_IP2Bus_WrAck2 : STD_LOGIC;
+ signal AXI_IP2Bus_WrAck20 : STD_LOGIC;
+ signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
+ signal \^bus2iic_reset\ : STD_LOGIC;
+ signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
+ signal \I_SLAVE_ATTACHMENT/I_DECODER/p_27_in\ : STD_LOGIC;
+ signal X_INTERRUPT_CONTROL_n_0 : STD_LOGIC;
+ signal X_INTERRUPT_CONTROL_n_17 : STD_LOGIC;
+ signal ipif_glbl_irpt_enable_reg : STD_LOGIC;
+ signal irpt_wrack : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal p_0_in10_in : STD_LOGIC;
+ signal p_0_in13_in : STD_LOGIC;
+ signal p_0_in16_in : STD_LOGIC;
+ signal p_0_in1_in : STD_LOGIC;
+ signal p_0_in4_in : STD_LOGIC;
+ signal p_0_in7_in : STD_LOGIC;
+ signal p_1_in : STD_LOGIC;
+ signal p_1_in11_in : STD_LOGIC;
+ signal p_1_in14_in : STD_LOGIC;
+ signal p_1_in17_in : STD_LOGIC;
+ signal p_1_in2_in : STD_LOGIC;
+ signal p_1_in5_in : STD_LOGIC;
+ signal p_1_in8_in : STD_LOGIC;
+ signal reset_trig0 : STD_LOGIC;
+ signal s_axi_wdata_0_sn_1 : STD_LOGIC;
+ signal sw_rst_cond : STD_LOGIC;
+ signal sw_rst_cond_d1 : STD_LOGIC;
+begin
+ Bus2IIC_Reset <= \^bus2iic_reset\;
+ s_axi_wdata_0_sp_1 <= s_axi_wdata_0_sn_1;
+AXI_IP2Bus_RdAck1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AXI_IP2Bus_RdAck2,
+ Q => AXI_IP2Bus_RdAck1,
+ R => '0'
+ );
+AXI_IP2Bus_RdAck2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AXI_IP2Bus_RdAck20,
+ Q => AXI_IP2Bus_RdAck2,
+ R => '0'
+ );
+AXI_IP2Bus_WrAck1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AXI_IP2Bus_WrAck2,
+ Q => AXI_IP2Bus_WrAck1,
+ R => '0'
+ );
+AXI_IP2Bus_WrAck2_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => AXI_IP2Bus_WrAck20,
+ Q => AXI_IP2Bus_WrAck2,
+ R => '0'
+ );
+AXI_LITE_IPIF_I: entity work.TopLevel_axi_iic_0_0_axi_lite_ipif
+ port map (
+ AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
+ AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
+ AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
+ AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
+ AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
+ AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
+ AXI_IP2Bus_WrAck20 => AXI_IP2Bus_WrAck20,
+ Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
+ Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
+ Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
+ D(1 downto 0) => D(1 downto 0),
+ E(0) => AXI_Bus2IP_WrCE(10),
+ Q(4 downto 0) => Q(4 downto 0),
+ Rc_addr(1 downto 0) => Rc_addr(1 downto 0),
+ Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
+ Tx_addr(0 to 3) => Tx_addr(0 to 3),
+ Tx_fifo_data(5 downto 0) => Tx_fifo_data(5 downto 0),
+ \bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
+ \cr_i_reg[2]\ => \cr_i_reg[2]\,
+ \cr_i_reg[2]_0\ => \cr_i_reg[2]_0\,
+ cr_txModeSelect_clr => cr_txModeSelect_clr,
+ cr_txModeSelect_set => cr_txModeSelect_set,
+ firstDynStartSeen => firstDynStartSeen,
+ gpo(0) => gpo(0),
+ ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
+ irpt_wrack => irpt_wrack,
+ is_read_reg => is_read_reg,
+ is_write_reg => is_write_reg,
+ p_1_in => p_1_in,
+ p_1_in11_in => p_1_in11_in,
+ p_1_in14_in => p_1_in14_in,
+ p_1_in17_in => p_1_in17_in,
+ p_1_in2_in => p_1_in2_in,
+ p_1_in5_in => p_1_in5_in,
+ p_1_in8_in => p_1_in8_in,
+ p_27_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_27_in\,
+ reset_trig0 => reset_trig0,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(0) => s_axi_bresp(0),
+ s_axi_bvalid_i_reg => s_axi_bvalid_i_reg,
+ s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
+ \s_axi_rdata_i[0]_i_2\(0) => \s_axi_rdata_i[0]_i_2\(0),
+ \s_axi_rdata_i[0]_i_2_0\ => \s_axi_rdata_i[0]_i_2_0\,
+ \s_axi_rdata_i[1]_i_2\ => \s_axi_rdata_i[1]_i_2\,
+ \s_axi_rdata_i[2]_i_2\ => \s_axi_rdata_i[2]_i_2\,
+ \s_axi_rdata_i[3]_i_2\(3 downto 0) => \s_axi_rdata_i[3]_i_2\(3 downto 0),
+ \s_axi_rdata_i[3]_i_2_0\ => \s_axi_rdata_i[3]_i_2_0\,
+ \s_axi_rdata_i[7]_i_8\(5 downto 0) => \s_axi_rdata_i[7]_i_8\(5 downto 0),
+ \s_axi_rdata_i[7]_i_8_0\(4 downto 0) => \s_axi_rdata_i[7]_i_8_0\(4 downto 0),
+ \s_axi_rdata_i_reg[0]\ => X_INTERRUPT_CONTROL_n_0,
+ \s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\,
+ \s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\,
+ \s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\,
+ \s_axi_rdata_i_reg[4]_i_2\ => \s_axi_rdata_i_reg[4]_i_2\,
+ \s_axi_rdata_i_reg[5]_i_2\ => \s_axi_rdata_i_reg[5]_i_2\,
+ \s_axi_rdata_i_reg[6]_i_2\ => \s_axi_rdata_i_reg[6]_i_2\,
+ \s_axi_rdata_i_reg[7]\(7) => p_0_in16_in,
+ \s_axi_rdata_i_reg[7]\(6) => p_0_in13_in,
+ \s_axi_rdata_i_reg[7]\(5) => p_0_in10_in,
+ \s_axi_rdata_i_reg[7]\(4) => p_0_in7_in,
+ \s_axi_rdata_i_reg[7]\(3) => p_0_in4_in,
+ \s_axi_rdata_i_reg[7]\(2) => p_0_in1_in,
+ \s_axi_rdata_i_reg[7]\(1) => p_0_in,
+ \s_axi_rdata_i_reg[7]\(0) => X_INTERRUPT_CONTROL_n_17,
+ \s_axi_rdata_i_reg[7]_i_2\ => \s_axi_rdata_i_reg[7]_i_2\,
+ \s_axi_rdata_i_reg[7]_i_6\(5 downto 0) => \s_axi_rdata_i_reg[7]_i_6\(5 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_0\(5 downto 0) => \s_axi_rdata_i_reg[7]_i_6_0\(5 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_1\(4 downto 0) => \s_axi_rdata_i_reg[7]_i_6_1\(4 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_2\(3 downto 0) => \s_axi_rdata_i_reg[7]_i_6_2\(3 downto 0),
+ \s_axi_rdata_i_reg[7]_i_7\(7 downto 0) => \s_axi_rdata_i_reg[7]_i_7\(7 downto 0),
+ \s_axi_rdata_i_reg[7]_i_7_0\(7 downto 0) => \s_axi_rdata_i_reg[7]_i_7_0\(7 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(0) => s_axi_rresp(0),
+ s_axi_rvalid_i_reg => s_axi_rvalid_i_reg,
+ s_axi_wdata(5) => s_axi_wdata(10),
+ s_axi_wdata(4) => s_axi_wdata(5),
+ s_axi_wdata(3 downto 0) => s_axi_wdata(3 downto 0),
+ \s_axi_wdata[31]\ => AXI_LITE_IPIF_I_n_33,
+ \s_axi_wdata[5]\(1 downto 0) => \s_axi_wdata[5]\(1 downto 0),
+ s_axi_wdata_0_sp_1 => s_axi_wdata_0_sn_1,
+ s_axi_wvalid => s_axi_wvalid,
+ sw_rst_cond => sw_rst_cond,
+ sw_rst_cond_d1 => sw_rst_cond_d1
+ );
+X_INTERRUPT_CONTROL: entity work.TopLevel_axi_iic_0_0_interrupt_control
+ port map (
+ Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
+ E(0) => AXI_Bus2IP_WrCE(10),
+ \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => X_INTERRUPT_CONTROL_n_0,
+ IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
+ Q(7) => p_0_in16_in,
+ Q(6) => p_0_in13_in,
+ Q(5) => p_0_in10_in,
+ Q(4) => p_0_in7_in,
+ Q(3) => p_0_in4_in,
+ Q(2) => p_0_in1_in,
+ Q(1) => p_0_in,
+ Q(0) => X_INTERRUPT_CONTROL_n_17,
+ SR(0) => \^bus2iic_reset\,
+ iic2intc_irpt => iic2intc_irpt,
+ ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
+ ipif_glbl_irpt_enable_reg_reg_0 => AXI_LITE_IPIF_I_n_33,
+ irpt_wrack => irpt_wrack,
+ p_1_in => p_1_in,
+ p_1_in11_in => p_1_in11_in,
+ p_1_in14_in => p_1_in14_in,
+ p_1_in17_in => p_1_in17_in,
+ p_1_in2_in => p_1_in2_in,
+ p_1_in5_in => p_1_in5_in,
+ p_1_in8_in => p_1_in8_in,
+ p_27_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_27_in\,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
+ );
+X_SOFT_RESET: entity work.TopLevel_axi_iic_0_0_soft_reset
+ port map (
+ AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
+ SR(0) => \^bus2iic_reset\,
+ Tx_fifo_rst => Tx_fifo_rst,
+ ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
+ reset_trig0 => reset_trig0,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_wdata(1 downto 0) => s_axi_wdata(9 downto 8),
+ sw_rst_cond => sw_rst_cond,
+ sw_rst_cond_d1 => sw_rst_cond_d1
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_iic is
+ port (
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ is_write_reg : out STD_LOGIC;
+ is_read_reg : out STD_LOGIC;
+ sda_t : out STD_LOGIC;
+ s_axi_rvalid_i_reg : out STD_LOGIC;
+ s_axi_bvalid_i_reg : out STD_LOGIC;
+ iic2intc_irpt : out STD_LOGIC;
+ gpo : out STD_LOGIC_VECTOR ( 0 to 0 );
+ scl_t : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ scl_i : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 )
+ );
+end TopLevel_axi_iic_0_0_iic;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_iic is
+ signal Aas : STD_LOGIC;
+ signal Abgc : STD_LOGIC;
+ signal Adr : STD_LOGIC_VECTOR ( 0 to 6 );
+ signal Al : STD_LOGIC;
+ signal Bb : STD_LOGIC;
+ signal Bus2IIC_Addr : STD_LOGIC_VECTOR ( 2 to 6 );
+ signal Bus2IIC_RdCE : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal Bus2IIC_Reset : STD_LOGIC;
+ signal Bus2IIC_WrCE : STD_LOGIC_VECTOR ( 0 to 17 );
+ signal \CLKCNT/q_int_reg\ : STD_LOGIC_VECTOR ( 0 to 9 );
+ signal Cr : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal D : STD_LOGIC;
+ signal DYN_MASTER_I_n_5 : STD_LOGIC;
+ signal DYN_MASTER_I_n_6 : STD_LOGIC;
+ signal D_0 : STD_LOGIC;
+ signal Data_i2c : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal FILTER_I_n_2 : STD_LOGIC;
+ signal IIC2Bus_Data : STD_LOGIC_VECTOR ( 22 to 23 );
+ signal IIC2Bus_IntrEvent : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal IIC_CONTROL_I_n_31 : STD_LOGIC;
+ signal IIC_CONTROL_I_n_43 : STD_LOGIC;
+ signal IIC_CONTROL_I_n_44 : STD_LOGIC;
+ signal Msms_set : STD_LOGIC;
+ signal New_rcv_dta : STD_LOGIC;
+ signal READ_FIFO_I_n_13 : STD_LOGIC;
+ signal READ_FIFO_I_n_16 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_100 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_101 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_102 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_103 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_104 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_105 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_107 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_110 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_111 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_112 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_113 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_114 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_115 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_126 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_127 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_128 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_129 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_130 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_131 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_132 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_133 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_135 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_136 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_25 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_26 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_27 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_28 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_37 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_38 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_39 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_40 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_49 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_50 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_51 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_52 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_59 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_60 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_61 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_62 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_69 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_70 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_71 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_72 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_73 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_74 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_75 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_76 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_82 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_83 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_84 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_85 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_91 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_92 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_93 : STD_LOGIC;
+ signal REG_INTERFACE_I_n_94 : STD_LOGIC;
+ signal Rc_Data_Exists : STD_LOGIC;
+ signal Rc_addr : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal Rc_fifo_data : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal Rc_fifo_full : STD_LOGIC;
+ signal Rc_fifo_rd : STD_LOGIC;
+ signal Rc_fifo_rd_d : STD_LOGIC;
+ signal Rc_fifo_wr : STD_LOGIC;
+ signal Rc_fifo_wr_d : STD_LOGIC;
+ signal Rdy_new_xmt : STD_LOGIC;
+ signal Ro_prev : STD_LOGIC;
+ signal \SETUP_CNT/q_int_reg\ : STD_LOGIC_VECTOR ( 0 to 9 );
+ signal Srw : STD_LOGIC;
+ signal Timing_param_tbuf : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Timing_param_thdsta : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Timing_param_thigh : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Timing_param_tlow : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Timing_param_tsudat : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal Timing_param_tsusta : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Timing_param_tsusto : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal Tx_addr : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal Tx_data_exists : STD_LOGIC;
+ signal Tx_fifo_data : STD_LOGIC_VECTOR ( 0 to 7 );
+ signal Tx_fifo_full : STD_LOGIC;
+ signal Tx_fifo_rd : STD_LOGIC;
+ signal Tx_fifo_rd_d : STD_LOGIC;
+ signal Tx_fifo_rst : STD_LOGIC;
+ signal Tx_fifo_wr : STD_LOGIC;
+ signal Tx_fifo_wr_d : STD_LOGIC;
+ signal Tx_under_prev : STD_LOGIC;
+ signal Txer : STD_LOGIC;
+ signal WRITE_FIFO_CTRL_I_n_0 : STD_LOGIC;
+ signal WRITE_FIFO_CTRL_I_n_3 : STD_LOGIC;
+ signal WRITE_FIFO_CTRL_I_n_4 : STD_LOGIC;
+ signal WRITE_FIFO_I_n_14 : STD_LOGIC;
+ signal WRITE_FIFO_I_n_16 : STD_LOGIC;
+ signal X_AXI_IPIF_SSP1_n_14 : STD_LOGIC;
+ signal X_AXI_IPIF_SSP1_n_15 : STD_LOGIC;
+ signal X_AXI_IPIF_SSP1_n_28 : STD_LOGIC;
+ signal X_AXI_IPIF_SSP1_n_31 : STD_LOGIC;
+ signal ackDataState : STD_LOGIC;
+ signal clk_cnt_en1 : STD_LOGIC;
+ signal clk_cnt_en11_out : STD_LOGIC;
+ signal clk_cnt_en12_out : STD_LOGIC;
+ signal cr_txModeSelect_clr : STD_LOGIC;
+ signal cr_txModeSelect_set : STD_LOGIC;
+ signal ctrlFifoDin : STD_LOGIC_VECTOR ( 0 to 1 );
+ signal dynamic_MSMS : STD_LOGIC_VECTOR ( 0 to 1 );
+ signal earlyAckDataState : STD_LOGIC;
+ signal earlyAckHdr : STD_LOGIC;
+ signal firstDynStartSeen : STD_LOGIC;
+ signal \^gpo\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal new_rcv_dta_d1 : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal p_1_in : STD_LOGIC;
+ signal p_1_in4_in : STD_LOGIC;
+ signal p_1_in6_in : STD_LOGIC;
+ signal \p_1_in__0\ : STD_LOGIC;
+ signal p_1_out : STD_LOGIC_VECTOR ( 6 to 6 );
+ signal \p_2_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal p_3_in : STD_LOGIC;
+ signal p_6_out : STD_LOGIC;
+ signal rdCntrFrmTxFifo : STD_LOGIC;
+ signal rxCntDone : STD_LOGIC;
+ signal scl_clean : STD_LOGIC;
+ signal scl_rin_d1 : STD_LOGIC;
+ signal scl_rising_edge0 : STD_LOGIC;
+ signal sda_clean : STD_LOGIC;
+ signal sda_rin_d1 : STD_LOGIC;
+ signal shift_reg_ld : STD_LOGIC;
+ signal sr_i : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal stop_scl_reg : STD_LOGIC;
+begin
+ gpo(0) <= \^gpo\(0);
+DYN_MASTER_I: entity work.TopLevel_axi_iic_0_0_dynamic_master
+ port map (
+ Tx_data_exists => Tx_data_exists,
+ Tx_fifo_data(0 to 7) => Tx_fifo_data(0 to 7),
+ Tx_fifo_rd => Tx_fifo_rd,
+ Tx_fifo_rd_d => Tx_fifo_rd_d,
+ Tx_fifo_rst => Tx_fifo_rst,
+ ackDataState => ackDataState,
+ cr_txModeSelect_clr => cr_txModeSelect_clr,
+ cr_txModeSelect_set => cr_txModeSelect_set,
+ earlyAckDataState => earlyAckDataState,
+ earlyAckHdr => earlyAckHdr,
+ firstDynStartSeen => firstDynStartSeen,
+ firstDynStartSeen_reg_0 => REG_INTERFACE_I_n_105,
+ p_3_in => p_3_in,
+ \rdByteCntr_reg[2]_0\ => DYN_MASTER_I_n_5,
+ rdCntrFrmTxFifo => rdCntrFrmTxFifo,
+ rdCntrFrmTxFifo_reg_0 => DYN_MASTER_I_n_6,
+ rxCntDone => rxCntDone,
+ s_axi_aclk => s_axi_aclk
+ );
+FILTER_I: entity work.TopLevel_axi_iic_0_0_filter
+ port map (
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => FILTER_I_n_2,
+ \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => sda_clean,
+ s_axi_aclk => s_axi_aclk,
+ scl_i => scl_i,
+ scl_rin_d1 => scl_rin_d1,
+ scl_rising_edge0 => scl_rising_edge0,
+ scndry_out => scl_clean,
+ sda_i => sda_i,
+ sda_rin_d1 => sda_rin_d1
+ );
+IIC_CONTROL_I: entity work.TopLevel_axi_iic_0_0_iic_control
+ port map (
+ Aas => Aas,
+ Bb => Bb,
+ CO(0) => clk_cnt_en1,
+ D(3) => Al,
+ D(2) => Txer,
+ D(1) => \p_1_in__0\,
+ D(0) => p_0_out(0),
+ E(0) => Bus2IIC_WrCE(0),
+ \FSM_sequential_scl_state[0]_i_6_0\(3) => REG_INTERFACE_I_n_69,
+ \FSM_sequential_scl_state[0]_i_6_0\(2) => REG_INTERFACE_I_n_70,
+ \FSM_sequential_scl_state[0]_i_6_0\(1) => REG_INTERFACE_I_n_71,
+ \FSM_sequential_scl_state[0]_i_6_0\(0) => REG_INTERFACE_I_n_72,
+ \FSM_sequential_scl_state[1]_i_2_0\(3) => REG_INTERFACE_I_n_82,
+ \FSM_sequential_scl_state[1]_i_2_0\(2) => REG_INTERFACE_I_n_83,
+ \FSM_sequential_scl_state[1]_i_2_0\(1) => REG_INTERFACE_I_n_84,
+ \FSM_sequential_scl_state[1]_i_2_0\(0) => REG_INTERFACE_I_n_85,
+ \FSM_sequential_scl_state[3]_i_4\(3) => REG_INTERFACE_I_n_37,
+ \FSM_sequential_scl_state[3]_i_4\(2) => REG_INTERFACE_I_n_38,
+ \FSM_sequential_scl_state[3]_i_4\(1) => REG_INTERFACE_I_n_39,
+ \FSM_sequential_scl_state[3]_i_4\(0) => REG_INTERFACE_I_n_40,
+ \FSM_sequential_scl_state[3]_i_4_0\(3) => REG_INTERFACE_I_n_49,
+ \FSM_sequential_scl_state[3]_i_4_0\(2) => REG_INTERFACE_I_n_50,
+ \FSM_sequential_scl_state[3]_i_4_0\(1) => REG_INTERFACE_I_n_51,
+ \FSM_sequential_scl_state[3]_i_4_0\(0) => REG_INTERFACE_I_n_52,
+ \FSM_sequential_scl_state_reg[1]_0\ => IIC_CONTROL_I_n_31,
+ \FSM_sequential_scl_state_reg[2]_0\ => IIC_CONTROL_I_n_43,
+ \FSM_sequential_scl_state_reg[2]_1\(3) => REG_INTERFACE_I_n_73,
+ \FSM_sequential_scl_state_reg[2]_1\(2) => REG_INTERFACE_I_n_74,
+ \FSM_sequential_scl_state_reg[2]_1\(1) => REG_INTERFACE_I_n_75,
+ \FSM_sequential_scl_state_reg[2]_1\(0) => REG_INTERFACE_I_n_76,
+ \FSM_sequential_scl_state_reg[3]_0\(3) => REG_INTERFACE_I_n_59,
+ \FSM_sequential_scl_state_reg[3]_0\(2) => REG_INTERFACE_I_n_60,
+ \FSM_sequential_scl_state_reg[3]_0\(1) => REG_INTERFACE_I_n_61,
+ \FSM_sequential_scl_state_reg[3]_0\(0) => REG_INTERFACE_I_n_62,
+ \LEVEL_1_GEN.master_sda_reg_0\ => REG_INTERFACE_I_n_102,
+ Msms_set => Msms_set,
+ New_rcv_dta => New_rcv_dta,
+ Q(4) => Cr(1),
+ Q(3) => Cr(2),
+ Q(2) => Cr(4),
+ Q(1) => Cr(5),
+ Q(0) => Cr(7),
+ Rdy_new_xmt => Rdy_new_xmt,
+ Ro_prev => Ro_prev,
+ S(3) => REG_INTERFACE_I_n_25,
+ S(2) => REG_INTERFACE_I_n_26,
+ S(1) => REG_INTERFACE_I_n_27,
+ S(0) => REG_INTERFACE_I_n_28,
+ Tx_data_exists => Tx_data_exists,
+ Tx_fifo_data(6) => Tx_fifo_data(0),
+ Tx_fifo_data(5) => Tx_fifo_data(1),
+ Tx_fifo_data(4) => Tx_fifo_data(2),
+ Tx_fifo_data(3) => Tx_fifo_data(3),
+ Tx_fifo_data(2) => Tx_fifo_data(4),
+ Tx_fifo_data(1) => Tx_fifo_data(5),
+ Tx_fifo_data(0) => Tx_fifo_data(6),
+ Tx_under_prev => Tx_under_prev,
+ aas_i_reg_0(6) => Adr(0),
+ aas_i_reg_0(5) => Adr(1),
+ aas_i_reg_0(4) => Adr(2),
+ aas_i_reg_0(3) => Adr(3),
+ aas_i_reg_0(2) => Adr(4),
+ aas_i_reg_0(1) => Adr(5),
+ aas_i_reg_0(0) => Adr(6),
+ ackDataState => ackDataState,
+ \cr_i_reg[5]\ => WRITE_FIFO_I_n_16,
+ \cr_i_reg[5]_0\ => REG_INTERFACE_I_n_107,
+ \data_i2c_i_reg[7]_0\(7) => Data_i2c(0),
+ \data_i2c_i_reg[7]_0\(6) => Data_i2c(1),
+ \data_i2c_i_reg[7]_0\(5) => Data_i2c(2),
+ \data_i2c_i_reg[7]_0\(4) => Data_i2c(3),
+ \data_i2c_i_reg[7]_0\(3) => Data_i2c(4),
+ \data_i2c_i_reg[7]_0\(2) => Data_i2c(5),
+ \data_i2c_i_reg[7]_0\(1) => Data_i2c(6),
+ \data_i2c_i_reg[7]_0\(0) => Data_i2c(7),
+ \data_int_reg[0]\ => sda_clean,
+ \data_int_reg[0]_0\(0) => \p_2_in__0\(0),
+ detect_stop_b_reg_0 => FILTER_I_n_2,
+ dynamic_MSMS(0) => dynamic_MSMS(0),
+ earlyAckDataState => earlyAckDataState,
+ earlyAckHdr => earlyAckHdr,
+ new_rcv_dta_d1 => new_rcv_dta_d1,
+ p_6_out => p_6_out,
+ \q_int_reg[0]\(9) => \SETUP_CNT/q_int_reg\(0),
+ \q_int_reg[0]\(8) => \SETUP_CNT/q_int_reg\(1),
+ \q_int_reg[0]\(7) => \SETUP_CNT/q_int_reg\(2),
+ \q_int_reg[0]\(6) => \SETUP_CNT/q_int_reg\(3),
+ \q_int_reg[0]\(5) => \SETUP_CNT/q_int_reg\(4),
+ \q_int_reg[0]\(4) => \SETUP_CNT/q_int_reg\(5),
+ \q_int_reg[0]\(3) => \SETUP_CNT/q_int_reg\(6),
+ \q_int_reg[0]\(2) => \SETUP_CNT/q_int_reg\(7),
+ \q_int_reg[0]\(1) => \SETUP_CNT/q_int_reg\(8),
+ \q_int_reg[0]\(0) => \SETUP_CNT/q_int_reg\(9),
+ \q_int_reg[0]_0\(9) => \CLKCNT/q_int_reg\(0),
+ \q_int_reg[0]_0\(8) => \CLKCNT/q_int_reg\(1),
+ \q_int_reg[0]_0\(7) => \CLKCNT/q_int_reg\(2),
+ \q_int_reg[0]_0\(6) => \CLKCNT/q_int_reg\(3),
+ \q_int_reg[0]_0\(5) => \CLKCNT/q_int_reg\(4),
+ \q_int_reg[0]_0\(4) => \CLKCNT/q_int_reg\(5),
+ \q_int_reg[0]_0\(3) => \CLKCNT/q_int_reg\(6),
+ \q_int_reg[0]_0\(2) => \CLKCNT/q_int_reg\(7),
+ \q_int_reg[0]_0\(1) => \CLKCNT/q_int_reg\(8),
+ \q_int_reg[0]_0\(0) => \CLKCNT/q_int_reg\(9),
+ \q_int_reg[0]_1\ => REG_INTERFACE_I_n_101,
+ \q_int_reg[1]\ => REG_INTERFACE_I_n_103,
+ \q_int_reg[4]\ => REG_INTERFACE_I_n_104,
+ rxCntDone => rxCntDone,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_wdata(0) => s_axi_wdata(2),
+ \s_axi_wdata[2]\(0) => IIC_CONTROL_I_n_44,
+ scl_rin_d1 => scl_rin_d1,
+ scl_rising_edge0 => scl_rising_edge0,
+ scl_t => scl_t,
+ scndry_out => scl_clean,
+ sda_cout_reg_reg_0 => REG_INTERFACE_I_n_132,
+ sda_rin_d1 => sda_rin_d1,
+ sda_setup_reg_0(3) => REG_INTERFACE_I_n_91,
+ sda_setup_reg_0(2) => REG_INTERFACE_I_n_92,
+ sda_setup_reg_0(1) => REG_INTERFACE_I_n_93,
+ sda_setup_reg_0(0) => REG_INTERFACE_I_n_94,
+ sda_t => sda_t,
+ shift_reg_ld => shift_reg_ld,
+ sr_i(0) => sr_i(0),
+ srw_i_reg_0(1) => Srw,
+ srw_i_reg_0(0) => Abgc,
+ stop_scl_reg => stop_scl_reg,
+ \timing_param_tsusta_i_reg[9]\(0) => clk_cnt_en12_out,
+ \timing_param_tsusto_i_reg[9]\(0) => clk_cnt_en11_out
+ );
+READ_FIFO_I: entity work.TopLevel_axi_iic_0_0_SRL_FIFO
+ port map (
+ \Addr_Counters[0].FDRE_I_0\ => REG_INTERFACE_I_n_136,
+ \Addr_Counters[0].FDRE_I_1\ => REG_INTERFACE_I_n_135,
+ \Addr_Counters[1].FDRE_I_0\ => READ_FIFO_I_n_16,
+ Bus2IIC_Reset => Bus2IIC_Reset,
+ D(1) => p_1_out(6),
+ D(0) => Rc_fifo_full,
+ D_0 => D,
+ Msms_set => Msms_set,
+ Q(3) => p_1_in6_in,
+ Q(2) => p_1_in4_in,
+ Q(1) => p_1_in,
+ Q(0) => REG_INTERFACE_I_n_126,
+ Rc_Data_Exists => Rc_Data_Exists,
+ Rc_addr(0 to 3) => Rc_addr(0 to 3),
+ Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
+ Rc_fifo_rd => Rc_fifo_rd,
+ Rc_fifo_rd_d => Rc_fifo_rd_d,
+ Rc_fifo_wr => Rc_fifo_wr,
+ Rc_fifo_wr_d => Rc_fifo_wr_d,
+ msms_set_i_reg => READ_FIFO_I_n_13,
+ s_axi_aclk => s_axi_aclk,
+ \s_axi_rdata_i[7]_i_11\(7) => Data_i2c(0),
+ \s_axi_rdata_i[7]_i_11\(6) => Data_i2c(1),
+ \s_axi_rdata_i[7]_i_11\(5) => Data_i2c(2),
+ \s_axi_rdata_i[7]_i_11\(4) => Data_i2c(3),
+ \s_axi_rdata_i[7]_i_11\(3) => Data_i2c(4),
+ \s_axi_rdata_i[7]_i_11\(2) => Data_i2c(5),
+ \s_axi_rdata_i[7]_i_11\(1) => Data_i2c(6),
+ \s_axi_rdata_i[7]_i_11\(0) => Data_i2c(7)
+ );
+REG_INTERFACE_I: entity work.TopLevel_axi_iic_0_0_reg_interface
+ port map (
+ Aas => Aas,
+ Bus2IIC_RdCE(0) => Bus2IIC_RdCE(3),
+ Bus2IIC_Reset => Bus2IIC_Reset,
+ Bus2IIC_WrCE(11) => Bus2IIC_WrCE(0),
+ Bus2IIC_WrCE(10) => Bus2IIC_WrCE(2),
+ Bus2IIC_WrCE(9) => Bus2IIC_WrCE(4),
+ Bus2IIC_WrCE(8) => Bus2IIC_WrCE(8),
+ Bus2IIC_WrCE(7) => Bus2IIC_WrCE(10),
+ Bus2IIC_WrCE(6) => Bus2IIC_WrCE(11),
+ Bus2IIC_WrCE(5) => Bus2IIC_WrCE(12),
+ Bus2IIC_WrCE(4) => Bus2IIC_WrCE(13),
+ Bus2IIC_WrCE(3) => Bus2IIC_WrCE(14),
+ Bus2IIC_WrCE(2) => Bus2IIC_WrCE(15),
+ Bus2IIC_WrCE(1) => Bus2IIC_WrCE(16),
+ Bus2IIC_WrCE(0) => Bus2IIC_WrCE(17),
+ CO(0) => clk_cnt_en1,
+ D(0) => Ro_prev,
+ D_0 => D_0,
+ D_1 => D,
+ Data_Exists_DFF => WRITE_FIFO_CTRL_I_n_4,
+ Data_Exists_DFF_0 => WRITE_FIFO_CTRL_I_n_0,
+ Data_Exists_DFF_1 => READ_FIFO_I_n_16,
+ \FIFO_GEN_DTR.Tx_fifo_rd_reg_0\ => REG_INTERFACE_I_n_107,
+ \FIFO_GEN_DTR.Tx_fifo_wr_reg_0\ => REG_INTERFACE_I_n_133,
+ \GPO_GEN.gpo_i_reg[31]_0\ => REG_INTERFACE_I_n_131,
+ \GPO_GEN.gpo_i_reg[31]_1\ => X_AXI_IPIF_SSP1_n_31,
+ IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
+ \IIC2Bus_IntrEvent_reg[0]_0\(4) => Al,
+ \IIC2Bus_IntrEvent_reg[0]_0\(3) => Txer,
+ \IIC2Bus_IntrEvent_reg[0]_0\(2) => Tx_under_prev,
+ \IIC2Bus_IntrEvent_reg[0]_0\(1) => \p_1_in__0\,
+ \IIC2Bus_IntrEvent_reg[0]_0\(0) => p_0_out(0),
+ \IIC2Bus_IntrEvent_reg[5]_0\ => REG_INTERFACE_I_n_129,
+ \LEVEL_1_GEN.master_sda_reg\ => DYN_MASTER_I_n_5,
+ Msms_set => Msms_set,
+ New_rcv_dta => New_rcv_dta,
+ Q(6) => Cr(0),
+ Q(5) => Cr(1),
+ Q(4) => Cr(2),
+ Q(3) => Cr(3),
+ Q(2) => Cr(4),
+ Q(1) => Cr(5),
+ Q(0) => Cr(7),
+ \RD_FIFO_CNTRL.Rc_fifo_rd_reg_0\ => REG_INTERFACE_I_n_136,
+ \RD_FIFO_CNTRL.Rc_fifo_wr_reg_0\ => REG_INTERFACE_I_n_135,
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\(3) => p_1_in6_in,
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\(2) => p_1_in4_in,
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\(1) => p_1_in,
+ \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]_0\(0) => REG_INTERFACE_I_n_126,
+ \RD_FIFO_CNTRL.ro_prev_i_reg_0\ => READ_FIFO_I_n_13,
+ Rc_Data_Exists => Rc_Data_Exists,
+ Rc_addr(1) => Rc_addr(2),
+ Rc_addr(0) => Rc_addr(3),
+ Rc_fifo_rd => Rc_fifo_rd,
+ Rc_fifo_rd_d => Rc_fifo_rd_d,
+ Rc_fifo_wr => Rc_fifo_wr,
+ Rc_fifo_wr_d => Rc_fifo_wr_d,
+ Rdy_new_xmt => Rdy_new_xmt,
+ S(3) => REG_INTERFACE_I_n_25,
+ S(2) => REG_INTERFACE_I_n_26,
+ S(1) => REG_INTERFACE_I_n_27,
+ S(0) => REG_INTERFACE_I_n_28,
+ Tx_data_exists => Tx_data_exists,
+ Tx_fifo_data(1) => Tx_fifo_data(4),
+ Tx_fifo_data(0) => Tx_fifo_data(5),
+ Tx_fifo_rd => Tx_fifo_rd,
+ Tx_fifo_rd_d => Tx_fifo_rd_d,
+ Tx_fifo_rst => Tx_fifo_rst,
+ Tx_fifo_wr => Tx_fifo_wr,
+ Tx_fifo_wr_d => Tx_fifo_wr_d,
+ Tx_fifo_wr_d_reg => REG_INTERFACE_I_n_100,
+ \adr_i_reg[0]_0\(6) => Adr(0),
+ \adr_i_reg[0]_0\(5) => Adr(1),
+ \adr_i_reg[0]_0\(4) => Adr(2),
+ \adr_i_reg[0]_0\(3) => Adr(3),
+ \adr_i_reg[0]_0\(2) => Adr(4),
+ \adr_i_reg[0]_0\(1) => Adr(5),
+ \adr_i_reg[0]_0\(0) => Adr(6),
+ \adr_i_reg[6]_0\ => REG_INTERFACE_I_n_130,
+ \bus2ip_addr_i_reg[2]\(1) => IIC2Bus_Data(22),
+ \bus2ip_addr_i_reg[2]\(0) => IIC2Bus_Data(23),
+ \bus2ip_addr_i_reg[6]\ => REG_INTERFACE_I_n_115,
+ \bus2ip_addr_i_reg[6]_0\ => REG_INTERFACE_I_n_128,
+ \cr_i_reg[2]_0\ => REG_INTERFACE_I_n_104,
+ \cr_i_reg[2]_1\ => REG_INTERFACE_I_n_132,
+ \cr_i_reg[2]_2\(2) => X_AXI_IPIF_SSP1_n_14,
+ \cr_i_reg[2]_2\(1) => X_AXI_IPIF_SSP1_n_15,
+ \cr_i_reg[2]_2\(0) => IIC_CONTROL_I_n_44,
+ \cr_i_reg[3]_0\ => REG_INTERFACE_I_n_102,
+ \cr_i_reg[7]_0\ => REG_INTERFACE_I_n_101,
+ dynamic_MSMS(0) => dynamic_MSMS(1),
+ earlyAckDataState => earlyAckDataState,
+ firstDynStartSeen => firstDynStartSeen,
+ firstDynStartSeen_reg => REG_INTERFACE_I_n_105,
+ firstDynStartSeen_reg_0 => WRITE_FIFO_CTRL_I_n_3,
+ gpo(0) => \^gpo\(0),
+ new_rcv_dta_d1 => new_rcv_dta_d1,
+ \next_scl_state1_inferred__1/i__carry\(9) => \CLKCNT/q_int_reg\(0),
+ \next_scl_state1_inferred__1/i__carry\(8) => \CLKCNT/q_int_reg\(1),
+ \next_scl_state1_inferred__1/i__carry\(7) => \CLKCNT/q_int_reg\(2),
+ \next_scl_state1_inferred__1/i__carry\(6) => \CLKCNT/q_int_reg\(3),
+ \next_scl_state1_inferred__1/i__carry\(5) => \CLKCNT/q_int_reg\(4),
+ \next_scl_state1_inferred__1/i__carry\(4) => \CLKCNT/q_int_reg\(5),
+ \next_scl_state1_inferred__1/i__carry\(3) => \CLKCNT/q_int_reg\(6),
+ \next_scl_state1_inferred__1/i__carry\(2) => \CLKCNT/q_int_reg\(7),
+ \next_scl_state1_inferred__1/i__carry\(1) => \CLKCNT/q_int_reg\(8),
+ \next_scl_state1_inferred__1/i__carry\(0) => \CLKCNT/q_int_reg\(9),
+ p_0_in => p_0_in,
+ p_3_in => p_3_in,
+ p_6_out => p_6_out,
+ \q_int_reg[1]\(0) => clk_cnt_en11_out,
+ \q_int_reg[1]_0\(0) => clk_cnt_en12_out,
+ \q_int_reg[1]_1\ => IIC_CONTROL_I_n_31,
+ rdCntrFrmTxFifo => rdCntrFrmTxFifo,
+ s_axi_aclk => s_axi_aclk,
+ \s_axi_rdata_i[0]_i_7\(4) => Bus2IIC_Addr(2),
+ \s_axi_rdata_i[0]_i_7\(3) => Bus2IIC_Addr(3),
+ \s_axi_rdata_i[0]_i_7\(2) => Bus2IIC_Addr(4),
+ \s_axi_rdata_i[0]_i_7\(1) => Bus2IIC_Addr(5),
+ \s_axi_rdata_i[0]_i_7\(0) => Bus2IIC_Addr(6),
+ \s_axi_rdata_i_reg[8]\ => X_AXI_IPIF_SSP1_n_28,
+ s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
+ \sda_setup0_inferred__0/i__carry\(9) => \SETUP_CNT/q_int_reg\(0),
+ \sda_setup0_inferred__0/i__carry\(8) => \SETUP_CNT/q_int_reg\(1),
+ \sda_setup0_inferred__0/i__carry\(7) => \SETUP_CNT/q_int_reg\(2),
+ \sda_setup0_inferred__0/i__carry\(6) => \SETUP_CNT/q_int_reg\(3),
+ \sda_setup0_inferred__0/i__carry\(5) => \SETUP_CNT/q_int_reg\(4),
+ \sda_setup0_inferred__0/i__carry\(4) => \SETUP_CNT/q_int_reg\(5),
+ \sda_setup0_inferred__0/i__carry\(3) => \SETUP_CNT/q_int_reg\(6),
+ \sda_setup0_inferred__0/i__carry\(2) => \SETUP_CNT/q_int_reg\(7),
+ \sda_setup0_inferred__0/i__carry\(1) => \SETUP_CNT/q_int_reg\(8),
+ \sda_setup0_inferred__0/i__carry\(0) => \SETUP_CNT/q_int_reg\(9),
+ \sr_i_reg[0]_0\(0) => sr_i(0),
+ \sr_i_reg[0]_1\ => WRITE_FIFO_I_n_14,
+ \sr_i_reg[1]_0\(5) => p_1_out(6),
+ \sr_i_reg[1]_0\(4) => Rc_fifo_full,
+ \sr_i_reg[1]_0\(3) => Tx_fifo_full,
+ \sr_i_reg[1]_0\(2) => Srw,
+ \sr_i_reg[1]_0\(1) => Bb,
+ \sr_i_reg[1]_0\(0) => Abgc,
+ \sr_i_reg[4]_0\ => REG_INTERFACE_I_n_114,
+ \sr_i_reg[5]_0\ => REG_INTERFACE_I_n_127,
+ stop_scl_reg => stop_scl_reg,
+ stop_scl_reg_reg => REG_INTERFACE_I_n_103,
+ \timing_param_tbuf_i_reg[7]_0\(5 downto 2) => Timing_param_tbuf(7 downto 4),
+ \timing_param_tbuf_i_reg[7]_0\(1 downto 0) => Timing_param_tbuf(1 downto 0),
+ \timing_param_tbuf_i_reg[9]_0\(3) => REG_INTERFACE_I_n_59,
+ \timing_param_tbuf_i_reg[9]_0\(2) => REG_INTERFACE_I_n_60,
+ \timing_param_tbuf_i_reg[9]_0\(1) => REG_INTERFACE_I_n_61,
+ \timing_param_tbuf_i_reg[9]_0\(0) => REG_INTERFACE_I_n_62,
+ \timing_param_thddat_i_reg[9]_0\(3) => REG_INTERFACE_I_n_69,
+ \timing_param_thddat_i_reg[9]_0\(2) => REG_INTERFACE_I_n_70,
+ \timing_param_thddat_i_reg[9]_0\(1) => REG_INTERFACE_I_n_71,
+ \timing_param_thddat_i_reg[9]_0\(0) => REG_INTERFACE_I_n_72,
+ \timing_param_thdsta_i_reg[7]_0\(4 downto 1) => Timing_param_thdsta(7 downto 4),
+ \timing_param_thdsta_i_reg[7]_0\(0) => Timing_param_thdsta(0),
+ \timing_param_thdsta_i_reg[9]_0\(3) => REG_INTERFACE_I_n_73,
+ \timing_param_thdsta_i_reg[9]_0\(2) => REG_INTERFACE_I_n_74,
+ \timing_param_thdsta_i_reg[9]_0\(1) => REG_INTERFACE_I_n_75,
+ \timing_param_thdsta_i_reg[9]_0\(0) => REG_INTERFACE_I_n_76,
+ \timing_param_thigh_i_reg[7]_0\(7 downto 0) => Timing_param_thigh(7 downto 0),
+ \timing_param_tlow_i_reg[7]_0\(4 downto 1) => Timing_param_tlow(7 downto 4),
+ \timing_param_tlow_i_reg[7]_0\(0) => Timing_param_tlow(0),
+ \timing_param_tlow_i_reg[9]_0\(3) => REG_INTERFACE_I_n_82,
+ \timing_param_tlow_i_reg[9]_0\(2) => REG_INTERFACE_I_n_83,
+ \timing_param_tlow_i_reg[9]_0\(1) => REG_INTERFACE_I_n_84,
+ \timing_param_tlow_i_reg[9]_0\(0) => REG_INTERFACE_I_n_85,
+ \timing_param_tsudat_i_reg[3]_0\(3 downto 0) => Timing_param_tsudat(3 downto 0),
+ \timing_param_tsudat_i_reg[4]_0\ => REG_INTERFACE_I_n_110,
+ \timing_param_tsudat_i_reg[5]_0\ => REG_INTERFACE_I_n_111,
+ \timing_param_tsudat_i_reg[6]_0\ => REG_INTERFACE_I_n_112,
+ \timing_param_tsudat_i_reg[7]_0\ => REG_INTERFACE_I_n_113,
+ \timing_param_tsudat_i_reg[9]_0\(3) => REG_INTERFACE_I_n_91,
+ \timing_param_tsudat_i_reg[9]_0\(2) => REG_INTERFACE_I_n_92,
+ \timing_param_tsudat_i_reg[9]_0\(1) => REG_INTERFACE_I_n_93,
+ \timing_param_tsudat_i_reg[9]_0\(0) => REG_INTERFACE_I_n_94,
+ \timing_param_tsusta_i_reg[7]_0\(5 downto 2) => Timing_param_tsusta(7 downto 4),
+ \timing_param_tsusta_i_reg[7]_0\(1 downto 0) => Timing_param_tsusta(1 downto 0),
+ \timing_param_tsusta_i_reg[9]_0\(3) => REG_INTERFACE_I_n_49,
+ \timing_param_tsusta_i_reg[9]_0\(2) => REG_INTERFACE_I_n_50,
+ \timing_param_tsusta_i_reg[9]_0\(1) => REG_INTERFACE_I_n_51,
+ \timing_param_tsusta_i_reg[9]_0\(0) => REG_INTERFACE_I_n_52,
+ \timing_param_tsusto_i_reg[7]_0\(7 downto 0) => Timing_param_tsusto(7 downto 0),
+ \timing_param_tsusto_i_reg[9]_0\(3) => REG_INTERFACE_I_n_37,
+ \timing_param_tsusto_i_reg[9]_0\(2) => REG_INTERFACE_I_n_38,
+ \timing_param_tsusto_i_reg[9]_0\(1) => REG_INTERFACE_I_n_39,
+ \timing_param_tsusto_i_reg[9]_0\(0) => REG_INTERFACE_I_n_40
+ );
+Rc_fifo_rd_d_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Rc_fifo_rd,
+ Q => Rc_fifo_rd_d,
+ R => Bus2IIC_Reset
+ );
+Rc_fifo_wr_d_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Rc_fifo_wr,
+ Q => Rc_fifo_wr_d,
+ R => Bus2IIC_Reset
+ );
+Tx_fifo_rd_d_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Tx_fifo_rd,
+ Q => Tx_fifo_rd_d,
+ R => Bus2IIC_Reset
+ );
+Tx_fifo_wr_d_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => Tx_fifo_wr,
+ Q => Tx_fifo_wr_d,
+ R => Bus2IIC_Reset
+ );
+WRITE_FIFO_CTRL_I: entity work.\TopLevel_axi_iic_0_0_SRL_FIFO__parameterized0\
+ port map (
+ \Addr_Counters[0].FDRE_I_0\ => REG_INTERFACE_I_n_100,
+ \Addr_Counters[0].FDRE_I_1\ => DYN_MASTER_I_n_6,
+ \Addr_Counters[1].FDRE_I_0\ => WRITE_FIFO_CTRL_I_n_4,
+ D => D_0,
+ Data_Exists_DFF_0 => WRITE_FIFO_CTRL_I_n_0,
+ Data_Exists_DFF_1 => WRITE_FIFO_CTRL_I_n_3,
+ Tx_data_exists => Tx_data_exists,
+ Tx_fifo_rd => Tx_fifo_rd,
+ Tx_fifo_rd_d => Tx_fifo_rd_d,
+ Tx_fifo_rst => Tx_fifo_rst,
+ ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
+ dynamic_MSMS(0 to 1) => dynamic_MSMS(0 to 1),
+ rdCntrFrmTxFifo => rdCntrFrmTxFifo,
+ s_axi_aclk => s_axi_aclk
+ );
+WRITE_FIFO_I: entity work.TopLevel_axi_iic_0_0_SRL_FIFO_0
+ port map (
+ \Addr_Counters[0].FDRE_I_0\(0) => Tx_fifo_full,
+ \Addr_Counters[0].FDRE_I_1\ => REG_INTERFACE_I_n_133,
+ Data_Exists_DFF_0 => WRITE_FIFO_I_n_14,
+ Data_Exists_DFF_1 => WRITE_FIFO_I_n_16,
+ Data_Exists_DFF_2 => DYN_MASTER_I_n_6,
+ Tx_addr(0 to 3) => Tx_addr(0 to 3),
+ Tx_data_exists => Tx_data_exists,
+ Tx_fifo_data(0 to 7) => Tx_fifo_data(0 to 7),
+ Tx_fifo_rd => Tx_fifo_rd,
+ Tx_fifo_rd_d => Tx_fifo_rd_d,
+ Tx_fifo_rst => Tx_fifo_rst,
+ Tx_fifo_wr => Tx_fifo_wr,
+ Tx_fifo_wr_d => Tx_fifo_wr_d,
+ \data_int_reg[0]\ => sda_clean,
+ dynamic_MSMS(0) => dynamic_MSMS(1),
+ p_0_in => p_0_in,
+ rdCntrFrmTxFifo => rdCntrFrmTxFifo,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
+ shift_reg_ld => shift_reg_ld,
+ shift_reg_ld_reg(0) => \p_2_in__0\(0)
+ );
+X_AXI_IPIF_SSP1: entity work.TopLevel_axi_iic_0_0_axi_ipif_ssp1
+ port map (
+ Bus2IIC_RdCE(0) => Bus2IIC_RdCE(3),
+ Bus2IIC_Reset => Bus2IIC_Reset,
+ Bus2IIC_WrCE(11) => Bus2IIC_WrCE(0),
+ Bus2IIC_WrCE(10) => Bus2IIC_WrCE(2),
+ Bus2IIC_WrCE(9) => Bus2IIC_WrCE(4),
+ Bus2IIC_WrCE(8) => Bus2IIC_WrCE(8),
+ Bus2IIC_WrCE(7) => Bus2IIC_WrCE(10),
+ Bus2IIC_WrCE(6) => Bus2IIC_WrCE(11),
+ Bus2IIC_WrCE(5) => Bus2IIC_WrCE(12),
+ Bus2IIC_WrCE(4) => Bus2IIC_WrCE(13),
+ Bus2IIC_WrCE(3) => Bus2IIC_WrCE(14),
+ Bus2IIC_WrCE(2) => Bus2IIC_WrCE(15),
+ Bus2IIC_WrCE(1) => Bus2IIC_WrCE(16),
+ Bus2IIC_WrCE(0) => Bus2IIC_WrCE(17),
+ D(1) => IIC2Bus_Data(22),
+ D(0) => IIC2Bus_Data(23),
+ IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
+ Q(4) => Bus2IIC_Addr(2),
+ Q(3) => Bus2IIC_Addr(3),
+ Q(2) => Bus2IIC_Addr(4),
+ Q(1) => Bus2IIC_Addr(5),
+ Q(0) => Bus2IIC_Addr(6),
+ Rc_addr(1) => Rc_addr(0),
+ Rc_addr(0) => Rc_addr(1),
+ Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
+ Tx_addr(0 to 3) => Tx_addr(0 to 3),
+ Tx_fifo_data(5) => Tx_fifo_data(0),
+ Tx_fifo_data(4) => Tx_fifo_data(1),
+ Tx_fifo_data(3) => Tx_fifo_data(2),
+ Tx_fifo_data(2) => Tx_fifo_data(3),
+ Tx_fifo_data(1) => Tx_fifo_data(6),
+ Tx_fifo_data(0) => Tx_fifo_data(7),
+ Tx_fifo_rst => Tx_fifo_rst,
+ \bus2ip_addr_i_reg[3]\ => X_AXI_IPIF_SSP1_n_28,
+ \cr_i_reg[2]\ => IIC_CONTROL_I_n_43,
+ \cr_i_reg[2]_0\ => WRITE_FIFO_CTRL_I_n_3,
+ cr_txModeSelect_clr => cr_txModeSelect_clr,
+ cr_txModeSelect_set => cr_txModeSelect_set,
+ ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
+ firstDynStartSeen => firstDynStartSeen,
+ gpo(0) => \^gpo\(0),
+ iic2intc_irpt => iic2intc_irpt,
+ is_read_reg => is_read_reg,
+ is_write_reg => is_write_reg,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(0) => s_axi_bresp(0),
+ s_axi_bvalid_i_reg => s_axi_bvalid_i_reg,
+ s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
+ \s_axi_rdata_i[0]_i_2\(0) => REG_INTERFACE_I_n_126,
+ \s_axi_rdata_i[0]_i_2_0\ => REG_INTERFACE_I_n_131,
+ \s_axi_rdata_i[1]_i_2\ => REG_INTERFACE_I_n_129,
+ \s_axi_rdata_i[2]_i_2\ => REG_INTERFACE_I_n_127,
+ \s_axi_rdata_i[3]_i_2\(3 downto 0) => Timing_param_tsudat(3 downto 0),
+ \s_axi_rdata_i[3]_i_2_0\ => REG_INTERFACE_I_n_114,
+ \s_axi_rdata_i[7]_i_8\(5) => Cr(0),
+ \s_axi_rdata_i[7]_i_8\(4) => Cr(1),
+ \s_axi_rdata_i[7]_i_8\(3) => Cr(2),
+ \s_axi_rdata_i[7]_i_8\(2) => Cr(3),
+ \s_axi_rdata_i[7]_i_8\(1) => Cr(4),
+ \s_axi_rdata_i[7]_i_8\(0) => Cr(7),
+ \s_axi_rdata_i[7]_i_8_0\(4 downto 1) => Timing_param_tlow(7 downto 4),
+ \s_axi_rdata_i[7]_i_8_0\(0) => Timing_param_tlow(0),
+ \s_axi_rdata_i_reg[1]\ => REG_INTERFACE_I_n_130,
+ \s_axi_rdata_i_reg[2]\ => REG_INTERFACE_I_n_128,
+ \s_axi_rdata_i_reg[3]\ => REG_INTERFACE_I_n_115,
+ \s_axi_rdata_i_reg[4]_i_2\ => REG_INTERFACE_I_n_110,
+ \s_axi_rdata_i_reg[5]_i_2\ => REG_INTERFACE_I_n_111,
+ \s_axi_rdata_i_reg[6]_i_2\ => REG_INTERFACE_I_n_112,
+ \s_axi_rdata_i_reg[7]_i_2\ => REG_INTERFACE_I_n_113,
+ \s_axi_rdata_i_reg[7]_i_6\(5 downto 2) => Timing_param_tsusta(7 downto 4),
+ \s_axi_rdata_i_reg[7]_i_6\(1 downto 0) => Timing_param_tsusta(1 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_0\(5 downto 2) => Timing_param_tbuf(7 downto 4),
+ \s_axi_rdata_i_reg[7]_i_6_0\(1 downto 0) => Timing_param_tbuf(1 downto 0),
+ \s_axi_rdata_i_reg[7]_i_6_1\(4 downto 1) => Timing_param_thdsta(7 downto 4),
+ \s_axi_rdata_i_reg[7]_i_6_1\(0) => Timing_param_thdsta(0),
+ \s_axi_rdata_i_reg[7]_i_6_2\(3) => Adr(0),
+ \s_axi_rdata_i_reg[7]_i_6_2\(2) => Adr(1),
+ \s_axi_rdata_i_reg[7]_i_6_2\(1) => Adr(2),
+ \s_axi_rdata_i_reg[7]_i_6_2\(0) => Adr(3),
+ \s_axi_rdata_i_reg[7]_i_7\(7 downto 0) => Timing_param_tsusto(7 downto 0),
+ \s_axi_rdata_i_reg[7]_i_7_0\(7 downto 0) => Timing_param_thigh(7 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(0) => s_axi_rresp(0),
+ s_axi_rvalid_i_reg => s_axi_rvalid_i_reg,
+ s_axi_wdata(10 downto 0) => s_axi_wdata(10 downto 0),
+ \s_axi_wdata[5]\(1) => X_AXI_IPIF_SSP1_n_14,
+ \s_axi_wdata[5]\(0) => X_AXI_IPIF_SSP1_n_15,
+ s_axi_wdata_0_sp_1 => X_AXI_IPIF_SSP1_n_31,
+ s_axi_wvalid => s_axi_wvalid
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0_axi_iic is
+ port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ iic2intc_irpt : out STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ sda_o : out STD_LOGIC;
+ sda_t : out STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ scl_o : out STD_LOGIC;
+ scl_t : out STD_LOGIC;
+ gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute C_DEFAULT_VALUE : string;
+ attribute C_DEFAULT_VALUE of TopLevel_axi_iic_0_0_axi_iic : entity is "8'b00000000";
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of TopLevel_axi_iic_0_0_axi_iic : entity is "zynq";
+ attribute C_GPO_WIDTH : integer;
+ attribute C_GPO_WIDTH of TopLevel_axi_iic_0_0_axi_iic : entity is 1;
+ attribute C_IIC_FREQ : integer;
+ attribute C_IIC_FREQ of TopLevel_axi_iic_0_0_axi_iic : entity is 100000;
+ attribute C_SCL_INERTIAL_DELAY : integer;
+ attribute C_SCL_INERTIAL_DELAY of TopLevel_axi_iic_0_0_axi_iic : entity is 0;
+ attribute C_SDA_INERTIAL_DELAY : integer;
+ attribute C_SDA_INERTIAL_DELAY of TopLevel_axi_iic_0_0_axi_iic : entity is 0;
+ attribute C_SDA_LEVEL : integer;
+ attribute C_SDA_LEVEL of TopLevel_axi_iic_0_0_axi_iic : entity is 1;
+ attribute C_SMBUS_PMBUS_HOST : integer;
+ attribute C_SMBUS_PMBUS_HOST of TopLevel_axi_iic_0_0_axi_iic : entity is 0;
+ attribute C_S_AXI_ACLK_FREQ_HZ : integer;
+ attribute C_S_AXI_ACLK_FREQ_HZ of TopLevel_axi_iic_0_0_axi_iic : entity is 100000000;
+ attribute C_S_AXI_ADDR_WIDTH : integer;
+ attribute C_S_AXI_ADDR_WIDTH of TopLevel_axi_iic_0_0_axi_iic : entity is 9;
+ attribute C_S_AXI_DATA_WIDTH : integer;
+ attribute C_S_AXI_DATA_WIDTH of TopLevel_axi_iic_0_0_axi_iic : entity is 32;
+ attribute C_TEN_BIT_ADR : integer;
+ attribute C_TEN_BIT_ADR of TopLevel_axi_iic_0_0_axi_iic : entity is 0;
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of TopLevel_axi_iic_0_0_axi_iic : entity is "yes";
+end TopLevel_axi_iic_0_0_axi_iic;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0_axi_iic is
+ signal \<const0>\ : STD_LOGIC;
+ signal \^s_axi_awready\ : STD_LOGIC;
+ signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
+begin
+ s_axi_awready <= \^s_axi_awready\;
+ s_axi_bresp(1) <= \^s_axi_bresp\(1);
+ s_axi_bresp(0) <= \<const0>\;
+ s_axi_rdata(31) <= \^s_axi_rdata\(31);
+ s_axi_rdata(30) <= \<const0>\;
+ s_axi_rdata(29) <= \<const0>\;
+ s_axi_rdata(28) <= \<const0>\;
+ s_axi_rdata(27) <= \<const0>\;
+ s_axi_rdata(26) <= \<const0>\;
+ s_axi_rdata(25) <= \<const0>\;
+ s_axi_rdata(24) <= \<const0>\;
+ s_axi_rdata(23) <= \<const0>\;
+ s_axi_rdata(22) <= \<const0>\;
+ s_axi_rdata(21) <= \<const0>\;
+ s_axi_rdata(20) <= \<const0>\;
+ s_axi_rdata(19) <= \<const0>\;
+ s_axi_rdata(18) <= \<const0>\;
+ s_axi_rdata(17) <= \<const0>\;
+ s_axi_rdata(16) <= \<const0>\;
+ s_axi_rdata(15) <= \<const0>\;
+ s_axi_rdata(14) <= \<const0>\;
+ s_axi_rdata(13) <= \<const0>\;
+ s_axi_rdata(12) <= \<const0>\;
+ s_axi_rdata(11) <= \<const0>\;
+ s_axi_rdata(10) <= \<const0>\;
+ s_axi_rdata(9 downto 0) <= \^s_axi_rdata\(9 downto 0);
+ s_axi_rresp(1) <= \^s_axi_rresp\(1);
+ s_axi_rresp(0) <= \<const0>\;
+ s_axi_wready <= \^s_axi_awready\;
+ scl_o <= \<const0>\;
+ sda_o <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+X_IIC: entity work.TopLevel_axi_iic_0_0_iic
+ port map (
+ gpo(0) => gpo(0),
+ iic2intc_irpt => iic2intc_irpt,
+ is_read_reg => s_axi_arready,
+ is_write_reg => \^s_axi_awready\,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(0) => \^s_axi_bresp\(1),
+ s_axi_bvalid_i_reg => s_axi_bvalid,
+ s_axi_rdata(10) => \^s_axi_rdata\(31),
+ s_axi_rdata(9 downto 0) => \^s_axi_rdata\(9 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(0) => \^s_axi_rresp\(1),
+ s_axi_rvalid_i_reg => s_axi_rvalid,
+ s_axi_wdata(10) => s_axi_wdata(31),
+ s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
+ s_axi_wvalid => s_axi_wvalid,
+ scl_i => scl_i,
+ scl_t => scl_t,
+ sda_i => sda_i,
+ sda_t => sda_t
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_axi_iic_0_0 is
+ port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ iic2intc_irpt : out STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ sda_o : out STD_LOGIC;
+ sda_t : out STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ scl_o : out STD_LOGIC;
+ scl_t : out STD_LOGIC;
+ gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of TopLevel_axi_iic_0_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of TopLevel_axi_iic_0_0 : entity is "TopLevel_axi_iic_0_0,axi_iic,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of TopLevel_axi_iic_0_0 : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of TopLevel_axi_iic_0_0 : entity is "axi_iic,Vivado 2019.1";
+end TopLevel_axi_iic_0_0;
+
+architecture STRUCTURE of TopLevel_axi_iic_0_0 is
+ attribute C_DEFAULT_VALUE : string;
+ attribute C_DEFAULT_VALUE of U0 : label is "8'b00000000";
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of U0 : label is "zynq";
+ attribute C_GPO_WIDTH : integer;
+ attribute C_GPO_WIDTH of U0 : label is 1;
+ attribute C_IIC_FREQ : integer;
+ attribute C_IIC_FREQ of U0 : label is 100000;
+ attribute C_SCL_INERTIAL_DELAY : integer;
+ attribute C_SCL_INERTIAL_DELAY of U0 : label is 0;
+ attribute C_SDA_INERTIAL_DELAY : integer;
+ attribute C_SDA_INERTIAL_DELAY of U0 : label is 0;
+ attribute C_SDA_LEVEL : integer;
+ attribute C_SDA_LEVEL of U0 : label is 1;
+ attribute C_SMBUS_PMBUS_HOST : integer;
+ attribute C_SMBUS_PMBUS_HOST of U0 : label is 0;
+ attribute C_S_AXI_ACLK_FREQ_HZ : integer;
+ attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
+ attribute C_S_AXI_ADDR_WIDTH : integer;
+ attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
+ attribute C_S_AXI_DATA_WIDTH : integer;
+ attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
+ attribute C_TEN_BIT_ADR : integer;
+ attribute C_TEN_BIT_ADR of U0 : label is 0;
+ attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+ attribute x_interface_info : string;
+ attribute x_interface_info of iic2intc_irpt : signal is "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of iic2intc_irpt : signal is "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
+ attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+ attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+ attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+ attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+ attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+ attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+ attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+ attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+ attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+ attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+ attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+ attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+ attribute x_interface_info of scl_i : signal is "xilinx.com:interface:iic:1.0 IIC SCL_I";
+ attribute x_interface_info of scl_o : signal is "xilinx.com:interface:iic:1.0 IIC SCL_O";
+ attribute x_interface_info of scl_t : signal is "xilinx.com:interface:iic:1.0 IIC SCL_T";
+ attribute x_interface_info of sda_i : signal is "xilinx.com:interface:iic:1.0 IIC SDA_I";
+ attribute x_interface_parameter of sda_i : signal is "XIL_INTERFACENAME IIC, BOARD.ASSOCIATED_PARAM IIC_BOARD_INTERFACE";
+ attribute x_interface_info of sda_o : signal is "xilinx.com:interface:iic:1.0 IIC SDA_O";
+ attribute x_interface_info of sda_t : signal is "xilinx.com:interface:iic:1.0 IIC SDA_T";
+ attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+ attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+ attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+ attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+ attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+ attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+ attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+begin
+U0: entity work.TopLevel_axi_iic_0_0_axi_iic
+ port map (
+ gpo(0) => gpo(0),
+ iic2intc_irpt => iic2intc_irpt,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arready => s_axi_arready,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
+ s_axi_awready => s_axi_awready,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
+ s_axi_wready => s_axi_wready,
+ s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
+ s_axi_wvalid => s_axi_wvalid,
+ scl_i => scl_i,
+ scl_o => scl_o,
+ scl_t => scl_t,
+ sda_i => sda_i,
+ sda_o => sda_o,
+ sda_t => sda_t
+ );
+end STRUCTURE;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.v
new file mode 100644
index 0000000..8582f10
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.v
@@ -0,0 +1,50 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Mon Oct 14 17:13:30 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub -rename_top TopLevel_axi_iic_0_0 -prefix
+// TopLevel_axi_iic_0_0_ TopLevel_axi_iic_0_0_stub.v
+// Design : TopLevel_axi_iic_0_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_iic,Vivado 2019.1" *)
+module TopLevel_axi_iic_0_0(s_axi_aclk, s_axi_aresetn, iic2intc_irpt,
+ s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
+ s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
+ s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, sda_i, sda_o, sda_t, scl_i,
+ scl_o, scl_t, gpo)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,iic2intc_irpt,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,sda_i,sda_o,sda_t,scl_i,scl_o,scl_t,gpo[0:0]" */;
+ input s_axi_aclk;
+ input s_axi_aresetn;
+ output iic2intc_irpt;
+ input [8:0]s_axi_awaddr;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [31:0]s_axi_wdata;
+ input [3:0]s_axi_wstrb;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [1:0]s_axi_bresp;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [8:0]s_axi_araddr;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [31:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ input sda_i;
+ output sda_o;
+ output sda_t;
+ input scl_i;
+ output scl_o;
+ output scl_t;
+ output [0:0]gpo;
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.vhdl
new file mode 100644
index 0000000..0b46e49
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/TopLevel_axi_iic_0_0_stub.vhdl
@@ -0,0 +1,56 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Mon Oct 14 17:13:30 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub -rename_top TopLevel_axi_iic_0_0 -prefix
+-- TopLevel_axi_iic_0_0_ TopLevel_axi_iic_0_0_stub.vhdl
+-- Design : TopLevel_axi_iic_0_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity TopLevel_axi_iic_0_0 is
+ Port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ iic2intc_irpt : out STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ sda_i : in STD_LOGIC;
+ sda_o : out STD_LOGIC;
+ sda_t : out STD_LOGIC;
+ scl_i : in STD_LOGIC;
+ scl_o : out STD_LOGIC;
+ scl_t : out STD_LOGIC;
+ gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+
+end TopLevel_axi_iic_0_0;
+
+architecture stub of TopLevel_axi_iic_0_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,iic2intc_irpt,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,sda_i,sda_o,sda_t,scl_i,scl_o,scl_t,gpo[0:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_iic,Vivado 2019.1";
+begin
+end;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/sim/TopLevel_axi_iic_0_0.vhd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/sim/TopLevel_axi_iic_0_0.vhd
new file mode 100644
index 0000000..2505bc8
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/sim/TopLevel_axi_iic_0_0.vhd
@@ -0,0 +1,218 @@
+-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_iic:2.0
+-- IP Revision: 22
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_iic_v2_0_22;
+USE axi_iic_v2_0_22.axi_iic;
+
+ENTITY TopLevel_axi_iic_0_0 IS
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ iic2intc_irpt : OUT STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ sda_i : IN STD_LOGIC;
+ sda_o : OUT STD_LOGIC;
+ sda_t : OUT STD_LOGIC;
+ scl_i : IN STD_LOGIC;
+ scl_o : OUT STD_LOGIC;
+ scl_t : OUT STD_LOGIC;
+ gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+END TopLevel_axi_iic_0_0;
+
+ARCHITECTURE TopLevel_axi_iic_0_0_arch OF TopLevel_axi_iic_0_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF TopLevel_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT axi_iic IS
+ GENERIC (
+ C_FAMILY : STRING;
+ C_S_AXI_ADDR_WIDTH : INTEGER;
+ C_S_AXI_DATA_WIDTH : INTEGER;
+ C_IIC_FREQ : INTEGER;
+ C_TEN_BIT_ADR : INTEGER;
+ C_GPO_WIDTH : INTEGER;
+ C_S_AXI_ACLK_FREQ_HZ : INTEGER;
+ C_SCL_INERTIAL_DELAY : INTEGER;
+ C_SDA_INERTIAL_DELAY : INTEGER;
+ C_SDA_LEVEL : INTEGER;
+ C_SMBUS_PMBUS_HOST : INTEGER;
+ C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ iic2intc_irpt : OUT STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ sda_i : IN STD_LOGIC;
+ sda_o : OUT STD_LOGIC;
+ sda_t : OUT STD_LOGIC;
+ scl_i : IN STD_LOGIC;
+ scl_o : OUT STD_LOGIC;
+ scl_t : OUT STD_LOGIC;
+ gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+ END COMPONENT axi_iic;
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
+ ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
+ ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF sda_i: SIGNAL IS "XIL_INTERFACENAME IIC, BOARD.ASSOCIATED_PARAM IIC_BOARD_INTERFACE";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
+" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF iic2intc_irpt: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
+ ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+BEGIN
+ U0 : axi_iic
+ GENERIC MAP (
+ C_FAMILY => "zynq",
+ C_S_AXI_ADDR_WIDTH => 9,
+ C_S_AXI_DATA_WIDTH => 32,
+ C_IIC_FREQ => 100000,
+ C_TEN_BIT_ADR => 0,
+ C_GPO_WIDTH => 1,
+ C_S_AXI_ACLK_FREQ_HZ => 100000000,
+ C_SCL_INERTIAL_DELAY => 0,
+ C_SDA_INERTIAL_DELAY => 0,
+ C_SDA_LEVEL => 1,
+ C_SMBUS_PMBUS_HOST => 0,
+ C_DEFAULT_VALUE => X"00"
+ )
+ PORT MAP (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ iic2intc_irpt => iic2intc_irpt,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+ sda_i => sda_i,
+ sda_o => sda_o,
+ sda_t => sda_t,
+ scl_i => scl_i,
+ scl_o => scl_o,
+ scl_t => scl_t,
+ gpo => gpo
+ );
+END TopLevel_axi_iic_0_0_arch;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/synth/TopLevel_axi_iic_0_0.vhd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/synth/TopLevel_axi_iic_0_0.vhd
new file mode 100644
index 0000000..8ee2e74
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_axi_iic_0_0/synth/TopLevel_axi_iic_0_0.vhd
@@ -0,0 +1,224 @@
+-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_iic:2.0
+-- IP Revision: 22
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_iic_v2_0_22;
+USE axi_iic_v2_0_22.axi_iic;
+
+ENTITY TopLevel_axi_iic_0_0 IS
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ iic2intc_irpt : OUT STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ sda_i : IN STD_LOGIC;
+ sda_o : OUT STD_LOGIC;
+ sda_t : OUT STD_LOGIC;
+ scl_i : IN STD_LOGIC;
+ scl_o : OUT STD_LOGIC;
+ scl_t : OUT STD_LOGIC;
+ gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+END TopLevel_axi_iic_0_0;
+
+ARCHITECTURE TopLevel_axi_iic_0_0_arch OF TopLevel_axi_iic_0_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF TopLevel_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT axi_iic IS
+ GENERIC (
+ C_FAMILY : STRING;
+ C_S_AXI_ADDR_WIDTH : INTEGER;
+ C_S_AXI_DATA_WIDTH : INTEGER;
+ C_IIC_FREQ : INTEGER;
+ C_TEN_BIT_ADR : INTEGER;
+ C_GPO_WIDTH : INTEGER;
+ C_S_AXI_ACLK_FREQ_HZ : INTEGER;
+ C_SCL_INERTIAL_DELAY : INTEGER;
+ C_SDA_INERTIAL_DELAY : INTEGER;
+ C_SDA_LEVEL : INTEGER;
+ C_SMBUS_PMBUS_HOST : INTEGER;
+ C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ iic2intc_irpt : OUT STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ sda_i : IN STD_LOGIC;
+ sda_o : OUT STD_LOGIC;
+ sda_t : OUT STD_LOGIC;
+ scl_i : IN STD_LOGIC;
+ scl_o : OUT STD_LOGIC;
+ scl_t : OUT STD_LOGIC;
+ gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+ END COMPONENT axi_iic;
+ ATTRIBUTE X_CORE_INFO : STRING;
+ ATTRIBUTE X_CORE_INFO OF TopLevel_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2019.1";
+ ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+ ATTRIBUTE CHECK_LICENSE_TYPE OF TopLevel_axi_iic_0_0_arch : ARCHITECTURE IS "TopLevel_axi_iic_0_0,axi_iic,{}";
+ ATTRIBUTE CORE_GENERATION_INFO : STRING;
+ ATTRIBUTE CORE_GENERATION_INFO OF TopLevel_axi_iic_0_0_arch: ARCHITECTURE IS "TopLevel_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=22,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=100000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
+ ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
+ ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF sda_i: SIGNAL IS "XIL_INTERFACENAME IIC, BOARD.ASSOCIATED_PARAM IIC_BOARD_INTERFACE";
+ ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
+" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF iic2intc_irpt: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
+ ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+BEGIN
+ U0 : axi_iic
+ GENERIC MAP (
+ C_FAMILY => "zynq",
+ C_S_AXI_ADDR_WIDTH => 9,
+ C_S_AXI_DATA_WIDTH => 32,
+ C_IIC_FREQ => 100000,
+ C_TEN_BIT_ADR => 0,
+ C_GPO_WIDTH => 1,
+ C_S_AXI_ACLK_FREQ_HZ => 100000000,
+ C_SCL_INERTIAL_DELAY => 0,
+ C_SDA_INERTIAL_DELAY => 0,
+ C_SDA_LEVEL => 1,
+ C_SMBUS_PMBUS_HOST => 0,
+ C_DEFAULT_VALUE => X"00"
+ )
+ PORT MAP (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ iic2intc_irpt => iic2intc_irpt,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+ sda_i => sda_i,
+ sda_o => sda_o,
+ sda_t => sda_t,
+ scl_i => scl_i,
+ scl_o => scl_o,
+ scl_t => scl_t,
+ gpo => gpo
+ );
+END TopLevel_axi_iic_0_0_arch;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.dcp b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.dcp
new file mode 100644
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diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xci b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xci
new file mode 100644
index 0000000..5180c6a
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xci
@@ -0,0 +1,111 @@
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diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xml
new file mode 100644
index 0000000..361759a
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0.xml
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+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:name>ASSOCIATED_RESET</spirit:name>
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+ <spirit:name>CLK_DOMAIN</spirit:name>
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+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
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+ <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
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+ <spirit:name>outputProductCRC</spirit:name>
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+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI data bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI address bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">6</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
+ <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
+ <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">TopLevel_endeavour_axi_contro_5_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>endeavour_axi_controller_v1.0</xilinx:displayName>
+ <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:tags>
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+ <xilinx:tag xilinx:name="lbl.gov:user:endeavour_axi_controller:1.0_ARCHIVE_LOCATION">/home/kkrizka/Firmware/amacv2_tester/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="lbl.gov:endeavour:endeavour_axi_controller:1.0_ARCHIVE_LOCATION">/home/kkrizka/ITkStrips/AMACv2/amacv2_tester/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@fe8cac1_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ee3351_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c05d181_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11175760_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58ee0488_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7c81676d_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@676ae7e0_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@652e38ee_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7b0930a0_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7bb0de0e_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7d69e595_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23ab5969_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bbd6f03_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2d3908a7_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5da7258c_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d678bf6_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3bfd77ad_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7f5dab08_ARCHIVE_LOCATION">/home/kkrizka/Dropbox/HEP/ITkStrips/PowerBoard/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@135a994d_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d0809cf_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b664b0b_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@cb6c9f3_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c005e0b_ARCHIVE_LOCATION">/opt/local/strips/firmware/ip_repo/endeavour_axi_controller_1.0</xilinx:tag>
+ </xilinx:tags>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="206b0a70"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7274744c"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f96fcf9"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e7b50784"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="4b93d213"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.v
new file mode 100644
index 0000000..bc9839c
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.v
@@ -0,0 +1,7860 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Tue Oct 15 10:07:03 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode funcsim
+// /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.v
+// Design : TopLevel_endeavour_axi_contro_5_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "TopLevel_endeavour_axi_contro_5_0,endeavour_axi_controller_v1_0,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "endeavour_axi_controller_v1_0,Vivado 2019.1" *)
+(* NotValidForBitStream *)
+module TopLevel_endeavour_axi_contro_5_0
+ (busy,
+ datavalid,
+ error,
+ CMD_IN_P,
+ CMD_IN_N,
+ CMD_OUT_P,
+ CMD_OUT_N,
+ cmd_in,
+ cmd_out,
+ s00_axi_awaddr,
+ s00_axi_awprot,
+ s00_axi_awvalid,
+ s00_axi_awready,
+ s00_axi_wdata,
+ s00_axi_wstrb,
+ s00_axi_wvalid,
+ s00_axi_wready,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ s00_axi_bready,
+ s00_axi_araddr,
+ s00_axi_arprot,
+ s00_axi_arvalid,
+ s00_axi_arready,
+ s00_axi_rdata,
+ s00_axi_rresp,
+ s00_axi_rvalid,
+ s00_axi_rready,
+ s00_axi_aclk,
+ s00_axi_aresetn);
+ output busy;
+ output datavalid;
+ output error;
+ output CMD_IN_P;
+ output CMD_IN_N;
+ input CMD_OUT_P;
+ input CMD_OUT_N;
+ output cmd_in;
+ output cmd_out;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 8, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 6, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [5:0]s00_axi_awaddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s00_axi_awprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input s00_axi_awvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output s00_axi_awready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s00_axi_wdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s00_axi_wstrb;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input s00_axi_wvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output s00_axi_wready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s00_axi_bresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output s00_axi_bvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input s00_axi_bready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [5:0]s00_axi_araddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s00_axi_arprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input s00_axi_arvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output s00_axi_arready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s00_axi_rdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s00_axi_rresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output s00_axi_rvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input s00_axi_rready;
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input s00_axi_aclk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s00_axi_aresetn;
+
+ wire \<const0> ;
+ (* IOSTANDARD = "LVDS_25" *) (* SLEW = "SLOW" *) wire CMD_IN_N;
+ (* IOSTANDARD = "LVDS_25" *) (* SLEW = "SLOW" *) wire CMD_IN_P;
+ (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVDS_25" *) wire CMD_OUT_N;
+ (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVDS_25" *) wire CMD_OUT_P;
+ wire busy;
+ wire cmd_in;
+ wire cmd_out;
+ wire datavalid;
+ wire error;
+ wire s00_axi_aclk;
+ wire [5:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [5:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire s00_axi_bvalid;
+ wire [31:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire [3:0]s00_axi_wstrb;
+ wire s00_axi_wvalid;
+
+ assign s00_axi_bresp[1] = \<const0> ;
+ assign s00_axi_bresp[0] = \<const0> ;
+ assign s00_axi_rresp[1] = \<const0> ;
+ assign s00_axi_rresp[0] = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0 U0
+ (.CMD_IN_N(CMD_IN_N),
+ .CMD_IN_P(CMD_IN_P),
+ .CMD_OUT_N(CMD_OUT_N),
+ .CMD_OUT_P(CMD_OUT_P),
+ .D({error,datavalid,busy}),
+ .cmd_in(cmd_in),
+ .cmd_out(cmd_out),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr[5:2]),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr[5:2]),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(s00_axi_rdata),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wstrb(s00_axi_wstrb),
+ .s00_axi_wvalid(s00_axi_wvalid));
+endmodule
+
+(* ORIG_REF_NAME = "endeavour_axi_controller_v1_0" *)
+module TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0
+ (s00_axi_awready,
+ s00_axi_wready,
+ s00_axi_arready,
+ D,
+ s00_axi_rdata,
+ s00_axi_rvalid,
+ cmd_out,
+ CMD_IN_P,
+ CMD_IN_N,
+ cmd_in,
+ s00_axi_bvalid,
+ s00_axi_aclk,
+ s00_axi_awaddr,
+ s00_axi_wdata,
+ s00_axi_aresetn,
+ s00_axi_araddr,
+ s00_axi_wvalid,
+ s00_axi_awvalid,
+ s00_axi_wstrb,
+ s00_axi_arvalid,
+ CMD_OUT_P,
+ CMD_OUT_N,
+ s00_axi_bready,
+ s00_axi_rready);
+ output s00_axi_awready;
+ output s00_axi_wready;
+ output s00_axi_arready;
+ output [2:0]D;
+ output [31:0]s00_axi_rdata;
+ output s00_axi_rvalid;
+ output cmd_out;
+ output CMD_IN_P;
+ output CMD_IN_N;
+ output cmd_in;
+ output s00_axi_bvalid;
+ input s00_axi_aclk;
+ input [3:0]s00_axi_awaddr;
+ input [31:0]s00_axi_wdata;
+ input s00_axi_aresetn;
+ input [3:0]s00_axi_araddr;
+ input s00_axi_wvalid;
+ input s00_axi_awvalid;
+ input [3:0]s00_axi_wstrb;
+ input s00_axi_arvalid;
+ input CMD_OUT_P;
+ input CMD_OUT_N;
+ input s00_axi_bready;
+ input s00_axi_rready;
+
+ wire CMD_IN_N;
+ wire CMD_IN_P;
+ wire CMD_OUT_N;
+ wire CMD_OUT_P;
+ wire [2:0]D;
+ wire I;
+ wire [11:0]TICKS_BITGAP_MID;
+ wire [11:0]TICKS_DAH_MAX;
+ wire [11:0]TICKS_DAH_MID;
+ wire [7:0]TICKS_DAH_MIN;
+ wire [11:0]TICKS_DIT_MAX;
+ wire [11:0]TICKS_DIT_MID;
+ wire [7:0]TICKS_DIT_MIN;
+ wire [0:0]axi_config;
+ wire [1:0]axi_control;
+ wire [63:0]axi_datain;
+ wire [63:0]axi_dataout;
+ wire [5:0]axi_nbitsin;
+ wire [5:0]axi_nbitsout_integer;
+ wire cmd_in;
+ wire cmd_out;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_10;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_11;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_44;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_45;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_46;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_47;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_48;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_49;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_5;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_50;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_51;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_52;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_53;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_8;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_86;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_87;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_88;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_89;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_9;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_90;
+ wire endeavour_axi_controller_v1_0_S00_AXI_inst_n_91;
+ wire inst_endeavour_master_n_10;
+ wire inst_endeavour_master_n_11;
+ wire inst_endeavour_master_n_12;
+ wire inst_endeavour_master_n_13;
+ wire inst_endeavour_master_n_14;
+ wire inst_endeavour_master_n_15;
+ wire inst_endeavour_master_n_4;
+ wire inst_endeavour_master_n_5;
+ wire inst_endeavour_master_n_6;
+ wire inst_endeavour_master_n_7;
+ wire inst_endeavour_master_n_8;
+ wire inst_endeavour_master_n_9;
+ wire s00_axi_aclk;
+ wire [3:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [3:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire s00_axi_bvalid;
+ wire [31:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire [3:0]s00_axi_wstrb;
+ wire s00_axi_wvalid;
+ wire seriali_buf;
+
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* box_type = "PRIMITIVE" *)
+ OBUFDS CMD_IN_buf_inst
+ (.I(I),
+ .O(CMD_IN_P),
+ .OB(CMD_IN_N));
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ (* box_type = "PRIMITIVE" *)
+ IBUFDS CMD_OUT_buf_inst
+ (.I(CMD_OUT_P),
+ .IB(CMD_OUT_N),
+ .O(seriali_buf));
+ TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI endeavour_axi_controller_v1_0_S00_AXI_inst
+ (.D(axi_datain),
+ .DI({endeavour_axi_controller_v1_0_S00_AXI_inst_n_8,endeavour_axi_controller_v1_0_S00_AXI_inst_n_9,endeavour_axi_controller_v1_0_S00_AXI_inst_n_10,endeavour_axi_controller_v1_0_S00_AXI_inst_n_11}),
+ .Q({TICKS_DIT_MAX,TICKS_DIT_MID,TICKS_DIT_MIN}),
+ .S({endeavour_axi_controller_v1_0_S00_AXI_inst_n_46,endeavour_axi_controller_v1_0_S00_AXI_inst_n_47,endeavour_axi_controller_v1_0_S00_AXI_inst_n_48,endeavour_axi_controller_v1_0_S00_AXI_inst_n_49}),
+ .axi_control(axi_control),
+ .cmd_out(cmd_out),
+ .\reg_nbitsout1_inferred__0/i__carry__0 ({inst_endeavour_master_n_4,inst_endeavour_master_n_5,inst_endeavour_master_n_6,inst_endeavour_master_n_7,inst_endeavour_master_n_8,inst_endeavour_master_n_9,inst_endeavour_master_n_10,inst_endeavour_master_n_11,inst_endeavour_master_n_12,inst_endeavour_master_n_13,inst_endeavour_master_n_14,inst_endeavour_master_n_15}),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(s00_axi_rdata),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wstrb(s00_axi_wstrb),
+ .s00_axi_wvalid(s00_axi_wvalid),
+ .seriali_buf(seriali_buf),
+ .\slv_reg0_pulse_reg[1]_0 (endeavour_axi_controller_v1_0_S00_AXI_inst_n_5),
+ .\slv_reg0_read_reg[2]_0 (D),
+ .\slv_reg10_reg[0]_0 (axi_config),
+ .\slv_reg1_reg[5]_0 (axi_nbitsin),
+ .\slv_reg4_reg[5]_0 (axi_nbitsout_integer),
+ .\slv_reg6_reg[31]_0 (axi_dataout),
+ .\slv_reg7_reg[31]_0 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_44,endeavour_axi_controller_v1_0_S00_AXI_inst_n_45}),
+ .\slv_reg8_reg[27]_0 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_50,endeavour_axi_controller_v1_0_S00_AXI_inst_n_51,endeavour_axi_controller_v1_0_S00_AXI_inst_n_52,endeavour_axi_controller_v1_0_S00_AXI_inst_n_53}),
+ .\slv_reg8_reg[31]_0 ({TICKS_DAH_MAX,TICKS_DAH_MID,TICKS_DAH_MIN}),
+ .\slv_reg8_reg[31]_1 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_86,endeavour_axi_controller_v1_0_S00_AXI_inst_n_87}),
+ .\slv_reg8_reg[7]_0 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_88,endeavour_axi_controller_v1_0_S00_AXI_inst_n_89,endeavour_axi_controller_v1_0_S00_AXI_inst_n_90,endeavour_axi_controller_v1_0_S00_AXI_inst_n_91}),
+ .\slv_reg9_reg[19]_0 (TICKS_BITGAP_MID));
+ TopLevel_endeavour_axi_contro_5_0_endeavour_master inst_endeavour_master
+ (.CMD_IN_P(axi_config),
+ .D(D),
+ .DI({endeavour_axi_controller_v1_0_S00_AXI_inst_n_8,endeavour_axi_controller_v1_0_S00_AXI_inst_n_9,endeavour_axi_controller_v1_0_S00_AXI_inst_n_10,endeavour_axi_controller_v1_0_S00_AXI_inst_n_11}),
+ .I(I),
+ .Q({inst_endeavour_master_n_4,inst_endeavour_master_n_5,inst_endeavour_master_n_6,inst_endeavour_master_n_7,inst_endeavour_master_n_8,inst_endeavour_master_n_9,inst_endeavour_master_n_10,inst_endeavour_master_n_11,inst_endeavour_master_n_12,inst_endeavour_master_n_13,inst_endeavour_master_n_14,inst_endeavour_master_n_15}),
+ .S({endeavour_axi_controller_v1_0_S00_AXI_inst_n_46,endeavour_axi_controller_v1_0_S00_AXI_inst_n_47,endeavour_axi_controller_v1_0_S00_AXI_inst_n_48,endeavour_axi_controller_v1_0_S00_AXI_inst_n_49}),
+ .axi_control(axi_control),
+ .cmd_in(cmd_in),
+ .cmd_out(cmd_out),
+ .\counter_reg[11]_0 (TICKS_BITGAP_MID),
+ .\reg_datain_reg[63]_0 (axi_datain),
+ .\reg_dataout_reg[63]_0 (axi_dataout),
+ .\reg_nbitsin_reg[5]_0 (axi_nbitsin),
+ .\reg_nbitsout1_inferred__0/i__carry__0_0 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_50,endeavour_axi_controller_v1_0_S00_AXI_inst_n_51,endeavour_axi_controller_v1_0_S00_AXI_inst_n_52,endeavour_axi_controller_v1_0_S00_AXI_inst_n_53}),
+ .\reg_nbitsout1_inferred__0/i__carry__0_1 ({TICKS_DAH_MAX,TICKS_DAH_MID,TICKS_DAH_MIN}),
+ .\reg_nbitsout1_inferred__1/i__carry__0_0 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_88,endeavour_axi_controller_v1_0_S00_AXI_inst_n_89,endeavour_axi_controller_v1_0_S00_AXI_inst_n_90,endeavour_axi_controller_v1_0_S00_AXI_inst_n_91}),
+ .reg_nbitsout2_carry__0_0({TICKS_DIT_MAX,TICKS_DIT_MID,TICKS_DIT_MIN}),
+ .\reg_nbitsout_reg[5]_0 (axi_nbitsout_integer),
+ .\reg_nbitsout_reg[5]_1 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_44,endeavour_axi_controller_v1_0_S00_AXI_inst_n_45}),
+ .\reg_nbitsout_reg[5]_2 ({endeavour_axi_controller_v1_0_S00_AXI_inst_n_86,endeavour_axi_controller_v1_0_S00_AXI_inst_n_87}),
+ .\reg_nbitsout_reg[5]_3 (endeavour_axi_controller_v1_0_S00_AXI_inst_n_5),
+ .s00_axi_aclk(s00_axi_aclk));
+endmodule
+
+(* ORIG_REF_NAME = "endeavour_axi_controller_v1_0_S00_AXI" *)
+module TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI
+ (s00_axi_awready,
+ s00_axi_wready,
+ s00_axi_arready,
+ s00_axi_bvalid,
+ s00_axi_rvalid,
+ \slv_reg0_pulse_reg[1]_0 ,
+ axi_control,
+ DI,
+ Q,
+ \slv_reg7_reg[31]_0 ,
+ S,
+ \slv_reg8_reg[27]_0 ,
+ \slv_reg8_reg[31]_0 ,
+ \slv_reg8_reg[31]_1 ,
+ \slv_reg8_reg[7]_0 ,
+ cmd_out,
+ \slv_reg10_reg[0]_0 ,
+ D,
+ \slv_reg9_reg[19]_0 ,
+ \slv_reg1_reg[5]_0 ,
+ s00_axi_rdata,
+ s00_axi_aclk,
+ \reg_nbitsout1_inferred__0/i__carry__0 ,
+ seriali_buf,
+ s00_axi_awvalid,
+ s00_axi_wvalid,
+ s00_axi_bready,
+ s00_axi_arvalid,
+ s00_axi_rready,
+ s00_axi_awaddr,
+ s00_axi_wdata,
+ s00_axi_aresetn,
+ \slv_reg0_read_reg[2]_0 ,
+ \slv_reg4_reg[5]_0 ,
+ \slv_reg6_reg[31]_0 ,
+ s00_axi_araddr,
+ s00_axi_wstrb);
+ output s00_axi_awready;
+ output s00_axi_wready;
+ output s00_axi_arready;
+ output s00_axi_bvalid;
+ output s00_axi_rvalid;
+ output \slv_reg0_pulse_reg[1]_0 ;
+ output [1:0]axi_control;
+ output [3:0]DI;
+ output [31:0]Q;
+ output [1:0]\slv_reg7_reg[31]_0 ;
+ output [3:0]S;
+ output [3:0]\slv_reg8_reg[27]_0 ;
+ output [31:0]\slv_reg8_reg[31]_0 ;
+ output [1:0]\slv_reg8_reg[31]_1 ;
+ output [3:0]\slv_reg8_reg[7]_0 ;
+ output cmd_out;
+ output [0:0]\slv_reg10_reg[0]_0 ;
+ output [63:0]D;
+ output [11:0]\slv_reg9_reg[19]_0 ;
+ output [5:0]\slv_reg1_reg[5]_0 ;
+ output [31:0]s00_axi_rdata;
+ input s00_axi_aclk;
+ input [11:0]\reg_nbitsout1_inferred__0/i__carry__0 ;
+ input seriali_buf;
+ input s00_axi_awvalid;
+ input s00_axi_wvalid;
+ input s00_axi_bready;
+ input s00_axi_arvalid;
+ input s00_axi_rready;
+ input [3:0]s00_axi_awaddr;
+ input [31:0]s00_axi_wdata;
+ input s00_axi_aresetn;
+ input [2:0]\slv_reg0_read_reg[2]_0 ;
+ input [5:0]\slv_reg4_reg[5]_0 ;
+ input [63:0]\slv_reg6_reg[31]_0 ;
+ input [3:0]s00_axi_araddr;
+ input [3:0]s00_axi_wstrb;
+
+ wire [63:0]D;
+ wire [3:0]DI;
+ wire [31:0]Q;
+ wire [3:0]S;
+ wire [11:0]TICKS_BITGAP_MAX;
+ wire [7:0]TICKS_BITGAP_MIN;
+ wire axi_arready0;
+ wire axi_awready0;
+ wire axi_awready_i_1_n_0;
+ wire axi_bvalid_i_1_n_0;
+ wire [1:1]axi_config;
+ wire [1:0]axi_control;
+ wire \axi_rdata[0]_i_2_n_0 ;
+ wire \axi_rdata[0]_i_3_n_0 ;
+ wire \axi_rdata[0]_i_4_n_0 ;
+ wire \axi_rdata[10]_i_2_n_0 ;
+ wire \axi_rdata[10]_i_3_n_0 ;
+ wire \axi_rdata[10]_i_4_n_0 ;
+ wire \axi_rdata[11]_i_2_n_0 ;
+ wire \axi_rdata[11]_i_3_n_0 ;
+ wire \axi_rdata[11]_i_4_n_0 ;
+ wire \axi_rdata[12]_i_2_n_0 ;
+ wire \axi_rdata[12]_i_3_n_0 ;
+ wire \axi_rdata[12]_i_4_n_0 ;
+ wire \axi_rdata[13]_i_2_n_0 ;
+ wire \axi_rdata[13]_i_3_n_0 ;
+ wire \axi_rdata[13]_i_4_n_0 ;
+ wire \axi_rdata[14]_i_2_n_0 ;
+ wire \axi_rdata[14]_i_3_n_0 ;
+ wire \axi_rdata[14]_i_4_n_0 ;
+ wire \axi_rdata[15]_i_2_n_0 ;
+ wire \axi_rdata[15]_i_3_n_0 ;
+ wire \axi_rdata[15]_i_4_n_0 ;
+ wire \axi_rdata[16]_i_2_n_0 ;
+ wire \axi_rdata[16]_i_3_n_0 ;
+ wire \axi_rdata[16]_i_4_n_0 ;
+ wire \axi_rdata[17]_i_2_n_0 ;
+ wire \axi_rdata[17]_i_3_n_0 ;
+ wire \axi_rdata[17]_i_4_n_0 ;
+ wire \axi_rdata[18]_i_2_n_0 ;
+ wire \axi_rdata[18]_i_3_n_0 ;
+ wire \axi_rdata[18]_i_4_n_0 ;
+ wire \axi_rdata[19]_i_2_n_0 ;
+ wire \axi_rdata[19]_i_3_n_0 ;
+ wire \axi_rdata[19]_i_4_n_0 ;
+ wire \axi_rdata[1]_i_2_n_0 ;
+ wire \axi_rdata[1]_i_3_n_0 ;
+ wire \axi_rdata[1]_i_4_n_0 ;
+ wire \axi_rdata[20]_i_2_n_0 ;
+ wire \axi_rdata[20]_i_3_n_0 ;
+ wire \axi_rdata[20]_i_4_n_0 ;
+ wire \axi_rdata[21]_i_2_n_0 ;
+ wire \axi_rdata[21]_i_3_n_0 ;
+ wire \axi_rdata[21]_i_4_n_0 ;
+ wire \axi_rdata[22]_i_2_n_0 ;
+ wire \axi_rdata[22]_i_3_n_0 ;
+ wire \axi_rdata[22]_i_4_n_0 ;
+ wire \axi_rdata[23]_i_2_n_0 ;
+ wire \axi_rdata[23]_i_3_n_0 ;
+ wire \axi_rdata[23]_i_4_n_0 ;
+ wire \axi_rdata[24]_i_2_n_0 ;
+ wire \axi_rdata[24]_i_3_n_0 ;
+ wire \axi_rdata[24]_i_4_n_0 ;
+ wire \axi_rdata[25]_i_2_n_0 ;
+ wire \axi_rdata[25]_i_3_n_0 ;
+ wire \axi_rdata[25]_i_4_n_0 ;
+ wire \axi_rdata[26]_i_2_n_0 ;
+ wire \axi_rdata[26]_i_3_n_0 ;
+ wire \axi_rdata[26]_i_4_n_0 ;
+ wire \axi_rdata[27]_i_2_n_0 ;
+ wire \axi_rdata[27]_i_3_n_0 ;
+ wire \axi_rdata[27]_i_4_n_0 ;
+ wire \axi_rdata[28]_i_2_n_0 ;
+ wire \axi_rdata[28]_i_3_n_0 ;
+ wire \axi_rdata[28]_i_4_n_0 ;
+ wire \axi_rdata[29]_i_2_n_0 ;
+ wire \axi_rdata[29]_i_3_n_0 ;
+ wire \axi_rdata[29]_i_4_n_0 ;
+ wire \axi_rdata[2]_i_2_n_0 ;
+ wire \axi_rdata[2]_i_3_n_0 ;
+ wire \axi_rdata[2]_i_4_n_0 ;
+ wire \axi_rdata[30]_i_2_n_0 ;
+ wire \axi_rdata[30]_i_3_n_0 ;
+ wire \axi_rdata[30]_i_4_n_0 ;
+ wire \axi_rdata[31]_i_3_n_0 ;
+ wire \axi_rdata[31]_i_4_n_0 ;
+ wire \axi_rdata[31]_i_5_n_0 ;
+ wire \axi_rdata[3]_i_2_n_0 ;
+ wire \axi_rdata[3]_i_3_n_0 ;
+ wire \axi_rdata[3]_i_4_n_0 ;
+ wire \axi_rdata[4]_i_2_n_0 ;
+ wire \axi_rdata[4]_i_3_n_0 ;
+ wire \axi_rdata[4]_i_4_n_0 ;
+ wire \axi_rdata[5]_i_2_n_0 ;
+ wire \axi_rdata[5]_i_3_n_0 ;
+ wire \axi_rdata[5]_i_4_n_0 ;
+ wire \axi_rdata[6]_i_2_n_0 ;
+ wire \axi_rdata[6]_i_3_n_0 ;
+ wire \axi_rdata[6]_i_4_n_0 ;
+ wire \axi_rdata[7]_i_2_n_0 ;
+ wire \axi_rdata[7]_i_3_n_0 ;
+ wire \axi_rdata[7]_i_4_n_0 ;
+ wire \axi_rdata[8]_i_2_n_0 ;
+ wire \axi_rdata[8]_i_3_n_0 ;
+ wire \axi_rdata[8]_i_4_n_0 ;
+ wire \axi_rdata[9]_i_2_n_0 ;
+ wire \axi_rdata[9]_i_3_n_0 ;
+ wire \axi_rdata[9]_i_4_n_0 ;
+ wire axi_rvalid_i_1_n_0;
+ wire axi_wready0;
+ wire cmd_out;
+ wire [3:0]p_0_in;
+ wire [0:0]p_1_in;
+ wire [31:0]reg_data_out;
+ wire [11:0]\reg_nbitsout1_inferred__0/i__carry__0 ;
+ wire s00_axi_aclk;
+ wire [3:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [3:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire s00_axi_bvalid;
+ wire [31:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire [3:0]s00_axi_wstrb;
+ wire s00_axi_wvalid;
+ wire [3:0]sel0;
+ wire seriali_buf;
+ wire \slv_reg0_pulse[0]_i_1_n_0 ;
+ wire \slv_reg0_pulse[1]_i_1_n_0 ;
+ wire \slv_reg0_pulse_reg[1]_0 ;
+ wire [2:0]slv_reg0_read;
+ wire [2:0]\slv_reg0_read_reg[2]_0 ;
+ wire \slv_reg10[15]_i_1_n_0 ;
+ wire \slv_reg10[23]_i_1_n_0 ;
+ wire \slv_reg10[31]_i_1_n_0 ;
+ wire \slv_reg10[7]_i_1_n_0 ;
+ wire [0:0]\slv_reg10_reg[0]_0 ;
+ wire \slv_reg10_reg_n_0_[10] ;
+ wire \slv_reg10_reg_n_0_[11] ;
+ wire \slv_reg10_reg_n_0_[12] ;
+ wire \slv_reg10_reg_n_0_[13] ;
+ wire \slv_reg10_reg_n_0_[14] ;
+ wire \slv_reg10_reg_n_0_[15] ;
+ wire \slv_reg10_reg_n_0_[16] ;
+ wire \slv_reg10_reg_n_0_[17] ;
+ wire \slv_reg10_reg_n_0_[18] ;
+ wire \slv_reg10_reg_n_0_[19] ;
+ wire \slv_reg10_reg_n_0_[20] ;
+ wire \slv_reg10_reg_n_0_[21] ;
+ wire \slv_reg10_reg_n_0_[22] ;
+ wire \slv_reg10_reg_n_0_[23] ;
+ wire \slv_reg10_reg_n_0_[24] ;
+ wire \slv_reg10_reg_n_0_[25] ;
+ wire \slv_reg10_reg_n_0_[26] ;
+ wire \slv_reg10_reg_n_0_[27] ;
+ wire \slv_reg10_reg_n_0_[28] ;
+ wire \slv_reg10_reg_n_0_[29] ;
+ wire \slv_reg10_reg_n_0_[2] ;
+ wire \slv_reg10_reg_n_0_[30] ;
+ wire \slv_reg10_reg_n_0_[31] ;
+ wire \slv_reg10_reg_n_0_[3] ;
+ wire \slv_reg10_reg_n_0_[4] ;
+ wire \slv_reg10_reg_n_0_[5] ;
+ wire \slv_reg10_reg_n_0_[6] ;
+ wire \slv_reg10_reg_n_0_[7] ;
+ wire \slv_reg10_reg_n_0_[8] ;
+ wire \slv_reg10_reg_n_0_[9] ;
+ wire \slv_reg1[15]_i_1_n_0 ;
+ wire \slv_reg1[23]_i_1_n_0 ;
+ wire \slv_reg1[31]_i_1_n_0 ;
+ wire \slv_reg1[7]_i_1_n_0 ;
+ wire [5:0]\slv_reg1_reg[5]_0 ;
+ wire \slv_reg1_reg_n_0_[10] ;
+ wire \slv_reg1_reg_n_0_[11] ;
+ wire \slv_reg1_reg_n_0_[12] ;
+ wire \slv_reg1_reg_n_0_[13] ;
+ wire \slv_reg1_reg_n_0_[14] ;
+ wire \slv_reg1_reg_n_0_[15] ;
+ wire \slv_reg1_reg_n_0_[16] ;
+ wire \slv_reg1_reg_n_0_[17] ;
+ wire \slv_reg1_reg_n_0_[18] ;
+ wire \slv_reg1_reg_n_0_[19] ;
+ wire \slv_reg1_reg_n_0_[20] ;
+ wire \slv_reg1_reg_n_0_[21] ;
+ wire \slv_reg1_reg_n_0_[22] ;
+ wire \slv_reg1_reg_n_0_[23] ;
+ wire \slv_reg1_reg_n_0_[24] ;
+ wire \slv_reg1_reg_n_0_[25] ;
+ wire \slv_reg1_reg_n_0_[26] ;
+ wire \slv_reg1_reg_n_0_[27] ;
+ wire \slv_reg1_reg_n_0_[28] ;
+ wire \slv_reg1_reg_n_0_[29] ;
+ wire \slv_reg1_reg_n_0_[30] ;
+ wire \slv_reg1_reg_n_0_[31] ;
+ wire \slv_reg1_reg_n_0_[6] ;
+ wire \slv_reg1_reg_n_0_[7] ;
+ wire \slv_reg1_reg_n_0_[8] ;
+ wire \slv_reg1_reg_n_0_[9] ;
+ wire \slv_reg2[15]_i_1_n_0 ;
+ wire \slv_reg2[23]_i_1_n_0 ;
+ wire \slv_reg2[31]_i_1_n_0 ;
+ wire \slv_reg2[7]_i_1_n_0 ;
+ wire \slv_reg3[15]_i_1_n_0 ;
+ wire \slv_reg3[23]_i_1_n_0 ;
+ wire \slv_reg3[31]_i_1_n_0 ;
+ wire \slv_reg3[7]_i_1_n_0 ;
+ wire [5:0]slv_reg4;
+ wire [5:0]\slv_reg4_reg[5]_0 ;
+ wire [31:0]slv_reg5;
+ wire [31:0]slv_reg6;
+ wire [63:0]\slv_reg6_reg[31]_0 ;
+ wire \slv_reg7[15]_i_1_n_0 ;
+ wire \slv_reg7[23]_i_1_n_0 ;
+ wire \slv_reg7[31]_i_1_n_0 ;
+ wire \slv_reg7[7]_i_1_n_0 ;
+ wire [1:0]\slv_reg7_reg[31]_0 ;
+ wire \slv_reg8[15]_i_1_n_0 ;
+ wire \slv_reg8[23]_i_1_n_0 ;
+ wire \slv_reg8[31]_i_1_n_0 ;
+ wire \slv_reg8[7]_i_1_n_0 ;
+ wire [3:0]\slv_reg8_reg[27]_0 ;
+ wire [31:0]\slv_reg8_reg[31]_0 ;
+ wire [1:0]\slv_reg8_reg[31]_1 ;
+ wire [3:0]\slv_reg8_reg[7]_0 ;
+ wire \slv_reg9[15]_i_1_n_0 ;
+ wire \slv_reg9[23]_i_1_n_0 ;
+ wire \slv_reg9[31]_i_1_n_0 ;
+ wire \slv_reg9[7]_i_1_n_0 ;
+ wire [11:0]\slv_reg9_reg[19]_0 ;
+ wire slv_reg_rden;
+ wire slv_reg_wren__2;
+
+ FDSE \axi_araddr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(axi_arready0),
+ .D(s00_axi_araddr[0]),
+ .Q(sel0[0]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \axi_araddr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(axi_arready0),
+ .D(s00_axi_araddr[1]),
+ .Q(sel0[1]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \axi_araddr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(axi_arready0),
+ .D(s00_axi_araddr[2]),
+ .Q(sel0[2]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \axi_araddr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(axi_arready0),
+ .D(s00_axi_araddr[3]),
+ .Q(sel0[3]),
+ .S(axi_awready_i_1_n_0));
+ LUT2 #(
+ .INIT(4'h2))
+ axi_arready_i_1
+ (.I0(s00_axi_arvalid),
+ .I1(s00_axi_arready),
+ .O(axi_arready0));
+ FDRE axi_arready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(axi_arready0),
+ .Q(s00_axi_arready),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_awaddr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(axi_awready0),
+ .D(s00_axi_awaddr[0]),
+ .Q(p_0_in[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_awaddr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(axi_awready0),
+ .D(s00_axi_awaddr[1]),
+ .Q(p_0_in[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_awaddr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(axi_awready0),
+ .D(s00_axi_awaddr[2]),
+ .Q(p_0_in[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_awaddr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(axi_awready0),
+ .D(s00_axi_awaddr[3]),
+ .Q(p_0_in[3]),
+ .R(axi_awready_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ axi_awready_i_1
+ (.I0(s00_axi_aresetn),
+ .O(axi_awready_i_1_n_0));
+ LUT3 #(
+ .INIT(8'h08))
+ axi_awready_i_2
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_awready),
+ .O(axi_awready0));
+ FDRE axi_awready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(axi_awready0),
+ .Q(s00_axi_awready),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000FFFF80008000))
+ axi_bvalid_i_1
+ (.I0(s00_axi_awvalid),
+ .I1(s00_axi_awready),
+ .I2(s00_axi_wready),
+ .I3(s00_axi_wvalid),
+ .I4(s00_axi_bready),
+ .I5(s00_axi_bvalid),
+ .O(axi_bvalid_i_1_n_0));
+ FDRE axi_bvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(axi_bvalid_i_1_n_0),
+ .Q(s00_axi_bvalid),
+ .R(axi_awready_i_1_n_0));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[0]_i_1
+ (.I0(\axi_rdata[0]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[0]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[0]_i_4_n_0 ),
+ .O(reg_data_out[0]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[0]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [0]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[0]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg[0]_0 ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[0]_i_3
+ (.I0(Q[0]),
+ .I1(slv_reg6[0]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[0]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[0]),
+ .O(\axi_rdata[0]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[0]_i_4
+ (.I0(D[32]),
+ .I1(D[0]),
+ .I2(sel0[1]),
+ .I3(\slv_reg1_reg[5]_0 [0]),
+ .I4(sel0[0]),
+ .I5(slv_reg0_read[0]),
+ .O(\axi_rdata[0]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[10]_i_1
+ (.I0(\axi_rdata[10]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[10]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[10]_i_4_n_0 ),
+ .O(reg_data_out[10]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[10]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [10]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [2]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[10] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[10]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[10]_i_3
+ (.I0(Q[10]),
+ .I1(slv_reg6[10]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[10]),
+ .O(\axi_rdata[10]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[10]_i_4
+ (.I0(D[42]),
+ .I1(D[10]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[10] ),
+ .O(\axi_rdata[10]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[11]_i_1
+ (.I0(\axi_rdata[11]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[11]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[11]_i_4_n_0 ),
+ .O(reg_data_out[11]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[11]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [11]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [3]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[11] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[11]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[11]_i_3
+ (.I0(Q[11]),
+ .I1(slv_reg6[11]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[11]),
+ .O(\axi_rdata[11]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[11]_i_4
+ (.I0(D[43]),
+ .I1(D[11]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[11] ),
+ .O(\axi_rdata[11]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[12]_i_1
+ (.I0(\axi_rdata[12]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[12]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[12]_i_4_n_0 ),
+ .O(reg_data_out[12]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[12]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [12]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [4]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[12] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[12]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[12]_i_3
+ (.I0(Q[12]),
+ .I1(slv_reg6[12]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[12]),
+ .O(\axi_rdata[12]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[12]_i_4
+ (.I0(D[44]),
+ .I1(D[12]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[12] ),
+ .O(\axi_rdata[12]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[13]_i_1
+ (.I0(\axi_rdata[13]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[13]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[13]_i_4_n_0 ),
+ .O(reg_data_out[13]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[13]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [13]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [5]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[13] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[13]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[13]_i_3
+ (.I0(Q[13]),
+ .I1(slv_reg6[13]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[13]),
+ .O(\axi_rdata[13]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[13]_i_4
+ (.I0(D[45]),
+ .I1(D[13]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[13] ),
+ .O(\axi_rdata[13]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[14]_i_1
+ (.I0(\axi_rdata[14]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[14]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[14]_i_4_n_0 ),
+ .O(reg_data_out[14]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[14]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [14]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [6]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[14] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[14]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[14]_i_3
+ (.I0(Q[14]),
+ .I1(slv_reg6[14]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[14]),
+ .O(\axi_rdata[14]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[14]_i_4
+ (.I0(D[46]),
+ .I1(D[14]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[14] ),
+ .O(\axi_rdata[14]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[15]_i_1
+ (.I0(\axi_rdata[15]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[15]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[15]_i_4_n_0 ),
+ .O(reg_data_out[15]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[15]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [15]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [7]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[15] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[15]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[15]_i_3
+ (.I0(Q[15]),
+ .I1(slv_reg6[15]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[15]),
+ .O(\axi_rdata[15]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[15]_i_4
+ (.I0(D[47]),
+ .I1(D[15]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[15] ),
+ .O(\axi_rdata[15]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[16]_i_1
+ (.I0(\axi_rdata[16]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[16]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[16]_i_4_n_0 ),
+ .O(reg_data_out[16]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[16]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [16]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [8]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[16] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[16]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[16]_i_3
+ (.I0(Q[16]),
+ .I1(slv_reg6[16]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[16]),
+ .O(\axi_rdata[16]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[16]_i_4
+ (.I0(D[48]),
+ .I1(D[16]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[16] ),
+ .O(\axi_rdata[16]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[17]_i_1
+ (.I0(\axi_rdata[17]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[17]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[17]_i_4_n_0 ),
+ .O(reg_data_out[17]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[17]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [17]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [9]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[17] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[17]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[17]_i_3
+ (.I0(Q[17]),
+ .I1(slv_reg6[17]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[17]),
+ .O(\axi_rdata[17]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[17]_i_4
+ (.I0(D[49]),
+ .I1(D[17]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[17] ),
+ .O(\axi_rdata[17]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[18]_i_1
+ (.I0(\axi_rdata[18]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[18]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[18]_i_4_n_0 ),
+ .O(reg_data_out[18]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[18]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [18]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [10]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[18] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[18]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[18]_i_3
+ (.I0(Q[18]),
+ .I1(slv_reg6[18]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[18]),
+ .O(\axi_rdata[18]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[18]_i_4
+ (.I0(D[50]),
+ .I1(D[18]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[18] ),
+ .O(\axi_rdata[18]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[19]_i_1
+ (.I0(\axi_rdata[19]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[19]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[19]_i_4_n_0 ),
+ .O(reg_data_out[19]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[19]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [19]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [11]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[19] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[19]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[19]_i_3
+ (.I0(Q[19]),
+ .I1(slv_reg6[19]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[19]),
+ .O(\axi_rdata[19]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[19]_i_4
+ (.I0(D[51]),
+ .I1(D[19]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[19] ),
+ .O(\axi_rdata[19]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[1]_i_1
+ (.I0(\axi_rdata[1]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[1]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[1]_i_4_n_0 ),
+ .O(reg_data_out[1]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[1]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [1]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[1]),
+ .I3(sel0[1]),
+ .I4(axi_config),
+ .I5(sel0[2]),
+ .O(\axi_rdata[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[1]_i_3
+ (.I0(Q[1]),
+ .I1(slv_reg6[1]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[1]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[1]),
+ .O(\axi_rdata[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[1]_i_4
+ (.I0(D[33]),
+ .I1(D[1]),
+ .I2(sel0[1]),
+ .I3(\slv_reg1_reg[5]_0 [1]),
+ .I4(sel0[0]),
+ .I5(slv_reg0_read[1]),
+ .O(\axi_rdata[1]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[20]_i_1
+ (.I0(\axi_rdata[20]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[20]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[20]_i_4_n_0 ),
+ .O(reg_data_out[20]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[20]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [20]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[0]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[20] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[20]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[20]_i_3
+ (.I0(Q[20]),
+ .I1(slv_reg6[20]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[20]),
+ .O(\axi_rdata[20]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[20]_i_4
+ (.I0(D[52]),
+ .I1(D[20]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[20] ),
+ .O(\axi_rdata[20]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[21]_i_1
+ (.I0(\axi_rdata[21]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[21]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[21]_i_4_n_0 ),
+ .O(reg_data_out[21]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[21]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [21]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[1]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[21] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[21]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[21]_i_3
+ (.I0(Q[21]),
+ .I1(slv_reg6[21]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[21]),
+ .O(\axi_rdata[21]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[21]_i_4
+ (.I0(D[53]),
+ .I1(D[21]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[21] ),
+ .O(\axi_rdata[21]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[22]_i_1
+ (.I0(\axi_rdata[22]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[22]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[22]_i_4_n_0 ),
+ .O(reg_data_out[22]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[22]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [22]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[2]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[22] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[22]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[22]_i_3
+ (.I0(Q[22]),
+ .I1(slv_reg6[22]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[22]),
+ .O(\axi_rdata[22]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[22]_i_4
+ (.I0(D[54]),
+ .I1(D[22]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[22] ),
+ .O(\axi_rdata[22]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[23]_i_1
+ (.I0(\axi_rdata[23]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[23]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[23]_i_4_n_0 ),
+ .O(reg_data_out[23]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[23]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [23]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[3]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[23] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[23]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[23]_i_3
+ (.I0(Q[23]),
+ .I1(slv_reg6[23]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[23]),
+ .O(\axi_rdata[23]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[23]_i_4
+ (.I0(D[55]),
+ .I1(D[23]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[23] ),
+ .O(\axi_rdata[23]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[24]_i_1
+ (.I0(\axi_rdata[24]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[24]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[24]_i_4_n_0 ),
+ .O(reg_data_out[24]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[24]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [24]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[4]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[24] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[24]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[24]_i_3
+ (.I0(Q[24]),
+ .I1(slv_reg6[24]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[24]),
+ .O(\axi_rdata[24]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[24]_i_4
+ (.I0(D[56]),
+ .I1(D[24]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[24] ),
+ .O(\axi_rdata[24]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[25]_i_1
+ (.I0(\axi_rdata[25]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[25]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[25]_i_4_n_0 ),
+ .O(reg_data_out[25]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[25]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [25]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[5]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[25] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[25]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[25]_i_3
+ (.I0(Q[25]),
+ .I1(slv_reg6[25]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[25]),
+ .O(\axi_rdata[25]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[25]_i_4
+ (.I0(D[57]),
+ .I1(D[25]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[25] ),
+ .O(\axi_rdata[25]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[26]_i_1
+ (.I0(\axi_rdata[26]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[26]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[26]_i_4_n_0 ),
+ .O(reg_data_out[26]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[26]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [26]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[6]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[26] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[26]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[26]_i_3
+ (.I0(Q[26]),
+ .I1(slv_reg6[26]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[26]),
+ .O(\axi_rdata[26]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[26]_i_4
+ (.I0(D[58]),
+ .I1(D[26]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[26] ),
+ .O(\axi_rdata[26]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[27]_i_1
+ (.I0(\axi_rdata[27]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[27]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[27]_i_4_n_0 ),
+ .O(reg_data_out[27]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[27]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [27]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[7]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[27] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[27]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[27]_i_3
+ (.I0(Q[27]),
+ .I1(slv_reg6[27]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[27]),
+ .O(\axi_rdata[27]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[27]_i_4
+ (.I0(D[59]),
+ .I1(D[27]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[27] ),
+ .O(\axi_rdata[27]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[28]_i_1
+ (.I0(\axi_rdata[28]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[28]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[28]_i_4_n_0 ),
+ .O(reg_data_out[28]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[28]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [28]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[8]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[28] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[28]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[28]_i_3
+ (.I0(Q[28]),
+ .I1(slv_reg6[28]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[28]),
+ .O(\axi_rdata[28]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[28]_i_4
+ (.I0(D[60]),
+ .I1(D[28]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[28] ),
+ .O(\axi_rdata[28]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[29]_i_1
+ (.I0(\axi_rdata[29]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[29]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[29]_i_4_n_0 ),
+ .O(reg_data_out[29]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[29]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [29]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[9]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[29] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[29]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[29]_i_3
+ (.I0(Q[29]),
+ .I1(slv_reg6[29]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[29]),
+ .O(\axi_rdata[29]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[29]_i_4
+ (.I0(D[61]),
+ .I1(D[29]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[29] ),
+ .O(\axi_rdata[29]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[2]_i_1
+ (.I0(\axi_rdata[2]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[2]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[2]_i_4_n_0 ),
+ .O(reg_data_out[2]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[2]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [2]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[2]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[2] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[2]_i_3
+ (.I0(Q[2]),
+ .I1(slv_reg6[2]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[2]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[2]),
+ .O(\axi_rdata[2]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[2]_i_4
+ (.I0(D[34]),
+ .I1(D[2]),
+ .I2(sel0[1]),
+ .I3(\slv_reg1_reg[5]_0 [2]),
+ .I4(sel0[0]),
+ .I5(slv_reg0_read[2]),
+ .O(\axi_rdata[2]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[30]_i_1
+ (.I0(\axi_rdata[30]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[30]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[30]_i_4_n_0 ),
+ .O(reg_data_out[30]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[30]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [30]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[10]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[30] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[30]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[30]_i_3
+ (.I0(Q[30]),
+ .I1(slv_reg6[30]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[30]),
+ .O(\axi_rdata[30]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[30]_i_4
+ (.I0(D[62]),
+ .I1(D[30]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[30] ),
+ .O(\axi_rdata[30]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'h08))
+ \axi_rdata[31]_i_1
+ (.I0(s00_axi_arready),
+ .I1(s00_axi_arvalid),
+ .I2(s00_axi_rvalid),
+ .O(slv_reg_rden));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[31]_i_2
+ (.I0(\axi_rdata[31]_i_3_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[31]_i_4_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[31]_i_5_n_0 ),
+ .O(reg_data_out[31]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[31]_i_3
+ (.I0(\slv_reg8_reg[31]_0 [31]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MAX[11]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[31] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[31]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[31]_i_4
+ (.I0(Q[31]),
+ .I1(slv_reg6[31]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[31]),
+ .O(\axi_rdata[31]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[31]_i_5
+ (.I0(D[63]),
+ .I1(D[31]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[31] ),
+ .O(\axi_rdata[31]_i_5_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[3]_i_1
+ (.I0(\axi_rdata[3]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[3]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[3]_i_4_n_0 ),
+ .O(reg_data_out[3]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[3]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [3]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[3]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[3] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[3]_i_3
+ (.I0(Q[3]),
+ .I1(slv_reg6[3]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[3]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[3]),
+ .O(\axi_rdata[3]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[3]_i_4
+ (.I0(D[35]),
+ .I1(D[3]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg[5]_0 [3]),
+ .O(\axi_rdata[3]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[4]_i_1
+ (.I0(\axi_rdata[4]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[4]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[4]_i_4_n_0 ),
+ .O(reg_data_out[4]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[4]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [4]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[4]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[4] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[4]_i_3
+ (.I0(Q[4]),
+ .I1(slv_reg6[4]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[4]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[4]),
+ .O(\axi_rdata[4]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[4]_i_4
+ (.I0(D[36]),
+ .I1(D[4]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg[5]_0 [4]),
+ .O(\axi_rdata[4]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[5]_i_1
+ (.I0(\axi_rdata[5]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[5]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[5]_i_4_n_0 ),
+ .O(reg_data_out[5]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[5]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [5]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[5]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[5] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \axi_rdata[5]_i_3
+ (.I0(Q[5]),
+ .I1(slv_reg6[5]),
+ .I2(sel0[1]),
+ .I3(slv_reg5[5]),
+ .I4(sel0[0]),
+ .I5(slv_reg4[5]),
+ .O(\axi_rdata[5]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[5]_i_4
+ (.I0(D[37]),
+ .I1(D[5]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg[5]_0 [5]),
+ .O(\axi_rdata[5]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[6]_i_1
+ (.I0(\axi_rdata[6]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[6]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[6]_i_4_n_0 ),
+ .O(reg_data_out[6]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[6]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [6]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[6]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[6] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[6]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[6]_i_3
+ (.I0(Q[6]),
+ .I1(slv_reg6[6]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[6]),
+ .O(\axi_rdata[6]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[6]_i_4
+ (.I0(D[38]),
+ .I1(D[6]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[6] ),
+ .O(\axi_rdata[6]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[7]_i_1
+ (.I0(\axi_rdata[7]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[7]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[7]_i_4_n_0 ),
+ .O(reg_data_out[7]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[7]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [7]),
+ .I1(sel0[0]),
+ .I2(TICKS_BITGAP_MIN[7]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[7] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[7]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[7]_i_3
+ (.I0(Q[7]),
+ .I1(slv_reg6[7]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[7]),
+ .O(\axi_rdata[7]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[7]_i_4
+ (.I0(D[39]),
+ .I1(D[7]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[7] ),
+ .O(\axi_rdata[7]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[8]_i_1
+ (.I0(\axi_rdata[8]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[8]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[8]_i_4_n_0 ),
+ .O(reg_data_out[8]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[8]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [8]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [0]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[8] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[8]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[8]_i_3
+ (.I0(Q[8]),
+ .I1(slv_reg6[8]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[8]),
+ .O(\axi_rdata[8]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[8]_i_4
+ (.I0(D[40]),
+ .I1(D[8]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[8] ),
+ .O(\axi_rdata[8]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hB8BBB888))
+ \axi_rdata[9]_i_1
+ (.I0(\axi_rdata[9]_i_2_n_0 ),
+ .I1(sel0[3]),
+ .I2(\axi_rdata[9]_i_3_n_0 ),
+ .I3(sel0[2]),
+ .I4(\axi_rdata[9]_i_4_n_0 ),
+ .O(reg_data_out[9]));
+ LUT6 #(
+ .INIT(64'h0000000033E200E2))
+ \axi_rdata[9]_i_2
+ (.I0(\slv_reg8_reg[31]_0 [9]),
+ .I1(sel0[0]),
+ .I2(\slv_reg9_reg[19]_0 [1]),
+ .I3(sel0[1]),
+ .I4(\slv_reg10_reg_n_0_[9] ),
+ .I5(sel0[2]),
+ .O(\axi_rdata[9]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[9]_i_3
+ (.I0(Q[9]),
+ .I1(slv_reg6[9]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(slv_reg5[9]),
+ .O(\axi_rdata[9]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'hAFC0A0C0))
+ \axi_rdata[9]_i_4
+ (.I0(D[41]),
+ .I1(D[9]),
+ .I2(sel0[1]),
+ .I3(sel0[0]),
+ .I4(\slv_reg1_reg_n_0_[9] ),
+ .O(\axi_rdata[9]_i_4_n_0 ));
+ FDRE \axi_rdata_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[0]),
+ .Q(s00_axi_rdata[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[10]),
+ .Q(s00_axi_rdata[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[11]),
+ .Q(s00_axi_rdata[11]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[12]),
+ .Q(s00_axi_rdata[12]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[13]),
+ .Q(s00_axi_rdata[13]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[14]),
+ .Q(s00_axi_rdata[14]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[15]),
+ .Q(s00_axi_rdata[15]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[16]),
+ .Q(s00_axi_rdata[16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[17]),
+ .Q(s00_axi_rdata[17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[18]),
+ .Q(s00_axi_rdata[18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[19]),
+ .Q(s00_axi_rdata[19]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[1]),
+ .Q(s00_axi_rdata[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[20]),
+ .Q(s00_axi_rdata[20]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[21]),
+ .Q(s00_axi_rdata[21]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[22]),
+ .Q(s00_axi_rdata[22]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[23]),
+ .Q(s00_axi_rdata[23]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[24]),
+ .Q(s00_axi_rdata[24]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[25]),
+ .Q(s00_axi_rdata[25]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[26]),
+ .Q(s00_axi_rdata[26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[27]),
+ .Q(s00_axi_rdata[27]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[28]),
+ .Q(s00_axi_rdata[28]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[29]),
+ .Q(s00_axi_rdata[29]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[2]),
+ .Q(s00_axi_rdata[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[30]),
+ .Q(s00_axi_rdata[30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[31]),
+ .Q(s00_axi_rdata[31]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[3]),
+ .Q(s00_axi_rdata[3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[4]),
+ .Q(s00_axi_rdata[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[5]),
+ .Q(s00_axi_rdata[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[6]),
+ .Q(s00_axi_rdata[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[7]),
+ .Q(s00_axi_rdata[7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[8]),
+ .Q(s00_axi_rdata[8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \axi_rdata_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(slv_reg_rden),
+ .D(reg_data_out[9]),
+ .Q(s00_axi_rdata[9]),
+ .R(axi_awready_i_1_n_0));
+ LUT4 #(
+ .INIT(16'h08F8))
+ axi_rvalid_i_1
+ (.I0(s00_axi_arvalid),
+ .I1(s00_axi_arready),
+ .I2(s00_axi_rvalid),
+ .I3(s00_axi_rready),
+ .O(axi_rvalid_i_1_n_0));
+ FDRE axi_rvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(axi_rvalid_i_1_n_0),
+ .Q(s00_axi_rvalid),
+ .R(axi_awready_i_1_n_0));
+ LUT3 #(
+ .INIT(8'h08))
+ axi_wready_i_1
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_wready),
+ .O(axi_wready0));
+ FDRE axi_wready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(axi_wready0),
+ .Q(s00_axi_wready),
+ .R(axi_awready_i_1_n_0));
+ LUT2 #(
+ .INIT(4'h6))
+ cmd_out_INST_0
+ (.I0(seriali_buf),
+ .I1(axi_config),
+ .O(cmd_out));
+ LUT2 #(
+ .INIT(4'hE))
+ \counter[11]__0_i_1
+ (.I0(axi_control[1]),
+ .I1(axi_control[0]),
+ .O(\slv_reg0_pulse_reg[1]_0 ));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry__0_i_3__0
+ (.I0(\slv_reg8_reg[31]_0 [31]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [11]),
+ .I2(\slv_reg8_reg[31]_0 [30]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [10]),
+ .O(\slv_reg8_reg[31]_1 [1]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry__0_i_4__0
+ (.I0(\slv_reg8_reg[31]_0 [29]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [9]),
+ .I2(\slv_reg8_reg[31]_0 [28]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [8]),
+ .O(\slv_reg8_reg[31]_1 [0]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_5__0
+ (.I0(Q[7]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [7]),
+ .I2(Q[6]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [6]),
+ .O(S[3]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_5__1
+ (.I0(\slv_reg8_reg[31]_0 [27]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [7]),
+ .I2(\slv_reg8_reg[31]_0 [26]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [6]),
+ .O(\slv_reg8_reg[27]_0 [3]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_5__2
+ (.I0(\slv_reg8_reg[31]_0 [7]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [7]),
+ .I2(\slv_reg8_reg[31]_0 [6]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [6]),
+ .O(\slv_reg8_reg[7]_0 [3]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_6__0
+ (.I0(Q[5]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [5]),
+ .I2(Q[4]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [4]),
+ .O(S[2]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_6__1
+ (.I0(\slv_reg8_reg[31]_0 [25]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [5]),
+ .I2(\slv_reg8_reg[31]_0 [24]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [4]),
+ .O(\slv_reg8_reg[27]_0 [2]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_6__2
+ (.I0(\slv_reg8_reg[31]_0 [5]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [5]),
+ .I2(\slv_reg8_reg[31]_0 [4]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [4]),
+ .O(\slv_reg8_reg[7]_0 [2]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_7__0
+ (.I0(Q[3]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [3]),
+ .I2(Q[2]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [2]),
+ .O(S[1]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_7__1
+ (.I0(\slv_reg8_reg[31]_0 [23]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [3]),
+ .I2(\slv_reg8_reg[31]_0 [22]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [2]),
+ .O(\slv_reg8_reg[27]_0 [1]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_7__2
+ (.I0(\slv_reg8_reg[31]_0 [3]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [3]),
+ .I2(\slv_reg8_reg[31]_0 [2]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [2]),
+ .O(\slv_reg8_reg[7]_0 [1]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_8__0
+ (.I0(Q[1]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [1]),
+ .I2(Q[0]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [0]),
+ .O(S[0]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_8__1
+ (.I0(\slv_reg8_reg[31]_0 [21]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [1]),
+ .I2(\slv_reg8_reg[31]_0 [20]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [0]),
+ .O(\slv_reg8_reg[27]_0 [0]));
+ LUT4 #(
+ .INIT(16'h9009))
+ i__carry_i_8__2
+ (.I0(\slv_reg8_reg[31]_0 [1]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [1]),
+ .I2(\slv_reg8_reg[31]_0 [0]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [0]),
+ .O(\slv_reg8_reg[7]_0 [0]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry__0_i_1
+ (.I0(Q[31]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [11]),
+ .I2(Q[30]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [10]),
+ .O(\slv_reg7_reg[31]_0 [1]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry__0_i_2
+ (.I0(Q[29]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [9]),
+ .I2(Q[28]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [8]),
+ .O(\slv_reg7_reg[31]_0 [0]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry_i_1
+ (.I0(Q[27]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [7]),
+ .I2(Q[26]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [6]),
+ .O(DI[3]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry_i_2
+ (.I0(Q[25]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [5]),
+ .I2(Q[24]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [4]),
+ .O(DI[2]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry_i_3
+ (.I0(Q[23]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [3]),
+ .I2(Q[22]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [2]),
+ .O(DI[1]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ reg_nbitsout2_carry_i_4
+ (.I0(Q[21]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0 [1]),
+ .I2(Q[20]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0 [0]),
+ .O(DI[0]));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \slv_reg0_pulse[0]_i_1
+ (.I0(axi_control[0]),
+ .I1(p_1_in),
+ .I2(s00_axi_wdata[0]),
+ .I3(slv_reg_wren__2),
+ .I4(s00_axi_aresetn),
+ .O(\slv_reg0_pulse[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \slv_reg0_pulse[1]_i_1
+ (.I0(axi_control[1]),
+ .I1(p_1_in),
+ .I2(s00_axi_wdata[1]),
+ .I3(slv_reg_wren__2),
+ .I4(s00_axi_aresetn),
+ .O(\slv_reg0_pulse[1]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h00000010))
+ \slv_reg0_pulse[1]_i_2
+ (.I0(p_0_in[3]),
+ .I1(p_0_in[2]),
+ .I2(s00_axi_wstrb[0]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[1]),
+ .O(p_1_in));
+ LUT4 #(
+ .INIT(16'h8000))
+ \slv_reg0_pulse[1]_i_3
+ (.I0(s00_axi_awvalid),
+ .I1(s00_axi_awready),
+ .I2(s00_axi_wready),
+ .I3(s00_axi_wvalid),
+ .O(slv_reg_wren__2));
+ FDRE \slv_reg0_pulse_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg0_pulse[0]_i_1_n_0 ),
+ .Q(axi_control[0]),
+ .R(1'b0));
+ FDRE \slv_reg0_pulse_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg0_pulse[1]_i_1_n_0 ),
+ .Q(axi_control[1]),
+ .R(1'b0));
+ FDRE \slv_reg0_read_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg0_read_reg[2]_0 [0]),
+ .Q(slv_reg0_read[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg0_read_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg0_read_reg[2]_0 [1]),
+ .Q(slv_reg0_read[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg0_read_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg0_read_reg[2]_0 [2]),
+ .Q(slv_reg0_read[2]),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg10[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(s00_axi_wstrb[1]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[0]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg10[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg10[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(s00_axi_wstrb[2]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[0]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg10[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg10[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(s00_axi_wstrb[3]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[0]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg10[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg10[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(s00_axi_wstrb[0]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[0]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg10[7]_i_1_n_0 ));
+ FDRE \slv_reg10_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(\slv_reg10_reg[0]_0 ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(\slv_reg10_reg_n_0_[10] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(\slv_reg10_reg_n_0_[11] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(\slv_reg10_reg_n_0_[12] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(\slv_reg10_reg_n_0_[13] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(\slv_reg10_reg_n_0_[14] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(\slv_reg10_reg_n_0_[15] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(\slv_reg10_reg_n_0_[16] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(\slv_reg10_reg_n_0_[17] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(\slv_reg10_reg_n_0_[18] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(\slv_reg10_reg_n_0_[19] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(axi_config),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(\slv_reg10_reg_n_0_[20] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(\slv_reg10_reg_n_0_[21] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(\slv_reg10_reg_n_0_[22] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(\slv_reg10_reg_n_0_[23] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(\slv_reg10_reg_n_0_[24] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(\slv_reg10_reg_n_0_[25] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(\slv_reg10_reg_n_0_[26] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(\slv_reg10_reg_n_0_[27] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(\slv_reg10_reg_n_0_[28] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(\slv_reg10_reg_n_0_[29] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(\slv_reg10_reg_n_0_[2] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(\slv_reg10_reg_n_0_[30] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(\slv_reg10_reg_n_0_[31] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(\slv_reg10_reg_n_0_[3] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(\slv_reg10_reg_n_0_[4] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(\slv_reg10_reg_n_0_[5] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(\slv_reg10_reg_n_0_[6] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(\slv_reg10_reg_n_0_[7] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(\slv_reg10_reg_n_0_[8] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg10_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg10[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(\slv_reg10_reg_n_0_[9] ),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg1[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[1]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[0]),
+ .O(\slv_reg1[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg1[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[2]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[0]),
+ .O(\slv_reg1[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg1[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[3]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[0]),
+ .O(\slv_reg1[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg1[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[0]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[0]),
+ .O(\slv_reg1[7]_i_1_n_0 ));
+ FDRE \slv_reg1_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(\slv_reg1_reg[5]_0 [0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(\slv_reg1_reg_n_0_[10] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(\slv_reg1_reg_n_0_[11] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(\slv_reg1_reg_n_0_[12] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(\slv_reg1_reg_n_0_[13] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(\slv_reg1_reg_n_0_[14] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(\slv_reg1_reg_n_0_[15] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(\slv_reg1_reg_n_0_[16] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(\slv_reg1_reg_n_0_[17] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(\slv_reg1_reg_n_0_[18] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(\slv_reg1_reg_n_0_[19] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(\slv_reg1_reg[5]_0 [1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(\slv_reg1_reg_n_0_[20] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(\slv_reg1_reg_n_0_[21] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(\slv_reg1_reg_n_0_[22] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(\slv_reg1_reg_n_0_[23] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(\slv_reg1_reg_n_0_[24] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(\slv_reg1_reg_n_0_[25] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(\slv_reg1_reg_n_0_[26] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(\slv_reg1_reg_n_0_[27] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(\slv_reg1_reg_n_0_[28] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(\slv_reg1_reg_n_0_[29] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(\slv_reg1_reg[5]_0 [2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(\slv_reg1_reg_n_0_[30] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(\slv_reg1_reg_n_0_[31] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(\slv_reg1_reg[5]_0 [3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(\slv_reg1_reg[5]_0 [4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(\slv_reg1_reg[5]_0 [5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(\slv_reg1_reg_n_0_[6] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(\slv_reg1_reg_n_0_[7] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(\slv_reg1_reg_n_0_[8] ),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg1_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg1[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(\slv_reg1_reg_n_0_[9] ),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg2[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[1]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[1]),
+ .O(\slv_reg2[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg2[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[2]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[1]),
+ .O(\slv_reg2[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg2[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[3]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[1]),
+ .O(\slv_reg2[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg2[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[0]),
+ .I2(p_0_in[3]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[1]),
+ .O(\slv_reg2[7]_i_1_n_0 ));
+ FDRE \slv_reg2_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(D[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(D[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(D[11]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(D[12]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(D[13]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(D[14]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(D[15]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(D[16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(D[17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(D[18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(D[19]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(D[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(D[20]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(D[21]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(D[22]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(D[23]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(D[24]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(D[25]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(D[26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(D[27]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(D[28]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(D[29]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(D[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(D[30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(D[31]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(D[3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(D[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(D[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(D[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(D[7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(D[8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg2_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg2[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(D[9]),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg3[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[1]),
+ .I2(p_0_in[0]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg3[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg3[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[2]),
+ .I2(p_0_in[0]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg3[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg3[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[3]),
+ .I2(p_0_in[0]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg3[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg3[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(s00_axi_wstrb[0]),
+ .I2(p_0_in[0]),
+ .I3(p_0_in[1]),
+ .I4(p_0_in[2]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg3[7]_i_1_n_0 ));
+ FDRE \slv_reg3_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(D[32]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(D[42]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(D[43]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(D[44]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(D[45]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(D[46]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(D[47]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(D[48]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(D[49]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(D[50]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(D[51]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(D[33]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(D[52]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(D[53]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(D[54]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(D[55]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(D[56]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(D[57]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(D[58]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(D[59]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(D[60]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(D[61]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(D[34]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(D[62]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(D[63]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(D[35]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(D[36]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(D[37]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(D[38]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(D[39]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(D[40]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg3_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg3[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(D[41]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [0]),
+ .Q(slv_reg4[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [1]),
+ .Q(slv_reg4[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [2]),
+ .Q(slv_reg4[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [3]),
+ .Q(slv_reg4[3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [4]),
+ .Q(slv_reg4[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg4_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg4_reg[5]_0 [5]),
+ .Q(slv_reg4[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [0]),
+ .Q(slv_reg5[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [10]),
+ .Q(slv_reg5[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [11]),
+ .Q(slv_reg5[11]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [12]),
+ .Q(slv_reg5[12]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [13]),
+ .Q(slv_reg5[13]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [14]),
+ .Q(slv_reg5[14]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [15]),
+ .Q(slv_reg5[15]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [16]),
+ .Q(slv_reg5[16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [17]),
+ .Q(slv_reg5[17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [18]),
+ .Q(slv_reg5[18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [19]),
+ .Q(slv_reg5[19]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [1]),
+ .Q(slv_reg5[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [20]),
+ .Q(slv_reg5[20]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [21]),
+ .Q(slv_reg5[21]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [22]),
+ .Q(slv_reg5[22]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [23]),
+ .Q(slv_reg5[23]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [24]),
+ .Q(slv_reg5[24]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [25]),
+ .Q(slv_reg5[25]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [26]),
+ .Q(slv_reg5[26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [27]),
+ .Q(slv_reg5[27]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [28]),
+ .Q(slv_reg5[28]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [29]),
+ .Q(slv_reg5[29]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [2]),
+ .Q(slv_reg5[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [30]),
+ .Q(slv_reg5[30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [31]),
+ .Q(slv_reg5[31]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [3]),
+ .Q(slv_reg5[3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [4]),
+ .Q(slv_reg5[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [5]),
+ .Q(slv_reg5[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [6]),
+ .Q(slv_reg5[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [7]),
+ .Q(slv_reg5[7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [8]),
+ .Q(slv_reg5[8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg5_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [9]),
+ .Q(slv_reg5[9]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [32]),
+ .Q(slv_reg6[0]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [42]),
+ .Q(slv_reg6[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [43]),
+ .Q(slv_reg6[11]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [44]),
+ .Q(slv_reg6[12]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [45]),
+ .Q(slv_reg6[13]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [46]),
+ .Q(slv_reg6[14]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [47]),
+ .Q(slv_reg6[15]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [48]),
+ .Q(slv_reg6[16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [49]),
+ .Q(slv_reg6[17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [50]),
+ .Q(slv_reg6[18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [51]),
+ .Q(slv_reg6[19]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [33]),
+ .Q(slv_reg6[1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [52]),
+ .Q(slv_reg6[20]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [53]),
+ .Q(slv_reg6[21]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [54]),
+ .Q(slv_reg6[22]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [55]),
+ .Q(slv_reg6[23]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [56]),
+ .Q(slv_reg6[24]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [57]),
+ .Q(slv_reg6[25]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [58]),
+ .Q(slv_reg6[26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [59]),
+ .Q(slv_reg6[27]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [60]),
+ .Q(slv_reg6[28]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [61]),
+ .Q(slv_reg6[29]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [34]),
+ .Q(slv_reg6[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [62]),
+ .Q(slv_reg6[30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [63]),
+ .Q(slv_reg6[31]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [35]),
+ .Q(slv_reg6[3]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [36]),
+ .Q(slv_reg6[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [37]),
+ .Q(slv_reg6[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [38]),
+ .Q(slv_reg6[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [39]),
+ .Q(slv_reg6[7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [40]),
+ .Q(slv_reg6[8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg6_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\slv_reg6_reg[31]_0 [41]),
+ .Q(slv_reg6[9]),
+ .R(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000080000000))
+ \slv_reg7[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[2]),
+ .I2(s00_axi_wstrb[1]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg7[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000080000000))
+ \slv_reg7[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[2]),
+ .I2(s00_axi_wstrb[2]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg7[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000080000000))
+ \slv_reg7[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[2]),
+ .I2(s00_axi_wstrb[3]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg7[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000080000000))
+ \slv_reg7[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[2]),
+ .I2(s00_axi_wstrb[0]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[3]),
+ .O(\slv_reg7[7]_i_1_n_0 ));
+ FDSE \slv_reg7_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(Q[0]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(Q[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(Q[11]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(Q[12]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(Q[13]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(Q[14]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(Q[15]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(Q[16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(Q[17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(Q[18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(Q[19]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(Q[1]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(Q[20]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(Q[21]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(Q[22]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(Q[23]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(Q[24]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(Q[25]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(Q[26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(Q[27]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(Q[28]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(Q[29]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(Q[2]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(Q[30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(Q[31]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(Q[3]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(Q[4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(Q[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(Q[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg7_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(Q[7]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(Q[8]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg7_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg7[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(Q[9]),
+ .S(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg8[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[1]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(s00_axi_wstrb[1]),
+ .O(\slv_reg8[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg8[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[1]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(s00_axi_wstrb[2]),
+ .O(\slv_reg8[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg8[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[1]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(s00_axi_wstrb[3]),
+ .O(\slv_reg8[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000800000000))
+ \slv_reg8[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[1]),
+ .I3(p_0_in[0]),
+ .I4(p_0_in[2]),
+ .I5(s00_axi_wstrb[0]),
+ .O(\slv_reg8[7]_i_1_n_0 ));
+ FDRE \slv_reg8_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(\slv_reg8_reg[31]_0 [0]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(\slv_reg8_reg[31]_0 [10]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(\slv_reg8_reg[31]_0 [11]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(\slv_reg8_reg[31]_0 [12]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(\slv_reg8_reg[31]_0 [13]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(\slv_reg8_reg[31]_0 [14]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(\slv_reg8_reg[31]_0 [15]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(\slv_reg8_reg[31]_0 [16]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(\slv_reg8_reg[31]_0 [17]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(\slv_reg8_reg[31]_0 [18]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(\slv_reg8_reg[31]_0 [19]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(\slv_reg8_reg[31]_0 [1]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(\slv_reg8_reg[31]_0 [20]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(\slv_reg8_reg[31]_0 [21]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(\slv_reg8_reg[31]_0 [22]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(\slv_reg8_reg[31]_0 [23]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(\slv_reg8_reg[31]_0 [24]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(\slv_reg8_reg[31]_0 [25]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(\slv_reg8_reg[31]_0 [26]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(\slv_reg8_reg[31]_0 [27]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(\slv_reg8_reg[31]_0 [28]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(\slv_reg8_reg[31]_0 [29]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(\slv_reg8_reg[31]_0 [2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(\slv_reg8_reg[31]_0 [30]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(\slv_reg8_reg[31]_0 [31]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(\slv_reg8_reg[31]_0 [3]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(\slv_reg8_reg[31]_0 [4]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(\slv_reg8_reg[31]_0 [5]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(\slv_reg8_reg[31]_0 [6]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(\slv_reg8_reg[31]_0 [7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg8_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(\slv_reg8_reg[31]_0 [8]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg8_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg8[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(\slv_reg8_reg[31]_0 [9]),
+ .S(axi_awready_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg9[15]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[0]),
+ .I3(s00_axi_wstrb[1]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg9[15]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg9[23]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[0]),
+ .I3(s00_axi_wstrb[2]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg9[23]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg9[31]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[0]),
+ .I3(s00_axi_wstrb[3]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg9[31]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000008000))
+ \slv_reg9[7]_i_1
+ (.I0(slv_reg_wren__2),
+ .I1(p_0_in[3]),
+ .I2(p_0_in[0]),
+ .I3(s00_axi_wstrb[0]),
+ .I4(p_0_in[1]),
+ .I5(p_0_in[2]),
+ .O(\slv_reg9[7]_i_1_n_0 ));
+ FDSE \slv_reg9_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[0]),
+ .Q(TICKS_BITGAP_MIN[0]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[10]),
+ .Q(\slv_reg9_reg[19]_0 [2]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[11]),
+ .Q(\slv_reg9_reg[19]_0 [3]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[12]),
+ .Q(\slv_reg9_reg[19]_0 [4]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[13]),
+ .Q(\slv_reg9_reg[19]_0 [5]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[14]),
+ .Q(\slv_reg9_reg[19]_0 [6]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[15]),
+ .Q(\slv_reg9_reg[19]_0 [7]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[16]),
+ .Q(\slv_reg9_reg[19]_0 [8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[17]),
+ .Q(\slv_reg9_reg[19]_0 [9]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[18]),
+ .Q(\slv_reg9_reg[19]_0 [10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[19]),
+ .Q(\slv_reg9_reg[19]_0 [11]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[1]),
+ .Q(TICKS_BITGAP_MIN[1]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[20]),
+ .Q(TICKS_BITGAP_MAX[0]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[21]),
+ .Q(TICKS_BITGAP_MAX[1]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[22]),
+ .Q(TICKS_BITGAP_MAX[2]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[23]_i_1_n_0 ),
+ .D(s00_axi_wdata[23]),
+ .Q(TICKS_BITGAP_MAX[3]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[24]),
+ .Q(TICKS_BITGAP_MAX[4]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[25]),
+ .Q(TICKS_BITGAP_MAX[5]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[26]),
+ .Q(TICKS_BITGAP_MAX[6]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[27]),
+ .Q(TICKS_BITGAP_MAX[7]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[28]),
+ .Q(TICKS_BITGAP_MAX[8]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[29]),
+ .Q(TICKS_BITGAP_MAX[9]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[2]),
+ .Q(TICKS_BITGAP_MIN[2]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[30]),
+ .Q(TICKS_BITGAP_MAX[10]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[31]_i_1_n_0 ),
+ .D(s00_axi_wdata[31]),
+ .Q(TICKS_BITGAP_MAX[11]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[3]),
+ .Q(TICKS_BITGAP_MIN[3]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[4]),
+ .Q(TICKS_BITGAP_MIN[4]),
+ .S(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[5]),
+ .Q(TICKS_BITGAP_MIN[5]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[6]),
+ .Q(TICKS_BITGAP_MIN[6]),
+ .R(axi_awready_i_1_n_0));
+ FDRE \slv_reg9_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[7]_i_1_n_0 ),
+ .D(s00_axi_wdata[7]),
+ .Q(TICKS_BITGAP_MIN[7]),
+ .R(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[8]),
+ .Q(\slv_reg9_reg[19]_0 [0]),
+ .S(axi_awready_i_1_n_0));
+ FDSE \slv_reg9_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\slv_reg9[15]_i_1_n_0 ),
+ .D(s00_axi_wdata[9]),
+ .Q(\slv_reg9_reg[19]_0 [1]),
+ .S(axi_awready_i_1_n_0));
+endmodule
+
+(* ORIG_REF_NAME = "endeavour_master" *)
+module TopLevel_endeavour_axi_contro_5_0_endeavour_master
+ (D,
+ cmd_in,
+ Q,
+ \reg_nbitsout_reg[5]_0 ,
+ I,
+ \reg_dataout_reg[63]_0 ,
+ axi_control,
+ cmd_out,
+ s00_axi_aclk,
+ DI,
+ \reg_nbitsout_reg[5]_1 ,
+ S,
+ \reg_nbitsout1_inferred__0/i__carry__0_0 ,
+ \reg_nbitsout_reg[5]_2 ,
+ \reg_nbitsout1_inferred__1/i__carry__0_0 ,
+ \reg_nbitsin_reg[5]_0 ,
+ reg_nbitsout2_carry__0_0,
+ \reg_nbitsout1_inferred__0/i__carry__0_1 ,
+ CMD_IN_P,
+ \counter_reg[11]_0 ,
+ \reg_nbitsout_reg[5]_3 ,
+ \reg_datain_reg[63]_0 );
+ output [2:0]D;
+ output cmd_in;
+ output [11:0]Q;
+ output [5:0]\reg_nbitsout_reg[5]_0 ;
+ output I;
+ output [63:0]\reg_dataout_reg[63]_0 ;
+ input [1:0]axi_control;
+ input cmd_out;
+ input s00_axi_aclk;
+ input [3:0]DI;
+ input [1:0]\reg_nbitsout_reg[5]_1 ;
+ input [3:0]S;
+ input [3:0]\reg_nbitsout1_inferred__0/i__carry__0_0 ;
+ input [1:0]\reg_nbitsout_reg[5]_2 ;
+ input [3:0]\reg_nbitsout1_inferred__1/i__carry__0_0 ;
+ input [5:0]\reg_nbitsin_reg[5]_0 ;
+ input [31:0]reg_nbitsout2_carry__0_0;
+ input [31:0]\reg_nbitsout1_inferred__0/i__carry__0_1 ;
+ input [0:0]CMD_IN_P;
+ input [11:0]\counter_reg[11]_0 ;
+ input \reg_nbitsout_reg[5]_3 ;
+ input [63:0]\reg_datain_reg[63]_0 ;
+
+ wire [0:0]CMD_IN_P;
+ wire [2:0]D;
+ wire [3:0]DI;
+ wire \FSM_sequential_fsm_rd[0]_i_1_n_0 ;
+ wire \FSM_sequential_fsm_rd[0]_i_2_n_0 ;
+ wire \FSM_sequential_fsm_rd[1]_i_1_n_0 ;
+ wire \FSM_sequential_fsm_rd[1]_i_2_n_0 ;
+ wire \FSM_sequential_fsm_rd[1]_i_3_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_1_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_2_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_3_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_4_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_5_n_0 ;
+ wire \FSM_sequential_fsm_rd[2]_i_6_n_0 ;
+ wire \FSM_sequential_fsm_wr[0]_i_1_n_0 ;
+ wire \FSM_sequential_fsm_wr[1]_i_1_n_0 ;
+ wire \FSM_sequential_fsm_wr[2]_i_1_n_0 ;
+ wire I;
+ wire [11:0]Q;
+ wire [3:0]S;
+ wire [1:0]axi_control;
+ wire cmd_in;
+ wire cmd_out;
+ wire counter;
+ wire counter0_carry__0_i_1_n_0;
+ wire counter0_carry__0_i_2_n_0;
+ wire counter0_carry__0_i_3_n_0;
+ wire counter0_carry__0_i_4_n_0;
+ wire counter0_carry__0_n_0;
+ wire counter0_carry__0_n_1;
+ wire counter0_carry__0_n_2;
+ wire counter0_carry__0_n_3;
+ wire counter0_carry__1_i_1_n_0;
+ wire counter0_carry__1_i_2_n_0;
+ wire counter0_carry__1_i_3_n_0;
+ wire counter0_carry__1_n_2;
+ wire counter0_carry__1_n_3;
+ wire counter0_carry_i_1_n_0;
+ wire counter0_carry_i_2_n_0;
+ wire counter0_carry_i_3_n_0;
+ wire counter0_carry_i_4_n_0;
+ wire counter0_carry_n_0;
+ wire counter0_carry_n_1;
+ wire counter0_carry_n_2;
+ wire counter0_carry_n_3;
+ wire \counter[0]__0_i_1_n_0 ;
+ wire \counter[0]_i_1_n_0 ;
+ wire \counter[0]_i_2_n_0 ;
+ wire \counter[0]_i_3_n_0 ;
+ wire \counter[10]__0_i_1_n_0 ;
+ wire \counter[10]_i_1_n_0 ;
+ wire \counter[10]_i_2_n_0 ;
+ wire \counter[10]_i_3_n_0 ;
+ wire \counter[11]__0_i_2_n_0 ;
+ wire \counter[11]__0_i_3_n_0 ;
+ wire \counter[11]_i_2_n_0 ;
+ wire \counter[11]_i_3_n_0 ;
+ wire \counter[11]_i_4_n_0 ;
+ wire \counter[1]__0_i_1_n_0 ;
+ wire \counter[1]_i_1_n_0 ;
+ wire \counter[1]_i_2_n_0 ;
+ wire \counter[2]__0_i_1_n_0 ;
+ wire \counter[2]_i_1_n_0 ;
+ wire \counter[2]_i_2_n_0 ;
+ wire \counter[3]__0_i_1_n_0 ;
+ wire \counter[3]_i_1_n_0 ;
+ wire \counter[3]_i_2_n_0 ;
+ wire \counter[3]_i_3_n_0 ;
+ wire \counter[4]__0_i_1_n_0 ;
+ wire \counter[4]_i_1_n_0 ;
+ wire \counter[4]_i_2_n_0 ;
+ wire \counter[5]__0_i_1_n_0 ;
+ wire \counter[5]_i_1_n_0 ;
+ wire \counter[5]_i_2_n_0 ;
+ wire \counter[5]_i_3_n_0 ;
+ wire \counter[6]__0_i_1_n_0 ;
+ wire \counter[6]_i_1_n_0 ;
+ wire \counter[6]_i_2_n_0 ;
+ wire \counter[6]_i_3_n_0 ;
+ wire \counter[7]__0_i_1_n_0 ;
+ wire \counter[7]_i_10_n_0 ;
+ wire \counter[7]_i_11_n_0 ;
+ wire \counter[7]_i_12_n_0 ;
+ wire \counter[7]_i_13_n_0 ;
+ wire \counter[7]_i_14_n_0 ;
+ wire \counter[7]_i_15_n_0 ;
+ wire \counter[7]_i_16_n_0 ;
+ wire \counter[7]_i_17_n_0 ;
+ wire \counter[7]_i_18_n_0 ;
+ wire \counter[7]_i_19_n_0 ;
+ wire \counter[7]_i_1_n_0 ;
+ wire \counter[7]_i_20_n_0 ;
+ wire \counter[7]_i_21_n_0 ;
+ wire \counter[7]_i_22_n_0 ;
+ wire \counter[7]_i_23_n_0 ;
+ wire \counter[7]_i_24_n_0 ;
+ wire \counter[7]_i_25_n_0 ;
+ wire \counter[7]_i_26_n_0 ;
+ wire \counter[7]_i_27_n_0 ;
+ wire \counter[7]_i_2_n_0 ;
+ wire \counter[7]_i_4_n_0 ;
+ wire \counter[7]_i_7_n_0 ;
+ wire \counter[7]_i_8_n_0 ;
+ wire \counter[7]_i_9_n_0 ;
+ wire \counter[8]__0_i_1_n_0 ;
+ wire \counter[8]_i_1_n_0 ;
+ wire \counter[8]_i_2_n_0 ;
+ wire \counter[8]_i_3_n_0 ;
+ wire \counter[9]__0_i_1_n_0 ;
+ wire \counter[9]_i_1_n_0 ;
+ wire \counter[9]_i_2_n_0 ;
+ wire \counter[9]_i_3_n_0 ;
+ wire [11:0]\counter_reg[11]_0 ;
+ wire \counter_reg[11]__0_i_4_n_2 ;
+ wire \counter_reg[11]__0_i_4_n_3 ;
+ wire \counter_reg[7]_i_3_n_0 ;
+ wire \counter_reg[7]_i_5_n_0 ;
+ wire \counter_reg[7]_i_6_n_0 ;
+ wire \counter_reg_n_0_[0] ;
+ wire \counter_reg_n_0_[10] ;
+ wire \counter_reg_n_0_[11] ;
+ wire \counter_reg_n_0_[1] ;
+ wire \counter_reg_n_0_[2] ;
+ wire \counter_reg_n_0_[3] ;
+ wire \counter_reg_n_0_[4] ;
+ wire \counter_reg_n_0_[5] ;
+ wire \counter_reg_n_0_[6] ;
+ wire \counter_reg_n_0_[7] ;
+ wire \counter_reg_n_0_[8] ;
+ wire \counter_reg_n_0_[9] ;
+ wire [11:1]data1;
+ wire fsm_rd02_in;
+ wire \fsm_rd0_inferred__1/i__carry__0_n_3 ;
+ wire \fsm_rd0_inferred__1/i__carry_n_0 ;
+ wire \fsm_rd0_inferred__1/i__carry_n_1 ;
+ wire \fsm_rd0_inferred__1/i__carry_n_2 ;
+ wire \fsm_rd0_inferred__1/i__carry_n_3 ;
+ wire [2:0]fsm_rd__0;
+ wire [2:0]fsm_wr;
+ wire i__carry__0_i_1__0_n_0;
+ wire i__carry__0_i_1__1_n_0;
+ wire i__carry__0_i_1__2_n_0;
+ wire i__carry__0_i_1_n_0;
+ wire i__carry__0_i_2__0_n_0;
+ wire i__carry__0_i_2__1_n_0;
+ wire i__carry__0_i_2__2_n_0;
+ wire i__carry__0_i_2_n_0;
+ wire i__carry__0_i_3__1_n_0;
+ wire i__carry__0_i_3__2_n_0;
+ wire i__carry__0_i_3_n_0;
+ wire i__carry__0_i_4__1_n_0;
+ wire i__carry__0_i_4__2_n_0;
+ wire i__carry__0_i_4_n_0;
+ wire i__carry_i_1__0_n_0;
+ wire i__carry_i_1__1_n_0;
+ wire i__carry_i_1__2_n_0;
+ wire i__carry_i_1_n_0;
+ wire i__carry_i_2__0_n_0;
+ wire i__carry_i_2__1_n_0;
+ wire i__carry_i_2__2_n_0;
+ wire i__carry_i_2__2_n_1;
+ wire i__carry_i_2__2_n_2;
+ wire i__carry_i_2__2_n_3;
+ wire i__carry_i_2_n_0;
+ wire i__carry_i_3__0_n_0;
+ wire i__carry_i_3__1_n_0;
+ wire i__carry_i_3__2_n_0;
+ wire i__carry_i_3__2_n_1;
+ wire i__carry_i_3__2_n_2;
+ wire i__carry_i_3__2_n_3;
+ wire i__carry_i_3_n_0;
+ wire i__carry_i_4__0_n_0;
+ wire i__carry_i_4__1_n_0;
+ wire i__carry_i_4__2_n_0;
+ wire i__carry_i_4_n_0;
+ wire i__carry_i_5_n_0;
+ wire i__carry_i_6_n_0;
+ wire i__carry_i_7_n_0;
+ wire i__carry_i_8_n_0;
+ wire [5:0]p_0_in;
+ wire [11:1]p_0_in_0;
+ wire [0:0]p_1_in;
+ wire reg_busy_i_1_n_0;
+ wire reg_datain;
+ wire [63:0]\reg_datain_reg[63]_0 ;
+ wire \reg_datain_reg_n_0_[0] ;
+ wire \reg_datain_reg_n_0_[10] ;
+ wire \reg_datain_reg_n_0_[11] ;
+ wire \reg_datain_reg_n_0_[12] ;
+ wire \reg_datain_reg_n_0_[13] ;
+ wire \reg_datain_reg_n_0_[14] ;
+ wire \reg_datain_reg_n_0_[15] ;
+ wire \reg_datain_reg_n_0_[16] ;
+ wire \reg_datain_reg_n_0_[17] ;
+ wire \reg_datain_reg_n_0_[18] ;
+ wire \reg_datain_reg_n_0_[19] ;
+ wire \reg_datain_reg_n_0_[1] ;
+ wire \reg_datain_reg_n_0_[20] ;
+ wire \reg_datain_reg_n_0_[21] ;
+ wire \reg_datain_reg_n_0_[22] ;
+ wire \reg_datain_reg_n_0_[23] ;
+ wire \reg_datain_reg_n_0_[24] ;
+ wire \reg_datain_reg_n_0_[25] ;
+ wire \reg_datain_reg_n_0_[26] ;
+ wire \reg_datain_reg_n_0_[27] ;
+ wire \reg_datain_reg_n_0_[28] ;
+ wire \reg_datain_reg_n_0_[29] ;
+ wire \reg_datain_reg_n_0_[2] ;
+ wire \reg_datain_reg_n_0_[30] ;
+ wire \reg_datain_reg_n_0_[31] ;
+ wire \reg_datain_reg_n_0_[32] ;
+ wire \reg_datain_reg_n_0_[33] ;
+ wire \reg_datain_reg_n_0_[34] ;
+ wire \reg_datain_reg_n_0_[35] ;
+ wire \reg_datain_reg_n_0_[36] ;
+ wire \reg_datain_reg_n_0_[37] ;
+ wire \reg_datain_reg_n_0_[38] ;
+ wire \reg_datain_reg_n_0_[39] ;
+ wire \reg_datain_reg_n_0_[3] ;
+ wire \reg_datain_reg_n_0_[40] ;
+ wire \reg_datain_reg_n_0_[41] ;
+ wire \reg_datain_reg_n_0_[42] ;
+ wire \reg_datain_reg_n_0_[43] ;
+ wire \reg_datain_reg_n_0_[44] ;
+ wire \reg_datain_reg_n_0_[45] ;
+ wire \reg_datain_reg_n_0_[46] ;
+ wire \reg_datain_reg_n_0_[47] ;
+ wire \reg_datain_reg_n_0_[48] ;
+ wire \reg_datain_reg_n_0_[49] ;
+ wire \reg_datain_reg_n_0_[4] ;
+ wire \reg_datain_reg_n_0_[50] ;
+ wire \reg_datain_reg_n_0_[51] ;
+ wire \reg_datain_reg_n_0_[52] ;
+ wire \reg_datain_reg_n_0_[53] ;
+ wire \reg_datain_reg_n_0_[54] ;
+ wire \reg_datain_reg_n_0_[55] ;
+ wire \reg_datain_reg_n_0_[56] ;
+ wire \reg_datain_reg_n_0_[57] ;
+ wire \reg_datain_reg_n_0_[58] ;
+ wire \reg_datain_reg_n_0_[59] ;
+ wire \reg_datain_reg_n_0_[5] ;
+ wire \reg_datain_reg_n_0_[60] ;
+ wire \reg_datain_reg_n_0_[61] ;
+ wire \reg_datain_reg_n_0_[62] ;
+ wire \reg_datain_reg_n_0_[63] ;
+ wire \reg_datain_reg_n_0_[6] ;
+ wire \reg_datain_reg_n_0_[7] ;
+ wire \reg_datain_reg_n_0_[8] ;
+ wire \reg_datain_reg_n_0_[9] ;
+ wire \reg_dataout[63]_i_2_n_0 ;
+ wire [63:0]\reg_dataout_reg[63]_0 ;
+ wire reg_datavalid;
+ wire reg_datavalid_i_1_n_0;
+ wire reg_datavalid_i_2_n_0;
+ wire reg_datavalid_i_3_n_0;
+ wire reg_datavalid_i_4_n_0;
+ wire reg_datavalid_i_6_n_0;
+ wire reg_datavalid_i_7_n_0;
+ wire reg_datavalid_i_8_n_0;
+ wire reg_datavalid_i_9_n_0;
+ wire reg_error1_out;
+ wire reg_error_i_1_n_0;
+ wire reg_nbitsin;
+ wire \reg_nbitsin[0]_i_1_n_0 ;
+ wire \reg_nbitsin[1]_i_1_n_0 ;
+ wire \reg_nbitsin[2]_i_1_n_0 ;
+ wire \reg_nbitsin[3]_i_1_n_0 ;
+ wire \reg_nbitsin[3]_i_2_n_0 ;
+ wire \reg_nbitsin[4]_i_1_n_0 ;
+ wire \reg_nbitsin[4]_i_2_n_0 ;
+ wire \reg_nbitsin[5]_i_2_n_0 ;
+ wire \reg_nbitsin[5]_i_3_n_0 ;
+ wire [5:0]\reg_nbitsin_reg[5]_0 ;
+ wire \reg_nbitsin_reg_n_0_[0] ;
+ wire \reg_nbitsin_reg_n_0_[1] ;
+ wire \reg_nbitsin_reg_n_0_[2] ;
+ wire \reg_nbitsin_reg_n_0_[3] ;
+ wire \reg_nbitsin_reg_n_0_[4] ;
+ wire \reg_nbitsin_reg_n_0_[5] ;
+ wire reg_nbitsout;
+ wire reg_nbitsout1;
+ wire reg_nbitsout15_in;
+ wire [3:0]\reg_nbitsout1_inferred__0/i__carry__0_0 ;
+ wire [31:0]\reg_nbitsout1_inferred__0/i__carry__0_1 ;
+ wire \reg_nbitsout1_inferred__0/i__carry__0_n_3 ;
+ wire \reg_nbitsout1_inferred__0/i__carry_n_0 ;
+ wire \reg_nbitsout1_inferred__0/i__carry_n_1 ;
+ wire \reg_nbitsout1_inferred__0/i__carry_n_2 ;
+ wire \reg_nbitsout1_inferred__0/i__carry_n_3 ;
+ wire [3:0]\reg_nbitsout1_inferred__1/i__carry__0_0 ;
+ wire \reg_nbitsout1_inferred__1/i__carry__0_n_3 ;
+ wire \reg_nbitsout1_inferred__1/i__carry_n_0 ;
+ wire \reg_nbitsout1_inferred__1/i__carry_n_1 ;
+ wire \reg_nbitsout1_inferred__1/i__carry_n_2 ;
+ wire \reg_nbitsout1_inferred__1/i__carry_n_3 ;
+ wire reg_nbitsout2;
+ wire reg_nbitsout26_in;
+ wire [31:0]reg_nbitsout2_carry__0_0;
+ wire reg_nbitsout2_carry__0_i_3_n_0;
+ wire reg_nbitsout2_carry__0_i_4_n_0;
+ wire reg_nbitsout2_carry__0_n_3;
+ wire reg_nbitsout2_carry_i_5_n_0;
+ wire reg_nbitsout2_carry_i_6_n_0;
+ wire reg_nbitsout2_carry_i_7_n_0;
+ wire reg_nbitsout2_carry_i_8_n_0;
+ wire reg_nbitsout2_carry_n_0;
+ wire reg_nbitsout2_carry_n_1;
+ wire reg_nbitsout2_carry_n_2;
+ wire reg_nbitsout2_carry_n_3;
+ wire \reg_nbitsout2_inferred__0/i__carry__0_n_3 ;
+ wire \reg_nbitsout2_inferred__0/i__carry_n_0 ;
+ wire \reg_nbitsout2_inferred__0/i__carry_n_1 ;
+ wire \reg_nbitsout2_inferred__0/i__carry_n_2 ;
+ wire \reg_nbitsout2_inferred__0/i__carry_n_3 ;
+ wire [5:0]\reg_nbitsout_reg[5]_0 ;
+ wire [1:0]\reg_nbitsout_reg[5]_1 ;
+ wire [1:0]\reg_nbitsout_reg[5]_2 ;
+ wire \reg_nbitsout_reg[5]_3 ;
+ wire reg_serialin;
+ wire reg_serialin1;
+ wire s00_axi_aclk;
+ wire serialout_i_1_n_0;
+ wire serialout_i_2_n_0;
+ wire serialout_i_3_n_0;
+ wire serialout_i_4_n_0;
+ wire serialout_i_5_n_0;
+ wire [3:2]NLW_counter0_carry__1_CO_UNCONNECTED;
+ wire [3:3]NLW_counter0_carry__1_O_UNCONNECTED;
+ wire [3:2]\NLW_counter_reg[11]__0_i_4_CO_UNCONNECTED ;
+ wire [3:3]\NLW_counter_reg[11]__0_i_4_O_UNCONNECTED ;
+ wire [3:0]\NLW_fsm_rd0_inferred__1/i__carry_O_UNCONNECTED ;
+ wire [3:2]\NLW_fsm_rd0_inferred__1/i__carry__0_CO_UNCONNECTED ;
+ wire [3:0]\NLW_fsm_rd0_inferred__1/i__carry__0_O_UNCONNECTED ;
+ wire [3:0]\NLW_reg_nbitsout1_inferred__0/i__carry_O_UNCONNECTED ;
+ wire [3:2]\NLW_reg_nbitsout1_inferred__0/i__carry__0_CO_UNCONNECTED ;
+ wire [3:0]\NLW_reg_nbitsout1_inferred__0/i__carry__0_O_UNCONNECTED ;
+ wire [3:0]\NLW_reg_nbitsout1_inferred__1/i__carry_O_UNCONNECTED ;
+ wire [3:2]\NLW_reg_nbitsout1_inferred__1/i__carry__0_CO_UNCONNECTED ;
+ wire [3:0]\NLW_reg_nbitsout1_inferred__1/i__carry__0_O_UNCONNECTED ;
+ wire [3:0]NLW_reg_nbitsout2_carry_O_UNCONNECTED;
+ wire [3:2]NLW_reg_nbitsout2_carry__0_CO_UNCONNECTED;
+ wire [3:0]NLW_reg_nbitsout2_carry__0_O_UNCONNECTED;
+ wire [3:0]\NLW_reg_nbitsout2_inferred__0/i__carry_O_UNCONNECTED ;
+ wire [3:2]\NLW_reg_nbitsout2_inferred__0/i__carry__0_CO_UNCONNECTED ;
+ wire [3:0]\NLW_reg_nbitsout2_inferred__0/i__carry__0_O_UNCONNECTED ;
+
+ LUT2 #(
+ .INIT(4'h6))
+ CMD_IN_buf_inst_i_1
+ (.I0(cmd_in),
+ .I1(CMD_IN_P),
+ .O(I));
+ LUT6 #(
+ .INIT(64'h0000000008195500))
+ \FSM_sequential_fsm_rd[0]_i_1
+ (.I0(fsm_rd__0[2]),
+ .I1(reg_serialin),
+ .I2(reg_datavalid_i_3_n_0),
+ .I3(\FSM_sequential_fsm_rd[0]_i_2_n_0 ),
+ .I4(fsm_rd__0[0]),
+ .I5(\reg_nbitsout_reg[5]_3 ),
+ .O(\FSM_sequential_fsm_rd[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFF000000FFFF0808))
+ \FSM_sequential_fsm_rd[0]_i_2
+ (.I0(\FSM_sequential_fsm_rd[2]_i_5_n_0 ),
+ .I1(reg_datavalid_i_6_n_0),
+ .I2(reg_datavalid_i_7_n_0),
+ .I3(fsm_rd02_in),
+ .I4(fsm_rd__0[1]),
+ .I5(fsm_rd__0[0]),
+ .O(\FSM_sequential_fsm_rd[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000FBAA08AA))
+ \FSM_sequential_fsm_rd[1]_i_1
+ (.I0(fsm_rd__0[1]),
+ .I1(\FSM_sequential_fsm_rd[1]_i_2_n_0 ),
+ .I2(reg_datavalid_i_3_n_0),
+ .I3(\FSM_sequential_fsm_rd[2]_i_2_n_0 ),
+ .I4(\FSM_sequential_fsm_rd[1]_i_3_n_0 ),
+ .I5(\reg_nbitsout_reg[5]_3 ),
+ .O(\FSM_sequential_fsm_rd[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \FSM_sequential_fsm_rd[1]_i_2
+ (.I0(reg_serialin),
+ .I1(fsm_rd__0[2]),
+ .O(\FSM_sequential_fsm_rd[1]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h013C))
+ \FSM_sequential_fsm_rd[1]_i_3
+ (.I0(reg_serialin),
+ .I1(fsm_rd__0[0]),
+ .I2(fsm_rd__0[1]),
+ .I3(fsm_rd__0[2]),
+ .O(\FSM_sequential_fsm_rd[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000004CAA08AA))
+ \FSM_sequential_fsm_rd[2]_i_1
+ (.I0(fsm_rd__0[2]),
+ .I1(reg_serialin),
+ .I2(reg_datavalid_i_3_n_0),
+ .I3(\FSM_sequential_fsm_rd[2]_i_2_n_0 ),
+ .I4(\FSM_sequential_fsm_rd[2]_i_3_n_0 ),
+ .I5(\reg_nbitsout_reg[5]_3 ),
+ .O(\FSM_sequential_fsm_rd[2]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF45444444))
+ \FSM_sequential_fsm_rd[2]_i_2
+ (.I0(\FSM_sequential_fsm_rd[2]_i_4_n_0 ),
+ .I1(fsm_rd__0[1]),
+ .I2(reg_datavalid_i_7_n_0),
+ .I3(reg_datavalid_i_6_n_0),
+ .I4(\FSM_sequential_fsm_rd[2]_i_5_n_0 ),
+ .I5(\FSM_sequential_fsm_rd[2]_i_6_n_0 ),
+ .O(\FSM_sequential_fsm_rd[2]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \FSM_sequential_fsm_rd[2]_i_3
+ (.I0(fsm_rd__0[0]),
+ .I1(fsm_rd__0[1]),
+ .O(\FSM_sequential_fsm_rd[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT3 #(
+ .INIT(8'h2A))
+ \FSM_sequential_fsm_rd[2]_i_4
+ (.I0(fsm_rd__0[0]),
+ .I1(fsm_rd__0[1]),
+ .I2(fsm_rd02_in),
+ .O(\FSM_sequential_fsm_rd[2]_i_4_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h00000010))
+ \FSM_sequential_fsm_rd[2]_i_5
+ (.I0(p_0_in_0[9]),
+ .I1(p_0_in_0[8]),
+ .I2(p_0_in_0[4]),
+ .I3(p_0_in_0[5]),
+ .I4(reg_serialin),
+ .O(\FSM_sequential_fsm_rd[2]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT3 #(
+ .INIT(8'hEA))
+ \FSM_sequential_fsm_rd[2]_i_6
+ (.I0(fsm_rd__0[2]),
+ .I1(fsm_rd__0[0]),
+ .I2(reg_serialin),
+ .O(\FSM_sequential_fsm_rd[2]_i_6_n_0 ));
+ (* FSM_ENCODED_STATES = "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_rd_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_rd[0]_i_1_n_0 ),
+ .Q(fsm_rd__0[0]),
+ .R(1'b0));
+ (* FSM_ENCODED_STATES = "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_rd_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_rd[1]_i_1_n_0 ),
+ .Q(fsm_rd__0[1]),
+ .R(1'b0));
+ (* FSM_ENCODED_STATES = "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_rd_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_rd[2]_i_1_n_0 ),
+ .Q(fsm_rd__0[2]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h0FF005F500F00CFC))
+ \FSM_sequential_fsm_wr[0]_i_1
+ (.I0(serialout_i_3_n_0),
+ .I1(axi_control[1]),
+ .I2(fsm_wr[2]),
+ .I3(serialout_i_2_n_0),
+ .I4(fsm_wr[1]),
+ .I5(fsm_wr[0]),
+ .O(\FSM_sequential_fsm_wr[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h0A0C))
+ \FSM_sequential_fsm_wr[1]_i_1
+ (.I0(serialout_i_2_n_0),
+ .I1(fsm_wr[0]),
+ .I2(fsm_wr[2]),
+ .I3(fsm_wr[1]),
+ .O(\FSM_sequential_fsm_wr[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'hAA40))
+ \FSM_sequential_fsm_wr[2]_i_1
+ (.I0(serialout_i_2_n_0),
+ .I1(fsm_wr[0]),
+ .I2(fsm_wr[1]),
+ .I3(fsm_wr[2]),
+ .O(\FSM_sequential_fsm_wr[2]_i_1_n_0 ));
+ (* FSM_ENCODED_STATES = "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_wr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_wr[0]_i_1_n_0 ),
+ .Q(fsm_wr[0]),
+ .R(axi_control[0]));
+ (* FSM_ENCODED_STATES = "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_wr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_wr[1]_i_1_n_0 ),
+ .Q(fsm_wr[1]),
+ .R(axi_control[0]));
+ (* FSM_ENCODED_STATES = "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000" *)
+ FDRE #(
+ .INIT(1'b0))
+ \FSM_sequential_fsm_wr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\FSM_sequential_fsm_wr[2]_i_1_n_0 ),
+ .Q(fsm_wr[2]),
+ .R(axi_control[0]));
+ CARRY4 counter0_carry
+ (.CI(1'b0),
+ .CO({counter0_carry_n_0,counter0_carry_n_1,counter0_carry_n_2,counter0_carry_n_3}),
+ .CYINIT(\counter_reg_n_0_[0] ),
+ .DI({\counter_reg_n_0_[4] ,\counter_reg_n_0_[3] ,\counter_reg_n_0_[2] ,\counter_reg_n_0_[1] }),
+ .O(data1[4:1]),
+ .S({counter0_carry_i_1_n_0,counter0_carry_i_2_n_0,counter0_carry_i_3_n_0,counter0_carry_i_4_n_0}));
+ CARRY4 counter0_carry__0
+ (.CI(counter0_carry_n_0),
+ .CO({counter0_carry__0_n_0,counter0_carry__0_n_1,counter0_carry__0_n_2,counter0_carry__0_n_3}),
+ .CYINIT(1'b0),
+ .DI({\counter_reg_n_0_[8] ,\counter_reg_n_0_[7] ,\counter_reg_n_0_[6] ,\counter_reg_n_0_[5] }),
+ .O(data1[8:5]),
+ .S({counter0_carry__0_i_1_n_0,counter0_carry__0_i_2_n_0,counter0_carry__0_i_3_n_0,counter0_carry__0_i_4_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__0_i_1
+ (.I0(\counter_reg_n_0_[8] ),
+ .O(counter0_carry__0_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__0_i_2
+ (.I0(\counter_reg_n_0_[7] ),
+ .O(counter0_carry__0_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__0_i_3
+ (.I0(\counter_reg_n_0_[6] ),
+ .O(counter0_carry__0_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__0_i_4
+ (.I0(\counter_reg_n_0_[5] ),
+ .O(counter0_carry__0_i_4_n_0));
+ CARRY4 counter0_carry__1
+ (.CI(counter0_carry__0_n_0),
+ .CO({NLW_counter0_carry__1_CO_UNCONNECTED[3:2],counter0_carry__1_n_2,counter0_carry__1_n_3}),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,\counter_reg_n_0_[10] ,\counter_reg_n_0_[9] }),
+ .O({NLW_counter0_carry__1_O_UNCONNECTED[3],data1[11:9]}),
+ .S({1'b0,counter0_carry__1_i_1_n_0,counter0_carry__1_i_2_n_0,counter0_carry__1_i_3_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__1_i_1
+ (.I0(\counter_reg_n_0_[11] ),
+ .O(counter0_carry__1_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__1_i_2
+ (.I0(\counter_reg_n_0_[10] ),
+ .O(counter0_carry__1_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry__1_i_3
+ (.I0(\counter_reg_n_0_[9] ),
+ .O(counter0_carry__1_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry_i_1
+ (.I0(\counter_reg_n_0_[4] ),
+ .O(counter0_carry_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry_i_2
+ (.I0(\counter_reg_n_0_[3] ),
+ .O(counter0_carry_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry_i_3
+ (.I0(\counter_reg_n_0_[2] ),
+ .O(counter0_carry_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ counter0_carry_i_4
+ (.I0(\counter_reg_n_0_[1] ),
+ .O(counter0_carry_i_4_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT5 #(
+ .INIT(32'h55150203))
+ \counter[0]__0_i_1
+ (.I0(fsm_rd__0[2]),
+ .I1(fsm_rd__0[1]),
+ .I2(Q[0]),
+ .I3(reg_serialin),
+ .I4(fsm_rd__0[0]),
+ .O(\counter[0]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h01010101FFFF01FF))
+ \counter[0]_i_1
+ (.I0(\counter_reg_n_0_[0] ),
+ .I1(fsm_wr[1]),
+ .I2(fsm_wr[0]),
+ .I3(\counter[0]_i_2_n_0 ),
+ .I4(\counter[0]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hBBBBBFBB))
+ \counter[0]_i_2
+ (.I0(\counter_reg_n_0_[0] ),
+ .I1(fsm_wr[1]),
+ .I2(\counter_reg[11]_0 [0]),
+ .I3(fsm_wr[0]),
+ .I4(serialout_i_2_n_0),
+ .O(\counter[0]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \counter[0]_i_3
+ (.I0(reg_nbitsout2_carry__0_0[8]),
+ .I1(\counter_reg[7]_i_3_n_0 ),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [8]),
+ .I3(fsm_wr[1]),
+ .I4(serialout_i_3_n_0),
+ .O(\counter[0]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[10]__0_i_1
+ (.I0(p_0_in_0[10]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[10]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[10]_i_1
+ (.I0(data1[10]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[10]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[10]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[10]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[10]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [10]),
+ .I2(fsm_wr[0]),
+ .I3(data1[10]),
+ .O(\counter[10]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[10]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[18]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [18]),
+ .O(\counter[10]_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'h02FB))
+ \counter[11]__0_i_2
+ (.I0(reg_serialin),
+ .I1(fsm_rd__0[0]),
+ .I2(fsm_rd__0[1]),
+ .I3(fsm_rd__0[2]),
+ .O(\counter[11]__0_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[11]__0_i_3
+ (.I0(p_0_in_0[11]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[11]__0_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'h3360))
+ \counter[11]_i_1
+ (.I0(fsm_wr[1]),
+ .I1(fsm_wr[2]),
+ .I2(serialout_i_2_n_0),
+ .I3(fsm_wr[0]),
+ .O(counter));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[11]_i_2
+ (.I0(data1[11]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[11]_i_3_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[11]_i_4_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[11]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[11]_i_3
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [11]),
+ .I2(fsm_wr[0]),
+ .I3(data1[11]),
+ .O(\counter[11]_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[11]_i_4
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[19]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [19]),
+ .O(\counter[11]_i_4_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[1]__0_i_1
+ (.I0(p_0_in_0[1]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[1]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFEEEFEAAAAAAAA))
+ \counter[1]_i_1
+ (.I0(\counter[1]_i_2_n_0 ),
+ .I1(serialout_i_3_n_0),
+ .I2(reg_nbitsout2_carry__0_0[9]),
+ .I3(\counter_reg[7]_i_3_n_0 ),
+ .I4(\reg_nbitsout1_inferred__0/i__carry__0_1 [9]),
+ .I5(\counter[7]_i_4_n_0 ),
+ .O(\counter[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000AAACAA00AA))
+ \counter[1]_i_2
+ (.I0(data1[1]),
+ .I1(\counter_reg[11]_0 [1]),
+ .I2(serialout_i_2_n_0),
+ .I3(fsm_wr[0]),
+ .I4(fsm_wr[1]),
+ .I5(fsm_wr[2]),
+ .O(\counter[1]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[2]__0_i_1
+ (.I0(p_0_in_0[2]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[2]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFEEEFEAAAAAAAA))
+ \counter[2]_i_1
+ (.I0(\counter[2]_i_2_n_0 ),
+ .I1(serialout_i_3_n_0),
+ .I2(reg_nbitsout2_carry__0_0[10]),
+ .I3(\counter_reg[7]_i_3_n_0 ),
+ .I4(\reg_nbitsout1_inferred__0/i__carry__0_1 [10]),
+ .I5(\counter[7]_i_4_n_0 ),
+ .O(\counter[2]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000AAACAA00AA))
+ \counter[2]_i_2
+ (.I0(data1[2]),
+ .I1(\counter_reg[11]_0 [2]),
+ .I2(serialout_i_2_n_0),
+ .I3(fsm_wr[0]),
+ .I4(fsm_wr[1]),
+ .I5(fsm_wr[2]),
+ .O(\counter[2]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[3]__0_i_1
+ (.I0(p_0_in_0[3]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[3]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[3]_i_1
+ (.I0(data1[3]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[3]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[3]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[3]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [3]),
+ .I2(fsm_wr[0]),
+ .I3(data1[3]),
+ .O(\counter[3]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[3]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[11]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [11]),
+ .O(\counter[3]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[4]__0_i_1
+ (.I0(p_0_in_0[4]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[4]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFEEEFEAAAAAAAA))
+ \counter[4]_i_1
+ (.I0(\counter[4]_i_2_n_0 ),
+ .I1(serialout_i_3_n_0),
+ .I2(reg_nbitsout2_carry__0_0[12]),
+ .I3(\counter_reg[7]_i_3_n_0 ),
+ .I4(\reg_nbitsout1_inferred__0/i__carry__0_1 [12]),
+ .I5(\counter[7]_i_4_n_0 ),
+ .O(\counter[4]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000AAACAA00AA))
+ \counter[4]_i_2
+ (.I0(data1[4]),
+ .I1(\counter_reg[11]_0 [4]),
+ .I2(serialout_i_2_n_0),
+ .I3(fsm_wr[0]),
+ .I4(fsm_wr[1]),
+ .I5(fsm_wr[2]),
+ .O(\counter[4]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[5]__0_i_1
+ (.I0(p_0_in_0[5]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[5]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[5]_i_1
+ (.I0(data1[5]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[5]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[5]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[5]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[5]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [5]),
+ .I2(fsm_wr[0]),
+ .I3(data1[5]),
+ .O(\counter[5]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[5]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[13]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [13]),
+ .O(\counter[5]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[6]__0_i_1
+ (.I0(p_0_in_0[6]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[6]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[6]_i_1
+ (.I0(data1[6]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[6]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[6]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[6]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[6]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [6]),
+ .I2(fsm_wr[0]),
+ .I3(data1[6]),
+ .O(\counter[6]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[6]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[14]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [14]),
+ .O(\counter[6]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[7]__0_i_1
+ (.I0(p_0_in_0[7]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[7]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFEEEFEAAAAAAAA))
+ \counter[7]_i_1
+ (.I0(\counter[7]_i_2_n_0 ),
+ .I1(serialout_i_3_n_0),
+ .I2(reg_nbitsout2_carry__0_0[15]),
+ .I3(\counter_reg[7]_i_3_n_0 ),
+ .I4(\reg_nbitsout1_inferred__0/i__carry__0_1 [15]),
+ .I5(\counter[7]_i_4_n_0 ),
+ .O(\counter[7]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFAFCFC0A0A0CFC0))
+ \counter[7]_i_10
+ (.I0(\counter[7]_i_24_n_0 ),
+ .I1(\counter[7]_i_25_n_0 ),
+ .I2(\reg_nbitsin[3]_i_2_n_0 ),
+ .I3(\counter[7]_i_26_n_0 ),
+ .I4(\counter[7]_i_14_n_0 ),
+ .I5(\counter[7]_i_27_n_0 ),
+ .O(\counter[7]_i_10_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_11
+ (.I0(\reg_datain_reg_n_0_[12] ),
+ .I1(\reg_datain_reg_n_0_[13] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[14] ),
+ .I5(\reg_datain_reg_n_0_[15] ),
+ .O(\counter[7]_i_11_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_12
+ (.I0(\reg_datain_reg_n_0_[8] ),
+ .I1(\reg_datain_reg_n_0_[9] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[10] ),
+ .I5(\reg_datain_reg_n_0_[11] ),
+ .O(\counter[7]_i_12_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_13
+ (.I0(\reg_datain_reg_n_0_[4] ),
+ .I1(\reg_datain_reg_n_0_[5] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[6] ),
+ .I5(\reg_datain_reg_n_0_[7] ),
+ .O(\counter[7]_i_13_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT3 #(
+ .INIT(8'hA9))
+ \counter[7]_i_14
+ (.I0(\reg_nbitsin_reg_n_0_[2] ),
+ .I1(\reg_nbitsin_reg_n_0_[0] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .O(\counter[7]_i_14_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_15
+ (.I0(\reg_datain_reg_n_0_[0] ),
+ .I1(\reg_datain_reg_n_0_[1] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[2] ),
+ .I5(\reg_datain_reg_n_0_[3] ),
+ .O(\counter[7]_i_15_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_16
+ (.I0(\reg_datain_reg_n_0_[28] ),
+ .I1(\reg_datain_reg_n_0_[29] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[30] ),
+ .I5(\reg_datain_reg_n_0_[31] ),
+ .O(\counter[7]_i_16_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_17
+ (.I0(\reg_datain_reg_n_0_[24] ),
+ .I1(\reg_datain_reg_n_0_[25] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[26] ),
+ .I5(\reg_datain_reg_n_0_[27] ),
+ .O(\counter[7]_i_17_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_18
+ (.I0(\reg_datain_reg_n_0_[20] ),
+ .I1(\reg_datain_reg_n_0_[21] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[22] ),
+ .I5(\reg_datain_reg_n_0_[23] ),
+ .O(\counter[7]_i_18_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_19
+ (.I0(\reg_datain_reg_n_0_[16] ),
+ .I1(\reg_datain_reg_n_0_[17] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[18] ),
+ .I5(\reg_datain_reg_n_0_[19] ),
+ .O(\counter[7]_i_19_n_0 ));
+ LUT6 #(
+ .INIT(64'h000000AAACAA00AA))
+ \counter[7]_i_2
+ (.I0(data1[7]),
+ .I1(\counter_reg[11]_0 [7]),
+ .I2(serialout_i_2_n_0),
+ .I3(fsm_wr[0]),
+ .I4(fsm_wr[1]),
+ .I5(fsm_wr[2]),
+ .O(\counter[7]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_20
+ (.I0(\reg_datain_reg_n_0_[40] ),
+ .I1(\reg_datain_reg_n_0_[41] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[42] ),
+ .I5(\reg_datain_reg_n_0_[43] ),
+ .O(\counter[7]_i_20_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_21
+ (.I0(\reg_datain_reg_n_0_[44] ),
+ .I1(\reg_datain_reg_n_0_[45] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[46] ),
+ .I5(\reg_datain_reg_n_0_[47] ),
+ .O(\counter[7]_i_21_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_22
+ (.I0(\reg_datain_reg_n_0_[36] ),
+ .I1(\reg_datain_reg_n_0_[37] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[38] ),
+ .I5(\reg_datain_reg_n_0_[39] ),
+ .O(\counter[7]_i_22_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_23
+ (.I0(\reg_datain_reg_n_0_[32] ),
+ .I1(\reg_datain_reg_n_0_[33] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[34] ),
+ .I5(\reg_datain_reg_n_0_[35] ),
+ .O(\counter[7]_i_23_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_24
+ (.I0(\reg_datain_reg_n_0_[60] ),
+ .I1(\reg_datain_reg_n_0_[61] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[62] ),
+ .I5(\reg_datain_reg_n_0_[63] ),
+ .O(\counter[7]_i_24_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_25
+ (.I0(\reg_datain_reg_n_0_[56] ),
+ .I1(\reg_datain_reg_n_0_[57] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[58] ),
+ .I5(\reg_datain_reg_n_0_[59] ),
+ .O(\counter[7]_i_25_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_26
+ (.I0(\reg_datain_reg_n_0_[48] ),
+ .I1(\reg_datain_reg_n_0_[49] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[50] ),
+ .I5(\reg_datain_reg_n_0_[51] ),
+ .O(\counter[7]_i_26_n_0 ));
+ LUT6 #(
+ .INIT(64'hFACF0ACFFAC00AC0))
+ \counter[7]_i_27
+ (.I0(\reg_datain_reg_n_0_[52] ),
+ .I1(\reg_datain_reg_n_0_[53] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_datain_reg_n_0_[54] ),
+ .I5(\reg_datain_reg_n_0_[55] ),
+ .O(\counter[7]_i_27_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h1))
+ \counter[7]_i_4
+ (.I0(fsm_wr[2]),
+ .I1(fsm_wr[1]),
+ .O(\counter[7]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \counter[7]_i_7
+ (.I0(\counter[7]_i_11_n_0 ),
+ .I1(\counter[7]_i_12_n_0 ),
+ .I2(\reg_nbitsin[3]_i_2_n_0 ),
+ .I3(\counter[7]_i_13_n_0 ),
+ .I4(\counter[7]_i_14_n_0 ),
+ .I5(\counter[7]_i_15_n_0 ),
+ .O(\counter[7]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \counter[7]_i_8
+ (.I0(\counter[7]_i_16_n_0 ),
+ .I1(\counter[7]_i_17_n_0 ),
+ .I2(\reg_nbitsin[3]_i_2_n_0 ),
+ .I3(\counter[7]_i_18_n_0 ),
+ .I4(\counter[7]_i_14_n_0 ),
+ .I5(\counter[7]_i_19_n_0 ),
+ .O(\counter[7]_i_8_n_0 ));
+ LUT6 #(
+ .INIT(64'hCFC0AFAFCFC0A0A0))
+ \counter[7]_i_9
+ (.I0(\counter[7]_i_20_n_0 ),
+ .I1(\counter[7]_i_21_n_0 ),
+ .I2(\reg_nbitsin[3]_i_2_n_0 ),
+ .I3(\counter[7]_i_22_n_0 ),
+ .I4(\counter[7]_i_14_n_0 ),
+ .I5(\counter[7]_i_23_n_0 ),
+ .O(\counter[7]_i_9_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[8]__0_i_1
+ (.I0(p_0_in_0[8]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[8]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[8]_i_1
+ (.I0(data1[8]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[8]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[8]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[8]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[8]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [8]),
+ .I2(fsm_wr[0]),
+ .I3(data1[8]),
+ .O(\counter[8]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[8]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[16]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [16]),
+ .O(\counter[8]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT5 #(
+ .INIT(32'h000A2002))
+ \counter[9]__0_i_1
+ (.I0(p_0_in_0[9]),
+ .I1(reg_serialin),
+ .I2(fsm_rd__0[0]),
+ .I3(fsm_rd__0[1]),
+ .I4(fsm_rd__0[2]),
+ .O(\counter[9]__0_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h002200220F220FFF))
+ \counter[9]_i_1
+ (.I0(data1[9]),
+ .I1(fsm_wr[0]),
+ .I2(\counter[9]_i_2_n_0 ),
+ .I3(fsm_wr[1]),
+ .I4(\counter[9]_i_3_n_0 ),
+ .I5(fsm_wr[2]),
+ .O(\counter[9]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h10BF))
+ \counter[9]_i_2
+ (.I0(serialout_i_2_n_0),
+ .I1(\counter_reg[11]_0 [9]),
+ .I2(fsm_wr[0]),
+ .I3(data1[9]),
+ .O(\counter[9]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hABFB))
+ \counter[9]_i_3
+ (.I0(serialout_i_3_n_0),
+ .I1(reg_nbitsout2_carry__0_0[17]),
+ .I2(\counter_reg[7]_i_3_n_0 ),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [17]),
+ .O(\counter[9]_i_3_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[0]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[0] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[0]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[0]__0_i_1_n_0 ),
+ .Q(Q[0]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[10]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[10] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[10]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[10]__0_i_1_n_0 ),
+ .Q(Q[10]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[11]_i_2_n_0 ),
+ .Q(\counter_reg_n_0_[11] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[11]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[11]__0_i_3_n_0 ),
+ .Q(Q[11]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ CARRY4 \counter_reg[11]__0_i_4
+ (.CI(i__carry_i_2__2_n_0),
+ .CO({\NLW_counter_reg[11]__0_i_4_CO_UNCONNECTED [3:2],\counter_reg[11]__0_i_4_n_2 ,\counter_reg[11]__0_i_4_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\NLW_counter_reg[11]__0_i_4_O_UNCONNECTED [3],p_0_in_0[11:9]}),
+ .S({1'b0,Q[11:9]}));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[1]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[1] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[1]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[1]__0_i_1_n_0 ),
+ .Q(Q[1]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[2]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[2] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[2]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[2]__0_i_1_n_0 ),
+ .Q(Q[2]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[3]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[3] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[3]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[3]__0_i_1_n_0 ),
+ .Q(Q[3]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[4]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[4] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[4]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[4]__0_i_1_n_0 ),
+ .Q(Q[4]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[5]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[5] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[5]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[5]__0_i_1_n_0 ),
+ .Q(Q[5]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[6]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[6] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[6]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[6]__0_i_1_n_0 ),
+ .Q(Q[6]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[7]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[7] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[7]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[7]__0_i_1_n_0 ),
+ .Q(Q[7]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ MUXF8 \counter_reg[7]_i_3
+ (.I0(\counter_reg[7]_i_5_n_0 ),
+ .I1(\counter_reg[7]_i_6_n_0 ),
+ .O(\counter_reg[7]_i_3_n_0 ),
+ .S(\reg_nbitsin[5]_i_3_n_0 ));
+ MUXF7 \counter_reg[7]_i_5
+ (.I0(\counter[7]_i_7_n_0 ),
+ .I1(\counter[7]_i_8_n_0 ),
+ .O(\counter_reg[7]_i_5_n_0 ),
+ .S(\reg_nbitsin[4]_i_2_n_0 ));
+ MUXF7 \counter_reg[7]_i_6
+ (.I0(\counter[7]_i_9_n_0 ),
+ .I1(\counter[7]_i_10_n_0 ),
+ .O(\counter_reg[7]_i_6_n_0 ),
+ .S(\reg_nbitsin[4]_i_2_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[8]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[8] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[8]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[8]__0_i_1_n_0 ),
+ .Q(Q[8]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(counter),
+ .D(\counter[9]_i_1_n_0 ),
+ .Q(\counter_reg_n_0_[9] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \counter_reg[9]__0
+ (.C(s00_axi_aclk),
+ .CE(\counter[11]__0_i_2_n_0 ),
+ .D(\counter[9]__0_i_1_n_0 ),
+ .Q(Q[9]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ CARRY4 \fsm_rd0_inferred__1/i__carry
+ (.CI(1'b0),
+ .CO({\fsm_rd0_inferred__1/i__carry_n_0 ,\fsm_rd0_inferred__1/i__carry_n_1 ,\fsm_rd0_inferred__1/i__carry_n_2 ,\fsm_rd0_inferred__1/i__carry_n_3 }),
+ .CYINIT(1'b0),
+ .DI({i__carry_i_1_n_0,p_0_in_0[5],p_0_in_0[3],i__carry_i_4_n_0}),
+ .O(\NLW_fsm_rd0_inferred__1/i__carry_O_UNCONNECTED [3:0]),
+ .S({i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0}));
+ CARRY4 \fsm_rd0_inferred__1/i__carry__0
+ (.CI(\fsm_rd0_inferred__1/i__carry_n_0 ),
+ .CO({\NLW_fsm_rd0_inferred__1/i__carry__0_CO_UNCONNECTED [3:2],fsm_rd02_in,\fsm_rd0_inferred__1/i__carry__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,i__carry__0_i_1_n_0,i__carry__0_i_2_n_0}),
+ .O(\NLW_fsm_rd0_inferred__1/i__carry__0_O_UNCONNECTED [3:0]),
+ .S({1'b0,1'b0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0}));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_1
+ (.I0(p_0_in_0[11]),
+ .I1(p_0_in_0[10]),
+ .O(i__carry__0_i_1_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry__0_i_1__0
+ (.I0(Q[11]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [31]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [30]),
+ .I3(Q[10]),
+ .O(i__carry__0_i_1__0_n_0));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_1__1
+ (.I0(Q[11]),
+ .I1(Q[10]),
+ .O(i__carry__0_i_1__1_n_0));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_1__2
+ (.I0(Q[11]),
+ .I1(Q[10]),
+ .O(i__carry__0_i_1__2_n_0));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_2
+ (.I0(p_0_in_0[9]),
+ .I1(p_0_in_0[8]),
+ .O(i__carry__0_i_2_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry__0_i_2__0
+ (.I0(Q[9]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [29]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [28]),
+ .I3(Q[8]),
+ .O(i__carry__0_i_2__0_n_0));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_2__1
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .O(i__carry__0_i_2__1_n_0));
+ LUT2 #(
+ .INIT(4'hE))
+ i__carry__0_i_2__2
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .O(i__carry__0_i_2__2_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_3
+ (.I0(p_0_in_0[10]),
+ .I1(p_0_in_0[11]),
+ .O(i__carry__0_i_3_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_3__1
+ (.I0(Q[10]),
+ .I1(Q[11]),
+ .O(i__carry__0_i_3__1_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_3__2
+ (.I0(Q[10]),
+ .I1(Q[11]),
+ .O(i__carry__0_i_3__2_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_4
+ (.I0(p_0_in_0[8]),
+ .I1(p_0_in_0[9]),
+ .O(i__carry__0_i_4_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_4__1
+ (.I0(Q[8]),
+ .I1(Q[9]),
+ .O(i__carry__0_i_4__1_n_0));
+ LUT2 #(
+ .INIT(4'h1))
+ i__carry__0_i_4__2
+ (.I0(Q[8]),
+ .I1(Q[9]),
+ .O(i__carry__0_i_4__2_n_0));
+ LUT2 #(
+ .INIT(4'h8))
+ i__carry_i_1
+ (.I0(p_0_in_0[7]),
+ .I1(p_0_in_0[6]),
+ .O(i__carry_i_1_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_1__0
+ (.I0(Q[7]),
+ .I1(reg_nbitsout2_carry__0_0[7]),
+ .I2(Q[6]),
+ .I3(reg_nbitsout2_carry__0_0[6]),
+ .O(i__carry_i_1__0_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry_i_1__1
+ (.I0(Q[7]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [27]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [26]),
+ .I3(Q[6]),
+ .O(i__carry_i_1__1_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_1__2
+ (.I0(Q[7]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [7]),
+ .I2(Q[6]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [6]),
+ .O(i__carry_i_1__2_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_2
+ (.I0(Q[5]),
+ .I1(reg_nbitsout2_carry__0_0[5]),
+ .I2(Q[4]),
+ .I3(reg_nbitsout2_carry__0_0[4]),
+ .O(i__carry_i_2_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry_i_2__0
+ (.I0(Q[5]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [25]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [24]),
+ .I3(Q[4]),
+ .O(i__carry_i_2__0_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_2__1
+ (.I0(Q[5]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [5]),
+ .I2(Q[4]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [4]),
+ .O(i__carry_i_2__1_n_0));
+ CARRY4 i__carry_i_2__2
+ (.CI(i__carry_i_3__2_n_0),
+ .CO({i__carry_i_2__2_n_0,i__carry_i_2__2_n_1,i__carry_i_2__2_n_2,i__carry_i_2__2_n_3}),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(p_0_in_0[8:5]),
+ .S(Q[8:5]));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_3
+ (.I0(Q[3]),
+ .I1(reg_nbitsout2_carry__0_0[3]),
+ .I2(Q[2]),
+ .I3(reg_nbitsout2_carry__0_0[2]),
+ .O(i__carry_i_3_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry_i_3__0
+ (.I0(Q[3]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [23]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [22]),
+ .I3(Q[2]),
+ .O(i__carry_i_3__0_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_3__1
+ (.I0(Q[3]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [3]),
+ .I2(Q[2]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [2]),
+ .O(i__carry_i_3__1_n_0));
+ CARRY4 i__carry_i_3__2
+ (.CI(1'b0),
+ .CO({i__carry_i_3__2_n_0,i__carry_i_3__2_n_1,i__carry_i_3__2_n_2,i__carry_i_3__2_n_3}),
+ .CYINIT(Q[0]),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(p_0_in_0[4:1]),
+ .S(Q[4:1]));
+ LUT2 #(
+ .INIT(4'h2))
+ i__carry_i_4
+ (.I0(p_0_in_0[1]),
+ .I1(Q[0]),
+ .O(i__carry_i_4_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_4__0
+ (.I0(Q[1]),
+ .I1(reg_nbitsout2_carry__0_0[1]),
+ .I2(Q[0]),
+ .I3(reg_nbitsout2_carry__0_0[0]),
+ .O(i__carry_i_4__0_n_0));
+ LUT4 #(
+ .INIT(16'h44D4))
+ i__carry_i_4__1
+ (.I0(Q[1]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [21]),
+ .I2(\reg_nbitsout1_inferred__0/i__carry__0_1 [20]),
+ .I3(Q[0]),
+ .O(i__carry_i_4__1_n_0));
+ LUT4 #(
+ .INIT(16'h22B2))
+ i__carry_i_4__2
+ (.I0(Q[1]),
+ .I1(\reg_nbitsout1_inferred__0/i__carry__0_1 [1]),
+ .I2(Q[0]),
+ .I3(\reg_nbitsout1_inferred__0/i__carry__0_1 [0]),
+ .O(i__carry_i_4__2_n_0));
+ LUT2 #(
+ .INIT(4'h2))
+ i__carry_i_5
+ (.I0(p_0_in_0[7]),
+ .I1(p_0_in_0[6]),
+ .O(i__carry_i_5_n_0));
+ LUT2 #(
+ .INIT(4'h2))
+ i__carry_i_6
+ (.I0(p_0_in_0[4]),
+ .I1(p_0_in_0[5]),
+ .O(i__carry_i_6_n_0));
+ LUT2 #(
+ .INIT(4'h2))
+ i__carry_i_7
+ (.I0(p_0_in_0[2]),
+ .I1(p_0_in_0[3]),
+ .O(i__carry_i_7_n_0));
+ LUT2 #(
+ .INIT(4'h8))
+ i__carry_i_8
+ (.I0(p_0_in_0[1]),
+ .I1(Q[0]),
+ .O(i__carry_i_8_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'hBBBFBBBC))
+ reg_busy_i_1
+ (.I0(D[0]),
+ .I1(fsm_wr[2]),
+ .I2(fsm_wr[0]),
+ .I3(fsm_wr[1]),
+ .I4(axi_control[1]),
+ .O(reg_busy_i_1_n_0));
+ FDRE reg_busy_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(reg_busy_i_1_n_0),
+ .Q(D[0]),
+ .R(axi_control[0]));
+ LUT4 #(
+ .INIT(16'h0002))
+ \reg_datain[63]_i_1
+ (.I0(axi_control[1]),
+ .I1(fsm_wr[1]),
+ .I2(fsm_wr[0]),
+ .I3(fsm_wr[2]),
+ .O(reg_datain));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [0]),
+ .Q(\reg_datain_reg_n_0_[0] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [10]),
+ .Q(\reg_datain_reg_n_0_[10] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [11]),
+ .Q(\reg_datain_reg_n_0_[11] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [12]),
+ .Q(\reg_datain_reg_n_0_[12] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [13]),
+ .Q(\reg_datain_reg_n_0_[13] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [14]),
+ .Q(\reg_datain_reg_n_0_[14] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [15]),
+ .Q(\reg_datain_reg_n_0_[15] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [16]),
+ .Q(\reg_datain_reg_n_0_[16] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [17]),
+ .Q(\reg_datain_reg_n_0_[17] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [18]),
+ .Q(\reg_datain_reg_n_0_[18] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [19]),
+ .Q(\reg_datain_reg_n_0_[19] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [1]),
+ .Q(\reg_datain_reg_n_0_[1] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [20]),
+ .Q(\reg_datain_reg_n_0_[20] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [21]),
+ .Q(\reg_datain_reg_n_0_[21] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [22]),
+ .Q(\reg_datain_reg_n_0_[22] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [23]),
+ .Q(\reg_datain_reg_n_0_[23] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [24]),
+ .Q(\reg_datain_reg_n_0_[24] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [25]),
+ .Q(\reg_datain_reg_n_0_[25] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [26]),
+ .Q(\reg_datain_reg_n_0_[26] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [27]),
+ .Q(\reg_datain_reg_n_0_[27] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [28]),
+ .Q(\reg_datain_reg_n_0_[28] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [29]),
+ .Q(\reg_datain_reg_n_0_[29] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [2]),
+ .Q(\reg_datain_reg_n_0_[2] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [30]),
+ .Q(\reg_datain_reg_n_0_[30] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [31]),
+ .Q(\reg_datain_reg_n_0_[31] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[32]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [32]),
+ .Q(\reg_datain_reg_n_0_[32] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[33]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [33]),
+ .Q(\reg_datain_reg_n_0_[33] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[34]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [34]),
+ .Q(\reg_datain_reg_n_0_[34] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[35]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [35]),
+ .Q(\reg_datain_reg_n_0_[35] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[36]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [36]),
+ .Q(\reg_datain_reg_n_0_[36] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[37]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [37]),
+ .Q(\reg_datain_reg_n_0_[37] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[38]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [38]),
+ .Q(\reg_datain_reg_n_0_[38] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[39]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [39]),
+ .Q(\reg_datain_reg_n_0_[39] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [3]),
+ .Q(\reg_datain_reg_n_0_[3] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[40]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [40]),
+ .Q(\reg_datain_reg_n_0_[40] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[41]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [41]),
+ .Q(\reg_datain_reg_n_0_[41] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[42]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [42]),
+ .Q(\reg_datain_reg_n_0_[42] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[43]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [43]),
+ .Q(\reg_datain_reg_n_0_[43] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[44]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [44]),
+ .Q(\reg_datain_reg_n_0_[44] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[45]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [45]),
+ .Q(\reg_datain_reg_n_0_[45] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[46]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [46]),
+ .Q(\reg_datain_reg_n_0_[46] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[47]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [47]),
+ .Q(\reg_datain_reg_n_0_[47] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[48]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [48]),
+ .Q(\reg_datain_reg_n_0_[48] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[49]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [49]),
+ .Q(\reg_datain_reg_n_0_[49] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [4]),
+ .Q(\reg_datain_reg_n_0_[4] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[50]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [50]),
+ .Q(\reg_datain_reg_n_0_[50] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[51]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [51]),
+ .Q(\reg_datain_reg_n_0_[51] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[52]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [52]),
+ .Q(\reg_datain_reg_n_0_[52] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[53]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [53]),
+ .Q(\reg_datain_reg_n_0_[53] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[54]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [54]),
+ .Q(\reg_datain_reg_n_0_[54] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[55]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [55]),
+ .Q(\reg_datain_reg_n_0_[55] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[56]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [56]),
+ .Q(\reg_datain_reg_n_0_[56] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[57]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [57]),
+ .Q(\reg_datain_reg_n_0_[57] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[58]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [58]),
+ .Q(\reg_datain_reg_n_0_[58] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[59]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [59]),
+ .Q(\reg_datain_reg_n_0_[59] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [5]),
+ .Q(\reg_datain_reg_n_0_[5] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[60]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [60]),
+ .Q(\reg_datain_reg_n_0_[60] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[61]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [61]),
+ .Q(\reg_datain_reg_n_0_[61] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[62]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [62]),
+ .Q(\reg_datain_reg_n_0_[62] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[63]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [63]),
+ .Q(\reg_datain_reg_n_0_[63] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [6]),
+ .Q(\reg_datain_reg_n_0_[6] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [7]),
+ .Q(\reg_datain_reg_n_0_[7] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [8]),
+ .Q(\reg_datain_reg_n_0_[8] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_datain_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(reg_datain),
+ .D(\reg_datain_reg[63]_0 [9]),
+ .Q(\reg_datain_reg_n_0_[9] ),
+ .R(axi_control[0]));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \reg_dataout[0]_i_1
+ (.I0(reg_nbitsout26_in),
+ .I1(reg_nbitsout2),
+ .O(p_1_in));
+ LUT6 #(
+ .INIT(64'h8888800080008000))
+ \reg_dataout[63]_i_1
+ (.I0(\reg_dataout[63]_i_2_n_0 ),
+ .I1(fsm_rd__0[1]),
+ .I2(reg_nbitsout2),
+ .I3(reg_nbitsout26_in),
+ .I4(reg_nbitsout1),
+ .I5(reg_nbitsout15_in),
+ .O(reg_nbitsout));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT2 #(
+ .INIT(4'h1))
+ \reg_dataout[63]_i_2
+ (.I0(fsm_rd__0[0]),
+ .I1(fsm_rd__0[2]),
+ .O(\reg_dataout[63]_i_2_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_1_in),
+ .Q(\reg_dataout_reg[63]_0 [0]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [9]),
+ .Q(\reg_dataout_reg[63]_0 [10]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [10]),
+ .Q(\reg_dataout_reg[63]_0 [11]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [11]),
+ .Q(\reg_dataout_reg[63]_0 [12]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [12]),
+ .Q(\reg_dataout_reg[63]_0 [13]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [13]),
+ .Q(\reg_dataout_reg[63]_0 [14]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [14]),
+ .Q(\reg_dataout_reg[63]_0 [15]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[16]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [15]),
+ .Q(\reg_dataout_reg[63]_0 [16]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[17]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [16]),
+ .Q(\reg_dataout_reg[63]_0 [17]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[18]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [17]),
+ .Q(\reg_dataout_reg[63]_0 [18]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[19]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [18]),
+ .Q(\reg_dataout_reg[63]_0 [19]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [0]),
+ .Q(\reg_dataout_reg[63]_0 [1]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[20]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [19]),
+ .Q(\reg_dataout_reg[63]_0 [20]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[21]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [20]),
+ .Q(\reg_dataout_reg[63]_0 [21]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[22]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [21]),
+ .Q(\reg_dataout_reg[63]_0 [22]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[23]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [22]),
+ .Q(\reg_dataout_reg[63]_0 [23]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[24]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [23]),
+ .Q(\reg_dataout_reg[63]_0 [24]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[25]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [24]),
+ .Q(\reg_dataout_reg[63]_0 [25]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[26]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [25]),
+ .Q(\reg_dataout_reg[63]_0 [26]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[27]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [26]),
+ .Q(\reg_dataout_reg[63]_0 [27]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[28]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [27]),
+ .Q(\reg_dataout_reg[63]_0 [28]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[29]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [28]),
+ .Q(\reg_dataout_reg[63]_0 [29]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [1]),
+ .Q(\reg_dataout_reg[63]_0 [2]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[30]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [29]),
+ .Q(\reg_dataout_reg[63]_0 [30]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[31]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [30]),
+ .Q(\reg_dataout_reg[63]_0 [31]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[32]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [31]),
+ .Q(\reg_dataout_reg[63]_0 [32]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[33]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [32]),
+ .Q(\reg_dataout_reg[63]_0 [33]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[34]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [33]),
+ .Q(\reg_dataout_reg[63]_0 [34]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[35]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [34]),
+ .Q(\reg_dataout_reg[63]_0 [35]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[36]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [35]),
+ .Q(\reg_dataout_reg[63]_0 [36]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[37]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [36]),
+ .Q(\reg_dataout_reg[63]_0 [37]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[38]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [37]),
+ .Q(\reg_dataout_reg[63]_0 [38]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[39]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [38]),
+ .Q(\reg_dataout_reg[63]_0 [39]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [2]),
+ .Q(\reg_dataout_reg[63]_0 [3]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[40]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [39]),
+ .Q(\reg_dataout_reg[63]_0 [40]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[41]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [40]),
+ .Q(\reg_dataout_reg[63]_0 [41]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[42]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [41]),
+ .Q(\reg_dataout_reg[63]_0 [42]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[43]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [42]),
+ .Q(\reg_dataout_reg[63]_0 [43]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[44]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [43]),
+ .Q(\reg_dataout_reg[63]_0 [44]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[45]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [44]),
+ .Q(\reg_dataout_reg[63]_0 [45]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[46]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [45]),
+ .Q(\reg_dataout_reg[63]_0 [46]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[47]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [46]),
+ .Q(\reg_dataout_reg[63]_0 [47]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[48]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [47]),
+ .Q(\reg_dataout_reg[63]_0 [48]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[49]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [48]),
+ .Q(\reg_dataout_reg[63]_0 [49]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [3]),
+ .Q(\reg_dataout_reg[63]_0 [4]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[50]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [49]),
+ .Q(\reg_dataout_reg[63]_0 [50]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[51]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [50]),
+ .Q(\reg_dataout_reg[63]_0 [51]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[52]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [51]),
+ .Q(\reg_dataout_reg[63]_0 [52]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[53]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [52]),
+ .Q(\reg_dataout_reg[63]_0 [53]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[54]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [53]),
+ .Q(\reg_dataout_reg[63]_0 [54]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[55]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [54]),
+ .Q(\reg_dataout_reg[63]_0 [55]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[56]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [55]),
+ .Q(\reg_dataout_reg[63]_0 [56]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[57]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [56]),
+ .Q(\reg_dataout_reg[63]_0 [57]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[58]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [57]),
+ .Q(\reg_dataout_reg[63]_0 [58]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[59]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [58]),
+ .Q(\reg_dataout_reg[63]_0 [59]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [4]),
+ .Q(\reg_dataout_reg[63]_0 [5]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[60]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [59]),
+ .Q(\reg_dataout_reg[63]_0 [60]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[61]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [60]),
+ .Q(\reg_dataout_reg[63]_0 [61]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[62]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [61]),
+ .Q(\reg_dataout_reg[63]_0 [62]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[63]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [62]),
+ .Q(\reg_dataout_reg[63]_0 [63]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [5]),
+ .Q(\reg_dataout_reg[63]_0 [6]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [6]),
+ .Q(\reg_dataout_reg[63]_0 [7]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [7]),
+ .Q(\reg_dataout_reg[63]_0 [8]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_dataout_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(\reg_dataout_reg[63]_0 [8]),
+ .Q(\reg_dataout_reg[63]_0 [9]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ LUT6 #(
+ .INIT(64'h00000000EEFE2202))
+ reg_datavalid_i_1
+ (.I0(D[1]),
+ .I1(reg_datavalid_i_2_n_0),
+ .I2(reg_datavalid_i_3_n_0),
+ .I3(reg_datavalid_i_4_n_0),
+ .I4(reg_datavalid),
+ .I5(\reg_nbitsout_reg[5]_3 ),
+ .O(reg_datavalid_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT5 #(
+ .INIT(32'h00000080))
+ reg_datavalid_i_2
+ (.I0(fsm_rd__0[1]),
+ .I1(fsm_rd__0[0]),
+ .I2(fsm_rd02_in),
+ .I3(fsm_rd__0[2]),
+ .I4(reg_serialin),
+ .O(reg_datavalid_i_2_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000000200))
+ reg_datavalid_i_3
+ (.I0(reg_datavalid_i_6_n_0),
+ .I1(p_0_in_0[5]),
+ .I2(p_0_in_0[9]),
+ .I3(p_0_in_0[8]),
+ .I4(p_0_in_0[4]),
+ .I5(reg_datavalid_i_7_n_0),
+ .O(reg_datavalid_i_3_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT4 #(
+ .INIT(16'hEFFF))
+ reg_datavalid_i_4
+ (.I0(fsm_rd__0[0]),
+ .I1(fsm_rd__0[1]),
+ .I2(fsm_rd__0[2]),
+ .I3(reg_serialin),
+ .O(reg_datavalid_i_4_n_0));
+ LUT6 #(
+ .INIT(64'h444444F444444444))
+ reg_datavalid_i_5
+ (.I0(fsm_rd__0[2]),
+ .I1(fsm_rd02_in),
+ .I2(reg_datavalid_i_6_n_0),
+ .I3(reg_datavalid_i_8_n_0),
+ .I4(reg_datavalid_i_7_n_0),
+ .I5(reg_datavalid_i_9_n_0),
+ .O(reg_datavalid));
+ LUT4 #(
+ .INIT(16'h0001))
+ reg_datavalid_i_6
+ (.I0(p_0_in_0[11]),
+ .I1(p_0_in_0[10]),
+ .I2(p_0_in_0[3]),
+ .I3(p_0_in_0[2]),
+ .O(reg_datavalid_i_6_n_0));
+ LUT4 #(
+ .INIT(16'hFFFD))
+ reg_datavalid_i_7
+ (.I0(Q[0]),
+ .I1(p_0_in_0[1]),
+ .I2(p_0_in_0[6]),
+ .I3(p_0_in_0[7]),
+ .O(reg_datavalid_i_7_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'hFFEF))
+ reg_datavalid_i_8
+ (.I0(p_0_in_0[5]),
+ .I1(p_0_in_0[9]),
+ .I2(p_0_in_0[8]),
+ .I3(p_0_in_0[4]),
+ .O(reg_datavalid_i_8_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT2 #(
+ .INIT(4'h1))
+ reg_datavalid_i_9
+ (.I0(fsm_rd__0[0]),
+ .I1(fsm_rd__0[1]),
+ .O(reg_datavalid_i_9_n_0));
+ FDRE reg_datavalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(reg_datavalid_i_1_n_0),
+ .Q(D[1]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'h00000000ABAAA8AA))
+ reg_error_i_1
+ (.I0(D[2]),
+ .I1(fsm_rd__0[0]),
+ .I2(fsm_rd__0[2]),
+ .I3(fsm_rd__0[1]),
+ .I4(reg_error1_out),
+ .I5(\reg_nbitsout_reg[5]_3 ),
+ .O(reg_error_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT4 #(
+ .INIT(16'h0777))
+ reg_error_i_2
+ (.I0(reg_nbitsout15_in),
+ .I1(reg_nbitsout1),
+ .I2(reg_nbitsout26_in),
+ .I3(reg_nbitsout2),
+ .O(reg_error1_out));
+ FDRE reg_error_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(reg_error_i_1_n_0),
+ .Q(D[2]),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'h72))
+ \reg_nbitsin[0]_i_1
+ (.I0(fsm_wr[0]),
+ .I1(\reg_nbitsin_reg_n_0_[0] ),
+ .I2(\reg_nbitsin_reg[5]_0 [0]),
+ .O(\reg_nbitsin[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'h99F0))
+ \reg_nbitsin[1]_i_1
+ (.I0(\reg_nbitsin_reg_n_0_[1] ),
+ .I1(\reg_nbitsin_reg_n_0_[0] ),
+ .I2(\reg_nbitsin_reg[5]_0 [1]),
+ .I3(fsm_wr[0]),
+ .O(\reg_nbitsin[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT5 #(
+ .INIT(32'hEEE2222E))
+ \reg_nbitsin[2]_i_1
+ (.I0(\reg_nbitsin_reg[5]_0 [2]),
+ .I1(fsm_wr[0]),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_nbitsin_reg_n_0_[2] ),
+ .O(\reg_nbitsin[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT3 #(
+ .INIT(8'hE2))
+ \reg_nbitsin[3]_i_1
+ (.I0(\reg_nbitsin_reg[5]_0 [3]),
+ .I1(fsm_wr[0]),
+ .I2(\reg_nbitsin[3]_i_2_n_0 ),
+ .O(\reg_nbitsin[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hAAA9))
+ \reg_nbitsin[3]_i_2
+ (.I0(\reg_nbitsin_reg_n_0_[3] ),
+ .I1(\reg_nbitsin_reg_n_0_[2] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .O(\reg_nbitsin[3]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hE2))
+ \reg_nbitsin[4]_i_1
+ (.I0(\reg_nbitsin_reg[5]_0 [4]),
+ .I1(fsm_wr[0]),
+ .I2(\reg_nbitsin[4]_i_2_n_0 ),
+ .O(\reg_nbitsin[4]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAAAAAAA9))
+ \reg_nbitsin[4]_i_2
+ (.I0(\reg_nbitsin_reg_n_0_[4] ),
+ .I1(\reg_nbitsin_reg_n_0_[3] ),
+ .I2(\reg_nbitsin_reg_n_0_[0] ),
+ .I3(\reg_nbitsin_reg_n_0_[1] ),
+ .I4(\reg_nbitsin_reg_n_0_[2] ),
+ .O(\reg_nbitsin[4]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h0003000A))
+ \reg_nbitsin[5]_i_1
+ (.I0(axi_control[1]),
+ .I1(serialout_i_3_n_0),
+ .I2(fsm_wr[1]),
+ .I3(fsm_wr[2]),
+ .I4(fsm_wr[0]),
+ .O(reg_nbitsin));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT3 #(
+ .INIT(8'hE2))
+ \reg_nbitsin[5]_i_2
+ (.I0(\reg_nbitsin_reg[5]_0 [5]),
+ .I1(fsm_wr[0]),
+ .I2(\reg_nbitsin[5]_i_3_n_0 ),
+ .O(\reg_nbitsin[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAAAAAAAAAAAAAAA9))
+ \reg_nbitsin[5]_i_3
+ (.I0(\reg_nbitsin_reg_n_0_[5] ),
+ .I1(\reg_nbitsin_reg_n_0_[4] ),
+ .I2(\reg_nbitsin_reg_n_0_[2] ),
+ .I3(\reg_nbitsin_reg_n_0_[1] ),
+ .I4(\reg_nbitsin_reg_n_0_[0] ),
+ .I5(\reg_nbitsin_reg_n_0_[3] ),
+ .O(\reg_nbitsin[5]_i_3_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[0]_i_1_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[0] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[1]_i_1_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[1] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[2]_i_1_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[2] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[3]_i_1_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[3] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[4]_i_1_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[4] ),
+ .R(axi_control[0]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsin_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsin),
+ .D(\reg_nbitsin[5]_i_2_n_0 ),
+ .Q(\reg_nbitsin_reg_n_0_[5] ),
+ .R(axi_control[0]));
+ CARRY4 \reg_nbitsout1_inferred__0/i__carry
+ (.CI(1'b0),
+ .CO({\reg_nbitsout1_inferred__0/i__carry_n_0 ,\reg_nbitsout1_inferred__0/i__carry_n_1 ,\reg_nbitsout1_inferred__0/i__carry_n_2 ,\reg_nbitsout1_inferred__0/i__carry_n_3 }),
+ .CYINIT(1'b0),
+ .DI({i__carry_i_1__1_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__1_n_0}),
+ .O(\NLW_reg_nbitsout1_inferred__0/i__carry_O_UNCONNECTED [3:0]),
+ .S(\reg_nbitsout1_inferred__0/i__carry__0_0 ));
+ CARRY4 \reg_nbitsout1_inferred__0/i__carry__0
+ (.CI(\reg_nbitsout1_inferred__0/i__carry_n_0 ),
+ .CO({\NLW_reg_nbitsout1_inferred__0/i__carry__0_CO_UNCONNECTED [3:2],reg_nbitsout1,\reg_nbitsout1_inferred__0/i__carry__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0}),
+ .O(\NLW_reg_nbitsout1_inferred__0/i__carry__0_O_UNCONNECTED [3:0]),
+ .S({1'b0,1'b0,\reg_nbitsout_reg[5]_2 }));
+ CARRY4 \reg_nbitsout1_inferred__1/i__carry
+ (.CI(1'b0),
+ .CO({\reg_nbitsout1_inferred__1/i__carry_n_0 ,\reg_nbitsout1_inferred__1/i__carry_n_1 ,\reg_nbitsout1_inferred__1/i__carry_n_2 ,\reg_nbitsout1_inferred__1/i__carry_n_3 }),
+ .CYINIT(1'b0),
+ .DI({i__carry_i_1__2_n_0,i__carry_i_2__1_n_0,i__carry_i_3__1_n_0,i__carry_i_4__2_n_0}),
+ .O(\NLW_reg_nbitsout1_inferred__1/i__carry_O_UNCONNECTED [3:0]),
+ .S(\reg_nbitsout1_inferred__1/i__carry__0_0 ));
+ CARRY4 \reg_nbitsout1_inferred__1/i__carry__0
+ (.CI(\reg_nbitsout1_inferred__1/i__carry_n_0 ),
+ .CO({\NLW_reg_nbitsout1_inferred__1/i__carry__0_CO_UNCONNECTED [3:2],reg_nbitsout15_in,\reg_nbitsout1_inferred__1/i__carry__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,i__carry__0_i_1__1_n_0,i__carry__0_i_2__1_n_0}),
+ .O(\NLW_reg_nbitsout1_inferred__1/i__carry__0_O_UNCONNECTED [3:0]),
+ .S({1'b0,1'b0,i__carry__0_i_3__1_n_0,i__carry__0_i_4__1_n_0}));
+ CARRY4 reg_nbitsout2_carry
+ (.CI(1'b0),
+ .CO({reg_nbitsout2_carry_n_0,reg_nbitsout2_carry_n_1,reg_nbitsout2_carry_n_2,reg_nbitsout2_carry_n_3}),
+ .CYINIT(1'b0),
+ .DI(DI),
+ .O(NLW_reg_nbitsout2_carry_O_UNCONNECTED[3:0]),
+ .S({reg_nbitsout2_carry_i_5_n_0,reg_nbitsout2_carry_i_6_n_0,reg_nbitsout2_carry_i_7_n_0,reg_nbitsout2_carry_i_8_n_0}));
+ CARRY4 reg_nbitsout2_carry__0
+ (.CI(reg_nbitsout2_carry_n_0),
+ .CO({NLW_reg_nbitsout2_carry__0_CO_UNCONNECTED[3:2],reg_nbitsout2,reg_nbitsout2_carry__0_n_3}),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,\reg_nbitsout_reg[5]_1 }),
+ .O(NLW_reg_nbitsout2_carry__0_O_UNCONNECTED[3:0]),
+ .S({1'b0,1'b0,reg_nbitsout2_carry__0_i_3_n_0,reg_nbitsout2_carry__0_i_4_n_0}));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry__0_i_3
+ (.I0(Q[11]),
+ .I1(reg_nbitsout2_carry__0_0[31]),
+ .I2(Q[10]),
+ .I3(reg_nbitsout2_carry__0_0[30]),
+ .O(reg_nbitsout2_carry__0_i_3_n_0));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry__0_i_4
+ (.I0(Q[9]),
+ .I1(reg_nbitsout2_carry__0_0[29]),
+ .I2(Q[8]),
+ .I3(reg_nbitsout2_carry__0_0[28]),
+ .O(reg_nbitsout2_carry__0_i_4_n_0));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry_i_5
+ (.I0(Q[7]),
+ .I1(reg_nbitsout2_carry__0_0[27]),
+ .I2(Q[6]),
+ .I3(reg_nbitsout2_carry__0_0[26]),
+ .O(reg_nbitsout2_carry_i_5_n_0));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry_i_6
+ (.I0(Q[5]),
+ .I1(reg_nbitsout2_carry__0_0[25]),
+ .I2(Q[4]),
+ .I3(reg_nbitsout2_carry__0_0[24]),
+ .O(reg_nbitsout2_carry_i_6_n_0));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry_i_7
+ (.I0(Q[3]),
+ .I1(reg_nbitsout2_carry__0_0[23]),
+ .I2(Q[2]),
+ .I3(reg_nbitsout2_carry__0_0[22]),
+ .O(reg_nbitsout2_carry_i_7_n_0));
+ LUT4 #(
+ .INIT(16'h9009))
+ reg_nbitsout2_carry_i_8
+ (.I0(Q[1]),
+ .I1(reg_nbitsout2_carry__0_0[21]),
+ .I2(reg_nbitsout2_carry__0_0[20]),
+ .I3(Q[0]),
+ .O(reg_nbitsout2_carry_i_8_n_0));
+ CARRY4 \reg_nbitsout2_inferred__0/i__carry
+ (.CI(1'b0),
+ .CO({\reg_nbitsout2_inferred__0/i__carry_n_0 ,\reg_nbitsout2_inferred__0/i__carry_n_1 ,\reg_nbitsout2_inferred__0/i__carry_n_2 ,\reg_nbitsout2_inferred__0/i__carry_n_3 }),
+ .CYINIT(1'b0),
+ .DI({i__carry_i_1__0_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4__0_n_0}),
+ .O(\NLW_reg_nbitsout2_inferred__0/i__carry_O_UNCONNECTED [3:0]),
+ .S(S));
+ CARRY4 \reg_nbitsout2_inferred__0/i__carry__0
+ (.CI(\reg_nbitsout2_inferred__0/i__carry_n_0 ),
+ .CO({\NLW_reg_nbitsout2_inferred__0/i__carry__0_CO_UNCONNECTED [3:2],reg_nbitsout26_in,\reg_nbitsout2_inferred__0/i__carry__0_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,i__carry__0_i_1__2_n_0,i__carry__0_i_2__2_n_0}),
+ .O(\NLW_reg_nbitsout2_inferred__0/i__carry__0_O_UNCONNECTED [3:0]),
+ .S({1'b0,1'b0,i__carry__0_i_3__2_n_0,i__carry__0_i_4__2_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ \reg_nbitsout[0]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [0]),
+ .O(p_0_in[0]));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'h6))
+ \reg_nbitsout[1]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [0]),
+ .I1(\reg_nbitsout_reg[5]_0 [1]),
+ .O(p_0_in[1]));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT3 #(
+ .INIT(8'h6A))
+ \reg_nbitsout[2]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [2]),
+ .I1(\reg_nbitsout_reg[5]_0 [1]),
+ .I2(\reg_nbitsout_reg[5]_0 [0]),
+ .O(p_0_in[2]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h6AAA))
+ \reg_nbitsout[3]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [3]),
+ .I1(\reg_nbitsout_reg[5]_0 [0]),
+ .I2(\reg_nbitsout_reg[5]_0 [1]),
+ .I3(\reg_nbitsout_reg[5]_0 [2]),
+ .O(p_0_in[3]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT5 #(
+ .INIT(32'h6AAAAAAA))
+ \reg_nbitsout[4]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [4]),
+ .I1(\reg_nbitsout_reg[5]_0 [2]),
+ .I2(\reg_nbitsout_reg[5]_0 [1]),
+ .I3(\reg_nbitsout_reg[5]_0 [0]),
+ .I4(\reg_nbitsout_reg[5]_0 [3]),
+ .O(p_0_in[4]));
+ LUT6 #(
+ .INIT(64'h6AAAAAAAAAAAAAAA))
+ \reg_nbitsout[5]_i_1
+ (.I0(\reg_nbitsout_reg[5]_0 [5]),
+ .I1(\reg_nbitsout_reg[5]_0 [3]),
+ .I2(\reg_nbitsout_reg[5]_0 [0]),
+ .I3(\reg_nbitsout_reg[5]_0 [1]),
+ .I4(\reg_nbitsout_reg[5]_0 [2]),
+ .I5(\reg_nbitsout_reg[5]_0 [4]),
+ .O(p_0_in[5]));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[0]),
+ .Q(\reg_nbitsout_reg[5]_0 [0]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[1]),
+ .Q(\reg_nbitsout_reg[5]_0 [1]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[2]),
+ .Q(\reg_nbitsout_reg[5]_0 [2]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[3]),
+ .Q(\reg_nbitsout_reg[5]_0 [3]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[4]),
+ .Q(\reg_nbitsout_reg[5]_0 [4]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE #(
+ .INIT(1'b0))
+ \reg_nbitsout_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(reg_nbitsout),
+ .D(p_0_in[5]),
+ .Q(\reg_nbitsout_reg[5]_0 [5]),
+ .R(\reg_nbitsout_reg[5]_3 ));
+ FDRE reg_serialin1_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(cmd_out),
+ .Q(reg_serialin1),
+ .R(axi_control[0]));
+ FDRE reg_serialin_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(reg_serialin1),
+ .Q(reg_serialin),
+ .R(axi_control[0]));
+ LUT6 #(
+ .INIT(64'hF8C0F8CC08000800))
+ serialout_i_1
+ (.I0(serialout_i_2_n_0),
+ .I1(fsm_wr[0]),
+ .I2(fsm_wr[2]),
+ .I3(fsm_wr[1]),
+ .I4(serialout_i_3_n_0),
+ .I5(cmd_in),
+ .O(serialout_i_1_n_0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFEFFFFFFFF))
+ serialout_i_2
+ (.I0(serialout_i_4_n_0),
+ .I1(\counter_reg_n_0_[10] ),
+ .I2(\counter_reg_n_0_[7] ),
+ .I3(\counter_reg_n_0_[4] ),
+ .I4(\counter_reg_n_0_[0] ),
+ .I5(serialout_i_5_n_0),
+ .O(serialout_i_2_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ serialout_i_3
+ (.I0(\reg_nbitsin_reg_n_0_[4] ),
+ .I1(\reg_nbitsin_reg_n_0_[2] ),
+ .I2(\reg_nbitsin_reg_n_0_[1] ),
+ .I3(\reg_nbitsin_reg_n_0_[0] ),
+ .I4(\reg_nbitsin_reg_n_0_[3] ),
+ .I5(\reg_nbitsin_reg_n_0_[5] ),
+ .O(serialout_i_3_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ serialout_i_4
+ (.I0(\counter_reg_n_0_[8] ),
+ .I1(\counter_reg_n_0_[9] ),
+ .I2(\counter_reg_n_0_[1] ),
+ .I3(\counter_reg_n_0_[11] ),
+ .O(serialout_i_4_n_0));
+ LUT4 #(
+ .INIT(16'h0001))
+ serialout_i_5
+ (.I0(\counter_reg_n_0_[2] ),
+ .I1(\counter_reg_n_0_[6] ),
+ .I2(\counter_reg_n_0_[3] ),
+ .I3(\counter_reg_n_0_[5] ),
+ .O(serialout_i_5_n_0));
+ FDRE serialout_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(serialout_i_1_n_0),
+ .Q(cmd_in),
+ .R(axi_control[0]));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.vhdl
new file mode 100644
index 0000000..9bab582
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.vhdl
@@ -0,0 +1,10165 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Tue Oct 15 10:07:03 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_sim_netlist.vhdl
+-- Design : TopLevel_endeavour_axi_contro_5_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI is
+ port (
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_rvalid : out STD_LOGIC;
+ \slv_reg0_pulse_reg[1]_0\ : out STD_LOGIC;
+ axi_control : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ DI : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ \slv_reg7_reg[31]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \slv_reg8_reg[27]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \slv_reg8_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ \slv_reg8_reg[31]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \slv_reg8_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ cmd_out : out STD_LOGIC;
+ \slv_reg10_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ D : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ \slv_reg9_reg[19]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \slv_reg1_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_aclk : in STD_LOGIC;
+ \reg_nbitsout1_inferred__0/i__carry__0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ seriali_buf : in STD_LOGIC;
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_aresetn : in STD_LOGIC;
+ \slv_reg0_read_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \slv_reg4_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \slv_reg6_reg[31]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI : entity is "endeavour_axi_controller_v1_0_S00_AXI";
+end TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI;
+
+architecture STRUCTURE of TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI is
+ signal \^d\ : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal TICKS_BITGAP_MAX : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_BITGAP_MIN : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal axi_arready0 : STD_LOGIC;
+ signal axi_awready0 : STD_LOGIC;
+ signal axi_awready_i_1_n_0 : STD_LOGIC;
+ signal axi_bvalid_i_1_n_0 : STD_LOGIC;
+ signal axi_config : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \^axi_control\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \axi_rdata[0]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[0]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[0]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[10]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[10]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[10]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[11]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[11]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[11]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[12]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[12]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[12]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[13]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[13]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[13]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[14]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[14]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[14]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[15]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[15]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[15]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[16]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[16]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[16]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[17]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[17]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[17]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[18]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[18]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[18]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[19]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[19]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[19]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[1]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[1]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[1]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[20]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[20]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[20]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[21]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[21]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[21]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[22]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[22]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[22]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[23]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[23]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[23]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[24]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[24]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[24]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[25]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[25]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[25]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[26]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[26]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[26]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[27]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[27]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[27]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[28]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[28]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[28]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[29]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[29]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[29]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[2]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[2]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[2]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[30]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[30]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[30]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[31]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[31]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[31]_i_5_n_0\ : STD_LOGIC;
+ signal \axi_rdata[3]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[3]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[3]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[4]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[4]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[4]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[5]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[5]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[5]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[6]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[6]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[6]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[7]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[7]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[7]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[8]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[8]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[8]_i_4_n_0\ : STD_LOGIC;
+ signal \axi_rdata[9]_i_2_n_0\ : STD_LOGIC;
+ signal \axi_rdata[9]_i_3_n_0\ : STD_LOGIC;
+ signal \axi_rdata[9]_i_4_n_0\ : STD_LOGIC;
+ signal axi_rvalid_i_1_n_0 : STD_LOGIC;
+ signal axi_wready0 : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \^s00_axi_arready\ : STD_LOGIC;
+ signal \^s00_axi_awready\ : STD_LOGIC;
+ signal \^s00_axi_bvalid\ : STD_LOGIC;
+ signal \^s00_axi_rvalid\ : STD_LOGIC;
+ signal \^s00_axi_wready\ : STD_LOGIC;
+ signal sel0 : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \slv_reg0_pulse[0]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg0_pulse[1]_i_1_n_0\ : STD_LOGIC;
+ signal slv_reg0_read : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \slv_reg10[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg10[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg10[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg10[7]_i_1_n_0\ : STD_LOGIC;
+ signal \^slv_reg10_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \slv_reg10_reg_n_0_[10]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[11]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[12]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[13]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[14]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[15]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[16]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[17]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[18]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[19]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[20]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[21]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[22]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[23]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[24]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[25]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[26]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[27]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[28]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[29]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[2]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[30]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[31]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[3]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[4]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[5]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[6]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[7]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[8]\ : STD_LOGIC;
+ signal \slv_reg10_reg_n_0_[9]\ : STD_LOGIC;
+ signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
+ signal \^slv_reg1_reg[5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal \slv_reg1_reg_n_0_[10]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[11]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[12]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[13]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[14]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[15]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[16]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[17]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[18]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[19]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[20]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[21]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[22]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[23]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[24]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[25]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[26]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[27]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[28]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[29]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[30]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[31]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[6]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[7]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[8]\ : STD_LOGIC;
+ signal \slv_reg1_reg_n_0_[9]\ : STD_LOGIC;
+ signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
+ signal slv_reg4 : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal slv_reg5 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal slv_reg6 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \slv_reg7[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg7[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg7[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg7[7]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg8[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg8[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg8[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg8[7]_i_1_n_0\ : STD_LOGIC;
+ signal \^slv_reg8_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \slv_reg9[15]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg9[23]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg9[31]_i_1_n_0\ : STD_LOGIC;
+ signal \slv_reg9[7]_i_1_n_0\ : STD_LOGIC;
+ signal \^slv_reg9_reg[19]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal slv_reg_rden : STD_LOGIC;
+ signal \slv_reg_wren__2\ : STD_LOGIC;
+begin
+ D(63 downto 0) <= \^d\(63 downto 0);
+ Q(31 downto 0) <= \^q\(31 downto 0);
+ axi_control(1 downto 0) <= \^axi_control\(1 downto 0);
+ s00_axi_arready <= \^s00_axi_arready\;
+ s00_axi_awready <= \^s00_axi_awready\;
+ s00_axi_bvalid <= \^s00_axi_bvalid\;
+ s00_axi_rvalid <= \^s00_axi_rvalid\;
+ s00_axi_wready <= \^s00_axi_wready\;
+ \slv_reg10_reg[0]_0\(0) <= \^slv_reg10_reg[0]_0\(0);
+ \slv_reg1_reg[5]_0\(5 downto 0) <= \^slv_reg1_reg[5]_0\(5 downto 0);
+ \slv_reg8_reg[31]_0\(31 downto 0) <= \^slv_reg8_reg[31]_0\(31 downto 0);
+ \slv_reg9_reg[19]_0\(11 downto 0) <= \^slv_reg9_reg[19]_0\(11 downto 0);
+\axi_araddr_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_arready0,
+ D => s00_axi_araddr(0),
+ Q => sel0(0),
+ S => axi_awready_i_1_n_0
+ );
+\axi_araddr_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_arready0,
+ D => s00_axi_araddr(1),
+ Q => sel0(1),
+ S => axi_awready_i_1_n_0
+ );
+\axi_araddr_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_arready0,
+ D => s00_axi_araddr(2),
+ Q => sel0(2),
+ S => axi_awready_i_1_n_0
+ );
+\axi_araddr_reg[5]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_arready0,
+ D => s00_axi_araddr(3),
+ Q => sel0(3),
+ S => axi_awready_i_1_n_0
+ );
+axi_arready_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => s00_axi_arvalid,
+ I1 => \^s00_axi_arready\,
+ O => axi_arready0
+ );
+axi_arready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => axi_arready0,
+ Q => \^s00_axi_arready\,
+ R => axi_awready_i_1_n_0
+ );
+\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_awready0,
+ D => s00_axi_awaddr(0),
+ Q => p_0_in(0),
+ R => axi_awready_i_1_n_0
+ );
+\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_awready0,
+ D => s00_axi_awaddr(1),
+ Q => p_0_in(1),
+ R => axi_awready_i_1_n_0
+ );
+\axi_awaddr_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_awready0,
+ D => s00_axi_awaddr(2),
+ Q => p_0_in(2),
+ R => axi_awready_i_1_n_0
+ );
+\axi_awaddr_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => axi_awready0,
+ D => s00_axi_awaddr(3),
+ Q => p_0_in(3),
+ R => axi_awready_i_1_n_0
+ );
+axi_awready_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ O => axi_awready_i_1_n_0
+ );
+axi_awready_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_awready\,
+ O => axi_awready0
+ );
+axi_awready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => axi_awready0,
+ Q => \^s00_axi_awready\,
+ R => axi_awready_i_1_n_0
+ );
+axi_bvalid_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000FFFF80008000"
+ )
+ port map (
+ I0 => s00_axi_awvalid,
+ I1 => \^s00_axi_awready\,
+ I2 => \^s00_axi_wready\,
+ I3 => s00_axi_wvalid,
+ I4 => s00_axi_bready,
+ I5 => \^s00_axi_bvalid\,
+ O => axi_bvalid_i_1_n_0
+ );
+axi_bvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => axi_bvalid_i_1_n_0,
+ Q => \^s00_axi_bvalid\,
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[0]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[0]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[0]_i_4_n_0\,
+ O => reg_data_out(0)
+ );
+\axi_rdata[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(0),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(0),
+ I3 => sel0(1),
+ I4 => \^slv_reg10_reg[0]_0\(0),
+ I5 => sel0(2),
+ O => \axi_rdata[0]_i_2_n_0\
+ );
+\axi_rdata[0]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => slv_reg6(0),
+ I2 => sel0(1),
+ I3 => slv_reg5(0),
+ I4 => sel0(0),
+ I5 => slv_reg4(0),
+ O => \axi_rdata[0]_i_3_n_0\
+ );
+\axi_rdata[0]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^d\(32),
+ I1 => \^d\(0),
+ I2 => sel0(1),
+ I3 => \^slv_reg1_reg[5]_0\(0),
+ I4 => sel0(0),
+ I5 => slv_reg0_read(0),
+ O => \axi_rdata[0]_i_4_n_0\
+ );
+\axi_rdata[10]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[10]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[10]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[10]_i_4_n_0\,
+ O => reg_data_out(10)
+ );
+\axi_rdata[10]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(10),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(2),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[10]\,
+ I5 => sel0(2),
+ O => \axi_rdata[10]_i_2_n_0\
+ );
+\axi_rdata[10]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(10),
+ I1 => slv_reg6(10),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(10),
+ O => \axi_rdata[10]_i_3_n_0\
+ );
+\axi_rdata[10]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(42),
+ I1 => \^d\(10),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[10]\,
+ O => \axi_rdata[10]_i_4_n_0\
+ );
+\axi_rdata[11]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[11]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[11]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[11]_i_4_n_0\,
+ O => reg_data_out(11)
+ );
+\axi_rdata[11]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(11),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(3),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[11]\,
+ I5 => sel0(2),
+ O => \axi_rdata[11]_i_2_n_0\
+ );
+\axi_rdata[11]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(11),
+ I1 => slv_reg6(11),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(11),
+ O => \axi_rdata[11]_i_3_n_0\
+ );
+\axi_rdata[11]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(43),
+ I1 => \^d\(11),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[11]\,
+ O => \axi_rdata[11]_i_4_n_0\
+ );
+\axi_rdata[12]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[12]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[12]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[12]_i_4_n_0\,
+ O => reg_data_out(12)
+ );
+\axi_rdata[12]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(12),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(4),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[12]\,
+ I5 => sel0(2),
+ O => \axi_rdata[12]_i_2_n_0\
+ );
+\axi_rdata[12]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(12),
+ I1 => slv_reg6(12),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(12),
+ O => \axi_rdata[12]_i_3_n_0\
+ );
+\axi_rdata[12]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(44),
+ I1 => \^d\(12),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[12]\,
+ O => \axi_rdata[12]_i_4_n_0\
+ );
+\axi_rdata[13]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[13]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[13]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[13]_i_4_n_0\,
+ O => reg_data_out(13)
+ );
+\axi_rdata[13]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(13),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(5),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[13]\,
+ I5 => sel0(2),
+ O => \axi_rdata[13]_i_2_n_0\
+ );
+\axi_rdata[13]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(13),
+ I1 => slv_reg6(13),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(13),
+ O => \axi_rdata[13]_i_3_n_0\
+ );
+\axi_rdata[13]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(45),
+ I1 => \^d\(13),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[13]\,
+ O => \axi_rdata[13]_i_4_n_0\
+ );
+\axi_rdata[14]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[14]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[14]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[14]_i_4_n_0\,
+ O => reg_data_out(14)
+ );
+\axi_rdata[14]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(14),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(6),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[14]\,
+ I5 => sel0(2),
+ O => \axi_rdata[14]_i_2_n_0\
+ );
+\axi_rdata[14]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(14),
+ I1 => slv_reg6(14),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(14),
+ O => \axi_rdata[14]_i_3_n_0\
+ );
+\axi_rdata[14]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(46),
+ I1 => \^d\(14),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[14]\,
+ O => \axi_rdata[14]_i_4_n_0\
+ );
+\axi_rdata[15]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[15]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[15]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[15]_i_4_n_0\,
+ O => reg_data_out(15)
+ );
+\axi_rdata[15]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(15),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(7),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[15]\,
+ I5 => sel0(2),
+ O => \axi_rdata[15]_i_2_n_0\
+ );
+\axi_rdata[15]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(15),
+ I1 => slv_reg6(15),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(15),
+ O => \axi_rdata[15]_i_3_n_0\
+ );
+\axi_rdata[15]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(47),
+ I1 => \^d\(15),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[15]\,
+ O => \axi_rdata[15]_i_4_n_0\
+ );
+\axi_rdata[16]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[16]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[16]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[16]_i_4_n_0\,
+ O => reg_data_out(16)
+ );
+\axi_rdata[16]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(16),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(8),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[16]\,
+ I5 => sel0(2),
+ O => \axi_rdata[16]_i_2_n_0\
+ );
+\axi_rdata[16]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(16),
+ I1 => slv_reg6(16),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(16),
+ O => \axi_rdata[16]_i_3_n_0\
+ );
+\axi_rdata[16]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(48),
+ I1 => \^d\(16),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[16]\,
+ O => \axi_rdata[16]_i_4_n_0\
+ );
+\axi_rdata[17]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[17]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[17]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[17]_i_4_n_0\,
+ O => reg_data_out(17)
+ );
+\axi_rdata[17]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(17),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(9),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[17]\,
+ I5 => sel0(2),
+ O => \axi_rdata[17]_i_2_n_0\
+ );
+\axi_rdata[17]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(17),
+ I1 => slv_reg6(17),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(17),
+ O => \axi_rdata[17]_i_3_n_0\
+ );
+\axi_rdata[17]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(49),
+ I1 => \^d\(17),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[17]\,
+ O => \axi_rdata[17]_i_4_n_0\
+ );
+\axi_rdata[18]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[18]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[18]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[18]_i_4_n_0\,
+ O => reg_data_out(18)
+ );
+\axi_rdata[18]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(18),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(10),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[18]\,
+ I5 => sel0(2),
+ O => \axi_rdata[18]_i_2_n_0\
+ );
+\axi_rdata[18]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(18),
+ I1 => slv_reg6(18),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(18),
+ O => \axi_rdata[18]_i_3_n_0\
+ );
+\axi_rdata[18]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(50),
+ I1 => \^d\(18),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[18]\,
+ O => \axi_rdata[18]_i_4_n_0\
+ );
+\axi_rdata[19]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[19]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[19]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[19]_i_4_n_0\,
+ O => reg_data_out(19)
+ );
+\axi_rdata[19]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(19),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(11),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[19]\,
+ I5 => sel0(2),
+ O => \axi_rdata[19]_i_2_n_0\
+ );
+\axi_rdata[19]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(19),
+ I1 => slv_reg6(19),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(19),
+ O => \axi_rdata[19]_i_3_n_0\
+ );
+\axi_rdata[19]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(51),
+ I1 => \^d\(19),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[19]\,
+ O => \axi_rdata[19]_i_4_n_0\
+ );
+\axi_rdata[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[1]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[1]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[1]_i_4_n_0\,
+ O => reg_data_out(1)
+ );
+\axi_rdata[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(1),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(1),
+ I3 => sel0(1),
+ I4 => axi_config(1),
+ I5 => sel0(2),
+ O => \axi_rdata[1]_i_2_n_0\
+ );
+\axi_rdata[1]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => slv_reg6(1),
+ I2 => sel0(1),
+ I3 => slv_reg5(1),
+ I4 => sel0(0),
+ I5 => slv_reg4(1),
+ O => \axi_rdata[1]_i_3_n_0\
+ );
+\axi_rdata[1]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^d\(33),
+ I1 => \^d\(1),
+ I2 => sel0(1),
+ I3 => \^slv_reg1_reg[5]_0\(1),
+ I4 => sel0(0),
+ I5 => slv_reg0_read(1),
+ O => \axi_rdata[1]_i_4_n_0\
+ );
+\axi_rdata[20]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[20]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[20]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[20]_i_4_n_0\,
+ O => reg_data_out(20)
+ );
+\axi_rdata[20]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(20),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(0),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[20]\,
+ I5 => sel0(2),
+ O => \axi_rdata[20]_i_2_n_0\
+ );
+\axi_rdata[20]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(20),
+ I1 => slv_reg6(20),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(20),
+ O => \axi_rdata[20]_i_3_n_0\
+ );
+\axi_rdata[20]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(52),
+ I1 => \^d\(20),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[20]\,
+ O => \axi_rdata[20]_i_4_n_0\
+ );
+\axi_rdata[21]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[21]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[21]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[21]_i_4_n_0\,
+ O => reg_data_out(21)
+ );
+\axi_rdata[21]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(21),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(1),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[21]\,
+ I5 => sel0(2),
+ O => \axi_rdata[21]_i_2_n_0\
+ );
+\axi_rdata[21]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(21),
+ I1 => slv_reg6(21),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(21),
+ O => \axi_rdata[21]_i_3_n_0\
+ );
+\axi_rdata[21]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(53),
+ I1 => \^d\(21),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[21]\,
+ O => \axi_rdata[21]_i_4_n_0\
+ );
+\axi_rdata[22]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[22]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[22]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[22]_i_4_n_0\,
+ O => reg_data_out(22)
+ );
+\axi_rdata[22]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(22),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(2),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[22]\,
+ I5 => sel0(2),
+ O => \axi_rdata[22]_i_2_n_0\
+ );
+\axi_rdata[22]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(22),
+ I1 => slv_reg6(22),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(22),
+ O => \axi_rdata[22]_i_3_n_0\
+ );
+\axi_rdata[22]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(54),
+ I1 => \^d\(22),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[22]\,
+ O => \axi_rdata[22]_i_4_n_0\
+ );
+\axi_rdata[23]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[23]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[23]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[23]_i_4_n_0\,
+ O => reg_data_out(23)
+ );
+\axi_rdata[23]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(23),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(3),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[23]\,
+ I5 => sel0(2),
+ O => \axi_rdata[23]_i_2_n_0\
+ );
+\axi_rdata[23]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(23),
+ I1 => slv_reg6(23),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(23),
+ O => \axi_rdata[23]_i_3_n_0\
+ );
+\axi_rdata[23]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(55),
+ I1 => \^d\(23),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[23]\,
+ O => \axi_rdata[23]_i_4_n_0\
+ );
+\axi_rdata[24]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[24]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[24]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[24]_i_4_n_0\,
+ O => reg_data_out(24)
+ );
+\axi_rdata[24]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(24),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(4),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[24]\,
+ I5 => sel0(2),
+ O => \axi_rdata[24]_i_2_n_0\
+ );
+\axi_rdata[24]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(24),
+ I1 => slv_reg6(24),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(24),
+ O => \axi_rdata[24]_i_3_n_0\
+ );
+\axi_rdata[24]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(56),
+ I1 => \^d\(24),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[24]\,
+ O => \axi_rdata[24]_i_4_n_0\
+ );
+\axi_rdata[25]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[25]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[25]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[25]_i_4_n_0\,
+ O => reg_data_out(25)
+ );
+\axi_rdata[25]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(25),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(5),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[25]\,
+ I5 => sel0(2),
+ O => \axi_rdata[25]_i_2_n_0\
+ );
+\axi_rdata[25]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(25),
+ I1 => slv_reg6(25),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(25),
+ O => \axi_rdata[25]_i_3_n_0\
+ );
+\axi_rdata[25]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(57),
+ I1 => \^d\(25),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[25]\,
+ O => \axi_rdata[25]_i_4_n_0\
+ );
+\axi_rdata[26]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[26]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[26]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[26]_i_4_n_0\,
+ O => reg_data_out(26)
+ );
+\axi_rdata[26]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(26),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(6),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[26]\,
+ I5 => sel0(2),
+ O => \axi_rdata[26]_i_2_n_0\
+ );
+\axi_rdata[26]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(26),
+ I1 => slv_reg6(26),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(26),
+ O => \axi_rdata[26]_i_3_n_0\
+ );
+\axi_rdata[26]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(58),
+ I1 => \^d\(26),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[26]\,
+ O => \axi_rdata[26]_i_4_n_0\
+ );
+\axi_rdata[27]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[27]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[27]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[27]_i_4_n_0\,
+ O => reg_data_out(27)
+ );
+\axi_rdata[27]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(27),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(7),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[27]\,
+ I5 => sel0(2),
+ O => \axi_rdata[27]_i_2_n_0\
+ );
+\axi_rdata[27]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(27),
+ I1 => slv_reg6(27),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(27),
+ O => \axi_rdata[27]_i_3_n_0\
+ );
+\axi_rdata[27]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(59),
+ I1 => \^d\(27),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[27]\,
+ O => \axi_rdata[27]_i_4_n_0\
+ );
+\axi_rdata[28]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[28]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[28]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[28]_i_4_n_0\,
+ O => reg_data_out(28)
+ );
+\axi_rdata[28]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(28),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(8),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[28]\,
+ I5 => sel0(2),
+ O => \axi_rdata[28]_i_2_n_0\
+ );
+\axi_rdata[28]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(28),
+ I1 => slv_reg6(28),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(28),
+ O => \axi_rdata[28]_i_3_n_0\
+ );
+\axi_rdata[28]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(60),
+ I1 => \^d\(28),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[28]\,
+ O => \axi_rdata[28]_i_4_n_0\
+ );
+\axi_rdata[29]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[29]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[29]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[29]_i_4_n_0\,
+ O => reg_data_out(29)
+ );
+\axi_rdata[29]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(29),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(9),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[29]\,
+ I5 => sel0(2),
+ O => \axi_rdata[29]_i_2_n_0\
+ );
+\axi_rdata[29]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(29),
+ I1 => slv_reg6(29),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(29),
+ O => \axi_rdata[29]_i_3_n_0\
+ );
+\axi_rdata[29]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(61),
+ I1 => \^d\(29),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[29]\,
+ O => \axi_rdata[29]_i_4_n_0\
+ );
+\axi_rdata[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[2]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[2]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[2]_i_4_n_0\,
+ O => reg_data_out(2)
+ );
+\axi_rdata[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(2),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(2),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[2]\,
+ I5 => sel0(2),
+ O => \axi_rdata[2]_i_2_n_0\
+ );
+\axi_rdata[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(2),
+ I1 => slv_reg6(2),
+ I2 => sel0(1),
+ I3 => slv_reg5(2),
+ I4 => sel0(0),
+ I5 => slv_reg4(2),
+ O => \axi_rdata[2]_i_3_n_0\
+ );
+\axi_rdata[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^d\(34),
+ I1 => \^d\(2),
+ I2 => sel0(1),
+ I3 => \^slv_reg1_reg[5]_0\(2),
+ I4 => sel0(0),
+ I5 => slv_reg0_read(2),
+ O => \axi_rdata[2]_i_4_n_0\
+ );
+\axi_rdata[30]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[30]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[30]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[30]_i_4_n_0\,
+ O => reg_data_out(30)
+ );
+\axi_rdata[30]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(30),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(10),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[30]\,
+ I5 => sel0(2),
+ O => \axi_rdata[30]_i_2_n_0\
+ );
+\axi_rdata[30]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(30),
+ I1 => slv_reg6(30),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(30),
+ O => \axi_rdata[30]_i_3_n_0\
+ );
+\axi_rdata[30]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(62),
+ I1 => \^d\(30),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[30]\,
+ O => \axi_rdata[30]_i_4_n_0\
+ );
+\axi_rdata[31]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => \^s00_axi_arready\,
+ I1 => s00_axi_arvalid,
+ I2 => \^s00_axi_rvalid\,
+ O => slv_reg_rden
+ );
+\axi_rdata[31]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[31]_i_3_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[31]_i_4_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[31]_i_5_n_0\,
+ O => reg_data_out(31)
+ );
+\axi_rdata[31]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(31),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MAX(11),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[31]\,
+ I5 => sel0(2),
+ O => \axi_rdata[31]_i_3_n_0\
+ );
+\axi_rdata[31]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(31),
+ I1 => slv_reg6(31),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(31),
+ O => \axi_rdata[31]_i_4_n_0\
+ );
+\axi_rdata[31]_i_5\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(63),
+ I1 => \^d\(31),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[31]\,
+ O => \axi_rdata[31]_i_5_n_0\
+ );
+\axi_rdata[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[3]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[3]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[3]_i_4_n_0\,
+ O => reg_data_out(3)
+ );
+\axi_rdata[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(3),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(3),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[3]\,
+ I5 => sel0(2),
+ O => \axi_rdata[3]_i_2_n_0\
+ );
+\axi_rdata[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => slv_reg6(3),
+ I2 => sel0(1),
+ I3 => slv_reg5(3),
+ I4 => sel0(0),
+ I5 => slv_reg4(3),
+ O => \axi_rdata[3]_i_3_n_0\
+ );
+\axi_rdata[3]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(35),
+ I1 => \^d\(3),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \^slv_reg1_reg[5]_0\(3),
+ O => \axi_rdata[3]_i_4_n_0\
+ );
+\axi_rdata[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[4]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[4]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[4]_i_4_n_0\,
+ O => reg_data_out(4)
+ );
+\axi_rdata[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(4),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(4),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[4]\,
+ I5 => sel0(2),
+ O => \axi_rdata[4]_i_2_n_0\
+ );
+\axi_rdata[4]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(4),
+ I1 => slv_reg6(4),
+ I2 => sel0(1),
+ I3 => slv_reg5(4),
+ I4 => sel0(0),
+ I5 => slv_reg4(4),
+ O => \axi_rdata[4]_i_3_n_0\
+ );
+\axi_rdata[4]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(36),
+ I1 => \^d\(4),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \^slv_reg1_reg[5]_0\(4),
+ O => \axi_rdata[4]_i_4_n_0\
+ );
+\axi_rdata[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[5]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[5]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[5]_i_4_n_0\,
+ O => reg_data_out(5)
+ );
+\axi_rdata[5]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(5),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(5),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[5]\,
+ I5 => sel0(2),
+ O => \axi_rdata[5]_i_2_n_0\
+ );
+\axi_rdata[5]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => slv_reg6(5),
+ I2 => sel0(1),
+ I3 => slv_reg5(5),
+ I4 => sel0(0),
+ I5 => slv_reg4(5),
+ O => \axi_rdata[5]_i_3_n_0\
+ );
+\axi_rdata[5]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(37),
+ I1 => \^d\(5),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \^slv_reg1_reg[5]_0\(5),
+ O => \axi_rdata[5]_i_4_n_0\
+ );
+\axi_rdata[6]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[6]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[6]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[6]_i_4_n_0\,
+ O => reg_data_out(6)
+ );
+\axi_rdata[6]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(6),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(6),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[6]\,
+ I5 => sel0(2),
+ O => \axi_rdata[6]_i_2_n_0\
+ );
+\axi_rdata[6]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(6),
+ I1 => slv_reg6(6),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(6),
+ O => \axi_rdata[6]_i_3_n_0\
+ );
+\axi_rdata[6]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(38),
+ I1 => \^d\(6),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[6]\,
+ O => \axi_rdata[6]_i_4_n_0\
+ );
+\axi_rdata[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[7]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[7]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[7]_i_4_n_0\,
+ O => reg_data_out(7)
+ );
+\axi_rdata[7]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(7),
+ I1 => sel0(0),
+ I2 => TICKS_BITGAP_MIN(7),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[7]\,
+ I5 => sel0(2),
+ O => \axi_rdata[7]_i_2_n_0\
+ );
+\axi_rdata[7]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => slv_reg6(7),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(7),
+ O => \axi_rdata[7]_i_3_n_0\
+ );
+\axi_rdata[7]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(39),
+ I1 => \^d\(7),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[7]\,
+ O => \axi_rdata[7]_i_4_n_0\
+ );
+\axi_rdata[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[8]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[8]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[8]_i_4_n_0\,
+ O => reg_data_out(8)
+ );
+\axi_rdata[8]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(8),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(0),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[8]\,
+ I5 => sel0(2),
+ O => \axi_rdata[8]_i_2_n_0\
+ );
+\axi_rdata[8]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(8),
+ I1 => slv_reg6(8),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(8),
+ O => \axi_rdata[8]_i_3_n_0\
+ );
+\axi_rdata[8]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(40),
+ I1 => \^d\(8),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[8]\,
+ O => \axi_rdata[8]_i_4_n_0\
+ );
+\axi_rdata[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"B8BBB888"
+ )
+ port map (
+ I0 => \axi_rdata[9]_i_2_n_0\,
+ I1 => sel0(3),
+ I2 => \axi_rdata[9]_i_3_n_0\,
+ I3 => sel0(2),
+ I4 => \axi_rdata[9]_i_4_n_0\,
+ O => reg_data_out(9)
+ );
+\axi_rdata[9]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000033E200E2"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(9),
+ I1 => sel0(0),
+ I2 => \^slv_reg9_reg[19]_0\(1),
+ I3 => sel0(1),
+ I4 => \slv_reg10_reg_n_0_[9]\,
+ I5 => sel0(2),
+ O => \axi_rdata[9]_i_2_n_0\
+ );
+\axi_rdata[9]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^q\(9),
+ I1 => slv_reg6(9),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => slv_reg5(9),
+ O => \axi_rdata[9]_i_3_n_0\
+ );
+\axi_rdata[9]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AFC0A0C0"
+ )
+ port map (
+ I0 => \^d\(41),
+ I1 => \^d\(9),
+ I2 => sel0(1),
+ I3 => sel0(0),
+ I4 => \slv_reg1_reg_n_0_[9]\,
+ O => \axi_rdata[9]_i_4_n_0\
+ );
+\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(0),
+ Q => s00_axi_rdata(0),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(10),
+ Q => s00_axi_rdata(10),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(11),
+ Q => s00_axi_rdata(11),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(12),
+ Q => s00_axi_rdata(12),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(13),
+ Q => s00_axi_rdata(13),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(14),
+ Q => s00_axi_rdata(14),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(15),
+ Q => s00_axi_rdata(15),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(16),
+ Q => s00_axi_rdata(16),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(17),
+ Q => s00_axi_rdata(17),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(18),
+ Q => s00_axi_rdata(18),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(19),
+ Q => s00_axi_rdata(19),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(1),
+ Q => s00_axi_rdata(1),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(20),
+ Q => s00_axi_rdata(20),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(21),
+ Q => s00_axi_rdata(21),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(22),
+ Q => s00_axi_rdata(22),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(23),
+ Q => s00_axi_rdata(23),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(24),
+ Q => s00_axi_rdata(24),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(25),
+ Q => s00_axi_rdata(25),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(26),
+ Q => s00_axi_rdata(26),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(27),
+ Q => s00_axi_rdata(27),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(28),
+ Q => s00_axi_rdata(28),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(29),
+ Q => s00_axi_rdata(29),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(2),
+ Q => s00_axi_rdata(2),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(30),
+ Q => s00_axi_rdata(30),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(31),
+ Q => s00_axi_rdata(31),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(3),
+ Q => s00_axi_rdata(3),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(4),
+ Q => s00_axi_rdata(4),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(5),
+ Q => s00_axi_rdata(5),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(6),
+ Q => s00_axi_rdata(6),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(7),
+ Q => s00_axi_rdata(7),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(8),
+ Q => s00_axi_rdata(8),
+ R => axi_awready_i_1_n_0
+ );
+\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => slv_reg_rden,
+ D => reg_data_out(9),
+ Q => s00_axi_rdata(9),
+ R => axi_awready_i_1_n_0
+ );
+axi_rvalid_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"08F8"
+ )
+ port map (
+ I0 => s00_axi_arvalid,
+ I1 => \^s00_axi_arready\,
+ I2 => \^s00_axi_rvalid\,
+ I3 => s00_axi_rready,
+ O => axi_rvalid_i_1_n_0
+ );
+axi_rvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => axi_rvalid_i_1_n_0,
+ Q => \^s00_axi_rvalid\,
+ R => axi_awready_i_1_n_0
+ );
+axi_wready_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_wready\,
+ O => axi_wready0
+ );
+axi_wready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => axi_wready0,
+ Q => \^s00_axi_wready\,
+ R => axi_awready_i_1_n_0
+ );
+cmd_out_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => seriali_buf,
+ I1 => axi_config(1),
+ O => cmd_out
+ );
+\counter[11]__0_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^axi_control\(1),
+ I1 => \^axi_control\(0),
+ O => \slv_reg0_pulse_reg[1]_0\
+ );
+\i__carry__0_i_3__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(31),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(11),
+ I2 => \^slv_reg8_reg[31]_0\(30),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(10),
+ O => \slv_reg8_reg[31]_1\(1)
+ );
+\i__carry__0_i_4__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(29),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(9),
+ I2 => \^slv_reg8_reg[31]_0\(28),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(8),
+ O => \slv_reg8_reg[31]_1\(0)
+ );
+\i__carry_i_5__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(7),
+ I2 => \^q\(6),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(6),
+ O => S(3)
+ );
+\i__carry_i_5__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(27),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(7),
+ I2 => \^slv_reg8_reg[31]_0\(26),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(6),
+ O => \slv_reg8_reg[27]_0\(3)
+ );
+\i__carry_i_5__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(7),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(7),
+ I2 => \^slv_reg8_reg[31]_0\(6),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(6),
+ O => \slv_reg8_reg[7]_0\(3)
+ );
+\i__carry_i_6__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(5),
+ I2 => \^q\(4),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(4),
+ O => S(2)
+ );
+\i__carry_i_6__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(25),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(5),
+ I2 => \^slv_reg8_reg[31]_0\(24),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(4),
+ O => \slv_reg8_reg[27]_0\(2)
+ );
+\i__carry_i_6__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(5),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(5),
+ I2 => \^slv_reg8_reg[31]_0\(4),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(4),
+ O => \slv_reg8_reg[7]_0\(2)
+ );
+\i__carry_i_7__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(3),
+ I2 => \^q\(2),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(2),
+ O => S(1)
+ );
+\i__carry_i_7__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(23),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(3),
+ I2 => \^slv_reg8_reg[31]_0\(22),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(2),
+ O => \slv_reg8_reg[27]_0\(1)
+ );
+\i__carry_i_7__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(3),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(3),
+ I2 => \^slv_reg8_reg[31]_0\(2),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(2),
+ O => \slv_reg8_reg[7]_0\(1)
+ );
+\i__carry_i_8__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(1),
+ I2 => \^q\(0),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(0),
+ O => S(0)
+ );
+\i__carry_i_8__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(21),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(1),
+ I2 => \^slv_reg8_reg[31]_0\(20),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(0),
+ O => \slv_reg8_reg[27]_0\(0)
+ );
+\i__carry_i_8__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^slv_reg8_reg[31]_0\(1),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(1),
+ I2 => \^slv_reg8_reg[31]_0\(0),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(0),
+ O => \slv_reg8_reg[7]_0\(0)
+ );
+\reg_nbitsout2_carry__0_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(31),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(11),
+ I2 => \^q\(30),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(10),
+ O => \slv_reg7_reg[31]_0\(1)
+ );
+\reg_nbitsout2_carry__0_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(29),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(9),
+ I2 => \^q\(28),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(8),
+ O => \slv_reg7_reg[31]_0\(0)
+ );
+reg_nbitsout2_carry_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(27),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(7),
+ I2 => \^q\(26),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(6),
+ O => DI(3)
+ );
+reg_nbitsout2_carry_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(25),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(5),
+ I2 => \^q\(24),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(4),
+ O => DI(2)
+ );
+reg_nbitsout2_carry_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(23),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(3),
+ I2 => \^q\(22),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(2),
+ O => DI(1)
+ );
+reg_nbitsout2_carry_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(21),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0\(1),
+ I2 => \^q\(20),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0\(0),
+ O => DI(0)
+ );
+\slv_reg0_pulse[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \^axi_control\(0),
+ I1 => p_1_in(0),
+ I2 => s00_axi_wdata(0),
+ I3 => \slv_reg_wren__2\,
+ I4 => s00_axi_aresetn,
+ O => \slv_reg0_pulse[0]_i_1_n_0\
+ );
+\slv_reg0_pulse[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \^axi_control\(1),
+ I1 => p_1_in(0),
+ I2 => s00_axi_wdata(1),
+ I3 => \slv_reg_wren__2\,
+ I4 => s00_axi_aresetn,
+ O => \slv_reg0_pulse[1]_i_1_n_0\
+ );
+\slv_reg0_pulse[1]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000010"
+ )
+ port map (
+ I0 => p_0_in(3),
+ I1 => p_0_in(2),
+ I2 => s00_axi_wstrb(0),
+ I3 => p_0_in(0),
+ I4 => p_0_in(1),
+ O => p_1_in(0)
+ );
+\slv_reg0_pulse[1]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_awvalid,
+ I1 => \^s00_axi_awready\,
+ I2 => \^s00_axi_wready\,
+ I3 => s00_axi_wvalid,
+ O => \slv_reg_wren__2\
+ );
+\slv_reg0_pulse_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg0_pulse[0]_i_1_n_0\,
+ Q => \^axi_control\(0),
+ R => '0'
+ );
+\slv_reg0_pulse_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg0_pulse[1]_i_1_n_0\,
+ Q => \^axi_control\(1),
+ R => '0'
+ );
+\slv_reg0_read_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg0_read_reg[2]_0\(0),
+ Q => slv_reg0_read(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg0_read_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg0_read_reg[2]_0\(1),
+ Q => slv_reg0_read(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg0_read_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg0_read_reg[2]_0\(2),
+ Q => slv_reg0_read(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => s00_axi_wstrb(1),
+ I3 => p_0_in(1),
+ I4 => p_0_in(0),
+ I5 => p_0_in(2),
+ O => \slv_reg10[15]_i_1_n_0\
+ );
+\slv_reg10[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => s00_axi_wstrb(2),
+ I3 => p_0_in(1),
+ I4 => p_0_in(0),
+ I5 => p_0_in(2),
+ O => \slv_reg10[23]_i_1_n_0\
+ );
+\slv_reg10[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => s00_axi_wstrb(3),
+ I3 => p_0_in(1),
+ I4 => p_0_in(0),
+ I5 => p_0_in(2),
+ O => \slv_reg10[31]_i_1_n_0\
+ );
+\slv_reg10[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => s00_axi_wstrb(0),
+ I3 => p_0_in(1),
+ I4 => p_0_in(0),
+ I5 => p_0_in(2),
+ O => \slv_reg10[7]_i_1_n_0\
+ );
+\slv_reg10_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^slv_reg10_reg[0]_0\(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \slv_reg10_reg_n_0_[10]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \slv_reg10_reg_n_0_[11]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \slv_reg10_reg_n_0_[12]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \slv_reg10_reg_n_0_[13]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \slv_reg10_reg_n_0_[14]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \slv_reg10_reg_n_0_[15]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \slv_reg10_reg_n_0_[16]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \slv_reg10_reg_n_0_[17]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \slv_reg10_reg_n_0_[18]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \slv_reg10_reg_n_0_[19]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => axi_config(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \slv_reg10_reg_n_0_[20]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \slv_reg10_reg_n_0_[21]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \slv_reg10_reg_n_0_[22]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \slv_reg10_reg_n_0_[23]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \slv_reg10_reg_n_0_[24]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \slv_reg10_reg_n_0_[25]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \slv_reg10_reg_n_0_[26]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \slv_reg10_reg_n_0_[27]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \slv_reg10_reg_n_0_[28]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \slv_reg10_reg_n_0_[29]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \slv_reg10_reg_n_0_[2]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \slv_reg10_reg_n_0_[30]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \slv_reg10_reg_n_0_[31]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \slv_reg10_reg_n_0_[3]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \slv_reg10_reg_n_0_[4]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \slv_reg10_reg_n_0_[5]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \slv_reg10_reg_n_0_[6]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \slv_reg10_reg_n_0_[7]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \slv_reg10_reg_n_0_[8]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg10_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg10[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \slv_reg10_reg_n_0_[9]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(1),
+ I2 => p_0_in(3),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(0),
+ O => \slv_reg1[15]_i_1_n_0\
+ );
+\slv_reg1[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(2),
+ I2 => p_0_in(3),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(0),
+ O => \slv_reg1[23]_i_1_n_0\
+ );
+\slv_reg1[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(3),
+ I2 => p_0_in(3),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(0),
+ O => \slv_reg1[31]_i_1_n_0\
+ );
+\slv_reg1[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(0),
+ I2 => p_0_in(3),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(0),
+ O => \slv_reg1[7]_i_1_n_0\
+ );
+\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^slv_reg1_reg[5]_0\(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \slv_reg1_reg_n_0_[10]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \slv_reg1_reg_n_0_[11]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \slv_reg1_reg_n_0_[12]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \slv_reg1_reg_n_0_[13]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \slv_reg1_reg_n_0_[14]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \slv_reg1_reg_n_0_[15]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \slv_reg1_reg_n_0_[16]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \slv_reg1_reg_n_0_[17]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \slv_reg1_reg_n_0_[18]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \slv_reg1_reg_n_0_[19]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => \^slv_reg1_reg[5]_0\(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \slv_reg1_reg_n_0_[20]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \slv_reg1_reg_n_0_[21]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \slv_reg1_reg_n_0_[22]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \slv_reg1_reg_n_0_[23]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \slv_reg1_reg_n_0_[24]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \slv_reg1_reg_n_0_[25]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \slv_reg1_reg_n_0_[26]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \slv_reg1_reg_n_0_[27]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \slv_reg1_reg_n_0_[28]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \slv_reg1_reg_n_0_[29]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \^slv_reg1_reg[5]_0\(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \slv_reg1_reg_n_0_[30]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \slv_reg1_reg_n_0_[31]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \^slv_reg1_reg[5]_0\(3),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \^slv_reg1_reg[5]_0\(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \^slv_reg1_reg[5]_0\(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \slv_reg1_reg_n_0_[6]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \slv_reg1_reg_n_0_[7]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \slv_reg1_reg_n_0_[8]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg1[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \slv_reg1_reg_n_0_[9]\,
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(1),
+ I2 => p_0_in(3),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => p_0_in(1),
+ O => \slv_reg2[15]_i_1_n_0\
+ );
+\slv_reg2[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(2),
+ I2 => p_0_in(3),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => p_0_in(1),
+ O => \slv_reg2[23]_i_1_n_0\
+ );
+\slv_reg2[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(3),
+ I2 => p_0_in(3),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => p_0_in(1),
+ O => \slv_reg2[31]_i_1_n_0\
+ );
+\slv_reg2[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(0),
+ I2 => p_0_in(3),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => p_0_in(1),
+ O => \slv_reg2[7]_i_1_n_0\
+ );
+\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^d\(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \^d\(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \^d\(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \^d\(12),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \^d\(13),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \^d\(14),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \^d\(15),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \^d\(16),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \^d\(17),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \^d\(18),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \^d\(19),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => \^d\(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \^d\(20),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \^d\(21),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \^d\(22),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \^d\(23),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \^d\(24),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \^d\(25),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \^d\(26),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \^d\(27),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \^d\(28),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \^d\(29),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \^d\(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \^d\(30),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \^d\(31),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \^d\(3),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \^d\(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \^d\(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \^d\(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \^d\(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \^d\(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg2[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \^d\(9),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(1),
+ I2 => p_0_in(0),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(3),
+ O => \slv_reg3[15]_i_1_n_0\
+ );
+\slv_reg3[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(2),
+ I2 => p_0_in(0),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(3),
+ O => \slv_reg3[23]_i_1_n_0\
+ );
+\slv_reg3[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(3),
+ I2 => p_0_in(0),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(3),
+ O => \slv_reg3[31]_i_1_n_0\
+ );
+\slv_reg3[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => s00_axi_wstrb(0),
+ I2 => p_0_in(0),
+ I3 => p_0_in(1),
+ I4 => p_0_in(2),
+ I5 => p_0_in(3),
+ O => \slv_reg3[7]_i_1_n_0\
+ );
+\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^d\(32),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \^d\(42),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \^d\(43),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \^d\(44),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \^d\(45),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \^d\(46),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \^d\(47),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \^d\(48),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \^d\(49),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \^d\(50),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \^d\(51),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => \^d\(33),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \^d\(52),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \^d\(53),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \^d\(54),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \^d\(55),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \^d\(56),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \^d\(57),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \^d\(58),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \^d\(59),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \^d\(60),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \^d\(61),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \^d\(34),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \^d\(62),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \^d\(63),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \^d\(35),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \^d\(36),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \^d\(37),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \^d\(38),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \^d\(39),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \^d\(40),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg3[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \^d\(41),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(0),
+ Q => slv_reg4(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(1),
+ Q => slv_reg4(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(2),
+ Q => slv_reg4(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(3),
+ Q => slv_reg4(3),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(4),
+ Q => slv_reg4(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg4_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg4_reg[5]_0\(5),
+ Q => slv_reg4(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(0),
+ Q => slv_reg5(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(10),
+ Q => slv_reg5(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(11),
+ Q => slv_reg5(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(12),
+ Q => slv_reg5(12),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(13),
+ Q => slv_reg5(13),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(14),
+ Q => slv_reg5(14),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(15),
+ Q => slv_reg5(15),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(16),
+ Q => slv_reg5(16),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(17),
+ Q => slv_reg5(17),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(18),
+ Q => slv_reg5(18),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(19),
+ Q => slv_reg5(19),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(1),
+ Q => slv_reg5(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(20),
+ Q => slv_reg5(20),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(21),
+ Q => slv_reg5(21),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(22),
+ Q => slv_reg5(22),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(23),
+ Q => slv_reg5(23),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(24),
+ Q => slv_reg5(24),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(25),
+ Q => slv_reg5(25),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(26),
+ Q => slv_reg5(26),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(27),
+ Q => slv_reg5(27),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(28),
+ Q => slv_reg5(28),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(29),
+ Q => slv_reg5(29),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(2),
+ Q => slv_reg5(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(30),
+ Q => slv_reg5(30),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(31),
+ Q => slv_reg5(31),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(3),
+ Q => slv_reg5(3),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(4),
+ Q => slv_reg5(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(5),
+ Q => slv_reg5(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(6),
+ Q => slv_reg5(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(7),
+ Q => slv_reg5(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(8),
+ Q => slv_reg5(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg5_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(9),
+ Q => slv_reg5(9),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(32),
+ Q => slv_reg6(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(42),
+ Q => slv_reg6(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(43),
+ Q => slv_reg6(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(44),
+ Q => slv_reg6(12),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(45),
+ Q => slv_reg6(13),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(46),
+ Q => slv_reg6(14),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(47),
+ Q => slv_reg6(15),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(48),
+ Q => slv_reg6(16),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(49),
+ Q => slv_reg6(17),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(50),
+ Q => slv_reg6(18),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(51),
+ Q => slv_reg6(19),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(33),
+ Q => slv_reg6(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(52),
+ Q => slv_reg6(20),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(53),
+ Q => slv_reg6(21),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(54),
+ Q => slv_reg6(22),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(55),
+ Q => slv_reg6(23),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(56),
+ Q => slv_reg6(24),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(57),
+ Q => slv_reg6(25),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(58),
+ Q => slv_reg6(26),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(59),
+ Q => slv_reg6(27),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(60),
+ Q => slv_reg6(28),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(61),
+ Q => slv_reg6(29),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(34),
+ Q => slv_reg6(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(62),
+ Q => slv_reg6(30),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(63),
+ Q => slv_reg6(31),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(35),
+ Q => slv_reg6(3),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(36),
+ Q => slv_reg6(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(37),
+ Q => slv_reg6(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(38),
+ Q => slv_reg6(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(39),
+ Q => slv_reg6(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(40),
+ Q => slv_reg6(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg6_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \slv_reg6_reg[31]_0\(41),
+ Q => slv_reg6(9),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(2),
+ I2 => s00_axi_wstrb(1),
+ I3 => p_0_in(0),
+ I4 => p_0_in(1),
+ I5 => p_0_in(3),
+ O => \slv_reg7[15]_i_1_n_0\
+ );
+\slv_reg7[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(2),
+ I2 => s00_axi_wstrb(2),
+ I3 => p_0_in(0),
+ I4 => p_0_in(1),
+ I5 => p_0_in(3),
+ O => \slv_reg7[23]_i_1_n_0\
+ );
+\slv_reg7[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(2),
+ I2 => s00_axi_wstrb(3),
+ I3 => p_0_in(0),
+ I4 => p_0_in(1),
+ I5 => p_0_in(3),
+ O => \slv_reg7[31]_i_1_n_0\
+ );
+\slv_reg7[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(2),
+ I2 => s00_axi_wstrb(0),
+ I3 => p_0_in(0),
+ I4 => p_0_in(1),
+ I5 => p_0_in(3),
+ O => \slv_reg7[7]_i_1_n_0\
+ );
+\slv_reg7_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^q\(0),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \^q\(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \^q\(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \^q\(12),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[13]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \^q\(13),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \^q\(14),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \^q\(15),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \^q\(16),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \^q\(17),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \^q\(18),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \^q\(19),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[1]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => \^q\(1),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[20]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \^q\(20),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[21]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \^q\(21),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[22]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \^q\(22),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \^q\(23),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[24]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \^q\(24),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[25]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \^q\(25),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \^q\(26),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \^q\(27),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \^q\(28),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \^q\(29),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[2]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \^q\(2),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \^q\(30),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \^q\(31),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \^q\(3),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \^q\(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \^q\(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \^q\(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \^q\(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \^q\(8),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg7_reg[9]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg7[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \^q\(9),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(1),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => s00_axi_wstrb(1),
+ O => \slv_reg8[15]_i_1_n_0\
+ );
+\slv_reg8[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(1),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => s00_axi_wstrb(2),
+ O => \slv_reg8[23]_i_1_n_0\
+ );
+\slv_reg8[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(1),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => s00_axi_wstrb(3),
+ O => \slv_reg8[31]_i_1_n_0\
+ );
+\slv_reg8[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000800000000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(1),
+ I3 => p_0_in(0),
+ I4 => p_0_in(2),
+ I5 => s00_axi_wstrb(0),
+ O => \slv_reg8[7]_i_1_n_0\
+ );
+\slv_reg8_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => \^slv_reg8_reg[31]_0\(0),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[10]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \^slv_reg8_reg[31]_0\(10),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[11]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \^slv_reg8_reg[31]_0\(11),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[12]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \^slv_reg8_reg[31]_0\(12),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[13]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \^slv_reg8_reg[31]_0\(13),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \^slv_reg8_reg[31]_0\(14),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[15]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \^slv_reg8_reg[31]_0\(15),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \^slv_reg8_reg[31]_0\(16),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \^slv_reg8_reg[31]_0\(17),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \^slv_reg8_reg[31]_0\(18),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \^slv_reg8_reg[31]_0\(19),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => \^slv_reg8_reg[31]_0\(1),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => \^slv_reg8_reg[31]_0\(20),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[21]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => \^slv_reg8_reg[31]_0\(21),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[22]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => \^slv_reg8_reg[31]_0\(22),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => \^slv_reg8_reg[31]_0\(23),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[24]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => \^slv_reg8_reg[31]_0\(24),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[25]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => \^slv_reg8_reg[31]_0\(25),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => \^slv_reg8_reg[31]_0\(26),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => \^slv_reg8_reg[31]_0\(27),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[28]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => \^slv_reg8_reg[31]_0\(28),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => \^slv_reg8_reg[31]_0\(29),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => \^slv_reg8_reg[31]_0\(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => \^slv_reg8_reg[31]_0\(30),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => \^slv_reg8_reg[31]_0\(31),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => \^slv_reg8_reg[31]_0\(3),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => \^slv_reg8_reg[31]_0\(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => \^slv_reg8_reg[31]_0\(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[6]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => \^slv_reg8_reg[31]_0\(6),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => \^slv_reg8_reg[31]_0\(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \^slv_reg8_reg[31]_0\(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg8_reg[9]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg8[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \^slv_reg8_reg[31]_0\(9),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(0),
+ I3 => s00_axi_wstrb(1),
+ I4 => p_0_in(1),
+ I5 => p_0_in(2),
+ O => \slv_reg9[15]_i_1_n_0\
+ );
+\slv_reg9[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(0),
+ I3 => s00_axi_wstrb(2),
+ I4 => p_0_in(1),
+ I5 => p_0_in(2),
+ O => \slv_reg9[23]_i_1_n_0\
+ );
+\slv_reg9[31]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(0),
+ I3 => s00_axi_wstrb(3),
+ I4 => p_0_in(1),
+ I5 => p_0_in(2),
+ O => \slv_reg9[31]_i_1_n_0\
+ );
+\slv_reg9[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000008000"
+ )
+ port map (
+ I0 => \slv_reg_wren__2\,
+ I1 => p_0_in(3),
+ I2 => p_0_in(0),
+ I3 => s00_axi_wstrb(0),
+ I4 => p_0_in(1),
+ I5 => p_0_in(2),
+ O => \slv_reg9[7]_i_1_n_0\
+ );
+\slv_reg9_reg[0]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(0),
+ Q => TICKS_BITGAP_MIN(0),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(10),
+ Q => \^slv_reg9_reg[19]_0\(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[11]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(11),
+ Q => \^slv_reg9_reg[19]_0\(3),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(12),
+ Q => \^slv_reg9_reg[19]_0\(4),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[13]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(13),
+ Q => \^slv_reg9_reg[19]_0\(5),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[14]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(14),
+ Q => \^slv_reg9_reg[19]_0\(6),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(15),
+ Q => \^slv_reg9_reg[19]_0\(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(16),
+ Q => \^slv_reg9_reg[19]_0\(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(17),
+ Q => \^slv_reg9_reg[19]_0\(9),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(18),
+ Q => \^slv_reg9_reg[19]_0\(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(19),
+ Q => \^slv_reg9_reg[19]_0\(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[1]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(1),
+ Q => TICKS_BITGAP_MIN(1),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[20]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(20),
+ Q => TICKS_BITGAP_MAX(0),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[21]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(21),
+ Q => TICKS_BITGAP_MAX(1),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(22),
+ Q => TICKS_BITGAP_MAX(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[23]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[23]_i_1_n_0\,
+ D => s00_axi_wdata(23),
+ Q => TICKS_BITGAP_MAX(3),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[24]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(24),
+ Q => TICKS_BITGAP_MAX(4),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[25]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(25),
+ Q => TICKS_BITGAP_MAX(5),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(26),
+ Q => TICKS_BITGAP_MAX(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[27]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(27),
+ Q => TICKS_BITGAP_MAX(7),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(28),
+ Q => TICKS_BITGAP_MAX(8),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(29),
+ Q => TICKS_BITGAP_MAX(9),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(2),
+ Q => TICKS_BITGAP_MIN(2),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(30),
+ Q => TICKS_BITGAP_MAX(10),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[31]_i_1_n_0\,
+ D => s00_axi_wdata(31),
+ Q => TICKS_BITGAP_MAX(11),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[3]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(3),
+ Q => TICKS_BITGAP_MIN(3),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[4]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(4),
+ Q => TICKS_BITGAP_MIN(4),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(5),
+ Q => TICKS_BITGAP_MIN(5),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(6),
+ Q => TICKS_BITGAP_MIN(6),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[7]_i_1_n_0\,
+ D => s00_axi_wdata(7),
+ Q => TICKS_BITGAP_MIN(7),
+ R => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[8]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(8),
+ Q => \^slv_reg9_reg[19]_0\(0),
+ S => axi_awready_i_1_n_0
+ );
+\slv_reg9_reg[9]\: unisim.vcomponents.FDSE
+ port map (
+ C => s00_axi_aclk,
+ CE => \slv_reg9[15]_i_1_n_0\,
+ D => s00_axi_wdata(9),
+ Q => \^slv_reg9_reg[19]_0\(1),
+ S => axi_awready_i_1_n_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_endeavour_axi_contro_5_0_endeavour_master is
+ port (
+ D : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ cmd_in : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ \reg_nbitsout_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ I : out STD_LOGIC;
+ \reg_dataout_reg[63]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ axi_control : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ cmd_out : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ DI : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \reg_nbitsout_reg[5]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \reg_nbitsout1_inferred__0/i__carry__0_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \reg_nbitsout_reg[5]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \reg_nbitsout1_inferred__1/i__carry__0_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \reg_nbitsin_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ \reg_nbitsout2_carry__0_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ \reg_nbitsout1_inferred__0/i__carry__0_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ CMD_IN_P : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \counter_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ \reg_nbitsout_reg[5]_3\ : in STD_LOGIC;
+ \reg_datain_reg[63]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_endeavour_axi_contro_5_0_endeavour_master : entity is "endeavour_master";
+end TopLevel_endeavour_axi_contro_5_0_endeavour_master;
+
+architecture STRUCTURE of TopLevel_endeavour_axi_contro_5_0_endeavour_master is
+ signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \FSM_sequential_fsm_rd[0]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[1]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_4_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_5_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_rd[2]_i_6_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_wr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_wr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_fsm_wr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal \^cmd_in\ : STD_LOGIC;
+ signal counter : STD_LOGIC;
+ signal \counter0_carry__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter0_carry__0_i_2_n_0\ : STD_LOGIC;
+ signal \counter0_carry__0_i_3_n_0\ : STD_LOGIC;
+ signal \counter0_carry__0_i_4_n_0\ : STD_LOGIC;
+ signal \counter0_carry__0_n_0\ : STD_LOGIC;
+ signal \counter0_carry__0_n_1\ : STD_LOGIC;
+ signal \counter0_carry__0_n_2\ : STD_LOGIC;
+ signal \counter0_carry__0_n_3\ : STD_LOGIC;
+ signal \counter0_carry__1_i_1_n_0\ : STD_LOGIC;
+ signal \counter0_carry__1_i_2_n_0\ : STD_LOGIC;
+ signal \counter0_carry__1_i_3_n_0\ : STD_LOGIC;
+ signal \counter0_carry__1_n_2\ : STD_LOGIC;
+ signal \counter0_carry__1_n_3\ : STD_LOGIC;
+ signal counter0_carry_i_1_n_0 : STD_LOGIC;
+ signal counter0_carry_i_2_n_0 : STD_LOGIC;
+ signal counter0_carry_i_3_n_0 : STD_LOGIC;
+ signal counter0_carry_i_4_n_0 : STD_LOGIC;
+ signal counter0_carry_n_0 : STD_LOGIC;
+ signal counter0_carry_n_1 : STD_LOGIC;
+ signal counter0_carry_n_2 : STD_LOGIC;
+ signal counter0_carry_n_3 : STD_LOGIC;
+ signal \counter[0]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[0]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[0]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[0]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[10]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[10]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[10]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[10]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[11]__0_i_2_n_0\ : STD_LOGIC;
+ signal \counter[11]__0_i_3_n_0\ : STD_LOGIC;
+ signal \counter[11]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[11]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[11]_i_4_n_0\ : STD_LOGIC;
+ signal \counter[1]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[1]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[1]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[2]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[2]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[2]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[3]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[3]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[3]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[3]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[4]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[4]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[4]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[5]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[5]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[5]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[5]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[6]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[6]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[6]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[6]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[7]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_10_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_11_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_12_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_13_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_14_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_15_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_16_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_17_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_18_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_19_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_20_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_21_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_22_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_23_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_24_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_25_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_26_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_27_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_4_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_7_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_8_n_0\ : STD_LOGIC;
+ signal \counter[7]_i_9_n_0\ : STD_LOGIC;
+ signal \counter[8]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[8]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[8]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[8]_i_3_n_0\ : STD_LOGIC;
+ signal \counter[9]__0_i_1_n_0\ : STD_LOGIC;
+ signal \counter[9]_i_1_n_0\ : STD_LOGIC;
+ signal \counter[9]_i_2_n_0\ : STD_LOGIC;
+ signal \counter[9]_i_3_n_0\ : STD_LOGIC;
+ signal \counter_reg[11]__0_i_4_n_2\ : STD_LOGIC;
+ signal \counter_reg[11]__0_i_4_n_3\ : STD_LOGIC;
+ signal \counter_reg[7]_i_3_n_0\ : STD_LOGIC;
+ signal \counter_reg[7]_i_5_n_0\ : STD_LOGIC;
+ signal \counter_reg[7]_i_6_n_0\ : STD_LOGIC;
+ signal \counter_reg_n_0_[0]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[10]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[11]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[1]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[2]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[3]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[4]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[5]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[6]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[7]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[8]\ : STD_LOGIC;
+ signal \counter_reg_n_0_[9]\ : STD_LOGIC;
+ signal data1 : STD_LOGIC_VECTOR ( 11 downto 1 );
+ signal fsm_rd02_in : STD_LOGIC;
+ signal \fsm_rd0_inferred__1/i__carry__0_n_3\ : STD_LOGIC;
+ signal \fsm_rd0_inferred__1/i__carry_n_0\ : STD_LOGIC;
+ signal \fsm_rd0_inferred__1/i__carry_n_1\ : STD_LOGIC;
+ signal \fsm_rd0_inferred__1/i__carry_n_2\ : STD_LOGIC;
+ signal \fsm_rd0_inferred__1/i__carry_n_3\ : STD_LOGIC;
+ signal \fsm_rd__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal fsm_wr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_1__1_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_1__2_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_2__1_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_2__2_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_3__1_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_3__2_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_4__1_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_4__2_n_0\ : STD_LOGIC;
+ signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
+ signal \i__carry_i_1__0_n_0\ : STD_LOGIC;
+ signal \i__carry_i_1__1_n_0\ : STD_LOGIC;
+ signal \i__carry_i_1__2_n_0\ : STD_LOGIC;
+ signal \i__carry_i_1_n_0\ : STD_LOGIC;
+ signal \i__carry_i_2__0_n_0\ : STD_LOGIC;
+ signal \i__carry_i_2__1_n_0\ : STD_LOGIC;
+ signal \i__carry_i_2__2_n_0\ : STD_LOGIC;
+ signal \i__carry_i_2__2_n_1\ : STD_LOGIC;
+ signal \i__carry_i_2__2_n_2\ : STD_LOGIC;
+ signal \i__carry_i_2__2_n_3\ : STD_LOGIC;
+ signal \i__carry_i_2_n_0\ : STD_LOGIC;
+ signal \i__carry_i_3__0_n_0\ : STD_LOGIC;
+ signal \i__carry_i_3__1_n_0\ : STD_LOGIC;
+ signal \i__carry_i_3__2_n_0\ : STD_LOGIC;
+ signal \i__carry_i_3__2_n_1\ : STD_LOGIC;
+ signal \i__carry_i_3__2_n_2\ : STD_LOGIC;
+ signal \i__carry_i_3__2_n_3\ : STD_LOGIC;
+ signal \i__carry_i_3_n_0\ : STD_LOGIC;
+ signal \i__carry_i_4__0_n_0\ : STD_LOGIC;
+ signal \i__carry_i_4__1_n_0\ : STD_LOGIC;
+ signal \i__carry_i_4__2_n_0\ : STD_LOGIC;
+ signal \i__carry_i_4_n_0\ : STD_LOGIC;
+ signal \i__carry_i_5_n_0\ : STD_LOGIC;
+ signal \i__carry_i_6_n_0\ : STD_LOGIC;
+ signal \i__carry_i_7_n_0\ : STD_LOGIC;
+ signal \i__carry_i_8_n_0\ : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal p_0_in_0 : STD_LOGIC_VECTOR ( 11 downto 1 );
+ signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal reg_busy_i_1_n_0 : STD_LOGIC;
+ signal reg_datain : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[0]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[10]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[11]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[12]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[13]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[14]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[15]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[16]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[17]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[18]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[19]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[1]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[20]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[21]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[22]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[23]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[24]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[25]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[26]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[27]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[28]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[29]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[2]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[30]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[31]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[32]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[33]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[34]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[35]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[36]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[37]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[38]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[39]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[3]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[40]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[41]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[42]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[43]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[44]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[45]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[46]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[47]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[48]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[49]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[4]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[50]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[51]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[52]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[53]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[54]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[55]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[56]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[57]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[58]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[59]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[5]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[60]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[61]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[62]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[63]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[6]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[7]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[8]\ : STD_LOGIC;
+ signal \reg_datain_reg_n_0_[9]\ : STD_LOGIC;
+ signal \reg_dataout[63]_i_2_n_0\ : STD_LOGIC;
+ signal \^reg_dataout_reg[63]_0\ : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal reg_datavalid : STD_LOGIC;
+ signal reg_datavalid_i_1_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_2_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_3_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_4_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_6_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_7_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_8_n_0 : STD_LOGIC;
+ signal reg_datavalid_i_9_n_0 : STD_LOGIC;
+ signal reg_error1_out : STD_LOGIC;
+ signal reg_error_i_1_n_0 : STD_LOGIC;
+ signal reg_nbitsin : STD_LOGIC;
+ signal \reg_nbitsin[0]_i_1_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[1]_i_1_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[2]_i_1_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[3]_i_1_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[3]_i_2_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[4]_i_1_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[4]_i_2_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[5]_i_2_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin[5]_i_3_n_0\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[0]\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[1]\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[2]\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[3]\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[4]\ : STD_LOGIC;
+ signal \reg_nbitsin_reg_n_0_[5]\ : STD_LOGIC;
+ signal reg_nbitsout : STD_LOGIC;
+ signal reg_nbitsout1 : STD_LOGIC;
+ signal reg_nbitsout15_in : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__0/i__carry_n_0\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__0/i__carry_n_1\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__0/i__carry_n_2\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__0/i__carry_n_3\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__1/i__carry__0_n_3\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__1/i__carry_n_0\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__1/i__carry_n_1\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__1/i__carry_n_2\ : STD_LOGIC;
+ signal \reg_nbitsout1_inferred__1/i__carry_n_3\ : STD_LOGIC;
+ signal reg_nbitsout2 : STD_LOGIC;
+ signal reg_nbitsout26_in : STD_LOGIC;
+ signal \reg_nbitsout2_carry__0_i_3_n_0\ : STD_LOGIC;
+ signal \reg_nbitsout2_carry__0_i_4_n_0\ : STD_LOGIC;
+ signal \reg_nbitsout2_carry__0_n_3\ : STD_LOGIC;
+ signal reg_nbitsout2_carry_i_5_n_0 : STD_LOGIC;
+ signal reg_nbitsout2_carry_i_6_n_0 : STD_LOGIC;
+ signal reg_nbitsout2_carry_i_7_n_0 : STD_LOGIC;
+ signal reg_nbitsout2_carry_i_8_n_0 : STD_LOGIC;
+ signal reg_nbitsout2_carry_n_0 : STD_LOGIC;
+ signal reg_nbitsout2_carry_n_1 : STD_LOGIC;
+ signal reg_nbitsout2_carry_n_2 : STD_LOGIC;
+ signal reg_nbitsout2_carry_n_3 : STD_LOGIC;
+ signal \reg_nbitsout2_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
+ signal \reg_nbitsout2_inferred__0/i__carry_n_0\ : STD_LOGIC;
+ signal \reg_nbitsout2_inferred__0/i__carry_n_1\ : STD_LOGIC;
+ signal \reg_nbitsout2_inferred__0/i__carry_n_2\ : STD_LOGIC;
+ signal \reg_nbitsout2_inferred__0/i__carry_n_3\ : STD_LOGIC;
+ signal \^reg_nbitsout_reg[5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal reg_serialin : STD_LOGIC;
+ signal reg_serialin1 : STD_LOGIC;
+ signal serialout_i_1_n_0 : STD_LOGIC;
+ signal serialout_i_2_n_0 : STD_LOGIC;
+ signal serialout_i_3_n_0 : STD_LOGIC;
+ signal serialout_i_4_n_0 : STD_LOGIC;
+ signal serialout_i_5_n_0 : STD_LOGIC;
+ signal \NLW_counter0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_counter0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_counter_reg[11]__0_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_counter_reg[11]__0_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_fsm_rd0_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_fsm_rd0_inferred__1/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_fsm_rd0_inferred__1/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout1_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_reg_nbitsout1_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout1_inferred__1/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_reg_nbitsout1_inferred__1/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_reg_nbitsout2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout2_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_reg_nbitsout2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout2_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_reg_nbitsout2_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
+ signal \NLW_reg_nbitsout2_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[1]_i_2\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[1]_i_3\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[2]_i_3\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[2]_i_4\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[2]_i_5\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_rd[2]_i_6\ : label is "soft_lutpair6";
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_rd_reg[0]\ : label is "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_rd_reg[1]\ : label is "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_rd_reg[2]\ : label is "waitdata:001,waitgap:011,readbit:010,idle:000,waitbit:100";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_wr[1]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \FSM_sequential_fsm_wr[2]_i_1\ : label is "soft_lutpair12";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_wr_reg[0]\ : label is "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_wr_reg[1]\ : label is "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_wr_reg[2]\ : label is "sendbit:011,sendgap:100,senddata:001,sendendgap:010,idle:000";
+ attribute SOFT_HLUTNM of \counter[0]__0_i_1\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \counter[10]__0_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \counter[11]__0_i_3\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \counter[1]__0_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \counter[7]__0_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \counter[7]_i_14\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \counter[7]_i_4\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \counter[8]__0_i_1\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \counter[9]__0_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of reg_busy_i_1 : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \reg_dataout[0]_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \reg_dataout[63]_i_2\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of reg_datavalid_i_2 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of reg_datavalid_i_4 : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of reg_datavalid_i_8 : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of reg_datavalid_i_9 : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of reg_error_i_2 : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \reg_nbitsin[0]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \reg_nbitsin[1]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \reg_nbitsin[2]_i_1\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \reg_nbitsin[3]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \reg_nbitsin[5]_i_2\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \reg_nbitsout[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \reg_nbitsout[2]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \reg_nbitsout[3]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \reg_nbitsout[4]_i_1\ : label is "soft_lutpair11";
+begin
+ D(2 downto 0) <= \^d\(2 downto 0);
+ Q(11 downto 0) <= \^q\(11 downto 0);
+ cmd_in <= \^cmd_in\;
+ \reg_dataout_reg[63]_0\(63 downto 0) <= \^reg_dataout_reg[63]_0\(63 downto 0);
+ \reg_nbitsout_reg[5]_0\(5 downto 0) <= \^reg_nbitsout_reg[5]_0\(5 downto 0);
+CMD_IN_buf_inst_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \^cmd_in\,
+ I1 => CMD_IN_P(0),
+ O => I
+ );
+\FSM_sequential_fsm_rd[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000008195500"
+ )
+ port map (
+ I0 => \fsm_rd__0\(2),
+ I1 => reg_serialin,
+ I2 => reg_datavalid_i_3_n_0,
+ I3 => \FSM_sequential_fsm_rd[0]_i_2_n_0\,
+ I4 => \fsm_rd__0\(0),
+ I5 => \reg_nbitsout_reg[5]_3\,
+ O => \FSM_sequential_fsm_rd[0]_i_1_n_0\
+ );
+\FSM_sequential_fsm_rd[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FF000000FFFF0808"
+ )
+ port map (
+ I0 => \FSM_sequential_fsm_rd[2]_i_5_n_0\,
+ I1 => reg_datavalid_i_6_n_0,
+ I2 => reg_datavalid_i_7_n_0,
+ I3 => fsm_rd02_in,
+ I4 => \fsm_rd__0\(1),
+ I5 => \fsm_rd__0\(0),
+ O => \FSM_sequential_fsm_rd[0]_i_2_n_0\
+ );
+\FSM_sequential_fsm_rd[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000FBAA08AA"
+ )
+ port map (
+ I0 => \fsm_rd__0\(1),
+ I1 => \FSM_sequential_fsm_rd[1]_i_2_n_0\,
+ I2 => reg_datavalid_i_3_n_0,
+ I3 => \FSM_sequential_fsm_rd[2]_i_2_n_0\,
+ I4 => \FSM_sequential_fsm_rd[1]_i_3_n_0\,
+ I5 => \reg_nbitsout_reg[5]_3\,
+ O => \FSM_sequential_fsm_rd[1]_i_1_n_0\
+ );
+\FSM_sequential_fsm_rd[1]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => reg_serialin,
+ I1 => \fsm_rd__0\(2),
+ O => \FSM_sequential_fsm_rd[1]_i_2_n_0\
+ );
+\FSM_sequential_fsm_rd[1]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"013C"
+ )
+ port map (
+ I0 => reg_serialin,
+ I1 => \fsm_rd__0\(0),
+ I2 => \fsm_rd__0\(1),
+ I3 => \fsm_rd__0\(2),
+ O => \FSM_sequential_fsm_rd[1]_i_3_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000004CAA08AA"
+ )
+ port map (
+ I0 => \fsm_rd__0\(2),
+ I1 => reg_serialin,
+ I2 => reg_datavalid_i_3_n_0,
+ I3 => \FSM_sequential_fsm_rd[2]_i_2_n_0\,
+ I4 => \FSM_sequential_fsm_rd[2]_i_3_n_0\,
+ I5 => \reg_nbitsout_reg[5]_3\,
+ O => \FSM_sequential_fsm_rd[2]_i_1_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF45444444"
+ )
+ port map (
+ I0 => \FSM_sequential_fsm_rd[2]_i_4_n_0\,
+ I1 => \fsm_rd__0\(1),
+ I2 => reg_datavalid_i_7_n_0,
+ I3 => reg_datavalid_i_6_n_0,
+ I4 => \FSM_sequential_fsm_rd[2]_i_5_n_0\,
+ I5 => \FSM_sequential_fsm_rd[2]_i_6_n_0\,
+ O => \FSM_sequential_fsm_rd[2]_i_2_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \fsm_rd__0\(0),
+ I1 => \fsm_rd__0\(1),
+ O => \FSM_sequential_fsm_rd[2]_i_3_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"2A"
+ )
+ port map (
+ I0 => \fsm_rd__0\(0),
+ I1 => \fsm_rd__0\(1),
+ I2 => fsm_rd02_in,
+ O => \FSM_sequential_fsm_rd[2]_i_4_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_5\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000010"
+ )
+ port map (
+ I0 => p_0_in_0(9),
+ I1 => p_0_in_0(8),
+ I2 => p_0_in_0(4),
+ I3 => p_0_in_0(5),
+ I4 => reg_serialin,
+ O => \FSM_sequential_fsm_rd[2]_i_5_n_0\
+ );
+\FSM_sequential_fsm_rd[2]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"EA"
+ )
+ port map (
+ I0 => \fsm_rd__0\(2),
+ I1 => \fsm_rd__0\(0),
+ I2 => reg_serialin,
+ O => \FSM_sequential_fsm_rd[2]_i_6_n_0\
+ );
+\FSM_sequential_fsm_rd_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_rd[0]_i_1_n_0\,
+ Q => \fsm_rd__0\(0),
+ R => '0'
+ );
+\FSM_sequential_fsm_rd_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_rd[1]_i_1_n_0\,
+ Q => \fsm_rd__0\(1),
+ R => '0'
+ );
+\FSM_sequential_fsm_rd_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_rd[2]_i_1_n_0\,
+ Q => \fsm_rd__0\(2),
+ R => '0'
+ );
+\FSM_sequential_fsm_wr[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0FF005F500F00CFC"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => axi_control(1),
+ I2 => fsm_wr(2),
+ I3 => serialout_i_2_n_0,
+ I4 => fsm_wr(1),
+ I5 => fsm_wr(0),
+ O => \FSM_sequential_fsm_wr[0]_i_1_n_0\
+ );
+\FSM_sequential_fsm_wr[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0A0C"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => fsm_wr(0),
+ I2 => fsm_wr(2),
+ I3 => fsm_wr(1),
+ O => \FSM_sequential_fsm_wr[1]_i_1_n_0\
+ );
+\FSM_sequential_fsm_wr[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AA40"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => fsm_wr(0),
+ I2 => fsm_wr(1),
+ I3 => fsm_wr(2),
+ O => \FSM_sequential_fsm_wr[2]_i_1_n_0\
+ );
+\FSM_sequential_fsm_wr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_wr[0]_i_1_n_0\,
+ Q => fsm_wr(0),
+ R => axi_control(0)
+ );
+\FSM_sequential_fsm_wr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_wr[1]_i_1_n_0\,
+ Q => fsm_wr(1),
+ R => axi_control(0)
+ );
+\FSM_sequential_fsm_wr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \FSM_sequential_fsm_wr[2]_i_1_n_0\,
+ Q => fsm_wr(2),
+ R => axi_control(0)
+ );
+counter0_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => counter0_carry_n_0,
+ CO(2) => counter0_carry_n_1,
+ CO(1) => counter0_carry_n_2,
+ CO(0) => counter0_carry_n_3,
+ CYINIT => \counter_reg_n_0_[0]\,
+ DI(3) => \counter_reg_n_0_[4]\,
+ DI(2) => \counter_reg_n_0_[3]\,
+ DI(1) => \counter_reg_n_0_[2]\,
+ DI(0) => \counter_reg_n_0_[1]\,
+ O(3 downto 0) => data1(4 downto 1),
+ S(3) => counter0_carry_i_1_n_0,
+ S(2) => counter0_carry_i_2_n_0,
+ S(1) => counter0_carry_i_3_n_0,
+ S(0) => counter0_carry_i_4_n_0
+ );
+\counter0_carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => counter0_carry_n_0,
+ CO(3) => \counter0_carry__0_n_0\,
+ CO(2) => \counter0_carry__0_n_1\,
+ CO(1) => \counter0_carry__0_n_2\,
+ CO(0) => \counter0_carry__0_n_3\,
+ CYINIT => '0',
+ DI(3) => \counter_reg_n_0_[8]\,
+ DI(2) => \counter_reg_n_0_[7]\,
+ DI(1) => \counter_reg_n_0_[6]\,
+ DI(0) => \counter_reg_n_0_[5]\,
+ O(3 downto 0) => data1(8 downto 5),
+ S(3) => \counter0_carry__0_i_1_n_0\,
+ S(2) => \counter0_carry__0_i_2_n_0\,
+ S(1) => \counter0_carry__0_i_3_n_0\,
+ S(0) => \counter0_carry__0_i_4_n_0\
+ );
+\counter0_carry__0_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[8]\,
+ O => \counter0_carry__0_i_1_n_0\
+ );
+\counter0_carry__0_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[7]\,
+ O => \counter0_carry__0_i_2_n_0\
+ );
+\counter0_carry__0_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[6]\,
+ O => \counter0_carry__0_i_3_n_0\
+ );
+\counter0_carry__0_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[5]\,
+ O => \counter0_carry__0_i_4_n_0\
+ );
+\counter0_carry__1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \counter0_carry__0_n_0\,
+ CO(3 downto 2) => \NLW_counter0_carry__1_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => \counter0_carry__1_n_2\,
+ CO(0) => \counter0_carry__1_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1) => \counter_reg_n_0_[10]\,
+ DI(0) => \counter_reg_n_0_[9]\,
+ O(3) => \NLW_counter0_carry__1_O_UNCONNECTED\(3),
+ O(2 downto 0) => data1(11 downto 9),
+ S(3) => '0',
+ S(2) => \counter0_carry__1_i_1_n_0\,
+ S(1) => \counter0_carry__1_i_2_n_0\,
+ S(0) => \counter0_carry__1_i_3_n_0\
+ );
+\counter0_carry__1_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[11]\,
+ O => \counter0_carry__1_i_1_n_0\
+ );
+\counter0_carry__1_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[10]\,
+ O => \counter0_carry__1_i_2_n_0\
+ );
+\counter0_carry__1_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[9]\,
+ O => \counter0_carry__1_i_3_n_0\
+ );
+counter0_carry_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[4]\,
+ O => counter0_carry_i_1_n_0
+ );
+counter0_carry_i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[3]\,
+ O => counter0_carry_i_2_n_0
+ );
+counter0_carry_i_3: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[2]\,
+ O => counter0_carry_i_3_n_0
+ );
+counter0_carry_i_4: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[1]\,
+ O => counter0_carry_i_4_n_0
+ );
+\counter[0]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55150203"
+ )
+ port map (
+ I0 => \fsm_rd__0\(2),
+ I1 => \fsm_rd__0\(1),
+ I2 => \^q\(0),
+ I3 => reg_serialin,
+ I4 => \fsm_rd__0\(0),
+ O => \counter[0]__0_i_1_n_0\
+ );
+\counter[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"01010101FFFF01FF"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[0]\,
+ I1 => fsm_wr(1),
+ I2 => fsm_wr(0),
+ I3 => \counter[0]_i_2_n_0\,
+ I4 => \counter[0]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[0]_i_1_n_0\
+ );
+\counter[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"BBBBBFBB"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[0]\,
+ I1 => fsm_wr(1),
+ I2 => \counter_reg[11]_0\(0),
+ I3 => fsm_wr(0),
+ I4 => serialout_i_2_n_0,
+ O => \counter[0]_i_2_n_0\
+ );
+\counter[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000000E2"
+ )
+ port map (
+ I0 => \reg_nbitsout2_carry__0_0\(8),
+ I1 => \counter_reg[7]_i_3_n_0\,
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(8),
+ I3 => fsm_wr(1),
+ I4 => serialout_i_3_n_0,
+ O => \counter[0]_i_3_n_0\
+ );
+\counter[10]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(10),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[10]__0_i_1_n_0\
+ );
+\counter[10]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(10),
+ I1 => fsm_wr(0),
+ I2 => \counter[10]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[10]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[10]_i_1_n_0\
+ );
+\counter[10]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(10),
+ I2 => fsm_wr(0),
+ I3 => data1(10),
+ O => \counter[10]_i_2_n_0\
+ );
+\counter[10]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(18),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(18),
+ O => \counter[10]_i_3_n_0\
+ );
+\counter[11]__0_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"02FB"
+ )
+ port map (
+ I0 => reg_serialin,
+ I1 => \fsm_rd__0\(0),
+ I2 => \fsm_rd__0\(1),
+ I3 => \fsm_rd__0\(2),
+ O => \counter[11]__0_i_2_n_0\
+ );
+\counter[11]__0_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(11),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[11]__0_i_3_n_0\
+ );
+\counter[11]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"3360"
+ )
+ port map (
+ I0 => fsm_wr(1),
+ I1 => fsm_wr(2),
+ I2 => serialout_i_2_n_0,
+ I3 => fsm_wr(0),
+ O => counter
+ );
+\counter[11]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(11),
+ I1 => fsm_wr(0),
+ I2 => \counter[11]_i_3_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[11]_i_4_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[11]_i_2_n_0\
+ );
+\counter[11]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(11),
+ I2 => fsm_wr(0),
+ I3 => data1(11),
+ O => \counter[11]_i_3_n_0\
+ );
+\counter[11]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(19),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(19),
+ O => \counter[11]_i_4_n_0\
+ );
+\counter[1]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(1),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[1]__0_i_1_n_0\
+ );
+\counter[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFEEEFEAAAAAAAA"
+ )
+ port map (
+ I0 => \counter[1]_i_2_n_0\,
+ I1 => serialout_i_3_n_0,
+ I2 => \reg_nbitsout2_carry__0_0\(9),
+ I3 => \counter_reg[7]_i_3_n_0\,
+ I4 => \reg_nbitsout1_inferred__0/i__carry__0_1\(9),
+ I5 => \counter[7]_i_4_n_0\,
+ O => \counter[1]_i_1_n_0\
+ );
+\counter[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000AAACAA00AA"
+ )
+ port map (
+ I0 => data1(1),
+ I1 => \counter_reg[11]_0\(1),
+ I2 => serialout_i_2_n_0,
+ I3 => fsm_wr(0),
+ I4 => fsm_wr(1),
+ I5 => fsm_wr(2),
+ O => \counter[1]_i_2_n_0\
+ );
+\counter[2]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(2),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[2]__0_i_1_n_0\
+ );
+\counter[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFEEEFEAAAAAAAA"
+ )
+ port map (
+ I0 => \counter[2]_i_2_n_0\,
+ I1 => serialout_i_3_n_0,
+ I2 => \reg_nbitsout2_carry__0_0\(10),
+ I3 => \counter_reg[7]_i_3_n_0\,
+ I4 => \reg_nbitsout1_inferred__0/i__carry__0_1\(10),
+ I5 => \counter[7]_i_4_n_0\,
+ O => \counter[2]_i_1_n_0\
+ );
+\counter[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000AAACAA00AA"
+ )
+ port map (
+ I0 => data1(2),
+ I1 => \counter_reg[11]_0\(2),
+ I2 => serialout_i_2_n_0,
+ I3 => fsm_wr(0),
+ I4 => fsm_wr(1),
+ I5 => fsm_wr(2),
+ O => \counter[2]_i_2_n_0\
+ );
+\counter[3]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(3),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[3]__0_i_1_n_0\
+ );
+\counter[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(3),
+ I1 => fsm_wr(0),
+ I2 => \counter[3]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[3]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[3]_i_1_n_0\
+ );
+\counter[3]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(3),
+ I2 => fsm_wr(0),
+ I3 => data1(3),
+ O => \counter[3]_i_2_n_0\
+ );
+\counter[3]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(11),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(11),
+ O => \counter[3]_i_3_n_0\
+ );
+\counter[4]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(4),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[4]__0_i_1_n_0\
+ );
+\counter[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFEEEFEAAAAAAAA"
+ )
+ port map (
+ I0 => \counter[4]_i_2_n_0\,
+ I1 => serialout_i_3_n_0,
+ I2 => \reg_nbitsout2_carry__0_0\(12),
+ I3 => \counter_reg[7]_i_3_n_0\,
+ I4 => \reg_nbitsout1_inferred__0/i__carry__0_1\(12),
+ I5 => \counter[7]_i_4_n_0\,
+ O => \counter[4]_i_1_n_0\
+ );
+\counter[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000AAACAA00AA"
+ )
+ port map (
+ I0 => data1(4),
+ I1 => \counter_reg[11]_0\(4),
+ I2 => serialout_i_2_n_0,
+ I3 => fsm_wr(0),
+ I4 => fsm_wr(1),
+ I5 => fsm_wr(2),
+ O => \counter[4]_i_2_n_0\
+ );
+\counter[5]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(5),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[5]__0_i_1_n_0\
+ );
+\counter[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(5),
+ I1 => fsm_wr(0),
+ I2 => \counter[5]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[5]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[5]_i_1_n_0\
+ );
+\counter[5]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(5),
+ I2 => fsm_wr(0),
+ I3 => data1(5),
+ O => \counter[5]_i_2_n_0\
+ );
+\counter[5]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(13),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(13),
+ O => \counter[5]_i_3_n_0\
+ );
+\counter[6]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(6),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[6]__0_i_1_n_0\
+ );
+\counter[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(6),
+ I1 => fsm_wr(0),
+ I2 => \counter[6]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[6]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[6]_i_1_n_0\
+ );
+\counter[6]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(6),
+ I2 => fsm_wr(0),
+ I3 => data1(6),
+ O => \counter[6]_i_2_n_0\
+ );
+\counter[6]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(14),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(14),
+ O => \counter[6]_i_3_n_0\
+ );
+\counter[7]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(7),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[7]__0_i_1_n_0\
+ );
+\counter[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFEEEFEAAAAAAAA"
+ )
+ port map (
+ I0 => \counter[7]_i_2_n_0\,
+ I1 => serialout_i_3_n_0,
+ I2 => \reg_nbitsout2_carry__0_0\(15),
+ I3 => \counter_reg[7]_i_3_n_0\,
+ I4 => \reg_nbitsout1_inferred__0/i__carry__0_1\(15),
+ I5 => \counter[7]_i_4_n_0\,
+ O => \counter[7]_i_1_n_0\
+ );
+\counter[7]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFAFCFC0A0A0CFC0"
+ )
+ port map (
+ I0 => \counter[7]_i_24_n_0\,
+ I1 => \counter[7]_i_25_n_0\,
+ I2 => \reg_nbitsin[3]_i_2_n_0\,
+ I3 => \counter[7]_i_26_n_0\,
+ I4 => \counter[7]_i_14_n_0\,
+ I5 => \counter[7]_i_27_n_0\,
+ O => \counter[7]_i_10_n_0\
+ );
+\counter[7]_i_11\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[12]\,
+ I1 => \reg_datain_reg_n_0_[13]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[14]\,
+ I5 => \reg_datain_reg_n_0_[15]\,
+ O => \counter[7]_i_11_n_0\
+ );
+\counter[7]_i_12\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[8]\,
+ I1 => \reg_datain_reg_n_0_[9]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[10]\,
+ I5 => \reg_datain_reg_n_0_[11]\,
+ O => \counter[7]_i_12_n_0\
+ );
+\counter[7]_i_13\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[4]\,
+ I1 => \reg_datain_reg_n_0_[5]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[6]\,
+ I5 => \reg_datain_reg_n_0_[7]\,
+ O => \counter[7]_i_13_n_0\
+ );
+\counter[7]_i_14\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A9"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[2]\,
+ I1 => \reg_nbitsin_reg_n_0_[0]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ O => \counter[7]_i_14_n_0\
+ );
+\counter[7]_i_15\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[0]\,
+ I1 => \reg_datain_reg_n_0_[1]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[2]\,
+ I5 => \reg_datain_reg_n_0_[3]\,
+ O => \counter[7]_i_15_n_0\
+ );
+\counter[7]_i_16\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[28]\,
+ I1 => \reg_datain_reg_n_0_[29]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[30]\,
+ I5 => \reg_datain_reg_n_0_[31]\,
+ O => \counter[7]_i_16_n_0\
+ );
+\counter[7]_i_17\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[24]\,
+ I1 => \reg_datain_reg_n_0_[25]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[26]\,
+ I5 => \reg_datain_reg_n_0_[27]\,
+ O => \counter[7]_i_17_n_0\
+ );
+\counter[7]_i_18\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[20]\,
+ I1 => \reg_datain_reg_n_0_[21]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[22]\,
+ I5 => \reg_datain_reg_n_0_[23]\,
+ O => \counter[7]_i_18_n_0\
+ );
+\counter[7]_i_19\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[16]\,
+ I1 => \reg_datain_reg_n_0_[17]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[18]\,
+ I5 => \reg_datain_reg_n_0_[19]\,
+ O => \counter[7]_i_19_n_0\
+ );
+\counter[7]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000AAACAA00AA"
+ )
+ port map (
+ I0 => data1(7),
+ I1 => \counter_reg[11]_0\(7),
+ I2 => serialout_i_2_n_0,
+ I3 => fsm_wr(0),
+ I4 => fsm_wr(1),
+ I5 => fsm_wr(2),
+ O => \counter[7]_i_2_n_0\
+ );
+\counter[7]_i_20\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[40]\,
+ I1 => \reg_datain_reg_n_0_[41]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[42]\,
+ I5 => \reg_datain_reg_n_0_[43]\,
+ O => \counter[7]_i_20_n_0\
+ );
+\counter[7]_i_21\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[44]\,
+ I1 => \reg_datain_reg_n_0_[45]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[46]\,
+ I5 => \reg_datain_reg_n_0_[47]\,
+ O => \counter[7]_i_21_n_0\
+ );
+\counter[7]_i_22\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[36]\,
+ I1 => \reg_datain_reg_n_0_[37]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[38]\,
+ I5 => \reg_datain_reg_n_0_[39]\,
+ O => \counter[7]_i_22_n_0\
+ );
+\counter[7]_i_23\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[32]\,
+ I1 => \reg_datain_reg_n_0_[33]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[34]\,
+ I5 => \reg_datain_reg_n_0_[35]\,
+ O => \counter[7]_i_23_n_0\
+ );
+\counter[7]_i_24\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[60]\,
+ I1 => \reg_datain_reg_n_0_[61]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[62]\,
+ I5 => \reg_datain_reg_n_0_[63]\,
+ O => \counter[7]_i_24_n_0\
+ );
+\counter[7]_i_25\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[56]\,
+ I1 => \reg_datain_reg_n_0_[57]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[58]\,
+ I5 => \reg_datain_reg_n_0_[59]\,
+ O => \counter[7]_i_25_n_0\
+ );
+\counter[7]_i_26\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[48]\,
+ I1 => \reg_datain_reg_n_0_[49]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[50]\,
+ I5 => \reg_datain_reg_n_0_[51]\,
+ O => \counter[7]_i_26_n_0\
+ );
+\counter[7]_i_27\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FACF0ACFFAC00AC0"
+ )
+ port map (
+ I0 => \reg_datain_reg_n_0_[52]\,
+ I1 => \reg_datain_reg_n_0_[53]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_datain_reg_n_0_[54]\,
+ I5 => \reg_datain_reg_n_0_[55]\,
+ O => \counter[7]_i_27_n_0\
+ );
+\counter[7]_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => fsm_wr(2),
+ I1 => fsm_wr(1),
+ O => \counter[7]_i_4_n_0\
+ );
+\counter[7]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \counter[7]_i_11_n_0\,
+ I1 => \counter[7]_i_12_n_0\,
+ I2 => \reg_nbitsin[3]_i_2_n_0\,
+ I3 => \counter[7]_i_13_n_0\,
+ I4 => \counter[7]_i_14_n_0\,
+ I5 => \counter[7]_i_15_n_0\,
+ O => \counter[7]_i_7_n_0\
+ );
+\counter[7]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \counter[7]_i_16_n_0\,
+ I1 => \counter[7]_i_17_n_0\,
+ I2 => \reg_nbitsin[3]_i_2_n_0\,
+ I3 => \counter[7]_i_18_n_0\,
+ I4 => \counter[7]_i_14_n_0\,
+ I5 => \counter[7]_i_19_n_0\,
+ O => \counter[7]_i_8_n_0\
+ );
+\counter[7]_i_9\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"CFC0AFAFCFC0A0A0"
+ )
+ port map (
+ I0 => \counter[7]_i_20_n_0\,
+ I1 => \counter[7]_i_21_n_0\,
+ I2 => \reg_nbitsin[3]_i_2_n_0\,
+ I3 => \counter[7]_i_22_n_0\,
+ I4 => \counter[7]_i_14_n_0\,
+ I5 => \counter[7]_i_23_n_0\,
+ O => \counter[7]_i_9_n_0\
+ );
+\counter[8]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(8),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[8]__0_i_1_n_0\
+ );
+\counter[8]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(8),
+ I1 => fsm_wr(0),
+ I2 => \counter[8]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[8]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[8]_i_1_n_0\
+ );
+\counter[8]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(8),
+ I2 => fsm_wr(0),
+ I3 => data1(8),
+ O => \counter[8]_i_2_n_0\
+ );
+\counter[8]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(16),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(16),
+ O => \counter[8]_i_3_n_0\
+ );
+\counter[9]__0_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000A2002"
+ )
+ port map (
+ I0 => p_0_in_0(9),
+ I1 => reg_serialin,
+ I2 => \fsm_rd__0\(0),
+ I3 => \fsm_rd__0\(1),
+ I4 => \fsm_rd__0\(2),
+ O => \counter[9]__0_i_1_n_0\
+ );
+\counter[9]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"002200220F220FFF"
+ )
+ port map (
+ I0 => data1(9),
+ I1 => fsm_wr(0),
+ I2 => \counter[9]_i_2_n_0\,
+ I3 => fsm_wr(1),
+ I4 => \counter[9]_i_3_n_0\,
+ I5 => fsm_wr(2),
+ O => \counter[9]_i_1_n_0\
+ );
+\counter[9]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"10BF"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => \counter_reg[11]_0\(9),
+ I2 => fsm_wr(0),
+ I3 => data1(9),
+ O => \counter[9]_i_2_n_0\
+ );
+\counter[9]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"ABFB"
+ )
+ port map (
+ I0 => serialout_i_3_n_0,
+ I1 => \reg_nbitsout2_carry__0_0\(17),
+ I2 => \counter_reg[7]_i_3_n_0\,
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(17),
+ O => \counter[9]_i_3_n_0\
+ );
+\counter_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[0]_i_1_n_0\,
+ Q => \counter_reg_n_0_[0]\,
+ R => axi_control(0)
+ );
+\counter_reg[0]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[0]__0_i_1_n_0\,
+ Q => \^q\(0),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[10]_i_1_n_0\,
+ Q => \counter_reg_n_0_[10]\,
+ R => axi_control(0)
+ );
+\counter_reg[10]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[10]__0_i_1_n_0\,
+ Q => \^q\(10),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[11]_i_2_n_0\,
+ Q => \counter_reg_n_0_[11]\,
+ R => axi_control(0)
+ );
+\counter_reg[11]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[11]__0_i_3_n_0\,
+ Q => \^q\(11),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[11]__0_i_4\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \i__carry_i_2__2_n_0\,
+ CO(3 downto 2) => \NLW_counter_reg[11]__0_i_4_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => \counter_reg[11]__0_i_4_n_2\,
+ CO(0) => \counter_reg[11]__0_i_4_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3) => \NLW_counter_reg[11]__0_i_4_O_UNCONNECTED\(3),
+ O(2 downto 0) => p_0_in_0(11 downto 9),
+ S(3) => '0',
+ S(2 downto 0) => \^q\(11 downto 9)
+ );
+\counter_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[1]_i_1_n_0\,
+ Q => \counter_reg_n_0_[1]\,
+ R => axi_control(0)
+ );
+\counter_reg[1]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[1]__0_i_1_n_0\,
+ Q => \^q\(1),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[2]_i_1_n_0\,
+ Q => \counter_reg_n_0_[2]\,
+ R => axi_control(0)
+ );
+\counter_reg[2]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[2]__0_i_1_n_0\,
+ Q => \^q\(2),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[3]_i_1_n_0\,
+ Q => \counter_reg_n_0_[3]\,
+ R => axi_control(0)
+ );
+\counter_reg[3]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[3]__0_i_1_n_0\,
+ Q => \^q\(3),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[4]_i_1_n_0\,
+ Q => \counter_reg_n_0_[4]\,
+ R => axi_control(0)
+ );
+\counter_reg[4]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[4]__0_i_1_n_0\,
+ Q => \^q\(4),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[5]_i_1_n_0\,
+ Q => \counter_reg_n_0_[5]\,
+ R => axi_control(0)
+ );
+\counter_reg[5]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[5]__0_i_1_n_0\,
+ Q => \^q\(5),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[6]_i_1_n_0\,
+ Q => \counter_reg_n_0_[6]\,
+ R => axi_control(0)
+ );
+\counter_reg[6]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[6]__0_i_1_n_0\,
+ Q => \^q\(6),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[7]_i_1_n_0\,
+ Q => \counter_reg_n_0_[7]\,
+ R => axi_control(0)
+ );
+\counter_reg[7]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[7]__0_i_1_n_0\,
+ Q => \^q\(7),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[7]_i_3\: unisim.vcomponents.MUXF8
+ port map (
+ I0 => \counter_reg[7]_i_5_n_0\,
+ I1 => \counter_reg[7]_i_6_n_0\,
+ O => \counter_reg[7]_i_3_n_0\,
+ S => \reg_nbitsin[5]_i_3_n_0\
+ );
+\counter_reg[7]_i_5\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \counter[7]_i_7_n_0\,
+ I1 => \counter[7]_i_8_n_0\,
+ O => \counter_reg[7]_i_5_n_0\,
+ S => \reg_nbitsin[4]_i_2_n_0\
+ );
+\counter_reg[7]_i_6\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \counter[7]_i_9_n_0\,
+ I1 => \counter[7]_i_10_n_0\,
+ O => \counter_reg[7]_i_6_n_0\,
+ S => \reg_nbitsin[4]_i_2_n_0\
+ );
+\counter_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[8]_i_1_n_0\,
+ Q => \counter_reg_n_0_[8]\,
+ R => axi_control(0)
+ );
+\counter_reg[8]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[8]__0_i_1_n_0\,
+ Q => \^q\(8),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\counter_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => counter,
+ D => \counter[9]_i_1_n_0\,
+ Q => \counter_reg_n_0_[9]\,
+ R => axi_control(0)
+ );
+\counter_reg[9]__0\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => \counter[11]__0_i_2_n_0\,
+ D => \counter[9]__0_i_1_n_0\,
+ Q => \^q\(9),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\fsm_rd0_inferred__1/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \fsm_rd0_inferred__1/i__carry_n_0\,
+ CO(2) => \fsm_rd0_inferred__1/i__carry_n_1\,
+ CO(1) => \fsm_rd0_inferred__1/i__carry_n_2\,
+ CO(0) => \fsm_rd0_inferred__1/i__carry_n_3\,
+ CYINIT => '0',
+ DI(3) => \i__carry_i_1_n_0\,
+ DI(2) => p_0_in_0(5),
+ DI(1) => p_0_in_0(3),
+ DI(0) => \i__carry_i_4_n_0\,
+ O(3 downto 0) => \NLW_fsm_rd0_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3) => \i__carry_i_5_n_0\,
+ S(2) => \i__carry_i_6_n_0\,
+ S(1) => \i__carry_i_7_n_0\,
+ S(0) => \i__carry_i_8_n_0\
+ );
+\fsm_rd0_inferred__1/i__carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \fsm_rd0_inferred__1/i__carry_n_0\,
+ CO(3 downto 2) => \NLW_fsm_rd0_inferred__1/i__carry__0_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => fsm_rd02_in,
+ CO(0) => \fsm_rd0_inferred__1/i__carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1) => \i__carry__0_i_1_n_0\,
+ DI(0) => \i__carry__0_i_2_n_0\,
+ O(3 downto 0) => \NLW_fsm_rd0_inferred__1/i__carry__0_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 2) => B"00",
+ S(1) => \i__carry__0_i_3_n_0\,
+ S(0) => \i__carry__0_i_4_n_0\
+ );
+\i__carry__0_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => p_0_in_0(11),
+ I1 => p_0_in_0(10),
+ O => \i__carry__0_i_1_n_0\
+ );
+\i__carry__0_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(11),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(31),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(30),
+ I3 => \^q\(10),
+ O => \i__carry__0_i_1__0_n_0\
+ );
+\i__carry__0_i_1__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^q\(11),
+ I1 => \^q\(10),
+ O => \i__carry__0_i_1__1_n_0\
+ );
+\i__carry__0_i_1__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^q\(11),
+ I1 => \^q\(10),
+ O => \i__carry__0_i_1__2_n_0\
+ );
+\i__carry__0_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => p_0_in_0(9),
+ I1 => p_0_in_0(8),
+ O => \i__carry__0_i_2_n_0\
+ );
+\i__carry__0_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(9),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(29),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(28),
+ I3 => \^q\(8),
+ O => \i__carry__0_i_2__0_n_0\
+ );
+\i__carry__0_i_2__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^q\(9),
+ I1 => \^q\(8),
+ O => \i__carry__0_i_2__1_n_0\
+ );
+\i__carry__0_i_2__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \^q\(9),
+ I1 => \^q\(8),
+ O => \i__carry__0_i_2__2_n_0\
+ );
+\i__carry__0_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => p_0_in_0(10),
+ I1 => p_0_in_0(11),
+ O => \i__carry__0_i_3_n_0\
+ );
+\i__carry__0_i_3__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(10),
+ I1 => \^q\(11),
+ O => \i__carry__0_i_3__1_n_0\
+ );
+\i__carry__0_i_3__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(10),
+ I1 => \^q\(11),
+ O => \i__carry__0_i_3__2_n_0\
+ );
+\i__carry__0_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => p_0_in_0(8),
+ I1 => p_0_in_0(9),
+ O => \i__carry__0_i_4_n_0\
+ );
+\i__carry__0_i_4__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(8),
+ I1 => \^q\(9),
+ O => \i__carry__0_i_4__1_n_0\
+ );
+\i__carry__0_i_4__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^q\(8),
+ I1 => \^q\(9),
+ O => \i__carry__0_i_4__2_n_0\
+ );
+\i__carry_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => p_0_in_0(7),
+ I1 => p_0_in_0(6),
+ O => \i__carry_i_1_n_0\
+ );
+\i__carry_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \reg_nbitsout2_carry__0_0\(7),
+ I2 => \^q\(6),
+ I3 => \reg_nbitsout2_carry__0_0\(6),
+ O => \i__carry_i_1__0_n_0\
+ );
+\i__carry_i_1__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(27),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(26),
+ I3 => \^q\(6),
+ O => \i__carry_i_1__1_n_0\
+ );
+\i__carry_i_1__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(7),
+ I2 => \^q\(6),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(6),
+ O => \i__carry_i_1__2_n_0\
+ );
+\i__carry_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \reg_nbitsout2_carry__0_0\(5),
+ I2 => \^q\(4),
+ I3 => \reg_nbitsout2_carry__0_0\(4),
+ O => \i__carry_i_2_n_0\
+ );
+\i__carry_i_2__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(25),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(24),
+ I3 => \^q\(4),
+ O => \i__carry_i_2__0_n_0\
+ );
+\i__carry_i_2__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(5),
+ I2 => \^q\(4),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(4),
+ O => \i__carry_i_2__1_n_0\
+ );
+\i__carry_i_2__2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \i__carry_i_3__2_n_0\,
+ CO(3) => \i__carry_i_2__2_n_0\,
+ CO(2) => \i__carry_i_2__2_n_1\,
+ CO(1) => \i__carry_i_2__2_n_2\,
+ CO(0) => \i__carry_i_2__2_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => p_0_in_0(8 downto 5),
+ S(3 downto 0) => \^q\(8 downto 5)
+ );
+\i__carry_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \reg_nbitsout2_carry__0_0\(3),
+ I2 => \^q\(2),
+ I3 => \reg_nbitsout2_carry__0_0\(2),
+ O => \i__carry_i_3_n_0\
+ );
+\i__carry_i_3__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(23),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(22),
+ I3 => \^q\(2),
+ O => \i__carry_i_3__0_n_0\
+ );
+\i__carry_i_3__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(3),
+ I2 => \^q\(2),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(2),
+ O => \i__carry_i_3__1_n_0\
+ );
+\i__carry_i_3__2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \i__carry_i_3__2_n_0\,
+ CO(2) => \i__carry_i_3__2_n_1\,
+ CO(1) => \i__carry_i_3__2_n_2\,
+ CO(0) => \i__carry_i_3__2_n_3\,
+ CYINIT => \^q\(0),
+ DI(3 downto 0) => B"0000",
+ O(3 downto 0) => p_0_in_0(4 downto 1),
+ S(3 downto 0) => \^q\(4 downto 1)
+ );
+\i__carry_i_4\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_0_in_0(1),
+ I1 => \^q\(0),
+ O => \i__carry_i_4_n_0\
+ );
+\i__carry_i_4__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \reg_nbitsout2_carry__0_0\(1),
+ I2 => \^q\(0),
+ I3 => \reg_nbitsout2_carry__0_0\(0),
+ O => \i__carry_i_4__0_n_0\
+ );
+\i__carry_i_4__1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"44D4"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(21),
+ I2 => \reg_nbitsout1_inferred__0/i__carry__0_1\(20),
+ I3 => \^q\(0),
+ O => \i__carry_i_4__1_n_0\
+ );
+\i__carry_i_4__2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"22B2"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \reg_nbitsout1_inferred__0/i__carry__0_1\(1),
+ I2 => \^q\(0),
+ I3 => \reg_nbitsout1_inferred__0/i__carry__0_1\(0),
+ O => \i__carry_i_4__2_n_0\
+ );
+\i__carry_i_5\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_0_in_0(7),
+ I1 => p_0_in_0(6),
+ O => \i__carry_i_5_n_0\
+ );
+\i__carry_i_6\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_0_in_0(4),
+ I1 => p_0_in_0(5),
+ O => \i__carry_i_6_n_0\
+ );
+\i__carry_i_7\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => p_0_in_0(2),
+ I1 => p_0_in_0(3),
+ O => \i__carry_i_7_n_0\
+ );
+\i__carry_i_8\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => p_0_in_0(1),
+ I1 => \^q\(0),
+ O => \i__carry_i_8_n_0\
+ );
+reg_busy_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"BBBFBBBC"
+ )
+ port map (
+ I0 => \^d\(0),
+ I1 => fsm_wr(2),
+ I2 => fsm_wr(0),
+ I3 => fsm_wr(1),
+ I4 => axi_control(1),
+ O => reg_busy_i_1_n_0
+ );
+reg_busy_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => reg_busy_i_1_n_0,
+ Q => \^d\(0),
+ R => axi_control(0)
+ );
+\reg_datain[63]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0002"
+ )
+ port map (
+ I0 => axi_control(1),
+ I1 => fsm_wr(1),
+ I2 => fsm_wr(0),
+ I3 => fsm_wr(2),
+ O => reg_datain
+ );
+\reg_datain_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(0),
+ Q => \reg_datain_reg_n_0_[0]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(10),
+ Q => \reg_datain_reg_n_0_[10]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(11),
+ Q => \reg_datain_reg_n_0_[11]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[12]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(12),
+ Q => \reg_datain_reg_n_0_[12]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[13]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(13),
+ Q => \reg_datain_reg_n_0_[13]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[14]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(14),
+ Q => \reg_datain_reg_n_0_[14]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[15]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(15),
+ Q => \reg_datain_reg_n_0_[15]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[16]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(16),
+ Q => \reg_datain_reg_n_0_[16]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[17]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(17),
+ Q => \reg_datain_reg_n_0_[17]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[18]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(18),
+ Q => \reg_datain_reg_n_0_[18]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[19]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(19),
+ Q => \reg_datain_reg_n_0_[19]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(1),
+ Q => \reg_datain_reg_n_0_[1]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[20]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(20),
+ Q => \reg_datain_reg_n_0_[20]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[21]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(21),
+ Q => \reg_datain_reg_n_0_[21]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[22]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(22),
+ Q => \reg_datain_reg_n_0_[22]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[23]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(23),
+ Q => \reg_datain_reg_n_0_[23]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[24]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(24),
+ Q => \reg_datain_reg_n_0_[24]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[25]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(25),
+ Q => \reg_datain_reg_n_0_[25]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[26]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(26),
+ Q => \reg_datain_reg_n_0_[26]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[27]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(27),
+ Q => \reg_datain_reg_n_0_[27]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[28]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(28),
+ Q => \reg_datain_reg_n_0_[28]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[29]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(29),
+ Q => \reg_datain_reg_n_0_[29]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(2),
+ Q => \reg_datain_reg_n_0_[2]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[30]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(30),
+ Q => \reg_datain_reg_n_0_[30]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[31]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(31),
+ Q => \reg_datain_reg_n_0_[31]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[32]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(32),
+ Q => \reg_datain_reg_n_0_[32]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[33]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(33),
+ Q => \reg_datain_reg_n_0_[33]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[34]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(34),
+ Q => \reg_datain_reg_n_0_[34]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[35]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(35),
+ Q => \reg_datain_reg_n_0_[35]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[36]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(36),
+ Q => \reg_datain_reg_n_0_[36]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[37]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(37),
+ Q => \reg_datain_reg_n_0_[37]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[38]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(38),
+ Q => \reg_datain_reg_n_0_[38]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[39]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(39),
+ Q => \reg_datain_reg_n_0_[39]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(3),
+ Q => \reg_datain_reg_n_0_[3]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[40]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(40),
+ Q => \reg_datain_reg_n_0_[40]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[41]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(41),
+ Q => \reg_datain_reg_n_0_[41]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[42]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(42),
+ Q => \reg_datain_reg_n_0_[42]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[43]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(43),
+ Q => \reg_datain_reg_n_0_[43]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[44]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(44),
+ Q => \reg_datain_reg_n_0_[44]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[45]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(45),
+ Q => \reg_datain_reg_n_0_[45]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[46]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(46),
+ Q => \reg_datain_reg_n_0_[46]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[47]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(47),
+ Q => \reg_datain_reg_n_0_[47]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[48]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(48),
+ Q => \reg_datain_reg_n_0_[48]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[49]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(49),
+ Q => \reg_datain_reg_n_0_[49]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(4),
+ Q => \reg_datain_reg_n_0_[4]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[50]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(50),
+ Q => \reg_datain_reg_n_0_[50]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[51]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(51),
+ Q => \reg_datain_reg_n_0_[51]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[52]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(52),
+ Q => \reg_datain_reg_n_0_[52]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[53]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(53),
+ Q => \reg_datain_reg_n_0_[53]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[54]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(54),
+ Q => \reg_datain_reg_n_0_[54]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[55]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(55),
+ Q => \reg_datain_reg_n_0_[55]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[56]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(56),
+ Q => \reg_datain_reg_n_0_[56]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[57]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(57),
+ Q => \reg_datain_reg_n_0_[57]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[58]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(58),
+ Q => \reg_datain_reg_n_0_[58]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[59]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(59),
+ Q => \reg_datain_reg_n_0_[59]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(5),
+ Q => \reg_datain_reg_n_0_[5]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[60]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(60),
+ Q => \reg_datain_reg_n_0_[60]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[61]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(61),
+ Q => \reg_datain_reg_n_0_[61]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[62]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(62),
+ Q => \reg_datain_reg_n_0_[62]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[63]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(63),
+ Q => \reg_datain_reg_n_0_[63]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(6),
+ Q => \reg_datain_reg_n_0_[6]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(7),
+ Q => \reg_datain_reg_n_0_[7]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(8),
+ Q => \reg_datain_reg_n_0_[8]\,
+ R => axi_control(0)
+ );
+\reg_datain_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_datain,
+ D => \reg_datain_reg[63]_0\(9),
+ Q => \reg_datain_reg_n_0_[9]\,
+ R => axi_control(0)
+ );
+\reg_dataout[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => reg_nbitsout26_in,
+ I1 => reg_nbitsout2,
+ O => p_1_in(0)
+ );
+\reg_dataout[63]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8888800080008000"
+ )
+ port map (
+ I0 => \reg_dataout[63]_i_2_n_0\,
+ I1 => \fsm_rd__0\(1),
+ I2 => reg_nbitsout2,
+ I3 => reg_nbitsout26_in,
+ I4 => reg_nbitsout1,
+ I5 => reg_nbitsout15_in,
+ O => reg_nbitsout
+ );
+\reg_dataout[63]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \fsm_rd__0\(0),
+ I1 => \fsm_rd__0\(2),
+ O => \reg_dataout[63]_i_2_n_0\
+ );
+\reg_dataout_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_1_in(0),
+ Q => \^reg_dataout_reg[63]_0\(0),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(9),
+ Q => \^reg_dataout_reg[63]_0\(10),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(10),
+ Q => \^reg_dataout_reg[63]_0\(11),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[12]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(11),
+ Q => \^reg_dataout_reg[63]_0\(12),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[13]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(12),
+ Q => \^reg_dataout_reg[63]_0\(13),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[14]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(13),
+ Q => \^reg_dataout_reg[63]_0\(14),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[15]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(14),
+ Q => \^reg_dataout_reg[63]_0\(15),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[16]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(15),
+ Q => \^reg_dataout_reg[63]_0\(16),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[17]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(16),
+ Q => \^reg_dataout_reg[63]_0\(17),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[18]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(17),
+ Q => \^reg_dataout_reg[63]_0\(18),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[19]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(18),
+ Q => \^reg_dataout_reg[63]_0\(19),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(0),
+ Q => \^reg_dataout_reg[63]_0\(1),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[20]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(19),
+ Q => \^reg_dataout_reg[63]_0\(20),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[21]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(20),
+ Q => \^reg_dataout_reg[63]_0\(21),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[22]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(21),
+ Q => \^reg_dataout_reg[63]_0\(22),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[23]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(22),
+ Q => \^reg_dataout_reg[63]_0\(23),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[24]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(23),
+ Q => \^reg_dataout_reg[63]_0\(24),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[25]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(24),
+ Q => \^reg_dataout_reg[63]_0\(25),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[26]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(25),
+ Q => \^reg_dataout_reg[63]_0\(26),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[27]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(26),
+ Q => \^reg_dataout_reg[63]_0\(27),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[28]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(27),
+ Q => \^reg_dataout_reg[63]_0\(28),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[29]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(28),
+ Q => \^reg_dataout_reg[63]_0\(29),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(1),
+ Q => \^reg_dataout_reg[63]_0\(2),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[30]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(29),
+ Q => \^reg_dataout_reg[63]_0\(30),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[31]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(30),
+ Q => \^reg_dataout_reg[63]_0\(31),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[32]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(31),
+ Q => \^reg_dataout_reg[63]_0\(32),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[33]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(32),
+ Q => \^reg_dataout_reg[63]_0\(33),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[34]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(33),
+ Q => \^reg_dataout_reg[63]_0\(34),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[35]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(34),
+ Q => \^reg_dataout_reg[63]_0\(35),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[36]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(35),
+ Q => \^reg_dataout_reg[63]_0\(36),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[37]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(36),
+ Q => \^reg_dataout_reg[63]_0\(37),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[38]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(37),
+ Q => \^reg_dataout_reg[63]_0\(38),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[39]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(38),
+ Q => \^reg_dataout_reg[63]_0\(39),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(2),
+ Q => \^reg_dataout_reg[63]_0\(3),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[40]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(39),
+ Q => \^reg_dataout_reg[63]_0\(40),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[41]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(40),
+ Q => \^reg_dataout_reg[63]_0\(41),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[42]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(41),
+ Q => \^reg_dataout_reg[63]_0\(42),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[43]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(42),
+ Q => \^reg_dataout_reg[63]_0\(43),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[44]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(43),
+ Q => \^reg_dataout_reg[63]_0\(44),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[45]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(44),
+ Q => \^reg_dataout_reg[63]_0\(45),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[46]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(45),
+ Q => \^reg_dataout_reg[63]_0\(46),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[47]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(46),
+ Q => \^reg_dataout_reg[63]_0\(47),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[48]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(47),
+ Q => \^reg_dataout_reg[63]_0\(48),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[49]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(48),
+ Q => \^reg_dataout_reg[63]_0\(49),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(3),
+ Q => \^reg_dataout_reg[63]_0\(4),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[50]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(49),
+ Q => \^reg_dataout_reg[63]_0\(50),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[51]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(50),
+ Q => \^reg_dataout_reg[63]_0\(51),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[52]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(51),
+ Q => \^reg_dataout_reg[63]_0\(52),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[53]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(52),
+ Q => \^reg_dataout_reg[63]_0\(53),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[54]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(53),
+ Q => \^reg_dataout_reg[63]_0\(54),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[55]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(54),
+ Q => \^reg_dataout_reg[63]_0\(55),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[56]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(55),
+ Q => \^reg_dataout_reg[63]_0\(56),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[57]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(56),
+ Q => \^reg_dataout_reg[63]_0\(57),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[58]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(57),
+ Q => \^reg_dataout_reg[63]_0\(58),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[59]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(58),
+ Q => \^reg_dataout_reg[63]_0\(59),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(4),
+ Q => \^reg_dataout_reg[63]_0\(5),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[60]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(59),
+ Q => \^reg_dataout_reg[63]_0\(60),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[61]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(60),
+ Q => \^reg_dataout_reg[63]_0\(61),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[62]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(61),
+ Q => \^reg_dataout_reg[63]_0\(62),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[63]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(62),
+ Q => \^reg_dataout_reg[63]_0\(63),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(5),
+ Q => \^reg_dataout_reg[63]_0\(6),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(6),
+ Q => \^reg_dataout_reg[63]_0\(7),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(7),
+ Q => \^reg_dataout_reg[63]_0\(8),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_dataout_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => \^reg_dataout_reg[63]_0\(8),
+ Q => \^reg_dataout_reg[63]_0\(9),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+reg_datavalid_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000EEFE2202"
+ )
+ port map (
+ I0 => \^d\(1),
+ I1 => reg_datavalid_i_2_n_0,
+ I2 => reg_datavalid_i_3_n_0,
+ I3 => reg_datavalid_i_4_n_0,
+ I4 => reg_datavalid,
+ I5 => \reg_nbitsout_reg[5]_3\,
+ O => reg_datavalid_i_1_n_0
+ );
+reg_datavalid_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000080"
+ )
+ port map (
+ I0 => \fsm_rd__0\(1),
+ I1 => \fsm_rd__0\(0),
+ I2 => fsm_rd02_in,
+ I3 => \fsm_rd__0\(2),
+ I4 => reg_serialin,
+ O => reg_datavalid_i_2_n_0
+ );
+reg_datavalid_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000200"
+ )
+ port map (
+ I0 => reg_datavalid_i_6_n_0,
+ I1 => p_0_in_0(5),
+ I2 => p_0_in_0(9),
+ I3 => p_0_in_0(8),
+ I4 => p_0_in_0(4),
+ I5 => reg_datavalid_i_7_n_0,
+ O => reg_datavalid_i_3_n_0
+ );
+reg_datavalid_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EFFF"
+ )
+ port map (
+ I0 => \fsm_rd__0\(0),
+ I1 => \fsm_rd__0\(1),
+ I2 => \fsm_rd__0\(2),
+ I3 => reg_serialin,
+ O => reg_datavalid_i_4_n_0
+ );
+reg_datavalid_i_5: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"444444F444444444"
+ )
+ port map (
+ I0 => \fsm_rd__0\(2),
+ I1 => fsm_rd02_in,
+ I2 => reg_datavalid_i_6_n_0,
+ I3 => reg_datavalid_i_8_n_0,
+ I4 => reg_datavalid_i_7_n_0,
+ I5 => reg_datavalid_i_9_n_0,
+ O => reg_datavalid
+ );
+reg_datavalid_i_6: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0001"
+ )
+ port map (
+ I0 => p_0_in_0(11),
+ I1 => p_0_in_0(10),
+ I2 => p_0_in_0(3),
+ I3 => p_0_in_0(2),
+ O => reg_datavalid_i_6_n_0
+ );
+reg_datavalid_i_7: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFD"
+ )
+ port map (
+ I0 => \^q\(0),
+ I1 => p_0_in_0(1),
+ I2 => p_0_in_0(6),
+ I3 => p_0_in_0(7),
+ O => reg_datavalid_i_7_n_0
+ );
+reg_datavalid_i_8: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFEF"
+ )
+ port map (
+ I0 => p_0_in_0(5),
+ I1 => p_0_in_0(9),
+ I2 => p_0_in_0(8),
+ I3 => p_0_in_0(4),
+ O => reg_datavalid_i_8_n_0
+ );
+reg_datavalid_i_9: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \fsm_rd__0\(0),
+ I1 => \fsm_rd__0\(1),
+ O => reg_datavalid_i_9_n_0
+ );
+reg_datavalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => reg_datavalid_i_1_n_0,
+ Q => \^d\(1),
+ R => '0'
+ );
+reg_error_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000ABAAA8AA"
+ )
+ port map (
+ I0 => \^d\(2),
+ I1 => \fsm_rd__0\(0),
+ I2 => \fsm_rd__0\(2),
+ I3 => \fsm_rd__0\(1),
+ I4 => reg_error1_out,
+ I5 => \reg_nbitsout_reg[5]_3\,
+ O => reg_error_i_1_n_0
+ );
+reg_error_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0777"
+ )
+ port map (
+ I0 => reg_nbitsout15_in,
+ I1 => reg_nbitsout1,
+ I2 => reg_nbitsout26_in,
+ I3 => reg_nbitsout2,
+ O => reg_error1_out
+ );
+reg_error_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => reg_error_i_1_n_0,
+ Q => \^d\(2),
+ R => '0'
+ );
+\reg_nbitsin[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"72"
+ )
+ port map (
+ I0 => fsm_wr(0),
+ I1 => \reg_nbitsin_reg_n_0_[0]\,
+ I2 => \reg_nbitsin_reg[5]_0\(0),
+ O => \reg_nbitsin[0]_i_1_n_0\
+ );
+\reg_nbitsin[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"99F0"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[1]\,
+ I1 => \reg_nbitsin_reg_n_0_[0]\,
+ I2 => \reg_nbitsin_reg[5]_0\(1),
+ I3 => fsm_wr(0),
+ O => \reg_nbitsin[1]_i_1_n_0\
+ );
+\reg_nbitsin[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EEE2222E"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg[5]_0\(2),
+ I1 => fsm_wr(0),
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_nbitsin_reg_n_0_[2]\,
+ O => \reg_nbitsin[2]_i_1_n_0\
+ );
+\reg_nbitsin[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"E2"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg[5]_0\(3),
+ I1 => fsm_wr(0),
+ I2 => \reg_nbitsin[3]_i_2_n_0\,
+ O => \reg_nbitsin[3]_i_1_n_0\
+ );
+\reg_nbitsin[3]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AAA9"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[3]\,
+ I1 => \reg_nbitsin_reg_n_0_[2]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ O => \reg_nbitsin[3]_i_2_n_0\
+ );
+\reg_nbitsin[4]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"E2"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg[5]_0\(4),
+ I1 => fsm_wr(0),
+ I2 => \reg_nbitsin[4]_i_2_n_0\,
+ O => \reg_nbitsin[4]_i_1_n_0\
+ );
+\reg_nbitsin[4]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAAA9"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[4]\,
+ I1 => \reg_nbitsin_reg_n_0_[3]\,
+ I2 => \reg_nbitsin_reg_n_0_[0]\,
+ I3 => \reg_nbitsin_reg_n_0_[1]\,
+ I4 => \reg_nbitsin_reg_n_0_[2]\,
+ O => \reg_nbitsin[4]_i_2_n_0\
+ );
+\reg_nbitsin[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0003000A"
+ )
+ port map (
+ I0 => axi_control(1),
+ I1 => serialout_i_3_n_0,
+ I2 => fsm_wr(1),
+ I3 => fsm_wr(2),
+ I4 => fsm_wr(0),
+ O => reg_nbitsin
+ );
+\reg_nbitsin[5]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"E2"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg[5]_0\(5),
+ I1 => fsm_wr(0),
+ I2 => \reg_nbitsin[5]_i_3_n_0\,
+ O => \reg_nbitsin[5]_i_2_n_0\
+ );
+\reg_nbitsin[5]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAAAAAAAAAAAA9"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[5]\,
+ I1 => \reg_nbitsin_reg_n_0_[4]\,
+ I2 => \reg_nbitsin_reg_n_0_[2]\,
+ I3 => \reg_nbitsin_reg_n_0_[1]\,
+ I4 => \reg_nbitsin_reg_n_0_[0]\,
+ I5 => \reg_nbitsin_reg_n_0_[3]\,
+ O => \reg_nbitsin[5]_i_3_n_0\
+ );
+\reg_nbitsin_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[0]_i_1_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[0]\,
+ R => axi_control(0)
+ );
+\reg_nbitsin_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[1]_i_1_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[1]\,
+ R => axi_control(0)
+ );
+\reg_nbitsin_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[2]_i_1_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[2]\,
+ R => axi_control(0)
+ );
+\reg_nbitsin_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[3]_i_1_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[3]\,
+ R => axi_control(0)
+ );
+\reg_nbitsin_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[4]_i_1_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[4]\,
+ R => axi_control(0)
+ );
+\reg_nbitsin_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsin,
+ D => \reg_nbitsin[5]_i_2_n_0\,
+ Q => \reg_nbitsin_reg_n_0_[5]\,
+ R => axi_control(0)
+ );
+\reg_nbitsout1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \reg_nbitsout1_inferred__0/i__carry_n_0\,
+ CO(2) => \reg_nbitsout1_inferred__0/i__carry_n_1\,
+ CO(1) => \reg_nbitsout1_inferred__0/i__carry_n_2\,
+ CO(0) => \reg_nbitsout1_inferred__0/i__carry_n_3\,
+ CYINIT => '0',
+ DI(3) => \i__carry_i_1__1_n_0\,
+ DI(2) => \i__carry_i_2__0_n_0\,
+ DI(1) => \i__carry_i_3__0_n_0\,
+ DI(0) => \i__carry_i_4__1_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \reg_nbitsout1_inferred__0/i__carry__0_0\(3 downto 0)
+ );
+\reg_nbitsout1_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \reg_nbitsout1_inferred__0/i__carry_n_0\,
+ CO(3 downto 2) => \NLW_reg_nbitsout1_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => reg_nbitsout1,
+ CO(0) => \reg_nbitsout1_inferred__0/i__carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1) => \i__carry__0_i_1__0_n_0\,
+ DI(0) => \i__carry__0_i_2__0_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout1_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 2) => B"00",
+ S(1 downto 0) => \reg_nbitsout_reg[5]_2\(1 downto 0)
+ );
+\reg_nbitsout1_inferred__1/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \reg_nbitsout1_inferred__1/i__carry_n_0\,
+ CO(2) => \reg_nbitsout1_inferred__1/i__carry_n_1\,
+ CO(1) => \reg_nbitsout1_inferred__1/i__carry_n_2\,
+ CO(0) => \reg_nbitsout1_inferred__1/i__carry_n_3\,
+ CYINIT => '0',
+ DI(3) => \i__carry_i_1__2_n_0\,
+ DI(2) => \i__carry_i_2__1_n_0\,
+ DI(1) => \i__carry_i_3__1_n_0\,
+ DI(0) => \i__carry_i_4__2_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout1_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => \reg_nbitsout1_inferred__1/i__carry__0_0\(3 downto 0)
+ );
+\reg_nbitsout1_inferred__1/i__carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \reg_nbitsout1_inferred__1/i__carry_n_0\,
+ CO(3 downto 2) => \NLW_reg_nbitsout1_inferred__1/i__carry__0_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => reg_nbitsout15_in,
+ CO(0) => \reg_nbitsout1_inferred__1/i__carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1) => \i__carry__0_i_1__1_n_0\,
+ DI(0) => \i__carry__0_i_2__1_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout1_inferred__1/i__carry__0_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 2) => B"00",
+ S(1) => \i__carry__0_i_3__1_n_0\,
+ S(0) => \i__carry__0_i_4__1_n_0\
+ );
+reg_nbitsout2_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => reg_nbitsout2_carry_n_0,
+ CO(2) => reg_nbitsout2_carry_n_1,
+ CO(1) => reg_nbitsout2_carry_n_2,
+ CO(0) => reg_nbitsout2_carry_n_3,
+ CYINIT => '0',
+ DI(3 downto 0) => DI(3 downto 0),
+ O(3 downto 0) => NLW_reg_nbitsout2_carry_O_UNCONNECTED(3 downto 0),
+ S(3) => reg_nbitsout2_carry_i_5_n_0,
+ S(2) => reg_nbitsout2_carry_i_6_n_0,
+ S(1) => reg_nbitsout2_carry_i_7_n_0,
+ S(0) => reg_nbitsout2_carry_i_8_n_0
+ );
+\reg_nbitsout2_carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => reg_nbitsout2_carry_n_0,
+ CO(3 downto 2) => \NLW_reg_nbitsout2_carry__0_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => reg_nbitsout2,
+ CO(0) => \reg_nbitsout2_carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1 downto 0) => \reg_nbitsout_reg[5]_1\(1 downto 0),
+ O(3 downto 0) => \NLW_reg_nbitsout2_carry__0_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 2) => B"00",
+ S(1) => \reg_nbitsout2_carry__0_i_3_n_0\,
+ S(0) => \reg_nbitsout2_carry__0_i_4_n_0\
+ );
+\reg_nbitsout2_carry__0_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(11),
+ I1 => \reg_nbitsout2_carry__0_0\(31),
+ I2 => \^q\(10),
+ I3 => \reg_nbitsout2_carry__0_0\(30),
+ O => \reg_nbitsout2_carry__0_i_3_n_0\
+ );
+\reg_nbitsout2_carry__0_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(9),
+ I1 => \reg_nbitsout2_carry__0_0\(29),
+ I2 => \^q\(8),
+ I3 => \reg_nbitsout2_carry__0_0\(28),
+ O => \reg_nbitsout2_carry__0_i_4_n_0\
+ );
+reg_nbitsout2_carry_i_5: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(7),
+ I1 => \reg_nbitsout2_carry__0_0\(27),
+ I2 => \^q\(6),
+ I3 => \reg_nbitsout2_carry__0_0\(26),
+ O => reg_nbitsout2_carry_i_5_n_0
+ );
+reg_nbitsout2_carry_i_6: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(5),
+ I1 => \reg_nbitsout2_carry__0_0\(25),
+ I2 => \^q\(4),
+ I3 => \reg_nbitsout2_carry__0_0\(24),
+ O => reg_nbitsout2_carry_i_6_n_0
+ );
+reg_nbitsout2_carry_i_7: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(3),
+ I1 => \reg_nbitsout2_carry__0_0\(23),
+ I2 => \^q\(2),
+ I3 => \reg_nbitsout2_carry__0_0\(22),
+ O => reg_nbitsout2_carry_i_7_n_0
+ );
+reg_nbitsout2_carry_i_8: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => \^q\(1),
+ I1 => \reg_nbitsout2_carry__0_0\(21),
+ I2 => \reg_nbitsout2_carry__0_0\(20),
+ I3 => \^q\(0),
+ O => reg_nbitsout2_carry_i_8_n_0
+ );
+\reg_nbitsout2_inferred__0/i__carry\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \reg_nbitsout2_inferred__0/i__carry_n_0\,
+ CO(2) => \reg_nbitsout2_inferred__0/i__carry_n_1\,
+ CO(1) => \reg_nbitsout2_inferred__0/i__carry_n_2\,
+ CO(0) => \reg_nbitsout2_inferred__0/i__carry_n_3\,
+ CYINIT => '0',
+ DI(3) => \i__carry_i_1__0_n_0\,
+ DI(2) => \i__carry_i_2_n_0\,
+ DI(1) => \i__carry_i_3_n_0\,
+ DI(0) => \i__carry_i_4__0_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout2_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 0) => S(3 downto 0)
+ );
+\reg_nbitsout2_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \reg_nbitsout2_inferred__0/i__carry_n_0\,
+ CO(3 downto 2) => \NLW_reg_nbitsout2_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2),
+ CO(1) => reg_nbitsout26_in,
+ CO(0) => \reg_nbitsout2_inferred__0/i__carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 2) => B"00",
+ DI(1) => \i__carry__0_i_1__2_n_0\,
+ DI(0) => \i__carry__0_i_2__2_n_0\,
+ O(3 downto 0) => \NLW_reg_nbitsout2_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
+ S(3 downto 2) => B"00",
+ S(1) => \i__carry__0_i_3__2_n_0\,
+ S(0) => \i__carry__0_i_4__2_n_0\
+ );
+\reg_nbitsout[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(0),
+ O => p_0_in(0)
+ );
+\reg_nbitsout[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(0),
+ I1 => \^reg_nbitsout_reg[5]_0\(1),
+ O => p_0_in(1)
+ );
+\reg_nbitsout[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"6A"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(2),
+ I1 => \^reg_nbitsout_reg[5]_0\(1),
+ I2 => \^reg_nbitsout_reg[5]_0\(0),
+ O => p_0_in(2)
+ );
+\reg_nbitsout[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6AAA"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(3),
+ I1 => \^reg_nbitsout_reg[5]_0\(0),
+ I2 => \^reg_nbitsout_reg[5]_0\(1),
+ I3 => \^reg_nbitsout_reg[5]_0\(2),
+ O => p_0_in(3)
+ );
+\reg_nbitsout[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"6AAAAAAA"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(4),
+ I1 => \^reg_nbitsout_reg[5]_0\(2),
+ I2 => \^reg_nbitsout_reg[5]_0\(1),
+ I3 => \^reg_nbitsout_reg[5]_0\(0),
+ I4 => \^reg_nbitsout_reg[5]_0\(3),
+ O => p_0_in(4)
+ );
+\reg_nbitsout[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6AAAAAAAAAAAAAAA"
+ )
+ port map (
+ I0 => \^reg_nbitsout_reg[5]_0\(5),
+ I1 => \^reg_nbitsout_reg[5]_0\(3),
+ I2 => \^reg_nbitsout_reg[5]_0\(0),
+ I3 => \^reg_nbitsout_reg[5]_0\(1),
+ I4 => \^reg_nbitsout_reg[5]_0\(2),
+ I5 => \^reg_nbitsout_reg[5]_0\(4),
+ O => p_0_in(5)
+ );
+\reg_nbitsout_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(0),
+ Q => \^reg_nbitsout_reg[5]_0\(0),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_nbitsout_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(1),
+ Q => \^reg_nbitsout_reg[5]_0\(1),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_nbitsout_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(2),
+ Q => \^reg_nbitsout_reg[5]_0\(2),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_nbitsout_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(3),
+ Q => \^reg_nbitsout_reg[5]_0\(3),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_nbitsout_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(4),
+ Q => \^reg_nbitsout_reg[5]_0\(4),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+\reg_nbitsout_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => reg_nbitsout,
+ D => p_0_in(5),
+ Q => \^reg_nbitsout_reg[5]_0\(5),
+ R => \reg_nbitsout_reg[5]_3\
+ );
+reg_serialin1_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => cmd_out,
+ Q => reg_serialin1,
+ R => axi_control(0)
+ );
+reg_serialin_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => reg_serialin1,
+ Q => reg_serialin,
+ R => axi_control(0)
+ );
+serialout_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F8C0F8CC08000800"
+ )
+ port map (
+ I0 => serialout_i_2_n_0,
+ I1 => fsm_wr(0),
+ I2 => fsm_wr(2),
+ I3 => fsm_wr(1),
+ I4 => serialout_i_3_n_0,
+ I5 => \^cmd_in\,
+ O => serialout_i_1_n_0
+ );
+serialout_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFEFFFFFFFF"
+ )
+ port map (
+ I0 => serialout_i_4_n_0,
+ I1 => \counter_reg_n_0_[10]\,
+ I2 => \counter_reg_n_0_[7]\,
+ I3 => \counter_reg_n_0_[4]\,
+ I4 => \counter_reg_n_0_[0]\,
+ I5 => serialout_i_5_n_0,
+ O => serialout_i_2_n_0
+ );
+serialout_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => \reg_nbitsin_reg_n_0_[4]\,
+ I1 => \reg_nbitsin_reg_n_0_[2]\,
+ I2 => \reg_nbitsin_reg_n_0_[1]\,
+ I3 => \reg_nbitsin_reg_n_0_[0]\,
+ I4 => \reg_nbitsin_reg_n_0_[3]\,
+ I5 => \reg_nbitsin_reg_n_0_[5]\,
+ O => serialout_i_3_n_0
+ );
+serialout_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[8]\,
+ I1 => \counter_reg_n_0_[9]\,
+ I2 => \counter_reg_n_0_[1]\,
+ I3 => \counter_reg_n_0_[11]\,
+ O => serialout_i_4_n_0
+ );
+serialout_i_5: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0001"
+ )
+ port map (
+ I0 => \counter_reg_n_0_[2]\,
+ I1 => \counter_reg_n_0_[6]\,
+ I2 => \counter_reg_n_0_[3]\,
+ I3 => \counter_reg_n_0_[5]\,
+ O => serialout_i_5_n_0
+ );
+serialout_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => serialout_i_1_n_0,
+ Q => \^cmd_in\,
+ R => axi_control(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0 is
+ port (
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ cmd_out : out STD_LOGIC;
+ CMD_IN_P : out STD_LOGIC;
+ CMD_IN_N : out STD_LOGIC;
+ cmd_in : out STD_LOGIC;
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_aresetn : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ CMD_OUT_P : in STD_LOGIC;
+ CMD_OUT_N : in STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0 : entity is "endeavour_axi_controller_v1_0";
+end TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0;
+
+architecture STRUCTURE of TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0 is
+ signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal I : STD_LOGIC;
+ signal TICKS_BITGAP_MID : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_DAH_MAX : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_DAH_MID : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_DAH_MIN : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal TICKS_DIT_MAX : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_DIT_MID : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal TICKS_DIT_MIN : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal axi_config : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal axi_control : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_datain : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal axi_dataout : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal axi_nbitsin : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal axi_nbitsout_integer : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal \^cmd_out\ : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_10 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_11 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_44 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_45 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_46 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_47 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_48 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_49 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_5 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_50 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_51 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_52 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_53 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_8 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_86 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_87 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_88 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_89 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_9 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_90 : STD_LOGIC;
+ signal endeavour_axi_controller_v1_0_S00_AXI_inst_n_91 : STD_LOGIC;
+ signal inst_endeavour_master_n_10 : STD_LOGIC;
+ signal inst_endeavour_master_n_11 : STD_LOGIC;
+ signal inst_endeavour_master_n_12 : STD_LOGIC;
+ signal inst_endeavour_master_n_13 : STD_LOGIC;
+ signal inst_endeavour_master_n_14 : STD_LOGIC;
+ signal inst_endeavour_master_n_15 : STD_LOGIC;
+ signal inst_endeavour_master_n_4 : STD_LOGIC;
+ signal inst_endeavour_master_n_5 : STD_LOGIC;
+ signal inst_endeavour_master_n_6 : STD_LOGIC;
+ signal inst_endeavour_master_n_7 : STD_LOGIC;
+ signal inst_endeavour_master_n_8 : STD_LOGIC;
+ signal inst_endeavour_master_n_9 : STD_LOGIC;
+ signal seriali_buf : STD_LOGIC;
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of CMD_IN_buf_inst : label is "DONT_CARE";
+ attribute box_type : string;
+ attribute box_type of CMD_IN_buf_inst : label is "PRIMITIVE";
+ attribute CAPACITANCE of CMD_OUT_buf_inst : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of CMD_OUT_buf_inst : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of CMD_OUT_buf_inst : label is "AUTO";
+ attribute box_type of CMD_OUT_buf_inst : label is "PRIMITIVE";
+begin
+ D(2 downto 0) <= \^d\(2 downto 0);
+ cmd_out <= \^cmd_out\;
+CMD_IN_buf_inst: unisim.vcomponents.OBUFDS
+ port map (
+ I => I,
+ O => CMD_IN_P,
+ OB => CMD_IN_N
+ );
+CMD_OUT_buf_inst: unisim.vcomponents.IBUFDS
+ port map (
+ I => CMD_OUT_P,
+ IB => CMD_OUT_N,
+ O => seriali_buf
+ );
+endeavour_axi_controller_v1_0_S00_AXI_inst: entity work.TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0_S00_AXI
+ port map (
+ D(63 downto 0) => axi_datain(63 downto 0),
+ DI(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_8,
+ DI(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_9,
+ DI(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_10,
+ DI(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_11,
+ Q(31 downto 20) => TICKS_DIT_MAX(11 downto 0),
+ Q(19 downto 8) => TICKS_DIT_MID(11 downto 0),
+ Q(7 downto 0) => TICKS_DIT_MIN(7 downto 0),
+ S(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_46,
+ S(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_47,
+ S(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_48,
+ S(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_49,
+ axi_control(1 downto 0) => axi_control(1 downto 0),
+ cmd_out => \^cmd_out\,
+ \reg_nbitsout1_inferred__0/i__carry__0\(11) => inst_endeavour_master_n_4,
+ \reg_nbitsout1_inferred__0/i__carry__0\(10) => inst_endeavour_master_n_5,
+ \reg_nbitsout1_inferred__0/i__carry__0\(9) => inst_endeavour_master_n_6,
+ \reg_nbitsout1_inferred__0/i__carry__0\(8) => inst_endeavour_master_n_7,
+ \reg_nbitsout1_inferred__0/i__carry__0\(7) => inst_endeavour_master_n_8,
+ \reg_nbitsout1_inferred__0/i__carry__0\(6) => inst_endeavour_master_n_9,
+ \reg_nbitsout1_inferred__0/i__carry__0\(5) => inst_endeavour_master_n_10,
+ \reg_nbitsout1_inferred__0/i__carry__0\(4) => inst_endeavour_master_n_11,
+ \reg_nbitsout1_inferred__0/i__carry__0\(3) => inst_endeavour_master_n_12,
+ \reg_nbitsout1_inferred__0/i__carry__0\(2) => inst_endeavour_master_n_13,
+ \reg_nbitsout1_inferred__0/i__carry__0\(1) => inst_endeavour_master_n_14,
+ \reg_nbitsout1_inferred__0/i__carry__0\(0) => inst_endeavour_master_n_15,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(3 downto 0) => s00_axi_araddr(3 downto 0),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(3 downto 0) => s00_axi_awaddr(3 downto 0),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
+ s00_axi_wvalid => s00_axi_wvalid,
+ seriali_buf => seriali_buf,
+ \slv_reg0_pulse_reg[1]_0\ => endeavour_axi_controller_v1_0_S00_AXI_inst_n_5,
+ \slv_reg0_read_reg[2]_0\(2 downto 0) => \^d\(2 downto 0),
+ \slv_reg10_reg[0]_0\(0) => axi_config(0),
+ \slv_reg1_reg[5]_0\(5 downto 0) => axi_nbitsin(5 downto 0),
+ \slv_reg4_reg[5]_0\(5 downto 0) => axi_nbitsout_integer(5 downto 0),
+ \slv_reg6_reg[31]_0\(63 downto 0) => axi_dataout(63 downto 0),
+ \slv_reg7_reg[31]_0\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_44,
+ \slv_reg7_reg[31]_0\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_45,
+ \slv_reg8_reg[27]_0\(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_50,
+ \slv_reg8_reg[27]_0\(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_51,
+ \slv_reg8_reg[27]_0\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_52,
+ \slv_reg8_reg[27]_0\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_53,
+ \slv_reg8_reg[31]_0\(31 downto 20) => TICKS_DAH_MAX(11 downto 0),
+ \slv_reg8_reg[31]_0\(19 downto 8) => TICKS_DAH_MID(11 downto 0),
+ \slv_reg8_reg[31]_0\(7 downto 0) => TICKS_DAH_MIN(7 downto 0),
+ \slv_reg8_reg[31]_1\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_86,
+ \slv_reg8_reg[31]_1\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_87,
+ \slv_reg8_reg[7]_0\(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_88,
+ \slv_reg8_reg[7]_0\(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_89,
+ \slv_reg8_reg[7]_0\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_90,
+ \slv_reg8_reg[7]_0\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_91,
+ \slv_reg9_reg[19]_0\(11 downto 0) => TICKS_BITGAP_MID(11 downto 0)
+ );
+inst_endeavour_master: entity work.TopLevel_endeavour_axi_contro_5_0_endeavour_master
+ port map (
+ CMD_IN_P(0) => axi_config(0),
+ D(2 downto 0) => \^d\(2 downto 0),
+ DI(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_8,
+ DI(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_9,
+ DI(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_10,
+ DI(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_11,
+ I => I,
+ Q(11) => inst_endeavour_master_n_4,
+ Q(10) => inst_endeavour_master_n_5,
+ Q(9) => inst_endeavour_master_n_6,
+ Q(8) => inst_endeavour_master_n_7,
+ Q(7) => inst_endeavour_master_n_8,
+ Q(6) => inst_endeavour_master_n_9,
+ Q(5) => inst_endeavour_master_n_10,
+ Q(4) => inst_endeavour_master_n_11,
+ Q(3) => inst_endeavour_master_n_12,
+ Q(2) => inst_endeavour_master_n_13,
+ Q(1) => inst_endeavour_master_n_14,
+ Q(0) => inst_endeavour_master_n_15,
+ S(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_46,
+ S(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_47,
+ S(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_48,
+ S(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_49,
+ axi_control(1 downto 0) => axi_control(1 downto 0),
+ cmd_in => cmd_in,
+ cmd_out => \^cmd_out\,
+ \counter_reg[11]_0\(11 downto 0) => TICKS_BITGAP_MID(11 downto 0),
+ \reg_datain_reg[63]_0\(63 downto 0) => axi_datain(63 downto 0),
+ \reg_dataout_reg[63]_0\(63 downto 0) => axi_dataout(63 downto 0),
+ \reg_nbitsin_reg[5]_0\(5 downto 0) => axi_nbitsin(5 downto 0),
+ \reg_nbitsout1_inferred__0/i__carry__0_0\(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_50,
+ \reg_nbitsout1_inferred__0/i__carry__0_0\(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_51,
+ \reg_nbitsout1_inferred__0/i__carry__0_0\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_52,
+ \reg_nbitsout1_inferred__0/i__carry__0_0\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_53,
+ \reg_nbitsout1_inferred__0/i__carry__0_1\(31 downto 20) => TICKS_DAH_MAX(11 downto 0),
+ \reg_nbitsout1_inferred__0/i__carry__0_1\(19 downto 8) => TICKS_DAH_MID(11 downto 0),
+ \reg_nbitsout1_inferred__0/i__carry__0_1\(7 downto 0) => TICKS_DAH_MIN(7 downto 0),
+ \reg_nbitsout1_inferred__1/i__carry__0_0\(3) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_88,
+ \reg_nbitsout1_inferred__1/i__carry__0_0\(2) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_89,
+ \reg_nbitsout1_inferred__1/i__carry__0_0\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_90,
+ \reg_nbitsout1_inferred__1/i__carry__0_0\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_91,
+ \reg_nbitsout2_carry__0_0\(31 downto 20) => TICKS_DIT_MAX(11 downto 0),
+ \reg_nbitsout2_carry__0_0\(19 downto 8) => TICKS_DIT_MID(11 downto 0),
+ \reg_nbitsout2_carry__0_0\(7 downto 0) => TICKS_DIT_MIN(7 downto 0),
+ \reg_nbitsout_reg[5]_0\(5 downto 0) => axi_nbitsout_integer(5 downto 0),
+ \reg_nbitsout_reg[5]_1\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_44,
+ \reg_nbitsout_reg[5]_1\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_45,
+ \reg_nbitsout_reg[5]_2\(1) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_86,
+ \reg_nbitsout_reg[5]_2\(0) => endeavour_axi_controller_v1_0_S00_AXI_inst_n_87,
+ \reg_nbitsout_reg[5]_3\ => endeavour_axi_controller_v1_0_S00_AXI_inst_n_5,
+ s00_axi_aclk => s00_axi_aclk
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_endeavour_axi_contro_5_0 is
+ port (
+ busy : out STD_LOGIC;
+ datavalid : out STD_LOGIC;
+ error : out STD_LOGIC;
+ CMD_IN_P : out STD_LOGIC;
+ CMD_IN_N : out STD_LOGIC;
+ CMD_OUT_P : in STD_LOGIC;
+ CMD_OUT_N : in STD_LOGIC;
+ cmd_in : out STD_LOGIC;
+ cmd_out : out STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of TopLevel_endeavour_axi_contro_5_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of TopLevel_endeavour_axi_contro_5_0 : entity is "TopLevel_endeavour_axi_contro_5_0,endeavour_axi_controller_v1_0,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of TopLevel_endeavour_axi_contro_5_0 : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of TopLevel_endeavour_axi_contro_5_0 : entity is "endeavour_axi_controller_v1_0,Vivado 2019.1";
+end TopLevel_endeavour_axi_contro_5_0;
+
+architecture STRUCTURE of TopLevel_endeavour_axi_contro_5_0 is
+ signal \<const0>\ : STD_LOGIC;
+ attribute x_interface_info : string;
+ attribute x_interface_info of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ attribute x_interface_info of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
+ attribute x_interface_parameter of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ attribute x_interface_info of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
+ attribute x_interface_info of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
+ attribute x_interface_info of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
+ attribute x_interface_info of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
+ attribute x_interface_info of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
+ attribute x_interface_info of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
+ attribute x_interface_info of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
+ attribute x_interface_info of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
+ attribute x_interface_info of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
+ attribute x_interface_info of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
+ attribute x_interface_info of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
+ attribute x_interface_info of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
+ attribute x_interface_info of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
+ attribute x_interface_parameter of s00_axi_awaddr : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 8, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 6, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute x_interface_info of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
+ attribute x_interface_info of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
+ attribute x_interface_info of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
+ attribute x_interface_info of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
+ attribute x_interface_info of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
+ attribute x_interface_info of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
+begin
+ s00_axi_bresp(1) <= \<const0>\;
+ s00_axi_bresp(0) <= \<const0>\;
+ s00_axi_rresp(1) <= \<const0>\;
+ s00_axi_rresp(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+U0: entity work.TopLevel_endeavour_axi_contro_5_0_endeavour_axi_controller_v1_0
+ port map (
+ CMD_IN_N => CMD_IN_N,
+ CMD_IN_P => CMD_IN_P,
+ CMD_OUT_N => CMD_OUT_N,
+ CMD_OUT_P => CMD_OUT_P,
+ D(2) => error,
+ D(1) => datavalid,
+ D(0) => busy,
+ cmd_in => cmd_in,
+ cmd_out => cmd_out,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(3 downto 0) => s00_axi_araddr(5 downto 2),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(3 downto 0) => s00_axi_awaddr(5 downto 2),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
+ s00_axi_wvalid => s00_axi_wvalid
+ );
+end STRUCTURE;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.v
new file mode 100644
index 0000000..eeeeb60
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.v
@@ -0,0 +1,54 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Tue Oct 15 10:07:03 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub
+// /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.v
+// Design : TopLevel_endeavour_axi_contro_5_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "endeavour_axi_controller_v1_0,Vivado 2019.1" *)
+module TopLevel_endeavour_axi_contro_5_0(busy, datavalid, error, CMD_IN_P, CMD_IN_N,
+ CMD_OUT_P, CMD_OUT_N, cmd_in, cmd_out, s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid,
+ s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready,
+ s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr, s00_axi_arprot,
+ s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid,
+ s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
+/* synthesis syn_black_box black_box_pad_pin="busy,datavalid,error,CMD_IN_P,CMD_IN_N,CMD_OUT_P,CMD_OUT_N,cmd_in,cmd_out,s00_axi_awaddr[5:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[5:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
+ output busy;
+ output datavalid;
+ output error;
+ output CMD_IN_P;
+ output CMD_IN_N;
+ input CMD_OUT_P;
+ input CMD_OUT_N;
+ output cmd_in;
+ output cmd_out;
+ input [5:0]s00_axi_awaddr;
+ input [2:0]s00_axi_awprot;
+ input s00_axi_awvalid;
+ output s00_axi_awready;
+ input [31:0]s00_axi_wdata;
+ input [3:0]s00_axi_wstrb;
+ input s00_axi_wvalid;
+ output s00_axi_wready;
+ output [1:0]s00_axi_bresp;
+ output s00_axi_bvalid;
+ input s00_axi_bready;
+ input [5:0]s00_axi_araddr;
+ input [2:0]s00_axi_arprot;
+ input s00_axi_arvalid;
+ output s00_axi_arready;
+ output [31:0]s00_axi_rdata;
+ output [1:0]s00_axi_rresp;
+ output s00_axi_rvalid;
+ input s00_axi_rready;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.vhdl
new file mode 100644
index 0000000..c2b693e
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.vhdl
@@ -0,0 +1,59 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Tue Oct 15 10:07:03 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/TopLevel_endeavour_axi_contro_5_0_stub.vhdl
+-- Design : TopLevel_endeavour_axi_contro_5_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity TopLevel_endeavour_axi_contro_5_0 is
+ Port (
+ busy : out STD_LOGIC;
+ datavalid : out STD_LOGIC;
+ error : out STD_LOGIC;
+ CMD_IN_P : out STD_LOGIC;
+ CMD_IN_N : out STD_LOGIC;
+ CMD_OUT_P : in STD_LOGIC;
+ CMD_OUT_N : in STD_LOGIC;
+ cmd_in : out STD_LOGIC;
+ cmd_out : out STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC
+ );
+
+end TopLevel_endeavour_axi_contro_5_0;
+
+architecture stub of TopLevel_endeavour_axi_contro_5_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "busy,datavalid,error,CMD_IN_P,CMD_IN_N,CMD_OUT_P,CMD_OUT_N,cmd_in,cmd_out,s00_axi_awaddr[5:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[5:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "endeavour_axi_controller_v1_0,Vivado 2019.1";
+begin
+end;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/sim/TopLevel_endeavour_axi_contro_5_0.vhd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/sim/TopLevel_endeavour_axi_contro_5_0.vhd
new file mode 100644
index 0000000..7a42249
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/sim/TopLevel_endeavour_axi_contro_5_0.vhd
@@ -0,0 +1,197 @@
+-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: lbl.gov:endeavour:endeavour_axi_controller:1.0
+-- IP Revision: 5
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY TopLevel_endeavour_axi_contro_5_0 IS
+ PORT (
+ busy : OUT STD_LOGIC;
+ datavalid : OUT STD_LOGIC;
+ error : OUT STD_LOGIC;
+ CMD_IN_P : OUT STD_LOGIC;
+ CMD_IN_N : OUT STD_LOGIC;
+ CMD_OUT_P : IN STD_LOGIC;
+ CMD_OUT_N : IN STD_LOGIC;
+ cmd_in : OUT STD_LOGIC;
+ cmd_out : OUT STD_LOGIC;
+ s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_awvalid : IN STD_LOGIC;
+ s00_axi_awready : OUT STD_LOGIC;
+ s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s00_axi_wvalid : IN STD_LOGIC;
+ s00_axi_wready : OUT STD_LOGIC;
+ s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_bvalid : OUT STD_LOGIC;
+ s00_axi_bready : IN STD_LOGIC;
+ s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_arvalid : IN STD_LOGIC;
+ s00_axi_arready : OUT STD_LOGIC;
+ s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_rvalid : OUT STD_LOGIC;
+ s00_axi_rready : IN STD_LOGIC;
+ s00_axi_aclk : IN STD_LOGIC;
+ s00_axi_aresetn : IN STD_LOGIC
+ );
+END TopLevel_endeavour_axi_contro_5_0;
+
+ARCHITECTURE TopLevel_endeavour_axi_contro_5_0_arch OF TopLevel_endeavour_axi_contro_5_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF TopLevel_endeavour_axi_contro_5_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT endeavour_axi_controller_v1_0 IS
+ GENERIC (
+ C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
+ C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
+ );
+ PORT (
+ busy : OUT STD_LOGIC;
+ datavalid : OUT STD_LOGIC;
+ error : OUT STD_LOGIC;
+ CMD_IN_P : OUT STD_LOGIC;
+ CMD_IN_N : OUT STD_LOGIC;
+ CMD_OUT_P : IN STD_LOGIC;
+ CMD_OUT_N : IN STD_LOGIC;
+ cmd_in : OUT STD_LOGIC;
+ cmd_out : OUT STD_LOGIC;
+ s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_awvalid : IN STD_LOGIC;
+ s00_axi_awready : OUT STD_LOGIC;
+ s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s00_axi_wvalid : IN STD_LOGIC;
+ s00_axi_wready : OUT STD_LOGIC;
+ s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_bvalid : OUT STD_LOGIC;
+ s00_axi_bready : IN STD_LOGIC;
+ s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_arvalid : IN STD_LOGIC;
+ s00_axi_arready : OUT STD_LOGIC;
+ s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_rvalid : OUT STD_LOGIC;
+ s00_axi_rready : IN STD_LOGIC;
+ s00_axi_aclk : IN STD_LOGIC;
+ s00_axi_aresetn : IN STD_LOGIC
+ );
+ END COMPONENT endeavour_axi_controller_v1_0;
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 8, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 6, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_sys" &
+"tem7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
+BEGIN
+ U0 : endeavour_axi_controller_v1_0
+ GENERIC MAP (
+ C_S00_AXI_DATA_WIDTH => 32,
+ C_S00_AXI_ADDR_WIDTH => 6
+ )
+ PORT MAP (
+ busy => busy,
+ datavalid => datavalid,
+ error => error,
+ CMD_IN_P => CMD_IN_P,
+ CMD_IN_N => CMD_IN_N,
+ CMD_OUT_P => CMD_OUT_P,
+ CMD_OUT_N => CMD_OUT_N,
+ cmd_in => cmd_in,
+ cmd_out => cmd_out,
+ s00_axi_awaddr => s00_axi_awaddr,
+ s00_axi_awprot => s00_axi_awprot,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_wdata => s00_axi_wdata,
+ s00_axi_wstrb => s00_axi_wstrb,
+ s00_axi_wvalid => s00_axi_wvalid,
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_bresp => s00_axi_bresp,
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_araddr => s00_axi_araddr,
+ s00_axi_arprot => s00_axi_arprot,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_rdata => s00_axi_rdata,
+ s00_axi_rresp => s00_axi_rresp,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn
+ );
+END TopLevel_endeavour_axi_contro_5_0_arch;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/synth/TopLevel_endeavour_axi_contro_5_0.vhd b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/synth/TopLevel_endeavour_axi_contro_5_0.vhd
new file mode 100644
index 0000000..fea2f18
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_endeavour_axi_contro_5_0/synth/TopLevel_endeavour_axi_contro_5_0.vhd
@@ -0,0 +1,201 @@
+-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: lbl.gov:endeavour:endeavour_axi_controller:1.0
+-- IP Revision: 5
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY TopLevel_endeavour_axi_contro_5_0 IS
+ PORT (
+ busy : OUT STD_LOGIC;
+ datavalid : OUT STD_LOGIC;
+ error : OUT STD_LOGIC;
+ CMD_IN_P : OUT STD_LOGIC;
+ CMD_IN_N : OUT STD_LOGIC;
+ CMD_OUT_P : IN STD_LOGIC;
+ CMD_OUT_N : IN STD_LOGIC;
+ cmd_in : OUT STD_LOGIC;
+ cmd_out : OUT STD_LOGIC;
+ s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_awvalid : IN STD_LOGIC;
+ s00_axi_awready : OUT STD_LOGIC;
+ s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s00_axi_wvalid : IN STD_LOGIC;
+ s00_axi_wready : OUT STD_LOGIC;
+ s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_bvalid : OUT STD_LOGIC;
+ s00_axi_bready : IN STD_LOGIC;
+ s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_arvalid : IN STD_LOGIC;
+ s00_axi_arready : OUT STD_LOGIC;
+ s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_rvalid : OUT STD_LOGIC;
+ s00_axi_rready : IN STD_LOGIC;
+ s00_axi_aclk : IN STD_LOGIC;
+ s00_axi_aresetn : IN STD_LOGIC
+ );
+END TopLevel_endeavour_axi_contro_5_0;
+
+ARCHITECTURE TopLevel_endeavour_axi_contro_5_0_arch OF TopLevel_endeavour_axi_contro_5_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF TopLevel_endeavour_axi_contro_5_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT endeavour_axi_controller_v1_0 IS
+ GENERIC (
+ C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
+ C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
+ );
+ PORT (
+ busy : OUT STD_LOGIC;
+ datavalid : OUT STD_LOGIC;
+ error : OUT STD_LOGIC;
+ CMD_IN_P : OUT STD_LOGIC;
+ CMD_IN_N : OUT STD_LOGIC;
+ CMD_OUT_P : IN STD_LOGIC;
+ CMD_OUT_N : IN STD_LOGIC;
+ cmd_in : OUT STD_LOGIC;
+ cmd_out : OUT STD_LOGIC;
+ s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_awvalid : IN STD_LOGIC;
+ s00_axi_awready : OUT STD_LOGIC;
+ s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s00_axi_wvalid : IN STD_LOGIC;
+ s00_axi_wready : OUT STD_LOGIC;
+ s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_bvalid : OUT STD_LOGIC;
+ s00_axi_bready : IN STD_LOGIC;
+ s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ s00_axi_arvalid : IN STD_LOGIC;
+ s00_axi_arready : OUT STD_LOGIC;
+ s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s00_axi_rvalid : OUT STD_LOGIC;
+ s00_axi_rready : IN STD_LOGIC;
+ s00_axi_aclk : IN STD_LOGIC;
+ s00_axi_aresetn : IN STD_LOGIC
+ );
+ END COMPONENT endeavour_axi_controller_v1_0;
+ ATTRIBUTE X_CORE_INFO : STRING;
+ ATTRIBUTE X_CORE_INFO OF TopLevel_endeavour_axi_contro_5_0_arch: ARCHITECTURE IS "endeavour_axi_controller_v1_0,Vivado 2019.1";
+ ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+ ATTRIBUTE CHECK_LICENSE_TYPE OF TopLevel_endeavour_axi_contro_5_0_arch : ARCHITECTURE IS "TopLevel_endeavour_axi_contro_5_0,endeavour_axi_controller_v1_0,{}";
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 8, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 6, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN TopLevel_processing_sys" &
+"tem7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
+BEGIN
+ U0 : endeavour_axi_controller_v1_0
+ GENERIC MAP (
+ C_S00_AXI_DATA_WIDTH => 32,
+ C_S00_AXI_ADDR_WIDTH => 6
+ )
+ PORT MAP (
+ busy => busy,
+ datavalid => datavalid,
+ error => error,
+ CMD_IN_P => CMD_IN_P,
+ CMD_IN_N => CMD_IN_N,
+ CMD_OUT_P => CMD_OUT_P,
+ CMD_OUT_N => CMD_OUT_N,
+ cmd_in => cmd_in,
+ cmd_out => cmd_out,
+ s00_axi_awaddr => s00_axi_awaddr,
+ s00_axi_awprot => s00_axi_awprot,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_wdata => s00_axi_wdata,
+ s00_axi_wstrb => s00_axi_wstrb,
+ s00_axi_wvalid => s00_axi_wvalid,
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_bresp => s00_axi_bresp,
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_araddr => s00_axi_araddr,
+ s00_axi_arprot => s00_axi_arprot,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_rdata => s00_axi_rdata,
+ s00_axi_rresp => s00_axi_rresp,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn
+ );
+END TopLevel_endeavour_axi_contro_5_0_arch;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.dcp b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.dcp
new file mode 100644
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literal 0
HcmV?d00001
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xci b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xci
similarity index 99%
rename from pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xci
rename to pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xci
index e430d15..276e127 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xci
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xci
@@ -6,7 +6,7 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
- <spirit:instanceName>TopLevel_processing_system7_0_1</spirit:instanceName>
+ <spirit:instanceName>TopLevel_processing_system7_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="processing_system7" spirit:version="5.5"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE0_NFIQ.PortWidth">1</spirit:configurableElementValue>
@@ -161,7 +161,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ENET1_EXT_INTIN.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.ASSOCIATED_RESET"/>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.PHASE">0.000</spirit:configurableElementValue>
@@ -244,7 +244,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.HAS_BRESP">1</spirit:configurableElementValue>
@@ -270,7 +270,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.ASSOCIATED_RESET"/>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.PHASE">0.000</spirit:configurableElementValue>
@@ -545,7 +545,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">TopLevel_processing_system7_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">TopLevel_processing_system7_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_APU_PERIPHERAL_FREQMHZ">666.666687</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
@@ -1254,13 +1254,13 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_BASEADDR">0xE0104000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ">111.111115</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ">111.111115</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ">111.111115</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_HIGHADDR">0xE0104fff</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_TTC0_IO">EMIO</spirit:configurableElementValue>
@@ -1926,7 +1926,6 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_IO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE" xilinx:valueSource="user"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xdc b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xdc
new file mode 100644
index 0000000..4d916cb
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xdc
@@ -0,0 +1,654 @@
+############################################################################
+##
+## Xilinx, Inc. 2006 www.xilinx.com
+############################################################################
+## File name : ps7_constraints.xdc
+##
+## Details : Constraints file
+## FPGA family: zynq
+## FPGA: xc7z020clg400-1
+## Device Size: xc7z020
+## Package: clg400
+## Speedgrade: -1
+##
+##
+############################################################################
+############################################################################
+############################################################################
+# Clock constraints #
+############################################################################
+create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
+set_input_jitter clk_fpga_0 0.3
+#The clocks are asynchronous, user should constrain them appropriately.#
+
+
+############################################################################
+# I/O STANDARDS and Location Constraints #
+############################################################################
+
+# Enet 0 / mdio / MIO[53]
+set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
+set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
+set_property slew "slow" [get_ports "MIO[53]"]
+set_property drive "8" [get_ports "MIO[53]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
+# Enet 0 / mdc / MIO[52]
+set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
+set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
+set_property slew "slow" [get_ports "MIO[52]"]
+set_property drive "8" [get_ports "MIO[52]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
+# GPIO / gpio[51] / MIO[51]
+set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
+set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
+set_property slew "slow" [get_ports "MIO[51]"]
+set_property drive "8" [get_ports "MIO[51]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
+# SD 0 / wp / MIO[50]
+set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
+set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
+set_property slew "slow" [get_ports "MIO[50]"]
+set_property drive "8" [get_ports "MIO[50]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[50]"]
+# UART 1 / rx / MIO[49]
+set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
+set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
+set_property slew "slow" [get_ports "MIO[49]"]
+set_property drive "8" [get_ports "MIO[49]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
+# UART 1 / tx / MIO[48]
+set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
+set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
+set_property slew "slow" [get_ports "MIO[48]"]
+set_property drive "8" [get_ports "MIO[48]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
+# GPIO / gpio[47] / MIO[47]
+set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
+set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
+set_property slew "slow" [get_ports "MIO[47]"]
+set_property drive "8" [get_ports "MIO[47]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"]
+# SD 0 / cd / MIO[46]
+set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
+set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
+set_property slew "slow" [get_ports "MIO[46]"]
+set_property drive "8" [get_ports "MIO[46]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
+# SD 0 / data[3] / MIO[45]
+set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
+set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
+set_property slew "slow" [get_ports "MIO[45]"]
+set_property drive "8" [get_ports "MIO[45]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
+# SD 0 / data[2] / MIO[44]
+set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
+set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
+set_property slew "slow" [get_ports "MIO[44]"]
+set_property drive "8" [get_ports "MIO[44]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
+# SD 0 / data[1] / MIO[43]
+set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
+set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
+set_property slew "slow" [get_ports "MIO[43]"]
+set_property drive "8" [get_ports "MIO[43]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
+# SD 0 / data[0] / MIO[42]
+set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
+set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
+set_property slew "slow" [get_ports "MIO[42]"]
+set_property drive "8" [get_ports "MIO[42]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
+# SD 0 / cmd / MIO[41]
+set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
+set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
+set_property slew "slow" [get_ports "MIO[41]"]
+set_property drive "8" [get_ports "MIO[41]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
+# SD 0 / clk / MIO[40]
+set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
+set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
+set_property slew "slow" [get_ports "MIO[40]"]
+set_property drive "8" [get_ports "MIO[40]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
+# USB 0 / data[7] / MIO[39]
+set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
+set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
+set_property slew "slow" [get_ports "MIO[39]"]
+set_property drive "8" [get_ports "MIO[39]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
+# USB 0 / data[6] / MIO[38]
+set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
+set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
+set_property slew "slow" [get_ports "MIO[38]"]
+set_property drive "8" [get_ports "MIO[38]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
+# USB 0 / data[5] / MIO[37]
+set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
+set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
+set_property slew "slow" [get_ports "MIO[37]"]
+set_property drive "8" [get_ports "MIO[37]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
+# USB 0 / clk / MIO[36]
+set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
+set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
+set_property slew "slow" [get_ports "MIO[36]"]
+set_property drive "8" [get_ports "MIO[36]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
+# USB 0 / data[3] / MIO[35]
+set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
+set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
+set_property slew "slow" [get_ports "MIO[35]"]
+set_property drive "8" [get_ports "MIO[35]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
+# USB 0 / data[2] / MIO[34]
+set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
+set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
+set_property slew "slow" [get_ports "MIO[34]"]
+set_property drive "8" [get_ports "MIO[34]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
+# USB 0 / data[1] / MIO[33]
+set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
+set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
+set_property slew "slow" [get_ports "MIO[33]"]
+set_property drive "8" [get_ports "MIO[33]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
+# USB 0 / data[0] / MIO[32]
+set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
+set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
+set_property slew "slow" [get_ports "MIO[32]"]
+set_property drive "8" [get_ports "MIO[32]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
+# USB 0 / nxt / MIO[31]
+set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
+set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
+set_property slew "slow" [get_ports "MIO[31]"]
+set_property drive "8" [get_ports "MIO[31]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
+# USB 0 / stp / MIO[30]
+set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
+set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
+set_property slew "slow" [get_ports "MIO[30]"]
+set_property drive "8" [get_ports "MIO[30]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
+# USB 0 / dir / MIO[29]
+set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
+set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
+set_property slew "slow" [get_ports "MIO[29]"]
+set_property drive "8" [get_ports "MIO[29]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
+# USB 0 / data[4] / MIO[28]
+set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
+set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
+set_property slew "slow" [get_ports "MIO[28]"]
+set_property drive "8" [get_ports "MIO[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
+# Enet 0 / rx_ctl / MIO[27]
+set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
+set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
+set_property slew "slow" [get_ports "MIO[27]"]
+set_property drive "8" [get_ports "MIO[27]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
+# Enet 0 / rxd[3] / MIO[26]
+set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
+set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
+set_property slew "slow" [get_ports "MIO[26]"]
+set_property drive "8" [get_ports "MIO[26]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
+# Enet 0 / rxd[2] / MIO[25]
+set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
+set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
+set_property slew "slow" [get_ports "MIO[25]"]
+set_property drive "8" [get_ports "MIO[25]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
+# Enet 0 / rxd[1] / MIO[24]
+set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
+set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
+set_property slew "slow" [get_ports "MIO[24]"]
+set_property drive "8" [get_ports "MIO[24]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
+# Enet 0 / rxd[0] / MIO[23]
+set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
+set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
+set_property slew "slow" [get_ports "MIO[23]"]
+set_property drive "8" [get_ports "MIO[23]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
+# Enet 0 / rx_clk / MIO[22]
+set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
+set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
+set_property slew "slow" [get_ports "MIO[22]"]
+set_property drive "8" [get_ports "MIO[22]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
+# Enet 0 / tx_ctl / MIO[21]
+set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
+set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
+set_property slew "slow" [get_ports "MIO[21]"]
+set_property drive "8" [get_ports "MIO[21]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
+# Enet 0 / txd[3] / MIO[20]
+set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
+set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
+set_property slew "slow" [get_ports "MIO[20]"]
+set_property drive "8" [get_ports "MIO[20]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
+# Enet 0 / txd[2] / MIO[19]
+set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
+set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
+set_property slew "slow" [get_ports "MIO[19]"]
+set_property drive "8" [get_ports "MIO[19]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
+# Enet 0 / txd[1] / MIO[18]
+set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
+set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
+set_property slew "slow" [get_ports "MIO[18]"]
+set_property drive "8" [get_ports "MIO[18]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
+# Enet 0 / txd[0] / MIO[17]
+set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
+set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
+set_property slew "slow" [get_ports "MIO[17]"]
+set_property drive "8" [get_ports "MIO[17]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
+# Enet 0 / tx_clk / MIO[16]
+set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
+set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
+set_property slew "slow" [get_ports "MIO[16]"]
+set_property drive "8" [get_ports "MIO[16]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
+# GPIO / gpio[15] / MIO[15]
+set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
+set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
+set_property slew "slow" [get_ports "MIO[15]"]
+set_property drive "8" [get_ports "MIO[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
+# GPIO / gpio[14] / MIO[14]
+set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
+set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
+set_property slew "slow" [get_ports "MIO[14]"]
+set_property drive "8" [get_ports "MIO[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
+# GPIO / gpio[13] / MIO[13]
+set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
+set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
+set_property slew "slow" [get_ports "MIO[13]"]
+set_property drive "8" [get_ports "MIO[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
+# GPIO / gpio[12] / MIO[12]
+set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
+set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
+set_property slew "slow" [get_ports "MIO[12]"]
+set_property drive "8" [get_ports "MIO[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
+# GPIO / gpio[11] / MIO[11]
+set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
+set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
+set_property slew "slow" [get_ports "MIO[11]"]
+set_property drive "8" [get_ports "MIO[11]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
+# GPIO / gpio[10] / MIO[10]
+set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
+set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
+set_property slew "slow" [get_ports "MIO[10]"]
+set_property drive "8" [get_ports "MIO[10]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
+# GPIO / gpio[9] / MIO[9]
+set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
+set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
+set_property slew "slow" [get_ports "MIO[9]"]
+set_property drive "8" [get_ports "MIO[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
+# Quad SPI Flash / qspi_fbclk / MIO[8]
+set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
+set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
+set_property slew "slow" [get_ports "MIO[8]"]
+set_property drive "8" [get_ports "MIO[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
+# GPIO / gpio[7] / MIO[7]
+set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
+set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
+set_property slew "slow" [get_ports "MIO[7]"]
+set_property drive "8" [get_ports "MIO[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
+# Quad SPI Flash / qspi0_sclk / MIO[6]
+set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
+set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
+set_property slew "slow" [get_ports "MIO[6]"]
+set_property drive "8" [get_ports "MIO[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
+# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
+set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
+set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
+set_property slew "slow" [get_ports "MIO[5]"]
+set_property drive "8" [get_ports "MIO[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
+# Quad SPI Flash / qspi0_io[2] / MIO[4]
+set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
+set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
+set_property slew "slow" [get_ports "MIO[4]"]
+set_property drive "8" [get_ports "MIO[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
+# Quad SPI Flash / qspi0_io[1] / MIO[3]
+set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
+set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
+set_property slew "slow" [get_ports "MIO[3]"]
+set_property drive "8" [get_ports "MIO[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
+# Quad SPI Flash / qspi0_io[0] / MIO[2]
+set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
+set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
+set_property slew "slow" [get_ports "MIO[2]"]
+set_property drive "8" [get_ports "MIO[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
+# Quad SPI Flash / qspi0_ss_b / MIO[1]
+set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
+set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
+set_property slew "slow" [get_ports "MIO[1]"]
+set_property drive "8" [get_ports "MIO[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
+# GPIO / gpio[0] / MIO[0]
+set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
+set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
+set_property slew "slow" [get_ports "MIO[0]"]
+set_property drive "8" [get_ports "MIO[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
+set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
+set_property slew "FAST" [get_ports "DDR_VRP"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
+set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
+set_property slew "FAST" [get_ports "DDR_VRN"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
+set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
+set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
+set_property slew "SLOW" [get_ports "DDR_WEB"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
+set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
+set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
+set_property slew "SLOW" [get_ports "DDR_RAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
+set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
+set_property slew "SLOW" [get_ports "DDR_ODT"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
+set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
+set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
+set_property slew "FAST" [get_ports "DDR_DRSTB"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
+set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
+set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
+set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
+set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
+set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
+set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
+set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
+set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
+set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
+set_property slew "FAST" [get_ports "DDR_DQ[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
+set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
+set_property slew "FAST" [get_ports "DDR_DQ[8]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
+set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
+set_property slew "FAST" [get_ports "DDR_DQ[7]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
+set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
+set_property slew "FAST" [get_ports "DDR_DQ[6]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
+set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
+set_property slew "FAST" [get_ports "DDR_DQ[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
+set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
+set_property slew "FAST" [get_ports "DDR_DQ[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
+set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
+set_property slew "FAST" [get_ports "DDR_DQ[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
+set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
+set_property slew "FAST" [get_ports "DDR_DQ[31]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
+set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
+set_property slew "FAST" [get_ports "DDR_DQ[30]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
+set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
+set_property slew "FAST" [get_ports "DDR_DQ[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
+set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
+set_property slew "FAST" [get_ports "DDR_DQ[29]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
+set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
+set_property slew "FAST" [get_ports "DDR_DQ[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
+set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
+set_property slew "FAST" [get_ports "DDR_DQ[27]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
+set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
+set_property slew "FAST" [get_ports "DDR_DQ[26]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
+set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
+set_property slew "FAST" [get_ports "DDR_DQ[25]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
+set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
+set_property slew "FAST" [get_ports "DDR_DQ[24]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
+set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
+set_property slew "FAST" [get_ports "DDR_DQ[23]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
+set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
+set_property slew "FAST" [get_ports "DDR_DQ[22]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
+set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
+set_property slew "FAST" [get_ports "DDR_DQ[21]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
+set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
+set_property slew "FAST" [get_ports "DDR_DQ[20]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
+set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
+set_property slew "FAST" [get_ports "DDR_DQ[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
+set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
+set_property slew "FAST" [get_ports "DDR_DQ[19]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
+set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
+set_property slew "FAST" [get_ports "DDR_DQ[18]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
+set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
+set_property slew "FAST" [get_ports "DDR_DQ[17]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
+set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
+set_property slew "FAST" [get_ports "DDR_DQ[16]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
+set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
+set_property slew "FAST" [get_ports "DDR_DQ[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
+set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
+set_property slew "FAST" [get_ports "DDR_DQ[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
+set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
+set_property slew "FAST" [get_ports "DDR_DQ[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
+set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
+set_property slew "FAST" [get_ports "DDR_DQ[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
+set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
+set_property slew "FAST" [get_ports "DDR_DQ[11]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
+set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
+set_property slew "FAST" [get_ports "DDR_DQ[10]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
+set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
+set_property slew "FAST" [get_ports "DDR_DQ[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
+set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
+set_property slew "FAST" [get_ports "DDR_DM[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
+set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
+set_property slew "FAST" [get_ports "DDR_DM[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
+set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
+set_property slew "FAST" [get_ports "DDR_DM[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
+set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
+set_property slew "FAST" [get_ports "DDR_DM[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
+set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
+set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
+set_property slew "SLOW" [get_ports "DDR_CS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
+set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
+set_property slew "SLOW" [get_ports "DDR_CKE"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
+set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
+set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
+set_property slew "FAST" [get_ports "DDR_Clk"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
+set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
+set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
+set_property slew "FAST" [get_ports "DDR_Clk_n"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
+set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
+set_property slew "SLOW" [get_ports "DDR_CAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
+set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
+set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
+set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
+set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
+set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
+set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
+set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
+set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
+set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
+set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
+set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
+set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
+set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
+set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
+set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
+set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
+set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
+set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
+set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
+set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
+set_property slew "fast" [get_ports "PS_PORB"]
+set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
+set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
+set_property slew "fast" [get_ports "PS_SRSTB"]
+set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
+set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
+set_property slew "fast" [get_ports "PS_CLK"]
+
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xml b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xml
similarity index 93%
rename from pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xml
rename to pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xml
index 4c58ba9..e084df4 100644
--- a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_1/TopLevel_processing_system7_0_1.xml
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0.xml
@@ -2,7 +2,7 @@
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
- <spirit:name>TopLevel_processing_system7_0_1</spirit:name>
+ <spirit:name>TopLevel_processing_system7_0_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -4256,7 +4256,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -9120,7 +9120,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -10914,7 +10914,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_1_FCLK_CLK0</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">TopLevel_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -14390,6 +14390,166 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:modelName>processing_system7_v5_5_processing_system7</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:14 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:a1ab2663</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_synthesisconstraints</spirit:name>
+ <spirit:displayName>Synthesis Constraints</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:a1ab2663</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+ <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>TopLevel_processing_system7_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:14 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:a1ab2663</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:modelName>processing_system7_v1_0_processing_system7_vip</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_vip_1_1__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_vip_1_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:71ce9456</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_1</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:modelName>processing_system7</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_1_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:14 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:71ce9456</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>sim_type</spirit:name>
+ <spirit:value>tlm_dpi</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>sls_compatible</spirit:name>
+ <spirit:value>yes</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesimulationwrapper</spirit:name>
+ <spirit:displayName>Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:modelName>TopLevel_processing_system7_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:15 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:71ce9456</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_1</spirit:name>
+ <spirit:displayName>Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:modelName>TopLevel_processing_system7_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesimulationwrapper_1_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:06:16 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:71ce9456</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>sim_type</spirit:name>
+ <spirit:value>tlm_dpi</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_externalfiles</spirit:name>
+ <spirit:displayName>External Files</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Tue Oct 15 17:07:06 UTC 2019</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:a1ab2663</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CAN0_PHY_TX</spirit:name>
@@ -14398,7 +14558,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14417,7 +14578,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14439,7 +14601,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14458,7 +14621,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14484,7 +14648,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14507,7 +14672,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14526,7 +14692,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14545,7 +14712,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14564,7 +14732,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14583,7 +14752,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14602,7 +14772,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14621,7 +14792,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14640,7 +14812,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14659,7 +14832,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14678,7 +14852,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14697,7 +14872,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14716,7 +14892,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14735,7 +14912,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14754,7 +14932,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14777,7 +14956,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14796,7 +14976,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14818,7 +14999,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14840,7 +15022,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14859,7 +15042,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14881,7 +15065,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14903,7 +15088,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -14922,7 +15108,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14944,7 +15131,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14970,7 +15158,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -14996,7 +15185,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -15019,7 +15209,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -15038,7 +15229,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -15057,7 +15249,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -15076,7 +15269,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -15095,7 +15289,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15133,7 +15329,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15152,7 +15349,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15171,7 +15369,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15190,7 +15389,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15209,7 +15409,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15228,7 +15429,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15247,7 +15449,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15266,7 +15469,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15289,7 +15493,8 @@
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<spirit:typeName>reg</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15308,7 +15513,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15330,7 +15536,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15352,7 +15559,8 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15371,7 +15579,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15393,7 +15602,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15415,7 +15625,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15434,7 +15645,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15456,7 +15668,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15482,7 +15695,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -15508,7 +15722,8 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15534,7 +15749,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15557,7 +15773,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15576,7 +15793,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15598,7 +15816,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15617,7 +15836,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15636,7 +15856,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15658,7 +15879,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15677,7 +15899,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15696,7 +15919,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15718,7 +15942,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15737,7 +15962,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15756,7 +15982,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15778,7 +16005,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15797,7 +16025,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15816,7 +16045,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15838,7 +16068,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15860,7 +16091,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15882,7 +16114,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15901,7 +16134,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15920,7 +16154,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15961,7 +16197,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -15983,7 +16220,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16006,7 +16244,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16032,7 +16271,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16055,7 +16295,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16074,7 +16315,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16093,7 +16335,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16160,7 +16405,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16198,7 +16445,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16310,7 +16562,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16333,7 +16586,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16352,7 +16606,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16371,7 +16626,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16393,7 +16649,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16415,7 +16672,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16438,7 +16696,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16457,7 +16716,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16479,7 +16739,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16498,7 +16759,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16517,7 +16779,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16539,7 +16802,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16558,7 +16822,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16577,7 +16842,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16599,7 +16865,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16618,7 +16885,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16637,7 +16905,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16659,7 +16928,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16678,7 +16948,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16697,7 +16968,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16716,7 +16988,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16735,7 +17008,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16757,7 +17031,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16776,7 +17051,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16795,7 +17071,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16817,7 +17094,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16836,7 +17114,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16855,7 +17134,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16877,7 +17157,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16896,7 +17177,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16915,7 +17197,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16937,7 +17220,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16956,7 +17240,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -16975,7 +17260,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -16994,7 +17280,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17013,7 +17300,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17032,7 +17320,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17051,7 +17340,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17070,7 +17360,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17092,7 +17383,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17114,7 +17406,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17136,7 +17429,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17158,7 +17452,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17180,7 +17475,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17199,7 +17495,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17218,7 +17515,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17237,7 +17535,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17259,7 +17558,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17281,7 +17581,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17303,7 +17604,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17325,7 +17627,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17347,7 +17650,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17366,7 +17670,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17385,7 +17690,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17404,7 +17710,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17470,7 +17779,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17489,7 +17799,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17508,7 +17819,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17527,7 +17839,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17549,7 +17862,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17571,7 +17885,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17593,7 +17908,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17615,7 +17931,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17634,7 +17951,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17656,7 +17974,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17675,7 +17994,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17698,7 +18018,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17721,7 +18042,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17740,7 +18062,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17759,7 +18082,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17785,7 +18109,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17804,7 +18129,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17823,7 +18149,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17845,7 +18172,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17867,7 +18195,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17886,7 +18215,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17905,7 +18235,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -17924,7 +18255,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17943,7 +18275,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17962,7 +18295,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -17985,7 +18319,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18008,7 +18343,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18031,7 +18367,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18054,7 +18391,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18077,7 +18415,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18100,7 +18439,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18123,7 +18463,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18146,7 +18487,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18169,7 +18511,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18192,7 +18535,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18215,7 +18559,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18238,7 +18583,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18261,7 +18607,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18284,7 +18631,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18307,7 +18655,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18330,7 +18679,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18353,7 +18703,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18376,7 +18727,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18399,7 +18751,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18422,7 +18775,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18445,7 +18799,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18464,7 +18819,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18486,7 +18842,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18508,7 +18865,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18530,7 +18888,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18552,7 +18911,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18574,7 +18934,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18596,7 +18957,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18622,7 +18984,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18648,7 +19011,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -18700,7 +19065,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18726,7 +19092,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18748,7 +19115,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18767,7 +19135,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18786,7 +19155,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18805,7 +19175,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18824,7 +19195,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18843,7 +19215,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18866,7 +19239,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18889,7 +19263,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18912,7 +19287,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18935,7 +19311,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18958,7 +19335,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -18981,7 +19359,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19004,7 +19383,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19027,7 +19407,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19050,7 +19431,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19073,7 +19455,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19096,7 +19479,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19119,7 +19503,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19142,7 +19527,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19165,7 +19551,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19188,7 +19575,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19211,7 +19599,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19234,7 +19623,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19257,7 +19647,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19280,7 +19671,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19303,7 +19695,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19326,7 +19719,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19345,7 +19739,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19367,7 +19762,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19389,7 +19785,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19411,7 +19808,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19433,7 +19831,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19455,7 +19854,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19477,7 +19877,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19503,7 +19904,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19529,7 +19931,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19555,7 +19958,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19581,7 +19985,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19607,7 +20012,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -19629,7 +20035,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19648,7 +20055,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19667,7 +20075,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19686,7 +20095,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19705,7 +20115,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -19724,7 +20135,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19747,7 +20159,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19770,7 +20183,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19793,7 +20207,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19816,7 +20231,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19839,7 +20255,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19858,7 +20275,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19880,7 +20298,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19902,7 +20321,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19924,7 +20344,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19946,7 +20367,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19968,7 +20390,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -19990,7 +20413,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20016,7 +20440,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20042,7 +20467,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20068,7 +20494,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20094,7 +20521,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20120,7 +20548,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20146,7 +20575,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20172,7 +20602,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20198,7 +20629,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20224,7 +20656,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20250,7 +20683,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20276,7 +20710,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20302,7 +20737,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20328,7 +20764,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20354,7 +20791,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20380,7 +20818,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20406,7 +20845,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20432,7 +20872,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20458,7 +20899,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20484,7 +20926,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20510,7 +20953,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20536,7 +20980,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20558,7 +21003,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20577,7 +21023,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20596,7 +21043,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20615,7 +21063,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20634,7 +21083,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20653,7 +21103,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20676,7 +21127,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20699,7 +21151,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20722,7 +21175,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20745,7 +21199,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20768,7 +21223,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20787,7 +21243,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20809,7 +21266,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20831,7 +21289,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20853,7 +21312,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20875,7 +21335,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -20897,7 +21358,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20919,7 +21381,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20945,7 +21408,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20971,7 +21435,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -20997,7 +21462,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21023,7 +21489,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21049,7 +21516,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21075,7 +21543,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21101,7 +21570,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21127,7 +21597,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21153,7 +21624,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21179,7 +21651,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21205,7 +21678,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21231,7 +21705,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21257,7 +21732,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21283,7 +21759,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21309,7 +21786,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21335,7 +21813,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21361,7 +21840,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21387,7 +21867,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21413,7 +21894,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21439,7 +21921,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21465,7 +21948,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21487,7 +21971,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21506,7 +21991,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21525,7 +22011,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21544,7 +22031,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21563,7 +22051,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21582,7 +22071,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21605,7 +22095,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21628,7 +22119,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21651,7 +22143,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21674,7 +22167,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21697,7 +22191,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21716,7 +22211,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21738,7 +22234,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -21760,7 +22257,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21782,7 +22280,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21804,7 +22303,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21826,7 +22326,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21848,7 +22349,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21874,7 +22376,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21926,7 +22430,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21952,7 +22457,8 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -21978,7 +22484,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22004,7 +22511,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22030,7 +22538,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22056,7 +22565,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22082,7 +22592,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22108,7 +22619,8 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22134,7 +22646,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22160,7 +22673,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22186,7 +22700,8 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22212,7 +22727,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22238,7 +22754,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22264,7 +22781,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22290,7 +22808,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22316,7 +22835,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22342,7 +22862,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22368,7 +22889,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22394,7 +22916,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22420,7 +22943,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22446,7 +22970,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22468,7 +22993,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22487,7 +23013,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22506,7 +23033,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22525,7 +23053,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22544,7 +23073,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22563,7 +23093,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22586,7 +23117,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -22632,7 +23165,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22678,7 +23213,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22701,7 +23237,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22724,7 +23261,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22747,7 +23285,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22770,7 +23309,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22789,7 +23329,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22811,7 +23352,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22833,7 +23375,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22855,7 +23398,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22877,7 +23421,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22899,7 +23444,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22921,7 +23467,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22943,7 +23490,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22965,7 +23513,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -22991,7 +23540,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23017,7 +23567,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23043,7 +23594,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23069,7 +23621,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23095,7 +23648,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23121,7 +23675,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23147,7 +23702,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23173,7 +23729,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23199,7 +23756,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23225,7 +23783,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23251,7 +23810,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23277,7 +23837,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23303,7 +23864,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23329,7 +23891,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23355,7 +23918,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23381,7 +23945,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23407,7 +23972,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23433,7 +23999,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23459,7 +24026,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23485,7 +24053,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23511,7 +24080,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -23533,7 +24103,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23552,7 +24123,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23571,7 +24143,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23590,7 +24163,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23609,7 +24183,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23628,7 +24203,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23651,7 +24227,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23674,7 +24251,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23697,7 +24275,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23720,7 +24299,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23743,7 +24323,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23766,7 +24347,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23789,7 +24371,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23812,7 +24395,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23835,7 +24419,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -23854,7 +24439,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23876,7 +24462,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23898,7 +24485,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23920,7 +24508,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23942,7 +24531,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23964,7 +24554,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -23986,7 +24577,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24008,7 +24600,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24030,7 +24623,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24056,7 +24650,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24082,7 +24677,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24108,7 +24704,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24134,7 +24731,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24160,7 +24758,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24186,7 +24785,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24212,7 +24812,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24238,7 +24839,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24264,7 +24866,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24290,7 +24893,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24316,7 +24920,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24342,7 +24947,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24368,7 +24974,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24394,7 +25001,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24420,7 +25028,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24446,7 +25055,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24472,7 +25082,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24498,7 +25109,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24524,7 +25136,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24550,7 +25163,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24576,7 +25190,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24598,7 +25213,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24617,7 +25233,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24636,7 +25253,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24655,7 +25273,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24674,7 +25293,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24693,7 +25313,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24716,7 +25337,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24739,7 +25361,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24762,7 +25385,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24785,7 +25409,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24808,7 +25433,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24831,7 +25457,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24854,7 +25481,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24877,7 +25505,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24900,7 +25529,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -24919,7 +25549,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24941,7 +25572,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24963,7 +25595,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -24985,7 +25618,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25007,7 +25641,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25029,7 +25664,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25051,7 +25687,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25073,7 +25710,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25095,7 +25733,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25121,7 +25760,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25147,7 +25787,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25173,7 +25814,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25199,7 +25841,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25225,7 +25868,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25251,7 +25895,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -25277,7 +25922,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -25303,7 +25949,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -25329,7 +25976,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25355,7 +26003,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25381,7 +26030,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25407,7 +26057,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25433,7 +26084,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25459,7 +26111,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25485,7 +26138,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25511,7 +26165,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25537,7 +26192,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25563,7 +26219,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25589,7 +26246,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25615,7 +26273,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25641,7 +26300,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -25663,7 +26323,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25682,7 +26343,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25701,7 +26363,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25720,7 +26383,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25739,7 +26403,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25758,7 +26423,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25781,7 +26447,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25804,7 +26471,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:wire>
@@ -25827,7 +26495,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25850,7 +26519,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25873,7 +26543,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25896,7 +26567,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25919,7 +26591,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25942,7 +26615,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25965,7 +26639,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -25984,7 +26659,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26006,7 +26682,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26028,7 +26705,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26050,7 +26728,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26072,7 +26751,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26094,7 +26774,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26116,7 +26797,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26138,7 +26820,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -26160,7 +26843,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26186,7 +26870,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26212,7 +26897,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26238,7 +26924,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26264,7 +26951,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26290,7 +26978,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26316,7 +27005,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26342,7 +27032,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26368,7 +27059,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26394,7 +27086,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26420,7 +27113,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26446,7 +27140,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26472,7 +27167,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26498,7 +27194,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26524,7 +27221,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26550,7 +27248,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26576,7 +27275,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26602,7 +27302,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26628,7 +27329,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26654,7 +27356,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -26680,7 +27383,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -26706,7 +27410,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26728,7 +27433,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26747,7 +27453,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -26766,7 +27473,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26785,7 +27493,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -26804,7 +27513,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -26823,7 +27533,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26842,7 +27553,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26861,7 +27573,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26880,7 +27593,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26899,7 +27613,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26918,7 +27633,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26937,7 +27653,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26956,7 +27673,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26975,7 +27693,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -26994,7 +27713,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27013,7 +27733,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27032,7 +27753,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27051,7 +27773,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27070,7 +27793,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27089,7 +27813,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27108,7 +27833,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27127,7 +27853,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27146,7 +27873,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27165,7 +27893,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27184,7 +27913,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27203,7 +27933,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27222,7 +27953,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27241,7 +27973,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27260,7 +27993,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27283,7 +28017,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -27305,7 +28040,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27327,7 +28063,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27349,7 +28086,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27371,7 +28109,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27397,7 +28136,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27416,7 +28156,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27435,7 +28176,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27458,7 +28200,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27477,7 +28220,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27496,7 +28240,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27519,7 +28264,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27538,7 +28284,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27557,7 +28304,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27580,7 +28328,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -27599,7 +28348,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27618,7 +28368,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27637,7 +28388,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27659,7 +28411,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27681,7 +28434,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27703,7 +28457,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27725,7 +28480,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27747,7 +28503,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27769,7 +28526,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27791,7 +28549,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27813,7 +28572,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27835,7 +28595,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27857,7 +28618,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27879,7 +28641,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27901,7 +28664,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27923,7 +28687,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27945,7 +28710,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27967,7 +28733,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -27993,7 +28760,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28019,7 +28787,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28045,7 +28814,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28071,7 +28841,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28093,7 +28864,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28112,7 +28884,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28131,7 +28904,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28150,7 +28924,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28169,7 +28944,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28191,7 +28967,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28213,7 +28990,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28235,7 +29013,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28257,7 +29036,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28276,7 +29056,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28295,7 +29076,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28314,7 +29096,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28337,7 +29120,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28359,7 +29143,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28381,7 +29166,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28407,7 +29193,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28429,7 +29216,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28451,7 +29239,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28470,7 +29259,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28492,7 +29282,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28511,7 +29302,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28533,7 +29325,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28552,7 +29345,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28574,7 +29368,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28597,7 +29392,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28619,7 +29415,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28641,7 +29438,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -28660,7 +29458,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28682,7 +29481,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28701,7 +29501,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28723,7 +29524,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28742,7 +29544,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28764,7 +29567,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28787,7 +29591,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28806,7 +29611,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28828,7 +29634,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28851,7 +29658,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28874,7 +29682,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28893,7 +29702,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28919,7 +29729,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28945,7 +29756,8 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28957,7 +29769,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28976,7 +29789,8 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -28995,7 +29809,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -29014,7 +29829,8 @@
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29071,7 +29889,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29090,7 +29909,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29109,7 +29929,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29132,7 +29953,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29155,7 +29977,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29174,7 +29997,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29193,7 +30017,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29216,7 +30041,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29239,7 +30065,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29262,7 +30089,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29285,7 +30113,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29304,7 +30133,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29316,7 +30146,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29328,7 +30159,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -30716,6 +31548,270 @@
<spirit:enumeration>Share reset pin</spirit:enumeration>
</spirit:choice>
</spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:define>
+ <spirit:name>processing_order</spirit:name>
+ <spirit:value>early</spirit:value>
+ </spirit:define>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/verilog/TopLevel_processing_system7_0_0.hwdef</spirit:name>
+ <spirit:userFileType>hwdef</spirit:userFileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init.h</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init_gpl.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init_gpl.h</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>ps7_init.html</spirit:name>
+ <spirit:userFileType>html</spirit:userFileType>
+ <spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/verilog/processing_system7_v5_5_processing_system7.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>synth/TopLevel_processing_system7_0_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_infrastructure_v1_1_0</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="5a88adbb">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_vip_1_1__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/d4a8/hdl/axi_vip_v1_1_vl_rfs.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>axi_vip_v1_1_5</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_vip" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="a17fc184">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_vip_1_0__ref_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_local_params.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_vl_rfs.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_reg_params.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_reg_init.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_apis.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_unused_ports.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_gp.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_acp.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_hp.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>processing_system7_vip_v1_0_7</spirit:logicalName>
+ </spirit:file>
+ <spirit:vendorExtensions>
+ <xilinx:subCoreRef>
+ <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="processing_system7_vip" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="92e86c69">
+ <xilinx:mode xilinx:name="copy_mode"/>
+ </xilinx:componentRef>
+ </xilinx:subCoreRef>
+ </spirit:vendorExtensions>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_1_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>sim/libps7.so</spirit:name>
+ <spirit:fileType>swObjectLibrary</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>sim/libps7.dll</spirit:name>
+ <spirit:fileType>swObjectLibrary</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>sim/libremoteport.so</spirit:name>
+ <spirit:fileType>swObjectLibrary</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>sim/libremoteport.dll</spirit:name>
+ <spirit:fileType>swObjectLibrary</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>sim/TopLevel_processing_system7_0_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_1_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>sim/TopLevel_processing_system7_0_0.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>TopLevel_processing_system7_0_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
<spirit:cpus>
<spirit:cpu>
<spirit:name>CPU0_A9</spirit:name>
@@ -31769,7 +32865,7 @@
<spirit:parameter>
<spirit:name>PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ</spirit:name>
<spirit:displayName>PCW TTC0 CLK0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" spirit:order="25200" spirit:minimum="0.100000" spirit:maximum="200.000000">111.111115</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" spirit:order="25200" spirit:minimum="0.100000" spirit:maximum="200.000000">133.333333</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -31781,7 +32877,7 @@
<spirit:parameter>
<spirit:name>PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ</spirit:name>
<spirit:displayName>PCW TTC0 CLK1 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" spirit:order="25300" spirit:minimum="0.100000" spirit:maximum="200.000000">111.111115</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" spirit:order="25300" spirit:minimum="0.100000" spirit:maximum="200.000000">133.333333</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -31793,7 +32889,7 @@
<spirit:parameter>
<spirit:name>PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ</spirit:name>
<spirit:displayName>PCW TTC0 CLK2 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" spirit:order="25400" spirit:minimum="0.100000" spirit:maximum="200.000000">111.111115</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" spirit:order="25400" spirit:minimum="0.100000" spirit:maximum="200.000000">133.333333</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -37682,7 +38778,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">TopLevel_processing_system7_0_1</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">TopLevel_processing_system7_0_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
@@ -38171,7 +39267,6 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_IO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE" xilinx:valueSource="user"/>
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.v
new file mode 100644
index 0000000..0ba8e10
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.v
@@ -0,0 +1,5209 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Tue Oct 15 10:07:06 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode funcsim
+// /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.v
+// Design : TopLevel_processing_system7_0_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "TopLevel_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.1" *)
+(* NotValidForBitStream *)
+module TopLevel_processing_system7_0_0
+ (TTC0_WAVE0_OUT,
+ TTC0_WAVE1_OUT,
+ TTC0_WAVE2_OUT,
+ USB0_PORT_INDCTL,
+ USB0_VBUS_PWRSELECT,
+ USB0_VBUS_PWRFAULT,
+ M_AXI_GP0_ARVALID,
+ M_AXI_GP0_AWVALID,
+ M_AXI_GP0_BREADY,
+ M_AXI_GP0_RREADY,
+ M_AXI_GP0_WLAST,
+ M_AXI_GP0_WVALID,
+ M_AXI_GP0_ARID,
+ M_AXI_GP0_AWID,
+ M_AXI_GP0_WID,
+ M_AXI_GP0_ARBURST,
+ M_AXI_GP0_ARLOCK,
+ M_AXI_GP0_ARSIZE,
+ M_AXI_GP0_AWBURST,
+ M_AXI_GP0_AWLOCK,
+ M_AXI_GP0_AWSIZE,
+ M_AXI_GP0_ARPROT,
+ M_AXI_GP0_AWPROT,
+ M_AXI_GP0_ARADDR,
+ M_AXI_GP0_AWADDR,
+ M_AXI_GP0_WDATA,
+ M_AXI_GP0_ARCACHE,
+ M_AXI_GP0_ARLEN,
+ M_AXI_GP0_ARQOS,
+ M_AXI_GP0_AWCACHE,
+ M_AXI_GP0_AWLEN,
+ M_AXI_GP0_AWQOS,
+ M_AXI_GP0_WSTRB,
+ M_AXI_GP0_ACLK,
+ M_AXI_GP0_ARREADY,
+ M_AXI_GP0_AWREADY,
+ M_AXI_GP0_BVALID,
+ M_AXI_GP0_RLAST,
+ M_AXI_GP0_RVALID,
+ M_AXI_GP0_WREADY,
+ M_AXI_GP0_BID,
+ M_AXI_GP0_RID,
+ M_AXI_GP0_BRESP,
+ M_AXI_GP0_RRESP,
+ M_AXI_GP0_RDATA,
+ IRQ_F2P,
+ FCLK_CLK0,
+ FCLK_RESET0_N,
+ MIO,
+ DDR_CAS_n,
+ DDR_CKE,
+ DDR_Clk_n,
+ DDR_Clk,
+ DDR_CS_n,
+ DDR_DRSTB,
+ DDR_ODT,
+ DDR_RAS_n,
+ DDR_WEB,
+ DDR_BankAddr,
+ DDR_Addr,
+ DDR_VRN,
+ DDR_VRP,
+ DDR_DM,
+ DDR_DQ,
+ DDR_DQS_n,
+ DDR_DQS,
+ PS_SRSTB,
+ PS_CLK,
+ PS_PORB);
+ output TTC0_WAVE0_OUT;
+ output TTC0_WAVE1_OUT;
+ output TTC0_WAVE2_OUT;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input M_AXI_GP0_ACLK;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
+ (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
+
+ wire [14:0]DDR_Addr;
+ wire [2:0]DDR_BankAddr;
+ wire DDR_CAS_n;
+ wire DDR_CKE;
+ wire DDR_CS_n;
+ wire DDR_Clk;
+ wire DDR_Clk_n;
+ wire [3:0]DDR_DM;
+ wire [31:0]DDR_DQ;
+ wire [3:0]DDR_DQS;
+ wire [3:0]DDR_DQS_n;
+ wire DDR_DRSTB;
+ wire DDR_ODT;
+ wire DDR_RAS_n;
+ wire DDR_VRN;
+ wire DDR_VRP;
+ wire DDR_WEB;
+ wire FCLK_CLK0;
+ wire FCLK_RESET0_N;
+ wire [0:0]IRQ_F2P;
+ wire [53:0]MIO;
+ wire M_AXI_GP0_ACLK;
+ wire [31:0]M_AXI_GP0_ARADDR;
+ wire [1:0]M_AXI_GP0_ARBURST;
+ wire [3:0]M_AXI_GP0_ARCACHE;
+ wire [11:0]M_AXI_GP0_ARID;
+ wire [3:0]M_AXI_GP0_ARLEN;
+ wire [1:0]M_AXI_GP0_ARLOCK;
+ wire [2:0]M_AXI_GP0_ARPROT;
+ wire [3:0]M_AXI_GP0_ARQOS;
+ wire M_AXI_GP0_ARREADY;
+ wire [2:0]M_AXI_GP0_ARSIZE;
+ wire M_AXI_GP0_ARVALID;
+ wire [31:0]M_AXI_GP0_AWADDR;
+ wire [1:0]M_AXI_GP0_AWBURST;
+ wire [3:0]M_AXI_GP0_AWCACHE;
+ wire [11:0]M_AXI_GP0_AWID;
+ wire [3:0]M_AXI_GP0_AWLEN;
+ wire [1:0]M_AXI_GP0_AWLOCK;
+ wire [2:0]M_AXI_GP0_AWPROT;
+ wire [3:0]M_AXI_GP0_AWQOS;
+ wire M_AXI_GP0_AWREADY;
+ wire [2:0]M_AXI_GP0_AWSIZE;
+ wire M_AXI_GP0_AWVALID;
+ wire [11:0]M_AXI_GP0_BID;
+ wire M_AXI_GP0_BREADY;
+ wire [1:0]M_AXI_GP0_BRESP;
+ wire M_AXI_GP0_BVALID;
+ wire [31:0]M_AXI_GP0_RDATA;
+ wire [11:0]M_AXI_GP0_RID;
+ wire M_AXI_GP0_RLAST;
+ wire M_AXI_GP0_RREADY;
+ wire [1:0]M_AXI_GP0_RRESP;
+ wire M_AXI_GP0_RVALID;
+ wire [31:0]M_AXI_GP0_WDATA;
+ wire [11:0]M_AXI_GP0_WID;
+ wire M_AXI_GP0_WLAST;
+ wire M_AXI_GP0_WREADY;
+ wire [3:0]M_AXI_GP0_WSTRB;
+ wire M_AXI_GP0_WVALID;
+ wire PS_CLK;
+ wire PS_PORB;
+ wire PS_SRSTB;
+ wire TTC0_WAVE0_OUT;
+ wire TTC0_WAVE1_OUT;
+ wire TTC0_WAVE2_OUT;
+ wire [1:0]USB0_PORT_INDCTL;
+ wire USB0_VBUS_PWRFAULT;
+ wire USB0_VBUS_PWRSELECT;
+ wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+ wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+ wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+ wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+ wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+ wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+ wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+ wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+ wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+ wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+ wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+ wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+ wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+ wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+ wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+ wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+ wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+ wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+ wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+ wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+ wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+ wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+ wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+ wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+ wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+ wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+ wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+ wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+ wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+ wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+ wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+ wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+ wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+ wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+ wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+ wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+ wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+ wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+ wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+ wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+ wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+ wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+ wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+ wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+ wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+ wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
+ wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
+ wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
+ wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
+ wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+ wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+ wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+ wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+ wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+ wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+ wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+ wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+ wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+ wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+ wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+ wire NLW_inst_SDIO0_LED_UNCONNECTED;
+ wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+ wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+ wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+ wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+ wire NLW_inst_SDIO1_LED_UNCONNECTED;
+ wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+ wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+ wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+ wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+ wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+ wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+ wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+ wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+ wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+ wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+ wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+ wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+ wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+ wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+ wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+ wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+ wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+ wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+ wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+ wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+ wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+ wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+ wire NLW_inst_TRACE_CTL_UNCONNECTED;
+ wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+ wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+ wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+ wire NLW_inst_UART0_DTRN_UNCONNECTED;
+ wire NLW_inst_UART0_RTSN_UNCONNECTED;
+ wire NLW_inst_UART0_TX_UNCONNECTED;
+ wire NLW_inst_UART1_DTRN_UNCONNECTED;
+ wire NLW_inst_UART1_RTSN_UNCONNECTED;
+ wire NLW_inst_UART1_TX_UNCONNECTED;
+ wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+ wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+ wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+ wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+ wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+ wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+ wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+ wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+ wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+ wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+ wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+ wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+ wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+ wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+ wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+ wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+ wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+ wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+ wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+ wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+ wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+ wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+ wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+ wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+ wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+ wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+ wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+ wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+ wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+ wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+ wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+ wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+ wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+ wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+ wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+ wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+ wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+ wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+ wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+ wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+ wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+ wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+ wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+ wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+ wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+ wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+ wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+
+ (* C_DM_WIDTH = "4" *)
+ (* C_DQS_WIDTH = "4" *)
+ (* C_DQ_WIDTH = "32" *)
+ (* C_EMIO_GPIO_WIDTH = "64" *)
+ (* C_EN_EMIO_ENET0 = "0" *)
+ (* C_EN_EMIO_ENET1 = "0" *)
+ (* C_EN_EMIO_PJTAG = "0" *)
+ (* C_EN_EMIO_TRACE = "0" *)
+ (* C_FCLK_CLK0_BUF = "TRUE" *)
+ (* C_FCLK_CLK1_BUF = "FALSE" *)
+ (* C_FCLK_CLK2_BUF = "FALSE" *)
+ (* C_FCLK_CLK3_BUF = "FALSE" *)
+ (* C_GP0_EN_MODIFIABLE_TXN = "1" *)
+ (* C_GP1_EN_MODIFIABLE_TXN = "1" *)
+ (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
+ (* C_INCLUDE_TRACE_BUFFER = "0" *)
+ (* C_IRQ_F2P_MODE = "DIRECT" *)
+ (* C_MIO_PRIMITIVE = "54" *)
+ (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
+ (* C_M_AXI_GP0_ID_WIDTH = "12" *)
+ (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
+ (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
+ (* C_M_AXI_GP1_ID_WIDTH = "12" *)
+ (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
+ (* C_NUM_F2P_INTR_INPUTS = "1" *)
+ (* C_PACKAGE_NAME = "clg400" *)
+ (* C_PS7_SI_REV = "PRODUCTION" *)
+ (* C_S_AXI_ACP_ARUSER_VAL = "31" *)
+ (* C_S_AXI_ACP_AWUSER_VAL = "31" *)
+ (* C_S_AXI_ACP_ID_WIDTH = "3" *)
+ (* C_S_AXI_GP0_ID_WIDTH = "6" *)
+ (* C_S_AXI_GP1_ID_WIDTH = "6" *)
+ (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
+ (* C_S_AXI_HP0_ID_WIDTH = "6" *)
+ (* C_S_AXI_HP1_DATA_WIDTH = "64" *)
+ (* C_S_AXI_HP1_ID_WIDTH = "6" *)
+ (* C_S_AXI_HP2_DATA_WIDTH = "64" *)
+ (* C_S_AXI_HP2_ID_WIDTH = "6" *)
+ (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
+ (* C_S_AXI_HP3_ID_WIDTH = "6" *)
+ (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
+ (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
+ (* C_TRACE_INTERNAL_WIDTH = "2" *)
+ (* C_TRACE_PIPELINE_WIDTH = "8" *)
+ (* C_USE_AXI_NONSECURE = "0" *)
+ (* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
+ (* C_USE_M_AXI_GP0 = "1" *)
+ (* C_USE_M_AXI_GP1 = "0" *)
+ (* C_USE_S_AXI_ACP = "0" *)
+ (* C_USE_S_AXI_GP0 = "0" *)
+ (* C_USE_S_AXI_GP1 = "0" *)
+ (* C_USE_S_AXI_HP0 = "0" *)
+ (* C_USE_S_AXI_HP1 = "0" *)
+ (* C_USE_S_AXI_HP2 = "0" *)
+ (* C_USE_S_AXI_HP3 = "0" *)
+ (* HW_HANDOFF = "TopLevel_processing_system7_0_0.hwdef" *)
+ (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
+ (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
+ TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
+ (.CAN0_PHY_RX(1'b0),
+ .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+ .CAN1_PHY_RX(1'b0),
+ .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+ .Core0_nFIQ(1'b0),
+ .Core0_nIRQ(1'b0),
+ .Core1_nFIQ(1'b0),
+ .Core1_nIRQ(1'b0),
+ .DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
+ .DDR_Addr(DDR_Addr),
+ .DDR_BankAddr(DDR_BankAddr),
+ .DDR_CAS_n(DDR_CAS_n),
+ .DDR_CKE(DDR_CKE),
+ .DDR_CS_n(DDR_CS_n),
+ .DDR_Clk(DDR_Clk),
+ .DDR_Clk_n(DDR_Clk_n),
+ .DDR_DM(DDR_DM),
+ .DDR_DQ(DDR_DQ),
+ .DDR_DQS(DDR_DQS),
+ .DDR_DQS_n(DDR_DQS_n),
+ .DDR_DRSTB(DDR_DRSTB),
+ .DDR_ODT(DDR_ODT),
+ .DDR_RAS_n(DDR_RAS_n),
+ .DDR_VRN(DDR_VRN),
+ .DDR_VRP(DDR_VRP),
+ .DDR_WEB(DDR_WEB),
+ .DMA0_ACLK(1'b0),
+ .DMA0_DAREADY(1'b0),
+ .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+ .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+ .DMA0_DRLAST(1'b0),
+ .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+ .DMA0_DRTYPE({1'b0,1'b0}),
+ .DMA0_DRVALID(1'b0),
+ .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+ .DMA1_ACLK(1'b0),
+ .DMA1_DAREADY(1'b0),
+ .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+ .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+ .DMA1_DRLAST(1'b0),
+ .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+ .DMA1_DRTYPE({1'b0,1'b0}),
+ .DMA1_DRVALID(1'b0),
+ .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+ .DMA2_ACLK(1'b0),
+ .DMA2_DAREADY(1'b0),
+ .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+ .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+ .DMA2_DRLAST(1'b0),
+ .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+ .DMA2_DRTYPE({1'b0,1'b0}),
+ .DMA2_DRVALID(1'b0),
+ .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+ .DMA3_ACLK(1'b0),
+ .DMA3_DAREADY(1'b0),
+ .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+ .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+ .DMA3_DRLAST(1'b0),
+ .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+ .DMA3_DRTYPE({1'b0,1'b0}),
+ .DMA3_DRVALID(1'b0),
+ .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+ .ENET0_EXT_INTIN(1'b0),
+ .ENET0_GMII_COL(1'b0),
+ .ENET0_GMII_CRS(1'b0),
+ .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .ENET0_GMII_RX_CLK(1'b0),
+ .ENET0_GMII_RX_DV(1'b0),
+ .ENET0_GMII_RX_ER(1'b0),
+ .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+ .ENET0_GMII_TX_CLK(1'b0),
+ .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+ .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+ .ENET0_MDIO_I(1'b0),
+ .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+ .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+ .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+ .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+ .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+ .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+ .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+ .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+ .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+ .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+ .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+ .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+ .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+ .ENET1_EXT_INTIN(1'b0),
+ .ENET1_GMII_COL(1'b0),
+ .ENET1_GMII_CRS(1'b0),
+ .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .ENET1_GMII_RX_CLK(1'b0),
+ .ENET1_GMII_RX_DV(1'b0),
+ .ENET1_GMII_RX_ER(1'b0),
+ .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+ .ENET1_GMII_TX_CLK(1'b0),
+ .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+ .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+ .ENET1_MDIO_I(1'b0),
+ .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+ .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+ .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+ .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+ .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+ .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+ .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+ .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+ .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+ .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+ .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+ .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+ .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+ .EVENT_EVENTI(1'b0),
+ .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+ .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+ .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+ .FCLK_CLK0(FCLK_CLK0),
+ .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+ .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+ .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+ .FCLK_CLKTRIG0_N(1'b0),
+ .FCLK_CLKTRIG1_N(1'b0),
+ .FCLK_CLKTRIG2_N(1'b0),
+ .FCLK_CLKTRIG3_N(1'b0),
+ .FCLK_RESET0_N(FCLK_RESET0_N),
+ .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+ .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+ .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+ .FPGA_IDLE_N(1'b0),
+ .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
+ .FTMD_TRACEIN_CLK(1'b0),
+ .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .FTMD_TRACEIN_VALID(1'b0),
+ .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+ .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+ .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+ .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+ .FTMT_F2P_TRIG_0(1'b0),
+ .FTMT_F2P_TRIG_1(1'b0),
+ .FTMT_F2P_TRIG_2(1'b0),
+ .FTMT_F2P_TRIG_3(1'b0),
+ .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+ .FTMT_P2F_TRIGACK_0(1'b0),
+ .FTMT_P2F_TRIGACK_1(1'b0),
+ .FTMT_P2F_TRIGACK_2(1'b0),
+ .FTMT_P2F_TRIGACK_3(1'b0),
+ .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+ .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+ .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+ .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+ .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+ .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+ .I2C0_SCL_I(1'b0),
+ .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
+ .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
+ .I2C0_SDA_I(1'b0),
+ .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
+ .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
+ .I2C1_SCL_I(1'b0),
+ .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+ .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+ .I2C1_SDA_I(1'b0),
+ .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+ .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+ .IRQ_F2P(IRQ_F2P),
+ .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+ .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+ .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+ .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+ .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+ .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+ .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+ .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+ .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+ .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+ .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+ .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+ .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+ .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+ .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+ .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+ .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+ .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+ .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+ .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+ .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+ .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+ .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+ .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+ .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+ .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+ .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+ .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+ .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+ .MIO(MIO),
+ .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+ .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+ .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+ .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+ .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+ .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+ .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+ .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+ .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+ .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+ .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+ .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+ .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+ .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+ .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+ .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+ .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+ .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+ .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+ .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+ .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+ .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+ .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+ .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+ .M_AXI_GP0_BID(M_AXI_GP0_BID),
+ .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+ .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+ .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+ .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+ .M_AXI_GP0_RID(M_AXI_GP0_RID),
+ .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+ .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+ .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+ .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+ .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+ .M_AXI_GP0_WID(M_AXI_GP0_WID),
+ .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+ .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+ .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+ .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+ .M_AXI_GP1_ACLK(1'b0),
+ .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+ .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+ .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+ .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+ .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+ .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+ .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+ .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+ .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+ .M_AXI_GP1_ARREADY(1'b0),
+ .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+ .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+ .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+ .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+ .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+ .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+ .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+ .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+ .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+ .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+ .M_AXI_GP1_AWREADY(1'b0),
+ .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+ .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+ .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+ .M_AXI_GP1_BRESP({1'b0,1'b0}),
+ .M_AXI_GP1_BVALID(1'b0),
+ .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .M_AXI_GP1_RLAST(1'b0),
+ .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+ .M_AXI_GP1_RRESP({1'b0,1'b0}),
+ .M_AXI_GP1_RVALID(1'b0),
+ .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+ .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+ .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+ .M_AXI_GP1_WREADY(1'b0),
+ .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+ .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+ .PJTAG_TCK(1'b0),
+ .PJTAG_TDI(1'b0),
+ .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+ .PJTAG_TMS(1'b0),
+ .PS_CLK(PS_CLK),
+ .PS_PORB(PS_PORB),
+ .PS_SRSTB(PS_SRSTB),
+ .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+ .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+ .SDIO0_CDN(1'b0),
+ .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+ .SDIO0_CLK_FB(1'b0),
+ .SDIO0_CMD_I(1'b0),
+ .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+ .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+ .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
+ .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+ .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+ .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+ .SDIO0_WP(1'b0),
+ .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+ .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+ .SDIO1_CDN(1'b0),
+ .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+ .SDIO1_CLK_FB(1'b0),
+ .SDIO1_CMD_I(1'b0),
+ .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+ .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+ .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
+ .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+ .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+ .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+ .SDIO1_WP(1'b0),
+ .SPI0_MISO_I(1'b0),
+ .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+ .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+ .SPI0_MOSI_I(1'b0),
+ .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+ .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+ .SPI0_SCLK_I(1'b0),
+ .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+ .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+ .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+ .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+ .SPI0_SS_I(1'b0),
+ .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+ .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+ .SPI1_MISO_I(1'b0),
+ .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+ .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+ .SPI1_MOSI_I(1'b0),
+ .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+ .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+ .SPI1_SCLK_I(1'b0),
+ .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+ .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+ .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+ .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+ .SPI1_SS_I(1'b0),
+ .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+ .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+ .SRAM_INTIN(1'b0),
+ .S_AXI_ACP_ACLK(1'b0),
+ .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARBURST({1'b0,1'b0}),
+ .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+ .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARLOCK({1'b0,1'b0}),
+ .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+ .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_ARVALID(1'b0),
+ .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWBURST({1'b0,1'b0}),
+ .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWLOCK({1'b0,1'b0}),
+ .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+ .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_AWVALID(1'b0),
+ .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+ .S_AXI_ACP_BREADY(1'b0),
+ .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+ .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+ .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+ .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+ .S_AXI_ACP_RREADY(1'b0),
+ .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+ .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_WLAST(1'b0),
+ .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+ .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_ACP_WVALID(1'b0),
+ .S_AXI_GP0_ACLK(1'b0),
+ .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARBURST({1'b0,1'b0}),
+ .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+ .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARLOCK({1'b0,1'b0}),
+ .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+ .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_ARVALID(1'b0),
+ .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWBURST({1'b0,1'b0}),
+ .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWLOCK({1'b0,1'b0}),
+ .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+ .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_AWVALID(1'b0),
+ .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+ .S_AXI_GP0_BREADY(1'b0),
+ .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+ .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+ .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+ .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+ .S_AXI_GP0_RREADY(1'b0),
+ .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+ .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_WLAST(1'b0),
+ .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+ .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP0_WVALID(1'b0),
+ .S_AXI_GP1_ACLK(1'b0),
+ .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARBURST({1'b0,1'b0}),
+ .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+ .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARLOCK({1'b0,1'b0}),
+ .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+ .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_ARVALID(1'b0),
+ .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWBURST({1'b0,1'b0}),
+ .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWLOCK({1'b0,1'b0}),
+ .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+ .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_AWVALID(1'b0),
+ .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+ .S_AXI_GP1_BREADY(1'b0),
+ .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+ .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+ .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+ .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+ .S_AXI_GP1_RREADY(1'b0),
+ .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+ .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_WLAST(1'b0),
+ .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+ .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_GP1_WVALID(1'b0),
+ .S_AXI_HP0_ACLK(1'b0),
+ .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARBURST({1'b0,1'b0}),
+ .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+ .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARLOCK({1'b0,1'b0}),
+ .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+ .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_ARVALID(1'b0),
+ .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWBURST({1'b0,1'b0}),
+ .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWLOCK({1'b0,1'b0}),
+ .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+ .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_AWVALID(1'b0),
+ .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+ .S_AXI_HP0_BREADY(1'b0),
+ .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+ .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+ .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+ .S_AXI_HP0_RDISSUECAP1_EN(1'b0),
+ .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+ .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+ .S_AXI_HP0_RREADY(1'b0),
+ .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+ .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+ .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_WLAST(1'b0),
+ .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+ .S_AXI_HP0_WRISSUECAP1_EN(1'b0),
+ .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP0_WVALID(1'b0),
+ .S_AXI_HP1_ACLK(1'b0),
+ .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARBURST({1'b0,1'b0}),
+ .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+ .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARLOCK({1'b0,1'b0}),
+ .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+ .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_ARVALID(1'b0),
+ .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWBURST({1'b0,1'b0}),
+ .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWLOCK({1'b0,1'b0}),
+ .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+ .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_AWVALID(1'b0),
+ .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+ .S_AXI_HP1_BREADY(1'b0),
+ .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+ .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+ .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+ .S_AXI_HP1_RDISSUECAP1_EN(1'b0),
+ .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+ .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+ .S_AXI_HP1_RREADY(1'b0),
+ .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+ .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+ .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_WLAST(1'b0),
+ .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+ .S_AXI_HP1_WRISSUECAP1_EN(1'b0),
+ .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP1_WVALID(1'b0),
+ .S_AXI_HP2_ACLK(1'b0),
+ .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARBURST({1'b0,1'b0}),
+ .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+ .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARLOCK({1'b0,1'b0}),
+ .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+ .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_ARVALID(1'b0),
+ .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWBURST({1'b0,1'b0}),
+ .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWLOCK({1'b0,1'b0}),
+ .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+ .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_AWVALID(1'b0),
+ .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+ .S_AXI_HP2_BREADY(1'b0),
+ .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+ .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+ .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+ .S_AXI_HP2_RDISSUECAP1_EN(1'b0),
+ .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+ .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+ .S_AXI_HP2_RREADY(1'b0),
+ .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+ .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+ .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_WLAST(1'b0),
+ .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+ .S_AXI_HP2_WRISSUECAP1_EN(1'b0),
+ .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP2_WVALID(1'b0),
+ .S_AXI_HP3_ACLK(1'b0),
+ .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARBURST({1'b0,1'b0}),
+ .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+ .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARLOCK({1'b0,1'b0}),
+ .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+ .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_ARVALID(1'b0),
+ .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWBURST({1'b0,1'b0}),
+ .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWLOCK({1'b0,1'b0}),
+ .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+ .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_AWVALID(1'b0),
+ .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+ .S_AXI_HP3_BREADY(1'b0),
+ .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+ .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+ .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+ .S_AXI_HP3_RDISSUECAP1_EN(1'b0),
+ .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+ .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+ .S_AXI_HP3_RREADY(1'b0),
+ .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+ .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+ .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+ .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_WLAST(1'b0),
+ .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+ .S_AXI_HP3_WRISSUECAP1_EN(1'b0),
+ .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_HP3_WVALID(1'b0),
+ .TRACE_CLK(1'b0),
+ .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+ .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+ .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+ .TTC0_CLK0_IN(1'b0),
+ .TTC0_CLK1_IN(1'b0),
+ .TTC0_CLK2_IN(1'b0),
+ .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+ .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+ .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+ .TTC1_CLK0_IN(1'b0),
+ .TTC1_CLK1_IN(1'b0),
+ .TTC1_CLK2_IN(1'b0),
+ .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+ .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+ .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+ .UART0_CTSN(1'b0),
+ .UART0_DCDN(1'b0),
+ .UART0_DSRN(1'b0),
+ .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+ .UART0_RIN(1'b0),
+ .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+ .UART0_RX(1'b1),
+ .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
+ .UART1_CTSN(1'b0),
+ .UART1_DCDN(1'b0),
+ .UART1_DSRN(1'b0),
+ .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+ .UART1_RIN(1'b0),
+ .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+ .UART1_RX(1'b1),
+ .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+ .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+ .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+ .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+ .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+ .USB1_VBUS_PWRFAULT(1'b0),
+ .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+ .WDT_CLK_IN(1'b0),
+ .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
+(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
+(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
+(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
+(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
+(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
+(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
+(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
+(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
+(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
+(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
+(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
+(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
+(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
+(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
+(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
+(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "TopLevel_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
+(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
+module TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7
+ (CAN0_PHY_TX,
+ CAN0_PHY_RX,
+ CAN1_PHY_TX,
+ CAN1_PHY_RX,
+ ENET0_GMII_TX_EN,
+ ENET0_GMII_TX_ER,
+ ENET0_MDIO_MDC,
+ ENET0_MDIO_O,
+ ENET0_MDIO_T,
+ ENET0_PTP_DELAY_REQ_RX,
+ ENET0_PTP_DELAY_REQ_TX,
+ ENET0_PTP_PDELAY_REQ_RX,
+ ENET0_PTP_PDELAY_REQ_TX,
+ ENET0_PTP_PDELAY_RESP_RX,
+ ENET0_PTP_PDELAY_RESP_TX,
+ ENET0_PTP_SYNC_FRAME_RX,
+ ENET0_PTP_SYNC_FRAME_TX,
+ ENET0_SOF_RX,
+ ENET0_SOF_TX,
+ ENET0_GMII_TXD,
+ ENET0_GMII_COL,
+ ENET0_GMII_CRS,
+ ENET0_GMII_RX_CLK,
+ ENET0_GMII_RX_DV,
+ ENET0_GMII_RX_ER,
+ ENET0_GMII_TX_CLK,
+ ENET0_MDIO_I,
+ ENET0_EXT_INTIN,
+ ENET0_GMII_RXD,
+ ENET1_GMII_TX_EN,
+ ENET1_GMII_TX_ER,
+ ENET1_MDIO_MDC,
+ ENET1_MDIO_O,
+ ENET1_MDIO_T,
+ ENET1_PTP_DELAY_REQ_RX,
+ ENET1_PTP_DELAY_REQ_TX,
+ ENET1_PTP_PDELAY_REQ_RX,
+ ENET1_PTP_PDELAY_REQ_TX,
+ ENET1_PTP_PDELAY_RESP_RX,
+ ENET1_PTP_PDELAY_RESP_TX,
+ ENET1_PTP_SYNC_FRAME_RX,
+ ENET1_PTP_SYNC_FRAME_TX,
+ ENET1_SOF_RX,
+ ENET1_SOF_TX,
+ ENET1_GMII_TXD,
+ ENET1_GMII_COL,
+ ENET1_GMII_CRS,
+ ENET1_GMII_RX_CLK,
+ ENET1_GMII_RX_DV,
+ ENET1_GMII_RX_ER,
+ ENET1_GMII_TX_CLK,
+ ENET1_MDIO_I,
+ ENET1_EXT_INTIN,
+ ENET1_GMII_RXD,
+ GPIO_I,
+ GPIO_O,
+ GPIO_T,
+ I2C0_SDA_I,
+ I2C0_SDA_O,
+ I2C0_SDA_T,
+ I2C0_SCL_I,
+ I2C0_SCL_O,
+ I2C0_SCL_T,
+ I2C1_SDA_I,
+ I2C1_SDA_O,
+ I2C1_SDA_T,
+ I2C1_SCL_I,
+ I2C1_SCL_O,
+ I2C1_SCL_T,
+ PJTAG_TCK,
+ PJTAG_TMS,
+ PJTAG_TDI,
+ PJTAG_TDO,
+ SDIO0_CLK,
+ SDIO0_CLK_FB,
+ SDIO0_CMD_O,
+ SDIO0_CMD_I,
+ SDIO0_CMD_T,
+ SDIO0_DATA_I,
+ SDIO0_DATA_O,
+ SDIO0_DATA_T,
+ SDIO0_LED,
+ SDIO0_CDN,
+ SDIO0_WP,
+ SDIO0_BUSPOW,
+ SDIO0_BUSVOLT,
+ SDIO1_CLK,
+ SDIO1_CLK_FB,
+ SDIO1_CMD_O,
+ SDIO1_CMD_I,
+ SDIO1_CMD_T,
+ SDIO1_DATA_I,
+ SDIO1_DATA_O,
+ SDIO1_DATA_T,
+ SDIO1_LED,
+ SDIO1_CDN,
+ SDIO1_WP,
+ SDIO1_BUSPOW,
+ SDIO1_BUSVOLT,
+ SPI0_SCLK_I,
+ SPI0_SCLK_O,
+ SPI0_SCLK_T,
+ SPI0_MOSI_I,
+ SPI0_MOSI_O,
+ SPI0_MOSI_T,
+ SPI0_MISO_I,
+ SPI0_MISO_O,
+ SPI0_MISO_T,
+ SPI0_SS_I,
+ SPI0_SS_O,
+ SPI0_SS1_O,
+ SPI0_SS2_O,
+ SPI0_SS_T,
+ SPI1_SCLK_I,
+ SPI1_SCLK_O,
+ SPI1_SCLK_T,
+ SPI1_MOSI_I,
+ SPI1_MOSI_O,
+ SPI1_MOSI_T,
+ SPI1_MISO_I,
+ SPI1_MISO_O,
+ SPI1_MISO_T,
+ SPI1_SS_I,
+ SPI1_SS_O,
+ SPI1_SS1_O,
+ SPI1_SS2_O,
+ SPI1_SS_T,
+ UART0_DTRN,
+ UART0_RTSN,
+ UART0_TX,
+ UART0_CTSN,
+ UART0_DCDN,
+ UART0_DSRN,
+ UART0_RIN,
+ UART0_RX,
+ UART1_DTRN,
+ UART1_RTSN,
+ UART1_TX,
+ UART1_CTSN,
+ UART1_DCDN,
+ UART1_DSRN,
+ UART1_RIN,
+ UART1_RX,
+ TTC0_WAVE0_OUT,
+ TTC0_WAVE1_OUT,
+ TTC0_WAVE2_OUT,
+ TTC0_CLK0_IN,
+ TTC0_CLK1_IN,
+ TTC0_CLK2_IN,
+ TTC1_WAVE0_OUT,
+ TTC1_WAVE1_OUT,
+ TTC1_WAVE2_OUT,
+ TTC1_CLK0_IN,
+ TTC1_CLK1_IN,
+ TTC1_CLK2_IN,
+ WDT_CLK_IN,
+ WDT_RST_OUT,
+ TRACE_CLK,
+ TRACE_CTL,
+ TRACE_DATA,
+ TRACE_CLK_OUT,
+ USB0_PORT_INDCTL,
+ USB0_VBUS_PWRSELECT,
+ USB0_VBUS_PWRFAULT,
+ USB1_PORT_INDCTL,
+ USB1_VBUS_PWRSELECT,
+ USB1_VBUS_PWRFAULT,
+ SRAM_INTIN,
+ M_AXI_GP0_ARESETN,
+ M_AXI_GP0_ARVALID,
+ M_AXI_GP0_AWVALID,
+ M_AXI_GP0_BREADY,
+ M_AXI_GP0_RREADY,
+ M_AXI_GP0_WLAST,
+ M_AXI_GP0_WVALID,
+ M_AXI_GP0_ARID,
+ M_AXI_GP0_AWID,
+ M_AXI_GP0_WID,
+ M_AXI_GP0_ARBURST,
+ M_AXI_GP0_ARLOCK,
+ M_AXI_GP0_ARSIZE,
+ M_AXI_GP0_AWBURST,
+ M_AXI_GP0_AWLOCK,
+ M_AXI_GP0_AWSIZE,
+ M_AXI_GP0_ARPROT,
+ M_AXI_GP0_AWPROT,
+ M_AXI_GP0_ARADDR,
+ M_AXI_GP0_AWADDR,
+ M_AXI_GP0_WDATA,
+ M_AXI_GP0_ARCACHE,
+ M_AXI_GP0_ARLEN,
+ M_AXI_GP0_ARQOS,
+ M_AXI_GP0_AWCACHE,
+ M_AXI_GP0_AWLEN,
+ M_AXI_GP0_AWQOS,
+ M_AXI_GP0_WSTRB,
+ M_AXI_GP0_ACLK,
+ M_AXI_GP0_ARREADY,
+ M_AXI_GP0_AWREADY,
+ M_AXI_GP0_BVALID,
+ M_AXI_GP0_RLAST,
+ M_AXI_GP0_RVALID,
+ M_AXI_GP0_WREADY,
+ M_AXI_GP0_BID,
+ M_AXI_GP0_RID,
+ M_AXI_GP0_BRESP,
+ M_AXI_GP0_RRESP,
+ M_AXI_GP0_RDATA,
+ M_AXI_GP1_ARESETN,
+ M_AXI_GP1_ARVALID,
+ M_AXI_GP1_AWVALID,
+ M_AXI_GP1_BREADY,
+ M_AXI_GP1_RREADY,
+ M_AXI_GP1_WLAST,
+ M_AXI_GP1_WVALID,
+ M_AXI_GP1_ARID,
+ M_AXI_GP1_AWID,
+ M_AXI_GP1_WID,
+ M_AXI_GP1_ARBURST,
+ M_AXI_GP1_ARLOCK,
+ M_AXI_GP1_ARSIZE,
+ M_AXI_GP1_AWBURST,
+ M_AXI_GP1_AWLOCK,
+ M_AXI_GP1_AWSIZE,
+ M_AXI_GP1_ARPROT,
+ M_AXI_GP1_AWPROT,
+ M_AXI_GP1_ARADDR,
+ M_AXI_GP1_AWADDR,
+ M_AXI_GP1_WDATA,
+ M_AXI_GP1_ARCACHE,
+ M_AXI_GP1_ARLEN,
+ M_AXI_GP1_ARQOS,
+ M_AXI_GP1_AWCACHE,
+ M_AXI_GP1_AWLEN,
+ M_AXI_GP1_AWQOS,
+ M_AXI_GP1_WSTRB,
+ M_AXI_GP1_ACLK,
+ M_AXI_GP1_ARREADY,
+ M_AXI_GP1_AWREADY,
+ M_AXI_GP1_BVALID,
+ M_AXI_GP1_RLAST,
+ M_AXI_GP1_RVALID,
+ M_AXI_GP1_WREADY,
+ M_AXI_GP1_BID,
+ M_AXI_GP1_RID,
+ M_AXI_GP1_BRESP,
+ M_AXI_GP1_RRESP,
+ M_AXI_GP1_RDATA,
+ S_AXI_GP0_ARESETN,
+ S_AXI_GP0_ARREADY,
+ S_AXI_GP0_AWREADY,
+ S_AXI_GP0_BVALID,
+ S_AXI_GP0_RLAST,
+ S_AXI_GP0_RVALID,
+ S_AXI_GP0_WREADY,
+ S_AXI_GP0_BRESP,
+ S_AXI_GP0_RRESP,
+ S_AXI_GP0_RDATA,
+ S_AXI_GP0_BID,
+ S_AXI_GP0_RID,
+ S_AXI_GP0_ACLK,
+ S_AXI_GP0_ARVALID,
+ S_AXI_GP0_AWVALID,
+ S_AXI_GP0_BREADY,
+ S_AXI_GP0_RREADY,
+ S_AXI_GP0_WLAST,
+ S_AXI_GP0_WVALID,
+ S_AXI_GP0_ARBURST,
+ S_AXI_GP0_ARLOCK,
+ S_AXI_GP0_ARSIZE,
+ S_AXI_GP0_AWBURST,
+ S_AXI_GP0_AWLOCK,
+ S_AXI_GP0_AWSIZE,
+ S_AXI_GP0_ARPROT,
+ S_AXI_GP0_AWPROT,
+ S_AXI_GP0_ARADDR,
+ S_AXI_GP0_AWADDR,
+ S_AXI_GP0_WDATA,
+ S_AXI_GP0_ARCACHE,
+ S_AXI_GP0_ARLEN,
+ S_AXI_GP0_ARQOS,
+ S_AXI_GP0_AWCACHE,
+ S_AXI_GP0_AWLEN,
+ S_AXI_GP0_AWQOS,
+ S_AXI_GP0_WSTRB,
+ S_AXI_GP0_ARID,
+ S_AXI_GP0_AWID,
+ S_AXI_GP0_WID,
+ S_AXI_GP1_ARESETN,
+ S_AXI_GP1_ARREADY,
+ S_AXI_GP1_AWREADY,
+ S_AXI_GP1_BVALID,
+ S_AXI_GP1_RLAST,
+ S_AXI_GP1_RVALID,
+ S_AXI_GP1_WREADY,
+ S_AXI_GP1_BRESP,
+ S_AXI_GP1_RRESP,
+ S_AXI_GP1_RDATA,
+ S_AXI_GP1_BID,
+ S_AXI_GP1_RID,
+ S_AXI_GP1_ACLK,
+ S_AXI_GP1_ARVALID,
+ S_AXI_GP1_AWVALID,
+ S_AXI_GP1_BREADY,
+ S_AXI_GP1_RREADY,
+ S_AXI_GP1_WLAST,
+ S_AXI_GP1_WVALID,
+ S_AXI_GP1_ARBURST,
+ S_AXI_GP1_ARLOCK,
+ S_AXI_GP1_ARSIZE,
+ S_AXI_GP1_AWBURST,
+ S_AXI_GP1_AWLOCK,
+ S_AXI_GP1_AWSIZE,
+ S_AXI_GP1_ARPROT,
+ S_AXI_GP1_AWPROT,
+ S_AXI_GP1_ARADDR,
+ S_AXI_GP1_AWADDR,
+ S_AXI_GP1_WDATA,
+ S_AXI_GP1_ARCACHE,
+ S_AXI_GP1_ARLEN,
+ S_AXI_GP1_ARQOS,
+ S_AXI_GP1_AWCACHE,
+ S_AXI_GP1_AWLEN,
+ S_AXI_GP1_AWQOS,
+ S_AXI_GP1_WSTRB,
+ S_AXI_GP1_ARID,
+ S_AXI_GP1_AWID,
+ S_AXI_GP1_WID,
+ S_AXI_ACP_ARESETN,
+ S_AXI_ACP_ARREADY,
+ S_AXI_ACP_AWREADY,
+ S_AXI_ACP_BVALID,
+ S_AXI_ACP_RLAST,
+ S_AXI_ACP_RVALID,
+ S_AXI_ACP_WREADY,
+ S_AXI_ACP_BRESP,
+ S_AXI_ACP_RRESP,
+ S_AXI_ACP_BID,
+ S_AXI_ACP_RID,
+ S_AXI_ACP_RDATA,
+ S_AXI_ACP_ACLK,
+ S_AXI_ACP_ARVALID,
+ S_AXI_ACP_AWVALID,
+ S_AXI_ACP_BREADY,
+ S_AXI_ACP_RREADY,
+ S_AXI_ACP_WLAST,
+ S_AXI_ACP_WVALID,
+ S_AXI_ACP_ARID,
+ S_AXI_ACP_ARPROT,
+ S_AXI_ACP_AWID,
+ S_AXI_ACP_AWPROT,
+ S_AXI_ACP_WID,
+ S_AXI_ACP_ARADDR,
+ S_AXI_ACP_AWADDR,
+ S_AXI_ACP_ARCACHE,
+ S_AXI_ACP_ARLEN,
+ S_AXI_ACP_ARQOS,
+ S_AXI_ACP_AWCACHE,
+ S_AXI_ACP_AWLEN,
+ S_AXI_ACP_AWQOS,
+ S_AXI_ACP_ARBURST,
+ S_AXI_ACP_ARLOCK,
+ S_AXI_ACP_ARSIZE,
+ S_AXI_ACP_AWBURST,
+ S_AXI_ACP_AWLOCK,
+ S_AXI_ACP_AWSIZE,
+ S_AXI_ACP_ARUSER,
+ S_AXI_ACP_AWUSER,
+ S_AXI_ACP_WDATA,
+ S_AXI_ACP_WSTRB,
+ S_AXI_HP0_ARESETN,
+ S_AXI_HP0_ARREADY,
+ S_AXI_HP0_AWREADY,
+ S_AXI_HP0_BVALID,
+ S_AXI_HP0_RLAST,
+ S_AXI_HP0_RVALID,
+ S_AXI_HP0_WREADY,
+ S_AXI_HP0_BRESP,
+ S_AXI_HP0_RRESP,
+ S_AXI_HP0_BID,
+ S_AXI_HP0_RID,
+ S_AXI_HP0_RDATA,
+ S_AXI_HP0_RCOUNT,
+ S_AXI_HP0_WCOUNT,
+ S_AXI_HP0_RACOUNT,
+ S_AXI_HP0_WACOUNT,
+ S_AXI_HP0_ACLK,
+ S_AXI_HP0_ARVALID,
+ S_AXI_HP0_AWVALID,
+ S_AXI_HP0_BREADY,
+ S_AXI_HP0_RDISSUECAP1_EN,
+ S_AXI_HP0_RREADY,
+ S_AXI_HP0_WLAST,
+ S_AXI_HP0_WRISSUECAP1_EN,
+ S_AXI_HP0_WVALID,
+ S_AXI_HP0_ARBURST,
+ S_AXI_HP0_ARLOCK,
+ S_AXI_HP0_ARSIZE,
+ S_AXI_HP0_AWBURST,
+ S_AXI_HP0_AWLOCK,
+ S_AXI_HP0_AWSIZE,
+ S_AXI_HP0_ARPROT,
+ S_AXI_HP0_AWPROT,
+ S_AXI_HP0_ARADDR,
+ S_AXI_HP0_AWADDR,
+ S_AXI_HP0_ARCACHE,
+ S_AXI_HP0_ARLEN,
+ S_AXI_HP0_ARQOS,
+ S_AXI_HP0_AWCACHE,
+ S_AXI_HP0_AWLEN,
+ S_AXI_HP0_AWQOS,
+ S_AXI_HP0_ARID,
+ S_AXI_HP0_AWID,
+ S_AXI_HP0_WID,
+ S_AXI_HP0_WDATA,
+ S_AXI_HP0_WSTRB,
+ S_AXI_HP1_ARESETN,
+ S_AXI_HP1_ARREADY,
+ S_AXI_HP1_AWREADY,
+ S_AXI_HP1_BVALID,
+ S_AXI_HP1_RLAST,
+ S_AXI_HP1_RVALID,
+ S_AXI_HP1_WREADY,
+ S_AXI_HP1_BRESP,
+ S_AXI_HP1_RRESP,
+ S_AXI_HP1_BID,
+ S_AXI_HP1_RID,
+ S_AXI_HP1_RDATA,
+ S_AXI_HP1_RCOUNT,
+ S_AXI_HP1_WCOUNT,
+ S_AXI_HP1_RACOUNT,
+ S_AXI_HP1_WACOUNT,
+ S_AXI_HP1_ACLK,
+ S_AXI_HP1_ARVALID,
+ S_AXI_HP1_AWVALID,
+ S_AXI_HP1_BREADY,
+ S_AXI_HP1_RDISSUECAP1_EN,
+ S_AXI_HP1_RREADY,
+ S_AXI_HP1_WLAST,
+ S_AXI_HP1_WRISSUECAP1_EN,
+ S_AXI_HP1_WVALID,
+ S_AXI_HP1_ARBURST,
+ S_AXI_HP1_ARLOCK,
+ S_AXI_HP1_ARSIZE,
+ S_AXI_HP1_AWBURST,
+ S_AXI_HP1_AWLOCK,
+ S_AXI_HP1_AWSIZE,
+ S_AXI_HP1_ARPROT,
+ S_AXI_HP1_AWPROT,
+ S_AXI_HP1_ARADDR,
+ S_AXI_HP1_AWADDR,
+ S_AXI_HP1_ARCACHE,
+ S_AXI_HP1_ARLEN,
+ S_AXI_HP1_ARQOS,
+ S_AXI_HP1_AWCACHE,
+ S_AXI_HP1_AWLEN,
+ S_AXI_HP1_AWQOS,
+ S_AXI_HP1_ARID,
+ S_AXI_HP1_AWID,
+ S_AXI_HP1_WID,
+ S_AXI_HP1_WDATA,
+ S_AXI_HP1_WSTRB,
+ S_AXI_HP2_ARESETN,
+ S_AXI_HP2_ARREADY,
+ S_AXI_HP2_AWREADY,
+ S_AXI_HP2_BVALID,
+ S_AXI_HP2_RLAST,
+ S_AXI_HP2_RVALID,
+ S_AXI_HP2_WREADY,
+ S_AXI_HP2_BRESP,
+ S_AXI_HP2_RRESP,
+ S_AXI_HP2_BID,
+ S_AXI_HP2_RID,
+ S_AXI_HP2_RDATA,
+ S_AXI_HP2_RCOUNT,
+ S_AXI_HP2_WCOUNT,
+ S_AXI_HP2_RACOUNT,
+ S_AXI_HP2_WACOUNT,
+ S_AXI_HP2_ACLK,
+ S_AXI_HP2_ARVALID,
+ S_AXI_HP2_AWVALID,
+ S_AXI_HP2_BREADY,
+ S_AXI_HP2_RDISSUECAP1_EN,
+ S_AXI_HP2_RREADY,
+ S_AXI_HP2_WLAST,
+ S_AXI_HP2_WRISSUECAP1_EN,
+ S_AXI_HP2_WVALID,
+ S_AXI_HP2_ARBURST,
+ S_AXI_HP2_ARLOCK,
+ S_AXI_HP2_ARSIZE,
+ S_AXI_HP2_AWBURST,
+ S_AXI_HP2_AWLOCK,
+ S_AXI_HP2_AWSIZE,
+ S_AXI_HP2_ARPROT,
+ S_AXI_HP2_AWPROT,
+ S_AXI_HP2_ARADDR,
+ S_AXI_HP2_AWADDR,
+ S_AXI_HP2_ARCACHE,
+ S_AXI_HP2_ARLEN,
+ S_AXI_HP2_ARQOS,
+ S_AXI_HP2_AWCACHE,
+ S_AXI_HP2_AWLEN,
+ S_AXI_HP2_AWQOS,
+ S_AXI_HP2_ARID,
+ S_AXI_HP2_AWID,
+ S_AXI_HP2_WID,
+ S_AXI_HP2_WDATA,
+ S_AXI_HP2_WSTRB,
+ S_AXI_HP3_ARESETN,
+ S_AXI_HP3_ARREADY,
+ S_AXI_HP3_AWREADY,
+ S_AXI_HP3_BVALID,
+ S_AXI_HP3_RLAST,
+ S_AXI_HP3_RVALID,
+ S_AXI_HP3_WREADY,
+ S_AXI_HP3_BRESP,
+ S_AXI_HP3_RRESP,
+ S_AXI_HP3_BID,
+ S_AXI_HP3_RID,
+ S_AXI_HP3_RDATA,
+ S_AXI_HP3_RCOUNT,
+ S_AXI_HP3_WCOUNT,
+ S_AXI_HP3_RACOUNT,
+ S_AXI_HP3_WACOUNT,
+ S_AXI_HP3_ACLK,
+ S_AXI_HP3_ARVALID,
+ S_AXI_HP3_AWVALID,
+ S_AXI_HP3_BREADY,
+ S_AXI_HP3_RDISSUECAP1_EN,
+ S_AXI_HP3_RREADY,
+ S_AXI_HP3_WLAST,
+ S_AXI_HP3_WRISSUECAP1_EN,
+ S_AXI_HP3_WVALID,
+ S_AXI_HP3_ARBURST,
+ S_AXI_HP3_ARLOCK,
+ S_AXI_HP3_ARSIZE,
+ S_AXI_HP3_AWBURST,
+ S_AXI_HP3_AWLOCK,
+ S_AXI_HP3_AWSIZE,
+ S_AXI_HP3_ARPROT,
+ S_AXI_HP3_AWPROT,
+ S_AXI_HP3_ARADDR,
+ S_AXI_HP3_AWADDR,
+ S_AXI_HP3_ARCACHE,
+ S_AXI_HP3_ARLEN,
+ S_AXI_HP3_ARQOS,
+ S_AXI_HP3_AWCACHE,
+ S_AXI_HP3_AWLEN,
+ S_AXI_HP3_AWQOS,
+ S_AXI_HP3_ARID,
+ S_AXI_HP3_AWID,
+ S_AXI_HP3_WID,
+ S_AXI_HP3_WDATA,
+ S_AXI_HP3_WSTRB,
+ IRQ_P2F_DMAC_ABORT,
+ IRQ_P2F_DMAC0,
+ IRQ_P2F_DMAC1,
+ IRQ_P2F_DMAC2,
+ IRQ_P2F_DMAC3,
+ IRQ_P2F_DMAC4,
+ IRQ_P2F_DMAC5,
+ IRQ_P2F_DMAC6,
+ IRQ_P2F_DMAC7,
+ IRQ_P2F_SMC,
+ IRQ_P2F_QSPI,
+ IRQ_P2F_CTI,
+ IRQ_P2F_GPIO,
+ IRQ_P2F_USB0,
+ IRQ_P2F_ENET0,
+ IRQ_P2F_ENET_WAKE0,
+ IRQ_P2F_SDIO0,
+ IRQ_P2F_I2C0,
+ IRQ_P2F_SPI0,
+ IRQ_P2F_UART0,
+ IRQ_P2F_CAN0,
+ IRQ_P2F_USB1,
+ IRQ_P2F_ENET1,
+ IRQ_P2F_ENET_WAKE1,
+ IRQ_P2F_SDIO1,
+ IRQ_P2F_I2C1,
+ IRQ_P2F_SPI1,
+ IRQ_P2F_UART1,
+ IRQ_P2F_CAN1,
+ IRQ_F2P,
+ Core0_nFIQ,
+ Core0_nIRQ,
+ Core1_nFIQ,
+ Core1_nIRQ,
+ DMA0_DATYPE,
+ DMA0_DAVALID,
+ DMA0_DRREADY,
+ DMA0_RSTN,
+ DMA1_DATYPE,
+ DMA1_DAVALID,
+ DMA1_DRREADY,
+ DMA1_RSTN,
+ DMA2_DATYPE,
+ DMA2_DAVALID,
+ DMA2_DRREADY,
+ DMA2_RSTN,
+ DMA3_DATYPE,
+ DMA3_DAVALID,
+ DMA3_DRREADY,
+ DMA3_RSTN,
+ DMA0_ACLK,
+ DMA0_DAREADY,
+ DMA0_DRLAST,
+ DMA0_DRVALID,
+ DMA1_ACLK,
+ DMA1_DAREADY,
+ DMA1_DRLAST,
+ DMA1_DRVALID,
+ DMA2_ACLK,
+ DMA2_DAREADY,
+ DMA2_DRLAST,
+ DMA2_DRVALID,
+ DMA3_ACLK,
+ DMA3_DAREADY,
+ DMA3_DRLAST,
+ DMA3_DRVALID,
+ DMA0_DRTYPE,
+ DMA1_DRTYPE,
+ DMA2_DRTYPE,
+ DMA3_DRTYPE,
+ FCLK_CLK3,
+ FCLK_CLK2,
+ FCLK_CLK1,
+ FCLK_CLK0,
+ FCLK_CLKTRIG3_N,
+ FCLK_CLKTRIG2_N,
+ FCLK_CLKTRIG1_N,
+ FCLK_CLKTRIG0_N,
+ FCLK_RESET3_N,
+ FCLK_RESET2_N,
+ FCLK_RESET1_N,
+ FCLK_RESET0_N,
+ FTMD_TRACEIN_DATA,
+ FTMD_TRACEIN_VALID,
+ FTMD_TRACEIN_CLK,
+ FTMD_TRACEIN_ATID,
+ FTMT_F2P_TRIG_0,
+ FTMT_F2P_TRIGACK_0,
+ FTMT_F2P_TRIG_1,
+ FTMT_F2P_TRIGACK_1,
+ FTMT_F2P_TRIG_2,
+ FTMT_F2P_TRIGACK_2,
+ FTMT_F2P_TRIG_3,
+ FTMT_F2P_TRIGACK_3,
+ FTMT_F2P_DEBUG,
+ FTMT_P2F_TRIGACK_0,
+ FTMT_P2F_TRIG_0,
+ FTMT_P2F_TRIGACK_1,
+ FTMT_P2F_TRIG_1,
+ FTMT_P2F_TRIGACK_2,
+ FTMT_P2F_TRIG_2,
+ FTMT_P2F_TRIGACK_3,
+ FTMT_P2F_TRIG_3,
+ FTMT_P2F_DEBUG,
+ FPGA_IDLE_N,
+ EVENT_EVENTO,
+ EVENT_STANDBYWFE,
+ EVENT_STANDBYWFI,
+ EVENT_EVENTI,
+ DDR_ARB,
+ MIO,
+ DDR_CAS_n,
+ DDR_CKE,
+ DDR_Clk_n,
+ DDR_Clk,
+ DDR_CS_n,
+ DDR_DRSTB,
+ DDR_ODT,
+ DDR_RAS_n,
+ DDR_WEB,
+ DDR_BankAddr,
+ DDR_Addr,
+ DDR_VRN,
+ DDR_VRP,
+ DDR_DM,
+ DDR_DQ,
+ DDR_DQS_n,
+ DDR_DQS,
+ PS_SRSTB,
+ PS_CLK,
+ PS_PORB);
+ output CAN0_PHY_TX;
+ input CAN0_PHY_RX;
+ output CAN1_PHY_TX;
+ input CAN1_PHY_RX;
+ output ENET0_GMII_TX_EN;
+ output ENET0_GMII_TX_ER;
+ output ENET0_MDIO_MDC;
+ output ENET0_MDIO_O;
+ output ENET0_MDIO_T;
+ output ENET0_PTP_DELAY_REQ_RX;
+ output ENET0_PTP_DELAY_REQ_TX;
+ output ENET0_PTP_PDELAY_REQ_RX;
+ output ENET0_PTP_PDELAY_REQ_TX;
+ output ENET0_PTP_PDELAY_RESP_RX;
+ output ENET0_PTP_PDELAY_RESP_TX;
+ output ENET0_PTP_SYNC_FRAME_RX;
+ output ENET0_PTP_SYNC_FRAME_TX;
+ output ENET0_SOF_RX;
+ output ENET0_SOF_TX;
+ output [7:0]ENET0_GMII_TXD;
+ input ENET0_GMII_COL;
+ input ENET0_GMII_CRS;
+ input ENET0_GMII_RX_CLK;
+ input ENET0_GMII_RX_DV;
+ input ENET0_GMII_RX_ER;
+ input ENET0_GMII_TX_CLK;
+ input ENET0_MDIO_I;
+ input ENET0_EXT_INTIN;
+ input [7:0]ENET0_GMII_RXD;
+ output ENET1_GMII_TX_EN;
+ output ENET1_GMII_TX_ER;
+ output ENET1_MDIO_MDC;
+ output ENET1_MDIO_O;
+ output ENET1_MDIO_T;
+ output ENET1_PTP_DELAY_REQ_RX;
+ output ENET1_PTP_DELAY_REQ_TX;
+ output ENET1_PTP_PDELAY_REQ_RX;
+ output ENET1_PTP_PDELAY_REQ_TX;
+ output ENET1_PTP_PDELAY_RESP_RX;
+ output ENET1_PTP_PDELAY_RESP_TX;
+ output ENET1_PTP_SYNC_FRAME_RX;
+ output ENET1_PTP_SYNC_FRAME_TX;
+ output ENET1_SOF_RX;
+ output ENET1_SOF_TX;
+ output [7:0]ENET1_GMII_TXD;
+ input ENET1_GMII_COL;
+ input ENET1_GMII_CRS;
+ input ENET1_GMII_RX_CLK;
+ input ENET1_GMII_RX_DV;
+ input ENET1_GMII_RX_ER;
+ input ENET1_GMII_TX_CLK;
+ input ENET1_MDIO_I;
+ input ENET1_EXT_INTIN;
+ input [7:0]ENET1_GMII_RXD;
+ input [63:0]GPIO_I;
+ output [63:0]GPIO_O;
+ output [63:0]GPIO_T;
+ input I2C0_SDA_I;
+ output I2C0_SDA_O;
+ output I2C0_SDA_T;
+ input I2C0_SCL_I;
+ output I2C0_SCL_O;
+ output I2C0_SCL_T;
+ input I2C1_SDA_I;
+ output I2C1_SDA_O;
+ output I2C1_SDA_T;
+ input I2C1_SCL_I;
+ output I2C1_SCL_O;
+ output I2C1_SCL_T;
+ input PJTAG_TCK;
+ input PJTAG_TMS;
+ input PJTAG_TDI;
+ output PJTAG_TDO;
+ output SDIO0_CLK;
+ input SDIO0_CLK_FB;
+ output SDIO0_CMD_O;
+ input SDIO0_CMD_I;
+ output SDIO0_CMD_T;
+ input [3:0]SDIO0_DATA_I;
+ output [3:0]SDIO0_DATA_O;
+ output [3:0]SDIO0_DATA_T;
+ output SDIO0_LED;
+ input SDIO0_CDN;
+ input SDIO0_WP;
+ output SDIO0_BUSPOW;
+ output [2:0]SDIO0_BUSVOLT;
+ output SDIO1_CLK;
+ input SDIO1_CLK_FB;
+ output SDIO1_CMD_O;
+ input SDIO1_CMD_I;
+ output SDIO1_CMD_T;
+ input [3:0]SDIO1_DATA_I;
+ output [3:0]SDIO1_DATA_O;
+ output [3:0]SDIO1_DATA_T;
+ output SDIO1_LED;
+ input SDIO1_CDN;
+ input SDIO1_WP;
+ output SDIO1_BUSPOW;
+ output [2:0]SDIO1_BUSVOLT;
+ input SPI0_SCLK_I;
+ output SPI0_SCLK_O;
+ output SPI0_SCLK_T;
+ input SPI0_MOSI_I;
+ output SPI0_MOSI_O;
+ output SPI0_MOSI_T;
+ input SPI0_MISO_I;
+ output SPI0_MISO_O;
+ output SPI0_MISO_T;
+ input SPI0_SS_I;
+ output SPI0_SS_O;
+ output SPI0_SS1_O;
+ output SPI0_SS2_O;
+ output SPI0_SS_T;
+ input SPI1_SCLK_I;
+ output SPI1_SCLK_O;
+ output SPI1_SCLK_T;
+ input SPI1_MOSI_I;
+ output SPI1_MOSI_O;
+ output SPI1_MOSI_T;
+ input SPI1_MISO_I;
+ output SPI1_MISO_O;
+ output SPI1_MISO_T;
+ input SPI1_SS_I;
+ output SPI1_SS_O;
+ output SPI1_SS1_O;
+ output SPI1_SS2_O;
+ output SPI1_SS_T;
+ output UART0_DTRN;
+ output UART0_RTSN;
+ output UART0_TX;
+ input UART0_CTSN;
+ input UART0_DCDN;
+ input UART0_DSRN;
+ input UART0_RIN;
+ input UART0_RX;
+ output UART1_DTRN;
+ output UART1_RTSN;
+ output UART1_TX;
+ input UART1_CTSN;
+ input UART1_DCDN;
+ input UART1_DSRN;
+ input UART1_RIN;
+ input UART1_RX;
+ output TTC0_WAVE0_OUT;
+ output TTC0_WAVE1_OUT;
+ output TTC0_WAVE2_OUT;
+ input TTC0_CLK0_IN;
+ input TTC0_CLK1_IN;
+ input TTC0_CLK2_IN;
+ output TTC1_WAVE0_OUT;
+ output TTC1_WAVE1_OUT;
+ output TTC1_WAVE2_OUT;
+ input TTC1_CLK0_IN;
+ input TTC1_CLK1_IN;
+ input TTC1_CLK2_IN;
+ input WDT_CLK_IN;
+ output WDT_RST_OUT;
+ input TRACE_CLK;
+ output TRACE_CTL;
+ output [1:0]TRACE_DATA;
+ output TRACE_CLK_OUT;
+ output [1:0]USB0_PORT_INDCTL;
+ output USB0_VBUS_PWRSELECT;
+ input USB0_VBUS_PWRFAULT;
+ output [1:0]USB1_PORT_INDCTL;
+ output USB1_VBUS_PWRSELECT;
+ input USB1_VBUS_PWRFAULT;
+ input SRAM_INTIN;
+ output M_AXI_GP0_ARESETN;
+ output M_AXI_GP0_ARVALID;
+ output M_AXI_GP0_AWVALID;
+ output M_AXI_GP0_BREADY;
+ output M_AXI_GP0_RREADY;
+ output M_AXI_GP0_WLAST;
+ output M_AXI_GP0_WVALID;
+ output [11:0]M_AXI_GP0_ARID;
+ output [11:0]M_AXI_GP0_AWID;
+ output [11:0]M_AXI_GP0_WID;
+ output [1:0]M_AXI_GP0_ARBURST;
+ output [1:0]M_AXI_GP0_ARLOCK;
+ output [2:0]M_AXI_GP0_ARSIZE;
+ output [1:0]M_AXI_GP0_AWBURST;
+ output [1:0]M_AXI_GP0_AWLOCK;
+ output [2:0]M_AXI_GP0_AWSIZE;
+ output [2:0]M_AXI_GP0_ARPROT;
+ output [2:0]M_AXI_GP0_AWPROT;
+ output [31:0]M_AXI_GP0_ARADDR;
+ output [31:0]M_AXI_GP0_AWADDR;
+ output [31:0]M_AXI_GP0_WDATA;
+ output [3:0]M_AXI_GP0_ARCACHE;
+ output [3:0]M_AXI_GP0_ARLEN;
+ output [3:0]M_AXI_GP0_ARQOS;
+ output [3:0]M_AXI_GP0_AWCACHE;
+ output [3:0]M_AXI_GP0_AWLEN;
+ output [3:0]M_AXI_GP0_AWQOS;
+ output [3:0]M_AXI_GP0_WSTRB;
+ input M_AXI_GP0_ACLK;
+ input M_AXI_GP0_ARREADY;
+ input M_AXI_GP0_AWREADY;
+ input M_AXI_GP0_BVALID;
+ input M_AXI_GP0_RLAST;
+ input M_AXI_GP0_RVALID;
+ input M_AXI_GP0_WREADY;
+ input [11:0]M_AXI_GP0_BID;
+ input [11:0]M_AXI_GP0_RID;
+ input [1:0]M_AXI_GP0_BRESP;
+ input [1:0]M_AXI_GP0_RRESP;
+ input [31:0]M_AXI_GP0_RDATA;
+ output M_AXI_GP1_ARESETN;
+ output M_AXI_GP1_ARVALID;
+ output M_AXI_GP1_AWVALID;
+ output M_AXI_GP1_BREADY;
+ output M_AXI_GP1_RREADY;
+ output M_AXI_GP1_WLAST;
+ output M_AXI_GP1_WVALID;
+ output [11:0]M_AXI_GP1_ARID;
+ output [11:0]M_AXI_GP1_AWID;
+ output [11:0]M_AXI_GP1_WID;
+ output [1:0]M_AXI_GP1_ARBURST;
+ output [1:0]M_AXI_GP1_ARLOCK;
+ output [2:0]M_AXI_GP1_ARSIZE;
+ output [1:0]M_AXI_GP1_AWBURST;
+ output [1:0]M_AXI_GP1_AWLOCK;
+ output [2:0]M_AXI_GP1_AWSIZE;
+ output [2:0]M_AXI_GP1_ARPROT;
+ output [2:0]M_AXI_GP1_AWPROT;
+ output [31:0]M_AXI_GP1_ARADDR;
+ output [31:0]M_AXI_GP1_AWADDR;
+ output [31:0]M_AXI_GP1_WDATA;
+ output [3:0]M_AXI_GP1_ARCACHE;
+ output [3:0]M_AXI_GP1_ARLEN;
+ output [3:0]M_AXI_GP1_ARQOS;
+ output [3:0]M_AXI_GP1_AWCACHE;
+ output [3:0]M_AXI_GP1_AWLEN;
+ output [3:0]M_AXI_GP1_AWQOS;
+ output [3:0]M_AXI_GP1_WSTRB;
+ input M_AXI_GP1_ACLK;
+ input M_AXI_GP1_ARREADY;
+ input M_AXI_GP1_AWREADY;
+ input M_AXI_GP1_BVALID;
+ input M_AXI_GP1_RLAST;
+ input M_AXI_GP1_RVALID;
+ input M_AXI_GP1_WREADY;
+ input [11:0]M_AXI_GP1_BID;
+ input [11:0]M_AXI_GP1_RID;
+ input [1:0]M_AXI_GP1_BRESP;
+ input [1:0]M_AXI_GP1_RRESP;
+ input [31:0]M_AXI_GP1_RDATA;
+ output S_AXI_GP0_ARESETN;
+ output S_AXI_GP0_ARREADY;
+ output S_AXI_GP0_AWREADY;
+ output S_AXI_GP0_BVALID;
+ output S_AXI_GP0_RLAST;
+ output S_AXI_GP0_RVALID;
+ output S_AXI_GP0_WREADY;
+ output [1:0]S_AXI_GP0_BRESP;
+ output [1:0]S_AXI_GP0_RRESP;
+ output [31:0]S_AXI_GP0_RDATA;
+ output [5:0]S_AXI_GP0_BID;
+ output [5:0]S_AXI_GP0_RID;
+ input S_AXI_GP0_ACLK;
+ input S_AXI_GP0_ARVALID;
+ input S_AXI_GP0_AWVALID;
+ input S_AXI_GP0_BREADY;
+ input S_AXI_GP0_RREADY;
+ input S_AXI_GP0_WLAST;
+ input S_AXI_GP0_WVALID;
+ input [1:0]S_AXI_GP0_ARBURST;
+ input [1:0]S_AXI_GP0_ARLOCK;
+ input [2:0]S_AXI_GP0_ARSIZE;
+ input [1:0]S_AXI_GP0_AWBURST;
+ input [1:0]S_AXI_GP0_AWLOCK;
+ input [2:0]S_AXI_GP0_AWSIZE;
+ input [2:0]S_AXI_GP0_ARPROT;
+ input [2:0]S_AXI_GP0_AWPROT;
+ input [31:0]S_AXI_GP0_ARADDR;
+ input [31:0]S_AXI_GP0_AWADDR;
+ input [31:0]S_AXI_GP0_WDATA;
+ input [3:0]S_AXI_GP0_ARCACHE;
+ input [3:0]S_AXI_GP0_ARLEN;
+ input [3:0]S_AXI_GP0_ARQOS;
+ input [3:0]S_AXI_GP0_AWCACHE;
+ input [3:0]S_AXI_GP0_AWLEN;
+ input [3:0]S_AXI_GP0_AWQOS;
+ input [3:0]S_AXI_GP0_WSTRB;
+ input [5:0]S_AXI_GP0_ARID;
+ input [5:0]S_AXI_GP0_AWID;
+ input [5:0]S_AXI_GP0_WID;
+ output S_AXI_GP1_ARESETN;
+ output S_AXI_GP1_ARREADY;
+ output S_AXI_GP1_AWREADY;
+ output S_AXI_GP1_BVALID;
+ output S_AXI_GP1_RLAST;
+ output S_AXI_GP1_RVALID;
+ output S_AXI_GP1_WREADY;
+ output [1:0]S_AXI_GP1_BRESP;
+ output [1:0]S_AXI_GP1_RRESP;
+ output [31:0]S_AXI_GP1_RDATA;
+ output [5:0]S_AXI_GP1_BID;
+ output [5:0]S_AXI_GP1_RID;
+ input S_AXI_GP1_ACLK;
+ input S_AXI_GP1_ARVALID;
+ input S_AXI_GP1_AWVALID;
+ input S_AXI_GP1_BREADY;
+ input S_AXI_GP1_RREADY;
+ input S_AXI_GP1_WLAST;
+ input S_AXI_GP1_WVALID;
+ input [1:0]S_AXI_GP1_ARBURST;
+ input [1:0]S_AXI_GP1_ARLOCK;
+ input [2:0]S_AXI_GP1_ARSIZE;
+ input [1:0]S_AXI_GP1_AWBURST;
+ input [1:0]S_AXI_GP1_AWLOCK;
+ input [2:0]S_AXI_GP1_AWSIZE;
+ input [2:0]S_AXI_GP1_ARPROT;
+ input [2:0]S_AXI_GP1_AWPROT;
+ input [31:0]S_AXI_GP1_ARADDR;
+ input [31:0]S_AXI_GP1_AWADDR;
+ input [31:0]S_AXI_GP1_WDATA;
+ input [3:0]S_AXI_GP1_ARCACHE;
+ input [3:0]S_AXI_GP1_ARLEN;
+ input [3:0]S_AXI_GP1_ARQOS;
+ input [3:0]S_AXI_GP1_AWCACHE;
+ input [3:0]S_AXI_GP1_AWLEN;
+ input [3:0]S_AXI_GP1_AWQOS;
+ input [3:0]S_AXI_GP1_WSTRB;
+ input [5:0]S_AXI_GP1_ARID;
+ input [5:0]S_AXI_GP1_AWID;
+ input [5:0]S_AXI_GP1_WID;
+ output S_AXI_ACP_ARESETN;
+ output S_AXI_ACP_ARREADY;
+ output S_AXI_ACP_AWREADY;
+ output S_AXI_ACP_BVALID;
+ output S_AXI_ACP_RLAST;
+ output S_AXI_ACP_RVALID;
+ output S_AXI_ACP_WREADY;
+ output [1:0]S_AXI_ACP_BRESP;
+ output [1:0]S_AXI_ACP_RRESP;
+ output [2:0]S_AXI_ACP_BID;
+ output [2:0]S_AXI_ACP_RID;
+ output [63:0]S_AXI_ACP_RDATA;
+ input S_AXI_ACP_ACLK;
+ input S_AXI_ACP_ARVALID;
+ input S_AXI_ACP_AWVALID;
+ input S_AXI_ACP_BREADY;
+ input S_AXI_ACP_RREADY;
+ input S_AXI_ACP_WLAST;
+ input S_AXI_ACP_WVALID;
+ input [2:0]S_AXI_ACP_ARID;
+ input [2:0]S_AXI_ACP_ARPROT;
+ input [2:0]S_AXI_ACP_AWID;
+ input [2:0]S_AXI_ACP_AWPROT;
+ input [2:0]S_AXI_ACP_WID;
+ input [31:0]S_AXI_ACP_ARADDR;
+ input [31:0]S_AXI_ACP_AWADDR;
+ input [3:0]S_AXI_ACP_ARCACHE;
+ input [3:0]S_AXI_ACP_ARLEN;
+ input [3:0]S_AXI_ACP_ARQOS;
+ input [3:0]S_AXI_ACP_AWCACHE;
+ input [3:0]S_AXI_ACP_AWLEN;
+ input [3:0]S_AXI_ACP_AWQOS;
+ input [1:0]S_AXI_ACP_ARBURST;
+ input [1:0]S_AXI_ACP_ARLOCK;
+ input [2:0]S_AXI_ACP_ARSIZE;
+ input [1:0]S_AXI_ACP_AWBURST;
+ input [1:0]S_AXI_ACP_AWLOCK;
+ input [2:0]S_AXI_ACP_AWSIZE;
+ input [4:0]S_AXI_ACP_ARUSER;
+ input [4:0]S_AXI_ACP_AWUSER;
+ input [63:0]S_AXI_ACP_WDATA;
+ input [7:0]S_AXI_ACP_WSTRB;
+ output S_AXI_HP0_ARESETN;
+ output S_AXI_HP0_ARREADY;
+ output S_AXI_HP0_AWREADY;
+ output S_AXI_HP0_BVALID;
+ output S_AXI_HP0_RLAST;
+ output S_AXI_HP0_RVALID;
+ output S_AXI_HP0_WREADY;
+ output [1:0]S_AXI_HP0_BRESP;
+ output [1:0]S_AXI_HP0_RRESP;
+ output [5:0]S_AXI_HP0_BID;
+ output [5:0]S_AXI_HP0_RID;
+ output [63:0]S_AXI_HP0_RDATA;
+ output [7:0]S_AXI_HP0_RCOUNT;
+ output [7:0]S_AXI_HP0_WCOUNT;
+ output [2:0]S_AXI_HP0_RACOUNT;
+ output [5:0]S_AXI_HP0_WACOUNT;
+ input S_AXI_HP0_ACLK;
+ input S_AXI_HP0_ARVALID;
+ input S_AXI_HP0_AWVALID;
+ input S_AXI_HP0_BREADY;
+ input S_AXI_HP0_RDISSUECAP1_EN;
+ input S_AXI_HP0_RREADY;
+ input S_AXI_HP0_WLAST;
+ input S_AXI_HP0_WRISSUECAP1_EN;
+ input S_AXI_HP0_WVALID;
+ input [1:0]S_AXI_HP0_ARBURST;
+ input [1:0]S_AXI_HP0_ARLOCK;
+ input [2:0]S_AXI_HP0_ARSIZE;
+ input [1:0]S_AXI_HP0_AWBURST;
+ input [1:0]S_AXI_HP0_AWLOCK;
+ input [2:0]S_AXI_HP0_AWSIZE;
+ input [2:0]S_AXI_HP0_ARPROT;
+ input [2:0]S_AXI_HP0_AWPROT;
+ input [31:0]S_AXI_HP0_ARADDR;
+ input [31:0]S_AXI_HP0_AWADDR;
+ input [3:0]S_AXI_HP0_ARCACHE;
+ input [3:0]S_AXI_HP0_ARLEN;
+ input [3:0]S_AXI_HP0_ARQOS;
+ input [3:0]S_AXI_HP0_AWCACHE;
+ input [3:0]S_AXI_HP0_AWLEN;
+ input [3:0]S_AXI_HP0_AWQOS;
+ input [5:0]S_AXI_HP0_ARID;
+ input [5:0]S_AXI_HP0_AWID;
+ input [5:0]S_AXI_HP0_WID;
+ input [63:0]S_AXI_HP0_WDATA;
+ input [7:0]S_AXI_HP0_WSTRB;
+ output S_AXI_HP1_ARESETN;
+ output S_AXI_HP1_ARREADY;
+ output S_AXI_HP1_AWREADY;
+ output S_AXI_HP1_BVALID;
+ output S_AXI_HP1_RLAST;
+ output S_AXI_HP1_RVALID;
+ output S_AXI_HP1_WREADY;
+ output [1:0]S_AXI_HP1_BRESP;
+ output [1:0]S_AXI_HP1_RRESP;
+ output [5:0]S_AXI_HP1_BID;
+ output [5:0]S_AXI_HP1_RID;
+ output [63:0]S_AXI_HP1_RDATA;
+ output [7:0]S_AXI_HP1_RCOUNT;
+ output [7:0]S_AXI_HP1_WCOUNT;
+ output [2:0]S_AXI_HP1_RACOUNT;
+ output [5:0]S_AXI_HP1_WACOUNT;
+ input S_AXI_HP1_ACLK;
+ input S_AXI_HP1_ARVALID;
+ input S_AXI_HP1_AWVALID;
+ input S_AXI_HP1_BREADY;
+ input S_AXI_HP1_RDISSUECAP1_EN;
+ input S_AXI_HP1_RREADY;
+ input S_AXI_HP1_WLAST;
+ input S_AXI_HP1_WRISSUECAP1_EN;
+ input S_AXI_HP1_WVALID;
+ input [1:0]S_AXI_HP1_ARBURST;
+ input [1:0]S_AXI_HP1_ARLOCK;
+ input [2:0]S_AXI_HP1_ARSIZE;
+ input [1:0]S_AXI_HP1_AWBURST;
+ input [1:0]S_AXI_HP1_AWLOCK;
+ input [2:0]S_AXI_HP1_AWSIZE;
+ input [2:0]S_AXI_HP1_ARPROT;
+ input [2:0]S_AXI_HP1_AWPROT;
+ input [31:0]S_AXI_HP1_ARADDR;
+ input [31:0]S_AXI_HP1_AWADDR;
+ input [3:0]S_AXI_HP1_ARCACHE;
+ input [3:0]S_AXI_HP1_ARLEN;
+ input [3:0]S_AXI_HP1_ARQOS;
+ input [3:0]S_AXI_HP1_AWCACHE;
+ input [3:0]S_AXI_HP1_AWLEN;
+ input [3:0]S_AXI_HP1_AWQOS;
+ input [5:0]S_AXI_HP1_ARID;
+ input [5:0]S_AXI_HP1_AWID;
+ input [5:0]S_AXI_HP1_WID;
+ input [63:0]S_AXI_HP1_WDATA;
+ input [7:0]S_AXI_HP1_WSTRB;
+ output S_AXI_HP2_ARESETN;
+ output S_AXI_HP2_ARREADY;
+ output S_AXI_HP2_AWREADY;
+ output S_AXI_HP2_BVALID;
+ output S_AXI_HP2_RLAST;
+ output S_AXI_HP2_RVALID;
+ output S_AXI_HP2_WREADY;
+ output [1:0]S_AXI_HP2_BRESP;
+ output [1:0]S_AXI_HP2_RRESP;
+ output [5:0]S_AXI_HP2_BID;
+ output [5:0]S_AXI_HP2_RID;
+ output [63:0]S_AXI_HP2_RDATA;
+ output [7:0]S_AXI_HP2_RCOUNT;
+ output [7:0]S_AXI_HP2_WCOUNT;
+ output [2:0]S_AXI_HP2_RACOUNT;
+ output [5:0]S_AXI_HP2_WACOUNT;
+ input S_AXI_HP2_ACLK;
+ input S_AXI_HP2_ARVALID;
+ input S_AXI_HP2_AWVALID;
+ input S_AXI_HP2_BREADY;
+ input S_AXI_HP2_RDISSUECAP1_EN;
+ input S_AXI_HP2_RREADY;
+ input S_AXI_HP2_WLAST;
+ input S_AXI_HP2_WRISSUECAP1_EN;
+ input S_AXI_HP2_WVALID;
+ input [1:0]S_AXI_HP2_ARBURST;
+ input [1:0]S_AXI_HP2_ARLOCK;
+ input [2:0]S_AXI_HP2_ARSIZE;
+ input [1:0]S_AXI_HP2_AWBURST;
+ input [1:0]S_AXI_HP2_AWLOCK;
+ input [2:0]S_AXI_HP2_AWSIZE;
+ input [2:0]S_AXI_HP2_ARPROT;
+ input [2:0]S_AXI_HP2_AWPROT;
+ input [31:0]S_AXI_HP2_ARADDR;
+ input [31:0]S_AXI_HP2_AWADDR;
+ input [3:0]S_AXI_HP2_ARCACHE;
+ input [3:0]S_AXI_HP2_ARLEN;
+ input [3:0]S_AXI_HP2_ARQOS;
+ input [3:0]S_AXI_HP2_AWCACHE;
+ input [3:0]S_AXI_HP2_AWLEN;
+ input [3:0]S_AXI_HP2_AWQOS;
+ input [5:0]S_AXI_HP2_ARID;
+ input [5:0]S_AXI_HP2_AWID;
+ input [5:0]S_AXI_HP2_WID;
+ input [63:0]S_AXI_HP2_WDATA;
+ input [7:0]S_AXI_HP2_WSTRB;
+ output S_AXI_HP3_ARESETN;
+ output S_AXI_HP3_ARREADY;
+ output S_AXI_HP3_AWREADY;
+ output S_AXI_HP3_BVALID;
+ output S_AXI_HP3_RLAST;
+ output S_AXI_HP3_RVALID;
+ output S_AXI_HP3_WREADY;
+ output [1:0]S_AXI_HP3_BRESP;
+ output [1:0]S_AXI_HP3_RRESP;
+ output [5:0]S_AXI_HP3_BID;
+ output [5:0]S_AXI_HP3_RID;
+ output [63:0]S_AXI_HP3_RDATA;
+ output [7:0]S_AXI_HP3_RCOUNT;
+ output [7:0]S_AXI_HP3_WCOUNT;
+ output [2:0]S_AXI_HP3_RACOUNT;
+ output [5:0]S_AXI_HP3_WACOUNT;
+ input S_AXI_HP3_ACLK;
+ input S_AXI_HP3_ARVALID;
+ input S_AXI_HP3_AWVALID;
+ input S_AXI_HP3_BREADY;
+ input S_AXI_HP3_RDISSUECAP1_EN;
+ input S_AXI_HP3_RREADY;
+ input S_AXI_HP3_WLAST;
+ input S_AXI_HP3_WRISSUECAP1_EN;
+ input S_AXI_HP3_WVALID;
+ input [1:0]S_AXI_HP3_ARBURST;
+ input [1:0]S_AXI_HP3_ARLOCK;
+ input [2:0]S_AXI_HP3_ARSIZE;
+ input [1:0]S_AXI_HP3_AWBURST;
+ input [1:0]S_AXI_HP3_AWLOCK;
+ input [2:0]S_AXI_HP3_AWSIZE;
+ input [2:0]S_AXI_HP3_ARPROT;
+ input [2:0]S_AXI_HP3_AWPROT;
+ input [31:0]S_AXI_HP3_ARADDR;
+ input [31:0]S_AXI_HP3_AWADDR;
+ input [3:0]S_AXI_HP3_ARCACHE;
+ input [3:0]S_AXI_HP3_ARLEN;
+ input [3:0]S_AXI_HP3_ARQOS;
+ input [3:0]S_AXI_HP3_AWCACHE;
+ input [3:0]S_AXI_HP3_AWLEN;
+ input [3:0]S_AXI_HP3_AWQOS;
+ input [5:0]S_AXI_HP3_ARID;
+ input [5:0]S_AXI_HP3_AWID;
+ input [5:0]S_AXI_HP3_WID;
+ input [63:0]S_AXI_HP3_WDATA;
+ input [7:0]S_AXI_HP3_WSTRB;
+ output IRQ_P2F_DMAC_ABORT;
+ output IRQ_P2F_DMAC0;
+ output IRQ_P2F_DMAC1;
+ output IRQ_P2F_DMAC2;
+ output IRQ_P2F_DMAC3;
+ output IRQ_P2F_DMAC4;
+ output IRQ_P2F_DMAC5;
+ output IRQ_P2F_DMAC6;
+ output IRQ_P2F_DMAC7;
+ output IRQ_P2F_SMC;
+ output IRQ_P2F_QSPI;
+ output IRQ_P2F_CTI;
+ output IRQ_P2F_GPIO;
+ output IRQ_P2F_USB0;
+ output IRQ_P2F_ENET0;
+ output IRQ_P2F_ENET_WAKE0;
+ output IRQ_P2F_SDIO0;
+ output IRQ_P2F_I2C0;
+ output IRQ_P2F_SPI0;
+ output IRQ_P2F_UART0;
+ output IRQ_P2F_CAN0;
+ output IRQ_P2F_USB1;
+ output IRQ_P2F_ENET1;
+ output IRQ_P2F_ENET_WAKE1;
+ output IRQ_P2F_SDIO1;
+ output IRQ_P2F_I2C1;
+ output IRQ_P2F_SPI1;
+ output IRQ_P2F_UART1;
+ output IRQ_P2F_CAN1;
+ input [0:0]IRQ_F2P;
+ input Core0_nFIQ;
+ input Core0_nIRQ;
+ input Core1_nFIQ;
+ input Core1_nIRQ;
+ output [1:0]DMA0_DATYPE;
+ output DMA0_DAVALID;
+ output DMA0_DRREADY;
+ output DMA0_RSTN;
+ output [1:0]DMA1_DATYPE;
+ output DMA1_DAVALID;
+ output DMA1_DRREADY;
+ output DMA1_RSTN;
+ output [1:0]DMA2_DATYPE;
+ output DMA2_DAVALID;
+ output DMA2_DRREADY;
+ output DMA2_RSTN;
+ output [1:0]DMA3_DATYPE;
+ output DMA3_DAVALID;
+ output DMA3_DRREADY;
+ output DMA3_RSTN;
+ input DMA0_ACLK;
+ input DMA0_DAREADY;
+ input DMA0_DRLAST;
+ input DMA0_DRVALID;
+ input DMA1_ACLK;
+ input DMA1_DAREADY;
+ input DMA1_DRLAST;
+ input DMA1_DRVALID;
+ input DMA2_ACLK;
+ input DMA2_DAREADY;
+ input DMA2_DRLAST;
+ input DMA2_DRVALID;
+ input DMA3_ACLK;
+ input DMA3_DAREADY;
+ input DMA3_DRLAST;
+ input DMA3_DRVALID;
+ input [1:0]DMA0_DRTYPE;
+ input [1:0]DMA1_DRTYPE;
+ input [1:0]DMA2_DRTYPE;
+ input [1:0]DMA3_DRTYPE;
+ output FCLK_CLK3;
+ output FCLK_CLK2;
+ output FCLK_CLK1;
+ output FCLK_CLK0;
+ input FCLK_CLKTRIG3_N;
+ input FCLK_CLKTRIG2_N;
+ input FCLK_CLKTRIG1_N;
+ input FCLK_CLKTRIG0_N;
+ output FCLK_RESET3_N;
+ output FCLK_RESET2_N;
+ output FCLK_RESET1_N;
+ output FCLK_RESET0_N;
+ input [31:0]FTMD_TRACEIN_DATA;
+ input FTMD_TRACEIN_VALID;
+ input FTMD_TRACEIN_CLK;
+ input [3:0]FTMD_TRACEIN_ATID;
+ input FTMT_F2P_TRIG_0;
+ output FTMT_F2P_TRIGACK_0;
+ input FTMT_F2P_TRIG_1;
+ output FTMT_F2P_TRIGACK_1;
+ input FTMT_F2P_TRIG_2;
+ output FTMT_F2P_TRIGACK_2;
+ input FTMT_F2P_TRIG_3;
+ output FTMT_F2P_TRIGACK_3;
+ input [31:0]FTMT_F2P_DEBUG;
+ input FTMT_P2F_TRIGACK_0;
+ output FTMT_P2F_TRIG_0;
+ input FTMT_P2F_TRIGACK_1;
+ output FTMT_P2F_TRIG_1;
+ input FTMT_P2F_TRIGACK_2;
+ output FTMT_P2F_TRIG_2;
+ input FTMT_P2F_TRIGACK_3;
+ output FTMT_P2F_TRIG_3;
+ output [31:0]FTMT_P2F_DEBUG;
+ input FPGA_IDLE_N;
+ output EVENT_EVENTO;
+ output [1:0]EVENT_STANDBYWFE;
+ output [1:0]EVENT_STANDBYWFI;
+ input EVENT_EVENTI;
+ input [3:0]DDR_ARB;
+ inout [53:0]MIO;
+ inout DDR_CAS_n;
+ inout DDR_CKE;
+ inout DDR_Clk_n;
+ inout DDR_Clk;
+ inout DDR_CS_n;
+ inout DDR_DRSTB;
+ inout DDR_ODT;
+ inout DDR_RAS_n;
+ inout DDR_WEB;
+ inout [2:0]DDR_BankAddr;
+ inout [14:0]DDR_Addr;
+ inout DDR_VRN;
+ inout DDR_VRP;
+ inout [3:0]DDR_DM;
+ inout [31:0]DDR_DQ;
+ inout [3:0]DDR_DQS_n;
+ inout [3:0]DDR_DQS;
+ inout PS_SRSTB;
+ inout PS_CLK;
+ inout PS_PORB;
+
+ wire \<const0> ;
+ wire \<const1> ;
+ wire CAN0_PHY_RX;
+ wire CAN0_PHY_TX;
+ wire CAN1_PHY_RX;
+ wire CAN1_PHY_TX;
+ wire Core0_nFIQ;
+ wire Core0_nIRQ;
+ wire Core1_nFIQ;
+ wire Core1_nIRQ;
+ wire [3:0]DDR_ARB;
+ wire [14:0]DDR_Addr;
+ wire [2:0]DDR_BankAddr;
+ wire DDR_CAS_n;
+ wire DDR_CKE;
+ wire DDR_CS_n;
+ wire DDR_Clk;
+ wire DDR_Clk_n;
+ wire [3:0]DDR_DM;
+ wire [31:0]DDR_DQ;
+ wire [3:0]DDR_DQS;
+ wire [3:0]DDR_DQS_n;
+ wire DDR_DRSTB;
+ wire DDR_ODT;
+ wire DDR_RAS_n;
+ wire DDR_VRN;
+ wire DDR_VRP;
+ wire DDR_WEB;
+ wire DMA0_ACLK;
+ wire DMA0_DAREADY;
+ wire [1:0]DMA0_DATYPE;
+ wire DMA0_DAVALID;
+ wire DMA0_DRLAST;
+ wire DMA0_DRREADY;
+ wire [1:0]DMA0_DRTYPE;
+ wire DMA0_DRVALID;
+ wire DMA0_RSTN;
+ wire DMA1_ACLK;
+ wire DMA1_DAREADY;
+ wire [1:0]DMA1_DATYPE;
+ wire DMA1_DAVALID;
+ wire DMA1_DRLAST;
+ wire DMA1_DRREADY;
+ wire [1:0]DMA1_DRTYPE;
+ wire DMA1_DRVALID;
+ wire DMA1_RSTN;
+ wire DMA2_ACLK;
+ wire DMA2_DAREADY;
+ wire [1:0]DMA2_DATYPE;
+ wire DMA2_DAVALID;
+ wire DMA2_DRLAST;
+ wire DMA2_DRREADY;
+ wire [1:0]DMA2_DRTYPE;
+ wire DMA2_DRVALID;
+ wire DMA2_RSTN;
+ wire DMA3_ACLK;
+ wire DMA3_DAREADY;
+ wire [1:0]DMA3_DATYPE;
+ wire DMA3_DAVALID;
+ wire DMA3_DRLAST;
+ wire DMA3_DRREADY;
+ wire [1:0]DMA3_DRTYPE;
+ wire DMA3_DRVALID;
+ wire DMA3_RSTN;
+ wire ENET0_EXT_INTIN;
+ wire ENET0_GMII_RX_CLK;
+ wire ENET0_GMII_TX_CLK;
+ wire ENET0_MDIO_I;
+ wire ENET0_MDIO_MDC;
+ wire ENET0_MDIO_O;
+ wire ENET0_MDIO_T;
+ wire ENET0_MDIO_T_n;
+ wire ENET0_PTP_DELAY_REQ_RX;
+ wire ENET0_PTP_DELAY_REQ_TX;
+ wire ENET0_PTP_PDELAY_REQ_RX;
+ wire ENET0_PTP_PDELAY_REQ_TX;
+ wire ENET0_PTP_PDELAY_RESP_RX;
+ wire ENET0_PTP_PDELAY_RESP_TX;
+ wire ENET0_PTP_SYNC_FRAME_RX;
+ wire ENET0_PTP_SYNC_FRAME_TX;
+ wire ENET0_SOF_RX;
+ wire ENET0_SOF_TX;
+ wire ENET1_EXT_INTIN;
+ wire ENET1_GMII_RX_CLK;
+ wire ENET1_GMII_TX_CLK;
+ wire ENET1_MDIO_I;
+ wire ENET1_MDIO_MDC;
+ wire ENET1_MDIO_O;
+ wire ENET1_MDIO_T;
+ wire ENET1_MDIO_T_n;
+ wire ENET1_PTP_DELAY_REQ_RX;
+ wire ENET1_PTP_DELAY_REQ_TX;
+ wire ENET1_PTP_PDELAY_REQ_RX;
+ wire ENET1_PTP_PDELAY_REQ_TX;
+ wire ENET1_PTP_PDELAY_RESP_RX;
+ wire ENET1_PTP_PDELAY_RESP_TX;
+ wire ENET1_PTP_SYNC_FRAME_RX;
+ wire ENET1_PTP_SYNC_FRAME_TX;
+ wire ENET1_SOF_RX;
+ wire ENET1_SOF_TX;
+ wire EVENT_EVENTI;
+ wire EVENT_EVENTO;
+ wire [1:0]EVENT_STANDBYWFE;
+ wire [1:0]EVENT_STANDBYWFI;
+ wire FCLK_CLK0;
+ wire FCLK_CLK1;
+ wire FCLK_CLK2;
+ wire FCLK_CLK3;
+ wire [0:0]FCLK_CLK_unbuffered;
+ wire FCLK_RESET0_N;
+ wire FCLK_RESET1_N;
+ wire FCLK_RESET2_N;
+ wire FCLK_RESET3_N;
+ wire FPGA_IDLE_N;
+ wire FTMD_TRACEIN_CLK;
+ wire [31:0]FTMT_F2P_DEBUG;
+ wire FTMT_F2P_TRIGACK_0;
+ wire FTMT_F2P_TRIGACK_1;
+ wire FTMT_F2P_TRIGACK_2;
+ wire FTMT_F2P_TRIGACK_3;
+ wire FTMT_F2P_TRIG_0;
+ wire FTMT_F2P_TRIG_1;
+ wire FTMT_F2P_TRIG_2;
+ wire FTMT_F2P_TRIG_3;
+ wire [31:0]FTMT_P2F_DEBUG;
+ wire FTMT_P2F_TRIGACK_0;
+ wire FTMT_P2F_TRIGACK_1;
+ wire FTMT_P2F_TRIGACK_2;
+ wire FTMT_P2F_TRIGACK_3;
+ wire FTMT_P2F_TRIG_0;
+ wire FTMT_P2F_TRIG_1;
+ wire FTMT_P2F_TRIG_2;
+ wire FTMT_P2F_TRIG_3;
+ wire [63:0]GPIO_I;
+ wire [63:0]GPIO_O;
+ wire [63:0]GPIO_T;
+ wire I2C0_SCL_I;
+ wire I2C0_SCL_O;
+ wire I2C0_SCL_T;
+ wire I2C0_SCL_T_n;
+ wire I2C0_SDA_I;
+ wire I2C0_SDA_O;
+ wire I2C0_SDA_T;
+ wire I2C0_SDA_T_n;
+ wire I2C1_SCL_I;
+ wire I2C1_SCL_O;
+ wire I2C1_SCL_T;
+ wire I2C1_SCL_T_n;
+ wire I2C1_SDA_I;
+ wire I2C1_SDA_O;
+ wire I2C1_SDA_T;
+ wire I2C1_SDA_T_n;
+ wire [0:0]IRQ_F2P;
+ wire IRQ_P2F_CAN0;
+ wire IRQ_P2F_CAN1;
+ wire IRQ_P2F_CTI;
+ wire IRQ_P2F_DMAC0;
+ wire IRQ_P2F_DMAC1;
+ wire IRQ_P2F_DMAC2;
+ wire IRQ_P2F_DMAC3;
+ wire IRQ_P2F_DMAC4;
+ wire IRQ_P2F_DMAC5;
+ wire IRQ_P2F_DMAC6;
+ wire IRQ_P2F_DMAC7;
+ wire IRQ_P2F_DMAC_ABORT;
+ wire IRQ_P2F_ENET0;
+ wire IRQ_P2F_ENET1;
+ wire IRQ_P2F_ENET_WAKE0;
+ wire IRQ_P2F_ENET_WAKE1;
+ wire IRQ_P2F_GPIO;
+ wire IRQ_P2F_I2C0;
+ wire IRQ_P2F_I2C1;
+ wire IRQ_P2F_QSPI;
+ wire IRQ_P2F_SDIO0;
+ wire IRQ_P2F_SDIO1;
+ wire IRQ_P2F_SMC;
+ wire IRQ_P2F_SPI0;
+ wire IRQ_P2F_SPI1;
+ wire IRQ_P2F_UART0;
+ wire IRQ_P2F_UART1;
+ wire IRQ_P2F_USB0;
+ wire IRQ_P2F_USB1;
+ wire [53:0]MIO;
+ wire M_AXI_GP0_ACLK;
+ wire [31:0]M_AXI_GP0_ARADDR;
+ wire [1:0]M_AXI_GP0_ARBURST;
+ wire [3:0]\^M_AXI_GP0_ARCACHE ;
+ wire M_AXI_GP0_ARESETN;
+ wire [11:0]M_AXI_GP0_ARID;
+ wire [3:0]M_AXI_GP0_ARLEN;
+ wire [1:0]M_AXI_GP0_ARLOCK;
+ wire [2:0]M_AXI_GP0_ARPROT;
+ wire [3:0]M_AXI_GP0_ARQOS;
+ wire M_AXI_GP0_ARREADY;
+ wire [1:0]\^M_AXI_GP0_ARSIZE ;
+ wire M_AXI_GP0_ARVALID;
+ wire [31:0]M_AXI_GP0_AWADDR;
+ wire [1:0]M_AXI_GP0_AWBURST;
+ wire [3:0]\^M_AXI_GP0_AWCACHE ;
+ wire [11:0]M_AXI_GP0_AWID;
+ wire [3:0]M_AXI_GP0_AWLEN;
+ wire [1:0]M_AXI_GP0_AWLOCK;
+ wire [2:0]M_AXI_GP0_AWPROT;
+ wire [3:0]M_AXI_GP0_AWQOS;
+ wire M_AXI_GP0_AWREADY;
+ wire [1:0]\^M_AXI_GP0_AWSIZE ;
+ wire M_AXI_GP0_AWVALID;
+ wire [11:0]M_AXI_GP0_BID;
+ wire M_AXI_GP0_BREADY;
+ wire [1:0]M_AXI_GP0_BRESP;
+ wire M_AXI_GP0_BVALID;
+ wire [31:0]M_AXI_GP0_RDATA;
+ wire [11:0]M_AXI_GP0_RID;
+ wire M_AXI_GP0_RLAST;
+ wire M_AXI_GP0_RREADY;
+ wire [1:0]M_AXI_GP0_RRESP;
+ wire M_AXI_GP0_RVALID;
+ wire [31:0]M_AXI_GP0_WDATA;
+ wire [11:0]M_AXI_GP0_WID;
+ wire M_AXI_GP0_WLAST;
+ wire M_AXI_GP0_WREADY;
+ wire [3:0]M_AXI_GP0_WSTRB;
+ wire M_AXI_GP0_WVALID;
+ wire M_AXI_GP1_ACLK;
+ wire [31:0]M_AXI_GP1_ARADDR;
+ wire [1:0]M_AXI_GP1_ARBURST;
+ wire [3:0]\^M_AXI_GP1_ARCACHE ;
+ wire M_AXI_GP1_ARESETN;
+ wire [11:0]M_AXI_GP1_ARID;
+ wire [3:0]M_AXI_GP1_ARLEN;
+ wire [1:0]M_AXI_GP1_ARLOCK;
+ wire [2:0]M_AXI_GP1_ARPROT;
+ wire [3:0]M_AXI_GP1_ARQOS;
+ wire M_AXI_GP1_ARREADY;
+ wire [1:0]\^M_AXI_GP1_ARSIZE ;
+ wire M_AXI_GP1_ARVALID;
+ wire [31:0]M_AXI_GP1_AWADDR;
+ wire [1:0]M_AXI_GP1_AWBURST;
+ wire [3:0]\^M_AXI_GP1_AWCACHE ;
+ wire [11:0]M_AXI_GP1_AWID;
+ wire [3:0]M_AXI_GP1_AWLEN;
+ wire [1:0]M_AXI_GP1_AWLOCK;
+ wire [2:0]M_AXI_GP1_AWPROT;
+ wire [3:0]M_AXI_GP1_AWQOS;
+ wire M_AXI_GP1_AWREADY;
+ wire [1:0]\^M_AXI_GP1_AWSIZE ;
+ wire M_AXI_GP1_AWVALID;
+ wire [11:0]M_AXI_GP1_BID;
+ wire M_AXI_GP1_BREADY;
+ wire [1:0]M_AXI_GP1_BRESP;
+ wire M_AXI_GP1_BVALID;
+ wire [31:0]M_AXI_GP1_RDATA;
+ wire [11:0]M_AXI_GP1_RID;
+ wire M_AXI_GP1_RLAST;
+ wire M_AXI_GP1_RREADY;
+ wire [1:0]M_AXI_GP1_RRESP;
+ wire M_AXI_GP1_RVALID;
+ wire [31:0]M_AXI_GP1_WDATA;
+ wire [11:0]M_AXI_GP1_WID;
+ wire M_AXI_GP1_WLAST;
+ wire M_AXI_GP1_WREADY;
+ wire [3:0]M_AXI_GP1_WSTRB;
+ wire M_AXI_GP1_WVALID;
+ wire PJTAG_TCK;
+ wire PJTAG_TDI;
+ wire PJTAG_TMS;
+ wire PS_CLK;
+ wire PS_PORB;
+ wire PS_SRSTB;
+ wire SDIO0_BUSPOW;
+ wire [2:0]SDIO0_BUSVOLT;
+ wire SDIO0_CDN;
+ wire SDIO0_CLK;
+ wire SDIO0_CLK_FB;
+ wire SDIO0_CMD_I;
+ wire SDIO0_CMD_O;
+ wire SDIO0_CMD_T;
+ wire SDIO0_CMD_T_n;
+ wire [3:0]SDIO0_DATA_I;
+ wire [3:0]SDIO0_DATA_O;
+ wire [3:0]SDIO0_DATA_T;
+ wire [3:0]SDIO0_DATA_T_n;
+ wire SDIO0_LED;
+ wire SDIO0_WP;
+ wire SDIO1_BUSPOW;
+ wire [2:0]SDIO1_BUSVOLT;
+ wire SDIO1_CDN;
+ wire SDIO1_CLK;
+ wire SDIO1_CLK_FB;
+ wire SDIO1_CMD_I;
+ wire SDIO1_CMD_O;
+ wire SDIO1_CMD_T;
+ wire SDIO1_CMD_T_n;
+ wire [3:0]SDIO1_DATA_I;
+ wire [3:0]SDIO1_DATA_O;
+ wire [3:0]SDIO1_DATA_T;
+ wire [3:0]SDIO1_DATA_T_n;
+ wire SDIO1_LED;
+ wire SDIO1_WP;
+ wire SPI0_MISO_I;
+ wire SPI0_MISO_O;
+ wire SPI0_MISO_T;
+ wire SPI0_MISO_T_n;
+ wire SPI0_MOSI_I;
+ wire SPI0_MOSI_O;
+ wire SPI0_MOSI_T;
+ wire SPI0_MOSI_T_n;
+ wire SPI0_SCLK_I;
+ wire SPI0_SCLK_O;
+ wire SPI0_SCLK_T;
+ wire SPI0_SCLK_T_n;
+ wire SPI0_SS1_O;
+ wire SPI0_SS2_O;
+ wire SPI0_SS_I;
+ wire SPI0_SS_O;
+ wire SPI0_SS_T;
+ wire SPI0_SS_T_n;
+ wire SPI1_MISO_I;
+ wire SPI1_MISO_O;
+ wire SPI1_MISO_T;
+ wire SPI1_MISO_T_n;
+ wire SPI1_MOSI_I;
+ wire SPI1_MOSI_O;
+ wire SPI1_MOSI_T;
+ wire SPI1_MOSI_T_n;
+ wire SPI1_SCLK_I;
+ wire SPI1_SCLK_O;
+ wire SPI1_SCLK_T;
+ wire SPI1_SCLK_T_n;
+ wire SPI1_SS1_O;
+ wire SPI1_SS2_O;
+ wire SPI1_SS_I;
+ wire SPI1_SS_O;
+ wire SPI1_SS_T;
+ wire SPI1_SS_T_n;
+ wire SRAM_INTIN;
+ wire S_AXI_ACP_ACLK;
+ wire [31:0]S_AXI_ACP_ARADDR;
+ wire [1:0]S_AXI_ACP_ARBURST;
+ wire [3:0]S_AXI_ACP_ARCACHE;
+ wire S_AXI_ACP_ARESETN;
+ wire [2:0]S_AXI_ACP_ARID;
+ wire [3:0]S_AXI_ACP_ARLEN;
+ wire [1:0]S_AXI_ACP_ARLOCK;
+ wire [2:0]S_AXI_ACP_ARPROT;
+ wire [3:0]S_AXI_ACP_ARQOS;
+ wire S_AXI_ACP_ARREADY;
+ wire [2:0]S_AXI_ACP_ARSIZE;
+ wire [4:0]S_AXI_ACP_ARUSER;
+ wire S_AXI_ACP_ARVALID;
+ wire [31:0]S_AXI_ACP_AWADDR;
+ wire [1:0]S_AXI_ACP_AWBURST;
+ wire [3:0]S_AXI_ACP_AWCACHE;
+ wire [2:0]S_AXI_ACP_AWID;
+ wire [3:0]S_AXI_ACP_AWLEN;
+ wire [1:0]S_AXI_ACP_AWLOCK;
+ wire [2:0]S_AXI_ACP_AWPROT;
+ wire [3:0]S_AXI_ACP_AWQOS;
+ wire S_AXI_ACP_AWREADY;
+ wire [2:0]S_AXI_ACP_AWSIZE;
+ wire [4:0]S_AXI_ACP_AWUSER;
+ wire S_AXI_ACP_AWVALID;
+ wire [2:0]S_AXI_ACP_BID;
+ wire S_AXI_ACP_BREADY;
+ wire [1:0]S_AXI_ACP_BRESP;
+ wire S_AXI_ACP_BVALID;
+ wire [63:0]S_AXI_ACP_RDATA;
+ wire [2:0]S_AXI_ACP_RID;
+ wire S_AXI_ACP_RLAST;
+ wire S_AXI_ACP_RREADY;
+ wire [1:0]S_AXI_ACP_RRESP;
+ wire S_AXI_ACP_RVALID;
+ wire [63:0]S_AXI_ACP_WDATA;
+ wire [2:0]S_AXI_ACP_WID;
+ wire S_AXI_ACP_WLAST;
+ wire S_AXI_ACP_WREADY;
+ wire [7:0]S_AXI_ACP_WSTRB;
+ wire S_AXI_ACP_WVALID;
+ wire S_AXI_GP0_ACLK;
+ wire [31:0]S_AXI_GP0_ARADDR;
+ wire [1:0]S_AXI_GP0_ARBURST;
+ wire [3:0]S_AXI_GP0_ARCACHE;
+ wire S_AXI_GP0_ARESETN;
+ wire [5:0]S_AXI_GP0_ARID;
+ wire [3:0]S_AXI_GP0_ARLEN;
+ wire [1:0]S_AXI_GP0_ARLOCK;
+ wire [2:0]S_AXI_GP0_ARPROT;
+ wire [3:0]S_AXI_GP0_ARQOS;
+ wire S_AXI_GP0_ARREADY;
+ wire [2:0]S_AXI_GP0_ARSIZE;
+ wire S_AXI_GP0_ARVALID;
+ wire [31:0]S_AXI_GP0_AWADDR;
+ wire [1:0]S_AXI_GP0_AWBURST;
+ wire [3:0]S_AXI_GP0_AWCACHE;
+ wire [5:0]S_AXI_GP0_AWID;
+ wire [3:0]S_AXI_GP0_AWLEN;
+ wire [1:0]S_AXI_GP0_AWLOCK;
+ wire [2:0]S_AXI_GP0_AWPROT;
+ wire [3:0]S_AXI_GP0_AWQOS;
+ wire S_AXI_GP0_AWREADY;
+ wire [2:0]S_AXI_GP0_AWSIZE;
+ wire S_AXI_GP0_AWVALID;
+ wire [5:0]S_AXI_GP0_BID;
+ wire S_AXI_GP0_BREADY;
+ wire [1:0]S_AXI_GP0_BRESP;
+ wire S_AXI_GP0_BVALID;
+ wire [31:0]S_AXI_GP0_RDATA;
+ wire [5:0]S_AXI_GP0_RID;
+ wire S_AXI_GP0_RLAST;
+ wire S_AXI_GP0_RREADY;
+ wire [1:0]S_AXI_GP0_RRESP;
+ wire S_AXI_GP0_RVALID;
+ wire [31:0]S_AXI_GP0_WDATA;
+ wire [5:0]S_AXI_GP0_WID;
+ wire S_AXI_GP0_WLAST;
+ wire S_AXI_GP0_WREADY;
+ wire [3:0]S_AXI_GP0_WSTRB;
+ wire S_AXI_GP0_WVALID;
+ wire S_AXI_GP1_ACLK;
+ wire [31:0]S_AXI_GP1_ARADDR;
+ wire [1:0]S_AXI_GP1_ARBURST;
+ wire [3:0]S_AXI_GP1_ARCACHE;
+ wire S_AXI_GP1_ARESETN;
+ wire [5:0]S_AXI_GP1_ARID;
+ wire [3:0]S_AXI_GP1_ARLEN;
+ wire [1:0]S_AXI_GP1_ARLOCK;
+ wire [2:0]S_AXI_GP1_ARPROT;
+ wire [3:0]S_AXI_GP1_ARQOS;
+ wire S_AXI_GP1_ARREADY;
+ wire [2:0]S_AXI_GP1_ARSIZE;
+ wire S_AXI_GP1_ARVALID;
+ wire [31:0]S_AXI_GP1_AWADDR;
+ wire [1:0]S_AXI_GP1_AWBURST;
+ wire [3:0]S_AXI_GP1_AWCACHE;
+ wire [5:0]S_AXI_GP1_AWID;
+ wire [3:0]S_AXI_GP1_AWLEN;
+ wire [1:0]S_AXI_GP1_AWLOCK;
+ wire [2:0]S_AXI_GP1_AWPROT;
+ wire [3:0]S_AXI_GP1_AWQOS;
+ wire S_AXI_GP1_AWREADY;
+ wire [2:0]S_AXI_GP1_AWSIZE;
+ wire S_AXI_GP1_AWVALID;
+ wire [5:0]S_AXI_GP1_BID;
+ wire S_AXI_GP1_BREADY;
+ wire [1:0]S_AXI_GP1_BRESP;
+ wire S_AXI_GP1_BVALID;
+ wire [31:0]S_AXI_GP1_RDATA;
+ wire [5:0]S_AXI_GP1_RID;
+ wire S_AXI_GP1_RLAST;
+ wire S_AXI_GP1_RREADY;
+ wire [1:0]S_AXI_GP1_RRESP;
+ wire S_AXI_GP1_RVALID;
+ wire [31:0]S_AXI_GP1_WDATA;
+ wire [5:0]S_AXI_GP1_WID;
+ wire S_AXI_GP1_WLAST;
+ wire S_AXI_GP1_WREADY;
+ wire [3:0]S_AXI_GP1_WSTRB;
+ wire S_AXI_GP1_WVALID;
+ wire S_AXI_HP0_ACLK;
+ wire [31:0]S_AXI_HP0_ARADDR;
+ wire [1:0]S_AXI_HP0_ARBURST;
+ wire [3:0]S_AXI_HP0_ARCACHE;
+ wire S_AXI_HP0_ARESETN;
+ wire [5:0]S_AXI_HP0_ARID;
+ wire [3:0]S_AXI_HP0_ARLEN;
+ wire [1:0]S_AXI_HP0_ARLOCK;
+ wire [2:0]S_AXI_HP0_ARPROT;
+ wire [3:0]S_AXI_HP0_ARQOS;
+ wire S_AXI_HP0_ARREADY;
+ wire [2:0]S_AXI_HP0_ARSIZE;
+ wire S_AXI_HP0_ARVALID;
+ wire [31:0]S_AXI_HP0_AWADDR;
+ wire [1:0]S_AXI_HP0_AWBURST;
+ wire [3:0]S_AXI_HP0_AWCACHE;
+ wire [5:0]S_AXI_HP0_AWID;
+ wire [3:0]S_AXI_HP0_AWLEN;
+ wire [1:0]S_AXI_HP0_AWLOCK;
+ wire [2:0]S_AXI_HP0_AWPROT;
+ wire [3:0]S_AXI_HP0_AWQOS;
+ wire S_AXI_HP0_AWREADY;
+ wire [2:0]S_AXI_HP0_AWSIZE;
+ wire S_AXI_HP0_AWVALID;
+ wire [5:0]S_AXI_HP0_BID;
+ wire S_AXI_HP0_BREADY;
+ wire [1:0]S_AXI_HP0_BRESP;
+ wire S_AXI_HP0_BVALID;
+ wire [2:0]S_AXI_HP0_RACOUNT;
+ wire [7:0]S_AXI_HP0_RCOUNT;
+ wire [63:0]S_AXI_HP0_RDATA;
+ wire S_AXI_HP0_RDISSUECAP1_EN;
+ wire [5:0]S_AXI_HP0_RID;
+ wire S_AXI_HP0_RLAST;
+ wire S_AXI_HP0_RREADY;
+ wire [1:0]S_AXI_HP0_RRESP;
+ wire S_AXI_HP0_RVALID;
+ wire [5:0]S_AXI_HP0_WACOUNT;
+ wire [7:0]S_AXI_HP0_WCOUNT;
+ wire [63:0]S_AXI_HP0_WDATA;
+ wire [5:0]S_AXI_HP0_WID;
+ wire S_AXI_HP0_WLAST;
+ wire S_AXI_HP0_WREADY;
+ wire S_AXI_HP0_WRISSUECAP1_EN;
+ wire [7:0]S_AXI_HP0_WSTRB;
+ wire S_AXI_HP0_WVALID;
+ wire S_AXI_HP1_ACLK;
+ wire [31:0]S_AXI_HP1_ARADDR;
+ wire [1:0]S_AXI_HP1_ARBURST;
+ wire [3:0]S_AXI_HP1_ARCACHE;
+ wire S_AXI_HP1_ARESETN;
+ wire [5:0]S_AXI_HP1_ARID;
+ wire [3:0]S_AXI_HP1_ARLEN;
+ wire [1:0]S_AXI_HP1_ARLOCK;
+ wire [2:0]S_AXI_HP1_ARPROT;
+ wire [3:0]S_AXI_HP1_ARQOS;
+ wire S_AXI_HP1_ARREADY;
+ wire [2:0]S_AXI_HP1_ARSIZE;
+ wire S_AXI_HP1_ARVALID;
+ wire [31:0]S_AXI_HP1_AWADDR;
+ wire [1:0]S_AXI_HP1_AWBURST;
+ wire [3:0]S_AXI_HP1_AWCACHE;
+ wire [5:0]S_AXI_HP1_AWID;
+ wire [3:0]S_AXI_HP1_AWLEN;
+ wire [1:0]S_AXI_HP1_AWLOCK;
+ wire [2:0]S_AXI_HP1_AWPROT;
+ wire [3:0]S_AXI_HP1_AWQOS;
+ wire S_AXI_HP1_AWREADY;
+ wire [2:0]S_AXI_HP1_AWSIZE;
+ wire S_AXI_HP1_AWVALID;
+ wire [5:0]S_AXI_HP1_BID;
+ wire S_AXI_HP1_BREADY;
+ wire [1:0]S_AXI_HP1_BRESP;
+ wire S_AXI_HP1_BVALID;
+ wire [2:0]S_AXI_HP1_RACOUNT;
+ wire [7:0]S_AXI_HP1_RCOUNT;
+ wire [63:0]S_AXI_HP1_RDATA;
+ wire S_AXI_HP1_RDISSUECAP1_EN;
+ wire [5:0]S_AXI_HP1_RID;
+ wire S_AXI_HP1_RLAST;
+ wire S_AXI_HP1_RREADY;
+ wire [1:0]S_AXI_HP1_RRESP;
+ wire S_AXI_HP1_RVALID;
+ wire [5:0]S_AXI_HP1_WACOUNT;
+ wire [7:0]S_AXI_HP1_WCOUNT;
+ wire [63:0]S_AXI_HP1_WDATA;
+ wire [5:0]S_AXI_HP1_WID;
+ wire S_AXI_HP1_WLAST;
+ wire S_AXI_HP1_WREADY;
+ wire S_AXI_HP1_WRISSUECAP1_EN;
+ wire [7:0]S_AXI_HP1_WSTRB;
+ wire S_AXI_HP1_WVALID;
+ wire S_AXI_HP2_ACLK;
+ wire [31:0]S_AXI_HP2_ARADDR;
+ wire [1:0]S_AXI_HP2_ARBURST;
+ wire [3:0]S_AXI_HP2_ARCACHE;
+ wire S_AXI_HP2_ARESETN;
+ wire [5:0]S_AXI_HP2_ARID;
+ wire [3:0]S_AXI_HP2_ARLEN;
+ wire [1:0]S_AXI_HP2_ARLOCK;
+ wire [2:0]S_AXI_HP2_ARPROT;
+ wire [3:0]S_AXI_HP2_ARQOS;
+ wire S_AXI_HP2_ARREADY;
+ wire [2:0]S_AXI_HP2_ARSIZE;
+ wire S_AXI_HP2_ARVALID;
+ wire [31:0]S_AXI_HP2_AWADDR;
+ wire [1:0]S_AXI_HP2_AWBURST;
+ wire [3:0]S_AXI_HP2_AWCACHE;
+ wire [5:0]S_AXI_HP2_AWID;
+ wire [3:0]S_AXI_HP2_AWLEN;
+ wire [1:0]S_AXI_HP2_AWLOCK;
+ wire [2:0]S_AXI_HP2_AWPROT;
+ wire [3:0]S_AXI_HP2_AWQOS;
+ wire S_AXI_HP2_AWREADY;
+ wire [2:0]S_AXI_HP2_AWSIZE;
+ wire S_AXI_HP2_AWVALID;
+ wire [5:0]S_AXI_HP2_BID;
+ wire S_AXI_HP2_BREADY;
+ wire [1:0]S_AXI_HP2_BRESP;
+ wire S_AXI_HP2_BVALID;
+ wire [2:0]S_AXI_HP2_RACOUNT;
+ wire [7:0]S_AXI_HP2_RCOUNT;
+ wire [63:0]S_AXI_HP2_RDATA;
+ wire S_AXI_HP2_RDISSUECAP1_EN;
+ wire [5:0]S_AXI_HP2_RID;
+ wire S_AXI_HP2_RLAST;
+ wire S_AXI_HP2_RREADY;
+ wire [1:0]S_AXI_HP2_RRESP;
+ wire S_AXI_HP2_RVALID;
+ wire [5:0]S_AXI_HP2_WACOUNT;
+ wire [7:0]S_AXI_HP2_WCOUNT;
+ wire [63:0]S_AXI_HP2_WDATA;
+ wire [5:0]S_AXI_HP2_WID;
+ wire S_AXI_HP2_WLAST;
+ wire S_AXI_HP2_WREADY;
+ wire S_AXI_HP2_WRISSUECAP1_EN;
+ wire [7:0]S_AXI_HP2_WSTRB;
+ wire S_AXI_HP2_WVALID;
+ wire S_AXI_HP3_ACLK;
+ wire [31:0]S_AXI_HP3_ARADDR;
+ wire [1:0]S_AXI_HP3_ARBURST;
+ wire [3:0]S_AXI_HP3_ARCACHE;
+ wire S_AXI_HP3_ARESETN;
+ wire [5:0]S_AXI_HP3_ARID;
+ wire [3:0]S_AXI_HP3_ARLEN;
+ wire [1:0]S_AXI_HP3_ARLOCK;
+ wire [2:0]S_AXI_HP3_ARPROT;
+ wire [3:0]S_AXI_HP3_ARQOS;
+ wire S_AXI_HP3_ARREADY;
+ wire [2:0]S_AXI_HP3_ARSIZE;
+ wire S_AXI_HP3_ARVALID;
+ wire [31:0]S_AXI_HP3_AWADDR;
+ wire [1:0]S_AXI_HP3_AWBURST;
+ wire [3:0]S_AXI_HP3_AWCACHE;
+ wire [5:0]S_AXI_HP3_AWID;
+ wire [3:0]S_AXI_HP3_AWLEN;
+ wire [1:0]S_AXI_HP3_AWLOCK;
+ wire [2:0]S_AXI_HP3_AWPROT;
+ wire [3:0]S_AXI_HP3_AWQOS;
+ wire S_AXI_HP3_AWREADY;
+ wire [2:0]S_AXI_HP3_AWSIZE;
+ wire S_AXI_HP3_AWVALID;
+ wire [5:0]S_AXI_HP3_BID;
+ wire S_AXI_HP3_BREADY;
+ wire [1:0]S_AXI_HP3_BRESP;
+ wire S_AXI_HP3_BVALID;
+ wire [2:0]S_AXI_HP3_RACOUNT;
+ wire [7:0]S_AXI_HP3_RCOUNT;
+ wire [63:0]S_AXI_HP3_RDATA;
+ wire S_AXI_HP3_RDISSUECAP1_EN;
+ wire [5:0]S_AXI_HP3_RID;
+ wire S_AXI_HP3_RLAST;
+ wire S_AXI_HP3_RREADY;
+ wire [1:0]S_AXI_HP3_RRESP;
+ wire S_AXI_HP3_RVALID;
+ wire [5:0]S_AXI_HP3_WACOUNT;
+ wire [7:0]S_AXI_HP3_WCOUNT;
+ wire [63:0]S_AXI_HP3_WDATA;
+ wire [5:0]S_AXI_HP3_WID;
+ wire S_AXI_HP3_WLAST;
+ wire S_AXI_HP3_WREADY;
+ wire S_AXI_HP3_WRISSUECAP1_EN;
+ wire [7:0]S_AXI_HP3_WSTRB;
+ wire S_AXI_HP3_WVALID;
+ wire TRACE_CLK;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
+ (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
+ (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
+ wire TTC0_CLK0_IN;
+ wire TTC0_CLK1_IN;
+ wire TTC0_CLK2_IN;
+ wire TTC0_WAVE0_OUT;
+ wire TTC0_WAVE1_OUT;
+ wire TTC0_WAVE2_OUT;
+ wire TTC1_CLK0_IN;
+ wire TTC1_CLK1_IN;
+ wire TTC1_CLK2_IN;
+ wire TTC1_WAVE0_OUT;
+ wire TTC1_WAVE1_OUT;
+ wire TTC1_WAVE2_OUT;
+ wire UART0_CTSN;
+ wire UART0_DCDN;
+ wire UART0_DSRN;
+ wire UART0_DTRN;
+ wire UART0_RIN;
+ wire UART0_RTSN;
+ wire UART0_RX;
+ wire UART0_TX;
+ wire UART1_CTSN;
+ wire UART1_DCDN;
+ wire UART1_DSRN;
+ wire UART1_DTRN;
+ wire UART1_RIN;
+ wire UART1_RTSN;
+ wire UART1_RX;
+ wire UART1_TX;
+ wire [1:0]USB0_PORT_INDCTL;
+ wire USB0_VBUS_PWRFAULT;
+ wire USB0_VBUS_PWRSELECT;
+ wire [1:0]USB1_PORT_INDCTL;
+ wire USB1_VBUS_PWRFAULT;
+ wire USB1_VBUS_PWRSELECT;
+ wire WDT_CLK_IN;
+ wire WDT_RST_OUT;
+ wire [14:0]buffered_DDR_Addr;
+ wire [2:0]buffered_DDR_BankAddr;
+ wire buffered_DDR_CAS_n;
+ wire buffered_DDR_CKE;
+ wire buffered_DDR_CS_n;
+ wire buffered_DDR_Clk;
+ wire buffered_DDR_Clk_n;
+ wire [3:0]buffered_DDR_DM;
+ wire [31:0]buffered_DDR_DQ;
+ wire [3:0]buffered_DDR_DQS;
+ wire [3:0]buffered_DDR_DQS_n;
+ wire buffered_DDR_DRSTB;
+ wire buffered_DDR_ODT;
+ wire buffered_DDR_RAS_n;
+ wire buffered_DDR_VRN;
+ wire buffered_DDR_VRP;
+ wire buffered_DDR_WEB;
+ wire [53:0]buffered_MIO;
+ wire buffered_PS_CLK;
+ wire buffered_PS_PORB;
+ wire buffered_PS_SRSTB;
+ wire [63:0]gpio_out_t_n;
+ wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+ wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+ wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+ wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+ wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+ wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+ wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+ wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+ wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+ wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+ wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
+ wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
+ wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
+ wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
+
+ assign ENET0_GMII_TXD[7] = \<const0> ;
+ assign ENET0_GMII_TXD[6] = \<const0> ;
+ assign ENET0_GMII_TXD[5] = \<const0> ;
+ assign ENET0_GMII_TXD[4] = \<const0> ;
+ assign ENET0_GMII_TXD[3] = \<const0> ;
+ assign ENET0_GMII_TXD[2] = \<const0> ;
+ assign ENET0_GMII_TXD[1] = \<const0> ;
+ assign ENET0_GMII_TXD[0] = \<const0> ;
+ assign ENET0_GMII_TX_EN = \<const0> ;
+ assign ENET0_GMII_TX_ER = \<const0> ;
+ assign ENET1_GMII_TXD[7] = \<const0> ;
+ assign ENET1_GMII_TXD[6] = \<const0> ;
+ assign ENET1_GMII_TXD[5] = \<const0> ;
+ assign ENET1_GMII_TXD[4] = \<const0> ;
+ assign ENET1_GMII_TXD[3] = \<const0> ;
+ assign ENET1_GMII_TXD[2] = \<const0> ;
+ assign ENET1_GMII_TXD[1] = \<const0> ;
+ assign ENET1_GMII_TXD[0] = \<const0> ;
+ assign ENET1_GMII_TX_EN = \<const0> ;
+ assign ENET1_GMII_TX_ER = \<const0> ;
+ assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
+ assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
+ assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
+ assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
+ assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
+ assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
+ assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
+ assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
+ assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
+ assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
+ assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
+ assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
+ assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
+ assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
+ assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
+ assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
+ assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
+ assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
+ assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
+ assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
+ assign PJTAG_TDO = \<const0> ;
+ assign TRACE_CLK_OUT = \<const0> ;
+ assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
+ assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_CAS_n_BIBUF
+ (.IO(buffered_DDR_CAS_n),
+ .PAD(DDR_CAS_n));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_CKE_BIBUF
+ (.IO(buffered_DDR_CKE),
+ .PAD(DDR_CKE));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_CS_n_BIBUF
+ (.IO(buffered_DDR_CS_n),
+ .PAD(DDR_CS_n));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_Clk_BIBUF
+ (.IO(buffered_DDR_Clk),
+ .PAD(DDR_Clk));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_Clk_n_BIBUF
+ (.IO(buffered_DDR_Clk_n),
+ .PAD(DDR_Clk_n));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_DRSTB_BIBUF
+ (.IO(buffered_DDR_DRSTB),
+ .PAD(DDR_DRSTB));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_ODT_BIBUF
+ (.IO(buffered_DDR_ODT),
+ .PAD(DDR_ODT));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_RAS_n_BIBUF
+ (.IO(buffered_DDR_RAS_n),
+ .PAD(DDR_RAS_n));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_VRN_BIBUF
+ (.IO(buffered_DDR_VRN),
+ .PAD(DDR_VRN));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_VRP_BIBUF
+ (.IO(buffered_DDR_VRP),
+ .PAD(DDR_VRP));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF DDR_WEB_BIBUF
+ (.IO(buffered_DDR_WEB),
+ .PAD(DDR_WEB));
+ LUT1 #(
+ .INIT(2'h1))
+ ENET0_MDIO_T_INST_0
+ (.I0(ENET0_MDIO_T_n),
+ .O(ENET0_MDIO_T));
+ LUT1 #(
+ .INIT(2'h1))
+ ENET1_MDIO_T_INST_0
+ (.I0(ENET1_MDIO_T_n),
+ .O(ENET1_MDIO_T));
+ GND GND
+ (.G(\<const0> ));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[0]_INST_0
+ (.I0(gpio_out_t_n[0]),
+ .O(GPIO_T[0]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[10]_INST_0
+ (.I0(gpio_out_t_n[10]),
+ .O(GPIO_T[10]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[11]_INST_0
+ (.I0(gpio_out_t_n[11]),
+ .O(GPIO_T[11]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[12]_INST_0
+ (.I0(gpio_out_t_n[12]),
+ .O(GPIO_T[12]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[13]_INST_0
+ (.I0(gpio_out_t_n[13]),
+ .O(GPIO_T[13]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[14]_INST_0
+ (.I0(gpio_out_t_n[14]),
+ .O(GPIO_T[14]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[15]_INST_0
+ (.I0(gpio_out_t_n[15]),
+ .O(GPIO_T[15]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[16]_INST_0
+ (.I0(gpio_out_t_n[16]),
+ .O(GPIO_T[16]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[17]_INST_0
+ (.I0(gpio_out_t_n[17]),
+ .O(GPIO_T[17]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[18]_INST_0
+ (.I0(gpio_out_t_n[18]),
+ .O(GPIO_T[18]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[19]_INST_0
+ (.I0(gpio_out_t_n[19]),
+ .O(GPIO_T[19]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[1]_INST_0
+ (.I0(gpio_out_t_n[1]),
+ .O(GPIO_T[1]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[20]_INST_0
+ (.I0(gpio_out_t_n[20]),
+ .O(GPIO_T[20]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[21]_INST_0
+ (.I0(gpio_out_t_n[21]),
+ .O(GPIO_T[21]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[22]_INST_0
+ (.I0(gpio_out_t_n[22]),
+ .O(GPIO_T[22]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[23]_INST_0
+ (.I0(gpio_out_t_n[23]),
+ .O(GPIO_T[23]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[24]_INST_0
+ (.I0(gpio_out_t_n[24]),
+ .O(GPIO_T[24]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[25]_INST_0
+ (.I0(gpio_out_t_n[25]),
+ .O(GPIO_T[25]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[26]_INST_0
+ (.I0(gpio_out_t_n[26]),
+ .O(GPIO_T[26]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[27]_INST_0
+ (.I0(gpio_out_t_n[27]),
+ .O(GPIO_T[27]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[28]_INST_0
+ (.I0(gpio_out_t_n[28]),
+ .O(GPIO_T[28]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[29]_INST_0
+ (.I0(gpio_out_t_n[29]),
+ .O(GPIO_T[29]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[2]_INST_0
+ (.I0(gpio_out_t_n[2]),
+ .O(GPIO_T[2]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[30]_INST_0
+ (.I0(gpio_out_t_n[30]),
+ .O(GPIO_T[30]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[31]_INST_0
+ (.I0(gpio_out_t_n[31]),
+ .O(GPIO_T[31]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[32]_INST_0
+ (.I0(gpio_out_t_n[32]),
+ .O(GPIO_T[32]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[33]_INST_0
+ (.I0(gpio_out_t_n[33]),
+ .O(GPIO_T[33]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[34]_INST_0
+ (.I0(gpio_out_t_n[34]),
+ .O(GPIO_T[34]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[35]_INST_0
+ (.I0(gpio_out_t_n[35]),
+ .O(GPIO_T[35]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[36]_INST_0
+ (.I0(gpio_out_t_n[36]),
+ .O(GPIO_T[36]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[37]_INST_0
+ (.I0(gpio_out_t_n[37]),
+ .O(GPIO_T[37]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[38]_INST_0
+ (.I0(gpio_out_t_n[38]),
+ .O(GPIO_T[38]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[39]_INST_0
+ (.I0(gpio_out_t_n[39]),
+ .O(GPIO_T[39]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[3]_INST_0
+ (.I0(gpio_out_t_n[3]),
+ .O(GPIO_T[3]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[40]_INST_0
+ (.I0(gpio_out_t_n[40]),
+ .O(GPIO_T[40]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[41]_INST_0
+ (.I0(gpio_out_t_n[41]),
+ .O(GPIO_T[41]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[42]_INST_0
+ (.I0(gpio_out_t_n[42]),
+ .O(GPIO_T[42]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[43]_INST_0
+ (.I0(gpio_out_t_n[43]),
+ .O(GPIO_T[43]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[44]_INST_0
+ (.I0(gpio_out_t_n[44]),
+ .O(GPIO_T[44]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[45]_INST_0
+ (.I0(gpio_out_t_n[45]),
+ .O(GPIO_T[45]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[46]_INST_0
+ (.I0(gpio_out_t_n[46]),
+ .O(GPIO_T[46]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[47]_INST_0
+ (.I0(gpio_out_t_n[47]),
+ .O(GPIO_T[47]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[48]_INST_0
+ (.I0(gpio_out_t_n[48]),
+ .O(GPIO_T[48]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[49]_INST_0
+ (.I0(gpio_out_t_n[49]),
+ .O(GPIO_T[49]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[4]_INST_0
+ (.I0(gpio_out_t_n[4]),
+ .O(GPIO_T[4]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[50]_INST_0
+ (.I0(gpio_out_t_n[50]),
+ .O(GPIO_T[50]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[51]_INST_0
+ (.I0(gpio_out_t_n[51]),
+ .O(GPIO_T[51]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[52]_INST_0
+ (.I0(gpio_out_t_n[52]),
+ .O(GPIO_T[52]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[53]_INST_0
+ (.I0(gpio_out_t_n[53]),
+ .O(GPIO_T[53]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[54]_INST_0
+ (.I0(gpio_out_t_n[54]),
+ .O(GPIO_T[54]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[55]_INST_0
+ (.I0(gpio_out_t_n[55]),
+ .O(GPIO_T[55]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[56]_INST_0
+ (.I0(gpio_out_t_n[56]),
+ .O(GPIO_T[56]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[57]_INST_0
+ (.I0(gpio_out_t_n[57]),
+ .O(GPIO_T[57]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[58]_INST_0
+ (.I0(gpio_out_t_n[58]),
+ .O(GPIO_T[58]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[59]_INST_0
+ (.I0(gpio_out_t_n[59]),
+ .O(GPIO_T[59]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[5]_INST_0
+ (.I0(gpio_out_t_n[5]),
+ .O(GPIO_T[5]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[60]_INST_0
+ (.I0(gpio_out_t_n[60]),
+ .O(GPIO_T[60]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[61]_INST_0
+ (.I0(gpio_out_t_n[61]),
+ .O(GPIO_T[61]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[62]_INST_0
+ (.I0(gpio_out_t_n[62]),
+ .O(GPIO_T[62]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[63]_INST_0
+ (.I0(gpio_out_t_n[63]),
+ .O(GPIO_T[63]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[6]_INST_0
+ (.I0(gpio_out_t_n[6]),
+ .O(GPIO_T[6]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[7]_INST_0
+ (.I0(gpio_out_t_n[7]),
+ .O(GPIO_T[7]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[8]_INST_0
+ (.I0(gpio_out_t_n[8]),
+ .O(GPIO_T[8]));
+ LUT1 #(
+ .INIT(2'h1))
+ \GPIO_T[9]_INST_0
+ (.I0(gpio_out_t_n[9]),
+ .O(GPIO_T[9]));
+ LUT1 #(
+ .INIT(2'h1))
+ I2C0_SCL_T_INST_0
+ (.I0(I2C0_SCL_T_n),
+ .O(I2C0_SCL_T));
+ LUT1 #(
+ .INIT(2'h1))
+ I2C0_SDA_T_INST_0
+ (.I0(I2C0_SDA_T_n),
+ .O(I2C0_SDA_T));
+ LUT1 #(
+ .INIT(2'h1))
+ I2C1_SCL_T_INST_0
+ (.I0(I2C1_SCL_T_n),
+ .O(I2C1_SCL_T));
+ LUT1 #(
+ .INIT(2'h1))
+ I2C1_SDA_T_INST_0
+ (.I0(I2C1_SDA_T_n),
+ .O(I2C1_SDA_T));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ PS7 PS7_i
+ (.DDRA(buffered_DDR_Addr),
+ .DDRARB(DDR_ARB),
+ .DDRBA(buffered_DDR_BankAddr),
+ .DDRCASB(buffered_DDR_CAS_n),
+ .DDRCKE(buffered_DDR_CKE),
+ .DDRCKN(buffered_DDR_Clk_n),
+ .DDRCKP(buffered_DDR_Clk),
+ .DDRCSB(buffered_DDR_CS_n),
+ .DDRDM(buffered_DDR_DM),
+ .DDRDQ(buffered_DDR_DQ),
+ .DDRDQSN(buffered_DDR_DQS_n),
+ .DDRDQSP(buffered_DDR_DQS),
+ .DDRDRSTB(buffered_DDR_DRSTB),
+ .DDRODT(buffered_DDR_ODT),
+ .DDRRASB(buffered_DDR_RAS_n),
+ .DDRVRN(buffered_DDR_VRN),
+ .DDRVRP(buffered_DDR_VRP),
+ .DDRWEB(buffered_DDR_WEB),
+ .DMA0ACLK(DMA0_ACLK),
+ .DMA0DAREADY(DMA0_DAREADY),
+ .DMA0DATYPE(DMA0_DATYPE),
+ .DMA0DAVALID(DMA0_DAVALID),
+ .DMA0DRLAST(DMA0_DRLAST),
+ .DMA0DRREADY(DMA0_DRREADY),
+ .DMA0DRTYPE(DMA0_DRTYPE),
+ .DMA0DRVALID(DMA0_DRVALID),
+ .DMA0RSTN(DMA0_RSTN),
+ .DMA1ACLK(DMA1_ACLK),
+ .DMA1DAREADY(DMA1_DAREADY),
+ .DMA1DATYPE(DMA1_DATYPE),
+ .DMA1DAVALID(DMA1_DAVALID),
+ .DMA1DRLAST(DMA1_DRLAST),
+ .DMA1DRREADY(DMA1_DRREADY),
+ .DMA1DRTYPE(DMA1_DRTYPE),
+ .DMA1DRVALID(DMA1_DRVALID),
+ .DMA1RSTN(DMA1_RSTN),
+ .DMA2ACLK(DMA2_ACLK),
+ .DMA2DAREADY(DMA2_DAREADY),
+ .DMA2DATYPE(DMA2_DATYPE),
+ .DMA2DAVALID(DMA2_DAVALID),
+ .DMA2DRLAST(DMA2_DRLAST),
+ .DMA2DRREADY(DMA2_DRREADY),
+ .DMA2DRTYPE(DMA2_DRTYPE),
+ .DMA2DRVALID(DMA2_DRVALID),
+ .DMA2RSTN(DMA2_RSTN),
+ .DMA3ACLK(DMA3_ACLK),
+ .DMA3DAREADY(DMA3_DAREADY),
+ .DMA3DATYPE(DMA3_DATYPE),
+ .DMA3DAVALID(DMA3_DAVALID),
+ .DMA3DRLAST(DMA3_DRLAST),
+ .DMA3DRREADY(DMA3_DRREADY),
+ .DMA3DRTYPE(DMA3_DRTYPE),
+ .DMA3DRVALID(DMA3_DRVALID),
+ .DMA3RSTN(DMA3_RSTN),
+ .EMIOCAN0PHYRX(CAN0_PHY_RX),
+ .EMIOCAN0PHYTX(CAN0_PHY_TX),
+ .EMIOCAN1PHYRX(CAN1_PHY_RX),
+ .EMIOCAN1PHYTX(CAN1_PHY_TX),
+ .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+ .EMIOENET0GMIICOL(1'b0),
+ .EMIOENET0GMIICRS(1'b0),
+ .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+ .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .EMIOENET0GMIIRXDV(1'b0),
+ .EMIOENET0GMIIRXER(1'b0),
+ .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+ .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+ .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+ .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+ .EMIOENET0MDIOI(ENET0_MDIO_I),
+ .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+ .EMIOENET0MDIOO(ENET0_MDIO_O),
+ .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+ .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+ .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+ .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+ .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+ .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+ .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+ .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+ .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+ .EMIOENET0SOFRX(ENET0_SOF_RX),
+ .EMIOENET0SOFTX(ENET0_SOF_TX),
+ .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+ .EMIOENET1GMIICOL(1'b0),
+ .EMIOENET1GMIICRS(1'b0),
+ .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+ .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .EMIOENET1GMIIRXDV(1'b0),
+ .EMIOENET1GMIIRXER(1'b0),
+ .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+ .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+ .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+ .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+ .EMIOENET1MDIOI(ENET1_MDIO_I),
+ .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+ .EMIOENET1MDIOO(ENET1_MDIO_O),
+ .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+ .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+ .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+ .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+ .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+ .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+ .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+ .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+ .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+ .EMIOENET1SOFRX(ENET1_SOF_RX),
+ .EMIOENET1SOFTX(ENET1_SOF_TX),
+ .EMIOGPIOI(GPIO_I),
+ .EMIOGPIOO(GPIO_O),
+ .EMIOGPIOTN(gpio_out_t_n),
+ .EMIOI2C0SCLI(I2C0_SCL_I),
+ .EMIOI2C0SCLO(I2C0_SCL_O),
+ .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+ .EMIOI2C0SDAI(I2C0_SDA_I),
+ .EMIOI2C0SDAO(I2C0_SDA_O),
+ .EMIOI2C0SDATN(I2C0_SDA_T_n),
+ .EMIOI2C1SCLI(I2C1_SCL_I),
+ .EMIOI2C1SCLO(I2C1_SCL_O),
+ .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+ .EMIOI2C1SDAI(I2C1_SDA_I),
+ .EMIOI2C1SDAO(I2C1_SDA_O),
+ .EMIOI2C1SDATN(I2C1_SDA_T_n),
+ .EMIOPJTAGTCK(PJTAG_TCK),
+ .EMIOPJTAGTDI(PJTAG_TDI),
+ .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+ .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+ .EMIOPJTAGTMS(PJTAG_TMS),
+ .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+ .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+ .EMIOSDIO0CDN(SDIO0_CDN),
+ .EMIOSDIO0CLK(SDIO0_CLK),
+ .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+ .EMIOSDIO0CMDI(SDIO0_CMD_I),
+ .EMIOSDIO0CMDO(SDIO0_CMD_O),
+ .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+ .EMIOSDIO0DATAI(SDIO0_DATA_I),
+ .EMIOSDIO0DATAO(SDIO0_DATA_O),
+ .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+ .EMIOSDIO0LED(SDIO0_LED),
+ .EMIOSDIO0WP(SDIO0_WP),
+ .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+ .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+ .EMIOSDIO1CDN(SDIO1_CDN),
+ .EMIOSDIO1CLK(SDIO1_CLK),
+ .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+ .EMIOSDIO1CMDI(SDIO1_CMD_I),
+ .EMIOSDIO1CMDO(SDIO1_CMD_O),
+ .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+ .EMIOSDIO1DATAI(SDIO1_DATA_I),
+ .EMIOSDIO1DATAO(SDIO1_DATA_O),
+ .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+ .EMIOSDIO1LED(SDIO1_LED),
+ .EMIOSDIO1WP(SDIO1_WP),
+ .EMIOSPI0MI(SPI0_MISO_I),
+ .EMIOSPI0MO(SPI0_MOSI_O),
+ .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+ .EMIOSPI0SCLKI(SPI0_SCLK_I),
+ .EMIOSPI0SCLKO(SPI0_SCLK_O),
+ .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+ .EMIOSPI0SI(SPI0_MOSI_I),
+ .EMIOSPI0SO(SPI0_MISO_O),
+ .EMIOSPI0SSIN(SPI0_SS_I),
+ .EMIOSPI0SSNTN(SPI0_SS_T_n),
+ .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+ .EMIOSPI0STN(SPI0_MISO_T_n),
+ .EMIOSPI1MI(SPI1_MISO_I),
+ .EMIOSPI1MO(SPI1_MOSI_O),
+ .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+ .EMIOSPI1SCLKI(SPI1_SCLK_I),
+ .EMIOSPI1SCLKO(SPI1_SCLK_O),
+ .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+ .EMIOSPI1SI(SPI1_MOSI_I),
+ .EMIOSPI1SO(SPI1_MISO_O),
+ .EMIOSPI1SSIN(SPI1_SS_I),
+ .EMIOSPI1SSNTN(SPI1_SS_T_n),
+ .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+ .EMIOSPI1STN(SPI1_MISO_T_n),
+ .EMIOSRAMINTIN(SRAM_INTIN),
+ .EMIOTRACECLK(TRACE_CLK),
+ .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+ .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+ .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+ .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+ .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+ .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+ .EMIOUART0CTSN(UART0_CTSN),
+ .EMIOUART0DCDN(UART0_DCDN),
+ .EMIOUART0DSRN(UART0_DSRN),
+ .EMIOUART0DTRN(UART0_DTRN),
+ .EMIOUART0RIN(UART0_RIN),
+ .EMIOUART0RTSN(UART0_RTSN),
+ .EMIOUART0RX(UART0_RX),
+ .EMIOUART0TX(UART0_TX),
+ .EMIOUART1CTSN(UART1_CTSN),
+ .EMIOUART1DCDN(UART1_DCDN),
+ .EMIOUART1DSRN(UART1_DSRN),
+ .EMIOUART1DTRN(UART1_DTRN),
+ .EMIOUART1RIN(UART1_RIN),
+ .EMIOUART1RTSN(UART1_RTSN),
+ .EMIOUART1RX(UART1_RX),
+ .EMIOUART1TX(UART1_TX),
+ .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+ .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+ .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+ .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+ .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+ .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+ .EMIOWDTCLKI(WDT_CLK_IN),
+ .EMIOWDTRSTO(WDT_RST_OUT),
+ .EVENTEVENTI(EVENT_EVENTI),
+ .EVENTEVENTO(EVENT_EVENTO),
+ .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+ .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+ .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+ .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
+ .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+ .FPGAIDLEN(FPGA_IDLE_N),
+ .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
+ .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+ .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .FTMDTRACEINVALID(1'b0),
+ .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+ .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+ .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+ .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+ .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+ .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+ .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
+ .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+ .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+ .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+ .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+ .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
+ .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+ .MAXIGP0ARID(M_AXI_GP0_ARID),
+ .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+ .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+ .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+ .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+ .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+ .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
+ .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+ .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+ .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+ .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
+ .MAXIGP0AWID(M_AXI_GP0_AWID),
+ .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+ .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+ .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+ .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+ .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+ .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
+ .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+ .MAXIGP0BID(M_AXI_GP0_BID),
+ .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+ .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+ .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+ .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+ .MAXIGP0RID(M_AXI_GP0_RID),
+ .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+ .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+ .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+ .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+ .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+ .MAXIGP0WID(M_AXI_GP0_WID),
+ .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+ .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+ .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+ .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+ .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+ .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+ .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+ .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
+ .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+ .MAXIGP1ARID(M_AXI_GP1_ARID),
+ .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+ .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+ .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+ .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+ .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+ .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
+ .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+ .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+ .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+ .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
+ .MAXIGP1AWID(M_AXI_GP1_AWID),
+ .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+ .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+ .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+ .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+ .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+ .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
+ .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+ .MAXIGP1BID(M_AXI_GP1_BID),
+ .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+ .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+ .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+ .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+ .MAXIGP1RID(M_AXI_GP1_RID),
+ .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+ .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+ .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+ .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+ .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+ .MAXIGP1WID(M_AXI_GP1_WID),
+ .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+ .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+ .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+ .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+ .MIO(buffered_MIO),
+ .PSCLK(buffered_PS_CLK),
+ .PSPORB(buffered_PS_PORB),
+ .PSSRSTB(buffered_PS_SRSTB),
+ .SAXIACPACLK(S_AXI_ACP_ACLK),
+ .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+ .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+ .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+ .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+ .SAXIACPARID(S_AXI_ACP_ARID),
+ .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+ .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+ .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+ .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+ .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+ .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+ .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+ .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+ .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+ .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+ .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+ .SAXIACPAWID(S_AXI_ACP_AWID),
+ .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+ .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+ .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+ .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+ .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+ .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+ .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+ .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+ .SAXIACPBID(S_AXI_ACP_BID),
+ .SAXIACPBREADY(S_AXI_ACP_BREADY),
+ .SAXIACPBRESP(S_AXI_ACP_BRESP),
+ .SAXIACPBVALID(S_AXI_ACP_BVALID),
+ .SAXIACPRDATA(S_AXI_ACP_RDATA),
+ .SAXIACPRID(S_AXI_ACP_RID),
+ .SAXIACPRLAST(S_AXI_ACP_RLAST),
+ .SAXIACPRREADY(S_AXI_ACP_RREADY),
+ .SAXIACPRRESP(S_AXI_ACP_RRESP),
+ .SAXIACPRVALID(S_AXI_ACP_RVALID),
+ .SAXIACPWDATA(S_AXI_ACP_WDATA),
+ .SAXIACPWID(S_AXI_ACP_WID),
+ .SAXIACPWLAST(S_AXI_ACP_WLAST),
+ .SAXIACPWREADY(S_AXI_ACP_WREADY),
+ .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+ .SAXIACPWVALID(S_AXI_ACP_WVALID),
+ .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+ .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+ .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+ .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+ .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+ .SAXIGP0ARID(S_AXI_GP0_ARID),
+ .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+ .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+ .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+ .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+ .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+ .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+ .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+ .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+ .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+ .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+ .SAXIGP0AWID(S_AXI_GP0_AWID),
+ .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+ .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+ .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+ .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+ .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+ .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+ .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+ .SAXIGP0BID(S_AXI_GP0_BID),
+ .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+ .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+ .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+ .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+ .SAXIGP0RID(S_AXI_GP0_RID),
+ .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+ .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+ .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+ .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+ .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+ .SAXIGP0WID(S_AXI_GP0_WID),
+ .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+ .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+ .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+ .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+ .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+ .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+ .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+ .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+ .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+ .SAXIGP1ARID(S_AXI_GP1_ARID),
+ .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+ .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+ .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+ .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+ .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+ .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+ .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+ .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+ .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+ .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+ .SAXIGP1AWID(S_AXI_GP1_AWID),
+ .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+ .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+ .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+ .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+ .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+ .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+ .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+ .SAXIGP1BID(S_AXI_GP1_BID),
+ .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+ .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+ .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+ .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+ .SAXIGP1RID(S_AXI_GP1_RID),
+ .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+ .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+ .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+ .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+ .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+ .SAXIGP1WID(S_AXI_GP1_WID),
+ .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+ .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+ .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+ .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+ .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+ .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+ .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+ .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+ .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+ .SAXIHP0ARID(S_AXI_HP0_ARID),
+ .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+ .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+ .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+ .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+ .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+ .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+ .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+ .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+ .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+ .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+ .SAXIHP0AWID(S_AXI_HP0_AWID),
+ .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+ .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+ .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+ .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+ .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+ .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+ .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+ .SAXIHP0BID(S_AXI_HP0_BID),
+ .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+ .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+ .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+ .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+ .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+ .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+ .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+ .SAXIHP0RID(S_AXI_HP0_RID),
+ .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+ .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+ .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+ .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+ .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+ .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+ .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+ .SAXIHP0WID(S_AXI_HP0_WID),
+ .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+ .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+ .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+ .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+ .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+ .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+ .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+ .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+ .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+ .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+ .SAXIHP1ARID(S_AXI_HP1_ARID),
+ .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+ .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+ .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+ .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+ .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+ .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+ .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+ .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+ .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+ .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+ .SAXIHP1AWID(S_AXI_HP1_AWID),
+ .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+ .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+ .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+ .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+ .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+ .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+ .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+ .SAXIHP1BID(S_AXI_HP1_BID),
+ .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+ .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+ .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+ .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+ .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+ .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+ .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+ .SAXIHP1RID(S_AXI_HP1_RID),
+ .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+ .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+ .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+ .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+ .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+ .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+ .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+ .SAXIHP1WID(S_AXI_HP1_WID),
+ .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+ .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+ .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+ .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+ .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+ .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+ .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+ .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+ .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+ .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+ .SAXIHP2ARID(S_AXI_HP2_ARID),
+ .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+ .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+ .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+ .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+ .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+ .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+ .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+ .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+ .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+ .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+ .SAXIHP2AWID(S_AXI_HP2_AWID),
+ .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+ .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+ .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+ .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+ .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+ .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+ .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+ .SAXIHP2BID(S_AXI_HP2_BID),
+ .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+ .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+ .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+ .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+ .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+ .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+ .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+ .SAXIHP2RID(S_AXI_HP2_RID),
+ .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+ .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+ .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+ .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+ .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+ .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+ .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+ .SAXIHP2WID(S_AXI_HP2_WID),
+ .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+ .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+ .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+ .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+ .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+ .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+ .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+ .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+ .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+ .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+ .SAXIHP3ARID(S_AXI_HP3_ARID),
+ .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+ .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+ .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+ .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+ .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+ .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+ .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+ .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+ .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+ .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+ .SAXIHP3AWID(S_AXI_HP3_AWID),
+ .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+ .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+ .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+ .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+ .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+ .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+ .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+ .SAXIHP3BID(S_AXI_HP3_BID),
+ .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+ .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+ .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+ .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+ .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+ .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+ .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+ .SAXIHP3RID(S_AXI_HP3_RID),
+ .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+ .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+ .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+ .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+ .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+ .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+ .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+ .SAXIHP3WID(S_AXI_HP3_WID),
+ .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+ .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+ .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+ .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+ .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF PS_CLK_BIBUF
+ (.IO(buffered_PS_CLK),
+ .PAD(PS_CLK));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF PS_PORB_BIBUF
+ (.IO(buffered_PS_PORB),
+ .PAD(PS_PORB));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF PS_SRSTB_BIBUF
+ (.IO(buffered_PS_SRSTB),
+ .PAD(PS_SRSTB));
+ LUT1 #(
+ .INIT(2'h1))
+ SDIO0_CMD_T_INST_0
+ (.I0(SDIO0_CMD_T_n),
+ .O(SDIO0_CMD_T));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO0_DATA_T[0]_INST_0
+ (.I0(SDIO0_DATA_T_n[0]),
+ .O(SDIO0_DATA_T[0]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO0_DATA_T[1]_INST_0
+ (.I0(SDIO0_DATA_T_n[1]),
+ .O(SDIO0_DATA_T[1]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO0_DATA_T[2]_INST_0
+ (.I0(SDIO0_DATA_T_n[2]),
+ .O(SDIO0_DATA_T[2]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO0_DATA_T[3]_INST_0
+ (.I0(SDIO0_DATA_T_n[3]),
+ .O(SDIO0_DATA_T[3]));
+ LUT1 #(
+ .INIT(2'h1))
+ SDIO1_CMD_T_INST_0
+ (.I0(SDIO1_CMD_T_n),
+ .O(SDIO1_CMD_T));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO1_DATA_T[0]_INST_0
+ (.I0(SDIO1_DATA_T_n[0]),
+ .O(SDIO1_DATA_T[0]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO1_DATA_T[1]_INST_0
+ (.I0(SDIO1_DATA_T_n[1]),
+ .O(SDIO1_DATA_T[1]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO1_DATA_T[2]_INST_0
+ (.I0(SDIO1_DATA_T_n[2]),
+ .O(SDIO1_DATA_T[2]));
+ LUT1 #(
+ .INIT(2'h1))
+ \SDIO1_DATA_T[3]_INST_0
+ (.I0(SDIO1_DATA_T_n[3]),
+ .O(SDIO1_DATA_T[3]));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI0_MISO_T_INST_0
+ (.I0(SPI0_MISO_T_n),
+ .O(SPI0_MISO_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI0_MOSI_T_INST_0
+ (.I0(SPI0_MOSI_T_n),
+ .O(SPI0_MOSI_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI0_SCLK_T_INST_0
+ (.I0(SPI0_SCLK_T_n),
+ .O(SPI0_SCLK_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI0_SS_T_INST_0
+ (.I0(SPI0_SS_T_n),
+ .O(SPI0_SS_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI1_MISO_T_INST_0
+ (.I0(SPI1_MISO_T_n),
+ .O(SPI1_MISO_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI1_MOSI_T_INST_0
+ (.I0(SPI1_MOSI_T_n),
+ .O(SPI1_MOSI_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI1_SCLK_T_INST_0
+ (.I0(SPI1_SCLK_T_n),
+ .O(SPI1_SCLK_T));
+ LUT1 #(
+ .INIT(2'h1))
+ SPI1_SS_T_INST_0
+ (.I0(SPI1_SS_T_n),
+ .O(SPI1_SS_T));
+ VCC VCC
+ (.P(\<const1> ));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
+ (.I(FCLK_CLK_unbuffered),
+ .O(FCLK_CLK0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[0].MIO_BIBUF
+ (.IO(buffered_MIO[0]),
+ .PAD(MIO[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[10].MIO_BIBUF
+ (.IO(buffered_MIO[10]),
+ .PAD(MIO[10]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[11].MIO_BIBUF
+ (.IO(buffered_MIO[11]),
+ .PAD(MIO[11]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[12].MIO_BIBUF
+ (.IO(buffered_MIO[12]),
+ .PAD(MIO[12]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[13].MIO_BIBUF
+ (.IO(buffered_MIO[13]),
+ .PAD(MIO[13]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[14].MIO_BIBUF
+ (.IO(buffered_MIO[14]),
+ .PAD(MIO[14]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[15].MIO_BIBUF
+ (.IO(buffered_MIO[15]),
+ .PAD(MIO[15]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[16].MIO_BIBUF
+ (.IO(buffered_MIO[16]),
+ .PAD(MIO[16]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[17].MIO_BIBUF
+ (.IO(buffered_MIO[17]),
+ .PAD(MIO[17]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[18].MIO_BIBUF
+ (.IO(buffered_MIO[18]),
+ .PAD(MIO[18]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[19].MIO_BIBUF
+ (.IO(buffered_MIO[19]),
+ .PAD(MIO[19]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[1].MIO_BIBUF
+ (.IO(buffered_MIO[1]),
+ .PAD(MIO[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[20].MIO_BIBUF
+ (.IO(buffered_MIO[20]),
+ .PAD(MIO[20]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[21].MIO_BIBUF
+ (.IO(buffered_MIO[21]),
+ .PAD(MIO[21]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[22].MIO_BIBUF
+ (.IO(buffered_MIO[22]),
+ .PAD(MIO[22]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[23].MIO_BIBUF
+ (.IO(buffered_MIO[23]),
+ .PAD(MIO[23]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[24].MIO_BIBUF
+ (.IO(buffered_MIO[24]),
+ .PAD(MIO[24]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[25].MIO_BIBUF
+ (.IO(buffered_MIO[25]),
+ .PAD(MIO[25]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[26].MIO_BIBUF
+ (.IO(buffered_MIO[26]),
+ .PAD(MIO[26]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[27].MIO_BIBUF
+ (.IO(buffered_MIO[27]),
+ .PAD(MIO[27]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[28].MIO_BIBUF
+ (.IO(buffered_MIO[28]),
+ .PAD(MIO[28]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[29].MIO_BIBUF
+ (.IO(buffered_MIO[29]),
+ .PAD(MIO[29]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[2].MIO_BIBUF
+ (.IO(buffered_MIO[2]),
+ .PAD(MIO[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[30].MIO_BIBUF
+ (.IO(buffered_MIO[30]),
+ .PAD(MIO[30]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[31].MIO_BIBUF
+ (.IO(buffered_MIO[31]),
+ .PAD(MIO[31]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[32].MIO_BIBUF
+ (.IO(buffered_MIO[32]),
+ .PAD(MIO[32]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[33].MIO_BIBUF
+ (.IO(buffered_MIO[33]),
+ .PAD(MIO[33]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[34].MIO_BIBUF
+ (.IO(buffered_MIO[34]),
+ .PAD(MIO[34]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[35].MIO_BIBUF
+ (.IO(buffered_MIO[35]),
+ .PAD(MIO[35]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[36].MIO_BIBUF
+ (.IO(buffered_MIO[36]),
+ .PAD(MIO[36]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[37].MIO_BIBUF
+ (.IO(buffered_MIO[37]),
+ .PAD(MIO[37]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[38].MIO_BIBUF
+ (.IO(buffered_MIO[38]),
+ .PAD(MIO[38]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[39].MIO_BIBUF
+ (.IO(buffered_MIO[39]),
+ .PAD(MIO[39]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[3].MIO_BIBUF
+ (.IO(buffered_MIO[3]),
+ .PAD(MIO[3]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[40].MIO_BIBUF
+ (.IO(buffered_MIO[40]),
+ .PAD(MIO[40]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[41].MIO_BIBUF
+ (.IO(buffered_MIO[41]),
+ .PAD(MIO[41]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[42].MIO_BIBUF
+ (.IO(buffered_MIO[42]),
+ .PAD(MIO[42]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[43].MIO_BIBUF
+ (.IO(buffered_MIO[43]),
+ .PAD(MIO[43]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[44].MIO_BIBUF
+ (.IO(buffered_MIO[44]),
+ .PAD(MIO[44]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[45].MIO_BIBUF
+ (.IO(buffered_MIO[45]),
+ .PAD(MIO[45]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[46].MIO_BIBUF
+ (.IO(buffered_MIO[46]),
+ .PAD(MIO[46]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[47].MIO_BIBUF
+ (.IO(buffered_MIO[47]),
+ .PAD(MIO[47]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[48].MIO_BIBUF
+ (.IO(buffered_MIO[48]),
+ .PAD(MIO[48]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[49].MIO_BIBUF
+ (.IO(buffered_MIO[49]),
+ .PAD(MIO[49]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[4].MIO_BIBUF
+ (.IO(buffered_MIO[4]),
+ .PAD(MIO[4]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[50].MIO_BIBUF
+ (.IO(buffered_MIO[50]),
+ .PAD(MIO[50]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[51].MIO_BIBUF
+ (.IO(buffered_MIO[51]),
+ .PAD(MIO[51]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[52].MIO_BIBUF
+ (.IO(buffered_MIO[52]),
+ .PAD(MIO[52]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[53].MIO_BIBUF
+ (.IO(buffered_MIO[53]),
+ .PAD(MIO[53]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[5].MIO_BIBUF
+ (.IO(buffered_MIO[5]),
+ .PAD(MIO[5]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[6].MIO_BIBUF
+ (.IO(buffered_MIO[6]),
+ .PAD(MIO[6]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[7].MIO_BIBUF
+ (.IO(buffered_MIO[7]),
+ .PAD(MIO[7]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[8].MIO_BIBUF
+ (.IO(buffered_MIO[8]),
+ .PAD(MIO[8]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk13[9].MIO_BIBUF
+ (.IO(buffered_MIO[9]),
+ .PAD(MIO[9]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk14[0].DDR_BankAddr_BIBUF
+ (.IO(buffered_DDR_BankAddr[0]),
+ .PAD(DDR_BankAddr[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk14[1].DDR_BankAddr_BIBUF
+ (.IO(buffered_DDR_BankAddr[1]),
+ .PAD(DDR_BankAddr[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk14[2].DDR_BankAddr_BIBUF
+ (.IO(buffered_DDR_BankAddr[2]),
+ .PAD(DDR_BankAddr[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[0].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[0]),
+ .PAD(DDR_Addr[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[10].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[10]),
+ .PAD(DDR_Addr[10]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[11].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[11]),
+ .PAD(DDR_Addr[11]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[12].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[12]),
+ .PAD(DDR_Addr[12]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[13].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[13]),
+ .PAD(DDR_Addr[13]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[14].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[14]),
+ .PAD(DDR_Addr[14]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[1].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[1]),
+ .PAD(DDR_Addr[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[2].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[2]),
+ .PAD(DDR_Addr[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[3].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[3]),
+ .PAD(DDR_Addr[3]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[4].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[4]),
+ .PAD(DDR_Addr[4]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[5].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[5]),
+ .PAD(DDR_Addr[5]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[6].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[6]),
+ .PAD(DDR_Addr[6]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[7].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[7]),
+ .PAD(DDR_Addr[7]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[8].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[8]),
+ .PAD(DDR_Addr[8]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk15[9].DDR_Addr_BIBUF
+ (.IO(buffered_DDR_Addr[9]),
+ .PAD(DDR_Addr[9]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk16[0].DDR_DM_BIBUF
+ (.IO(buffered_DDR_DM[0]),
+ .PAD(DDR_DM[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk16[1].DDR_DM_BIBUF
+ (.IO(buffered_DDR_DM[1]),
+ .PAD(DDR_DM[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk16[2].DDR_DM_BIBUF
+ (.IO(buffered_DDR_DM[2]),
+ .PAD(DDR_DM[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk16[3].DDR_DM_BIBUF
+ (.IO(buffered_DDR_DM[3]),
+ .PAD(DDR_DM[3]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[0].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[0]),
+ .PAD(DDR_DQ[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[10].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[10]),
+ .PAD(DDR_DQ[10]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[11].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[11]),
+ .PAD(DDR_DQ[11]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[12].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[12]),
+ .PAD(DDR_DQ[12]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[13].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[13]),
+ .PAD(DDR_DQ[13]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[14].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[14]),
+ .PAD(DDR_DQ[14]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[15].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[15]),
+ .PAD(DDR_DQ[15]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[16].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[16]),
+ .PAD(DDR_DQ[16]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[17].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[17]),
+ .PAD(DDR_DQ[17]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[18].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[18]),
+ .PAD(DDR_DQ[18]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[19].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[19]),
+ .PAD(DDR_DQ[19]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[1].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[1]),
+ .PAD(DDR_DQ[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[20].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[20]),
+ .PAD(DDR_DQ[20]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[21].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[21]),
+ .PAD(DDR_DQ[21]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[22].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[22]),
+ .PAD(DDR_DQ[22]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[23].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[23]),
+ .PAD(DDR_DQ[23]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[24].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[24]),
+ .PAD(DDR_DQ[24]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[25].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[25]),
+ .PAD(DDR_DQ[25]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[26].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[26]),
+ .PAD(DDR_DQ[26]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[27].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[27]),
+ .PAD(DDR_DQ[27]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[28].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[28]),
+ .PAD(DDR_DQ[28]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[29].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[29]),
+ .PAD(DDR_DQ[29]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[2].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[2]),
+ .PAD(DDR_DQ[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[30].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[30]),
+ .PAD(DDR_DQ[30]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[31].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[31]),
+ .PAD(DDR_DQ[31]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[3].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[3]),
+ .PAD(DDR_DQ[3]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[4].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[4]),
+ .PAD(DDR_DQ[4]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[5].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[5]),
+ .PAD(DDR_DQ[5]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[6].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[6]),
+ .PAD(DDR_DQ[6]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[7].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[7]),
+ .PAD(DDR_DQ[7]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[8].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[8]),
+ .PAD(DDR_DQ[8]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk17[9].DDR_DQ_BIBUF
+ (.IO(buffered_DDR_DQ[9]),
+ .PAD(DDR_DQ[9]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk18[0].DDR_DQS_n_BIBUF
+ (.IO(buffered_DDR_DQS_n[0]),
+ .PAD(DDR_DQS_n[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk18[1].DDR_DQS_n_BIBUF
+ (.IO(buffered_DDR_DQS_n[1]),
+ .PAD(DDR_DQS_n[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk18[2].DDR_DQS_n_BIBUF
+ (.IO(buffered_DDR_DQS_n[2]),
+ .PAD(DDR_DQS_n[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk18[3].DDR_DQS_n_BIBUF
+ (.IO(buffered_DDR_DQS_n[3]),
+ .PAD(DDR_DQS_n[3]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk19[0].DDR_DQS_BIBUF
+ (.IO(buffered_DDR_DQS[0]),
+ .PAD(DDR_DQS[0]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk19[1].DDR_DQS_BIBUF
+ (.IO(buffered_DDR_DQS[1]),
+ .PAD(DDR_DQS[1]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk19[2].DDR_DQS_BIBUF
+ (.IO(buffered_DDR_DQS[2]),
+ .PAD(DDR_DQS[2]));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BIBUF \genblk19[3].DDR_DQS_BIBUF
+ (.IO(buffered_DDR_DQS[3]),
+ .PAD(DDR_DQS[3]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_0
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[0] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_1
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[0] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_10
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[7] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_11
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[7] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_12
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[6] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_13
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[6] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_14
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[5] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_15
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[5] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_16
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[4] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_17
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[4] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_18
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[3] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_19
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[3] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_2
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[0] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_20
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[2] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_21
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[2] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_22
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[1] [1]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_23
+ (.I0(1'b0),
+ .O(\TRACE_DATA_PIPE[1] [0]));
+ LUT1 #(
+ .INIT(2'h2))
+ i_3
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[7] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_4
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[6] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_5
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[5] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_6
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[4] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_7
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[3] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_8
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[2] ));
+ LUT1 #(
+ .INIT(2'h2))
+ i_9
+ (.I0(1'b0),
+ .O(\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.vhdl
new file mode 100644
index 0000000..96c46a9
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.vhdl
@@ -0,0 +1,4611 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Tue Oct 15 10:07:06 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_sim_netlist.vhdl
+-- Design : TopLevel_processing_system7_0_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
+ port (
+ CAN0_PHY_TX : out STD_LOGIC;
+ CAN0_PHY_RX : in STD_LOGIC;
+ CAN1_PHY_TX : out STD_LOGIC;
+ CAN1_PHY_RX : in STD_LOGIC;
+ ENET0_GMII_TX_EN : out STD_LOGIC;
+ ENET0_GMII_TX_ER : out STD_LOGIC;
+ ENET0_MDIO_MDC : out STD_LOGIC;
+ ENET0_MDIO_O : out STD_LOGIC;
+ ENET0_MDIO_T : out STD_LOGIC;
+ ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
+ ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
+ ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
+ ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
+ ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
+ ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
+ ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
+ ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
+ ENET0_SOF_RX : out STD_LOGIC;
+ ENET0_SOF_TX : out STD_LOGIC;
+ ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ ENET0_GMII_COL : in STD_LOGIC;
+ ENET0_GMII_CRS : in STD_LOGIC;
+ ENET0_GMII_RX_CLK : in STD_LOGIC;
+ ENET0_GMII_RX_DV : in STD_LOGIC;
+ ENET0_GMII_RX_ER : in STD_LOGIC;
+ ENET0_GMII_TX_CLK : in STD_LOGIC;
+ ENET0_MDIO_I : in STD_LOGIC;
+ ENET0_EXT_INTIN : in STD_LOGIC;
+ ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ ENET1_GMII_TX_EN : out STD_LOGIC;
+ ENET1_GMII_TX_ER : out STD_LOGIC;
+ ENET1_MDIO_MDC : out STD_LOGIC;
+ ENET1_MDIO_O : out STD_LOGIC;
+ ENET1_MDIO_T : out STD_LOGIC;
+ ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
+ ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
+ ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
+ ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
+ ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
+ ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
+ ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
+ ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
+ ENET1_SOF_RX : out STD_LOGIC;
+ ENET1_SOF_TX : out STD_LOGIC;
+ ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ ENET1_GMII_COL : in STD_LOGIC;
+ ENET1_GMII_CRS : in STD_LOGIC;
+ ENET1_GMII_RX_CLK : in STD_LOGIC;
+ ENET1_GMII_RX_DV : in STD_LOGIC;
+ ENET1_GMII_RX_ER : in STD_LOGIC;
+ ENET1_GMII_TX_CLK : in STD_LOGIC;
+ ENET1_MDIO_I : in STD_LOGIC;
+ ENET1_EXT_INTIN : in STD_LOGIC;
+ ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ I2C0_SDA_I : in STD_LOGIC;
+ I2C0_SDA_O : out STD_LOGIC;
+ I2C0_SDA_T : out STD_LOGIC;
+ I2C0_SCL_I : in STD_LOGIC;
+ I2C0_SCL_O : out STD_LOGIC;
+ I2C0_SCL_T : out STD_LOGIC;
+ I2C1_SDA_I : in STD_LOGIC;
+ I2C1_SDA_O : out STD_LOGIC;
+ I2C1_SDA_T : out STD_LOGIC;
+ I2C1_SCL_I : in STD_LOGIC;
+ I2C1_SCL_O : out STD_LOGIC;
+ I2C1_SCL_T : out STD_LOGIC;
+ PJTAG_TCK : in STD_LOGIC;
+ PJTAG_TMS : in STD_LOGIC;
+ PJTAG_TDI : in STD_LOGIC;
+ PJTAG_TDO : out STD_LOGIC;
+ SDIO0_CLK : out STD_LOGIC;
+ SDIO0_CLK_FB : in STD_LOGIC;
+ SDIO0_CMD_O : out STD_LOGIC;
+ SDIO0_CMD_I : in STD_LOGIC;
+ SDIO0_CMD_T : out STD_LOGIC;
+ SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO0_LED : out STD_LOGIC;
+ SDIO0_CDN : in STD_LOGIC;
+ SDIO0_WP : in STD_LOGIC;
+ SDIO0_BUSPOW : out STD_LOGIC;
+ SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ SDIO1_CLK : out STD_LOGIC;
+ SDIO1_CLK_FB : in STD_LOGIC;
+ SDIO1_CMD_O : out STD_LOGIC;
+ SDIO1_CMD_I : in STD_LOGIC;
+ SDIO1_CMD_T : out STD_LOGIC;
+ SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ SDIO1_LED : out STD_LOGIC;
+ SDIO1_CDN : in STD_LOGIC;
+ SDIO1_WP : in STD_LOGIC;
+ SDIO1_BUSPOW : out STD_LOGIC;
+ SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ SPI0_SCLK_I : in STD_LOGIC;
+ SPI0_SCLK_O : out STD_LOGIC;
+ SPI0_SCLK_T : out STD_LOGIC;
+ SPI0_MOSI_I : in STD_LOGIC;
+ SPI0_MOSI_O : out STD_LOGIC;
+ SPI0_MOSI_T : out STD_LOGIC;
+ SPI0_MISO_I : in STD_LOGIC;
+ SPI0_MISO_O : out STD_LOGIC;
+ SPI0_MISO_T : out STD_LOGIC;
+ SPI0_SS_I : in STD_LOGIC;
+ SPI0_SS_O : out STD_LOGIC;
+ SPI0_SS1_O : out STD_LOGIC;
+ SPI0_SS2_O : out STD_LOGIC;
+ SPI0_SS_T : out STD_LOGIC;
+ SPI1_SCLK_I : in STD_LOGIC;
+ SPI1_SCLK_O : out STD_LOGIC;
+ SPI1_SCLK_T : out STD_LOGIC;
+ SPI1_MOSI_I : in STD_LOGIC;
+ SPI1_MOSI_O : out STD_LOGIC;
+ SPI1_MOSI_T : out STD_LOGIC;
+ SPI1_MISO_I : in STD_LOGIC;
+ SPI1_MISO_O : out STD_LOGIC;
+ SPI1_MISO_T : out STD_LOGIC;
+ SPI1_SS_I : in STD_LOGIC;
+ SPI1_SS_O : out STD_LOGIC;
+ SPI1_SS1_O : out STD_LOGIC;
+ SPI1_SS2_O : out STD_LOGIC;
+ SPI1_SS_T : out STD_LOGIC;
+ UART0_DTRN : out STD_LOGIC;
+ UART0_RTSN : out STD_LOGIC;
+ UART0_TX : out STD_LOGIC;
+ UART0_CTSN : in STD_LOGIC;
+ UART0_DCDN : in STD_LOGIC;
+ UART0_DSRN : in STD_LOGIC;
+ UART0_RIN : in STD_LOGIC;
+ UART0_RX : in STD_LOGIC;
+ UART1_DTRN : out STD_LOGIC;
+ UART1_RTSN : out STD_LOGIC;
+ UART1_TX : out STD_LOGIC;
+ UART1_CTSN : in STD_LOGIC;
+ UART1_DCDN : in STD_LOGIC;
+ UART1_DSRN : in STD_LOGIC;
+ UART1_RIN : in STD_LOGIC;
+ UART1_RX : in STD_LOGIC;
+ TTC0_WAVE0_OUT : out STD_LOGIC;
+ TTC0_WAVE1_OUT : out STD_LOGIC;
+ TTC0_WAVE2_OUT : out STD_LOGIC;
+ TTC0_CLK0_IN : in STD_LOGIC;
+ TTC0_CLK1_IN : in STD_LOGIC;
+ TTC0_CLK2_IN : in STD_LOGIC;
+ TTC1_WAVE0_OUT : out STD_LOGIC;
+ TTC1_WAVE1_OUT : out STD_LOGIC;
+ TTC1_WAVE2_OUT : out STD_LOGIC;
+ TTC1_CLK0_IN : in STD_LOGIC;
+ TTC1_CLK1_IN : in STD_LOGIC;
+ TTC1_CLK2_IN : in STD_LOGIC;
+ WDT_CLK_IN : in STD_LOGIC;
+ WDT_RST_OUT : out STD_LOGIC;
+ TRACE_CLK : in STD_LOGIC;
+ TRACE_CTL : out STD_LOGIC;
+ TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ TRACE_CLK_OUT : out STD_LOGIC;
+ USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ USB0_VBUS_PWRSELECT : out STD_LOGIC;
+ USB0_VBUS_PWRFAULT : in STD_LOGIC;
+ USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ USB1_VBUS_PWRSELECT : out STD_LOGIC;
+ USB1_VBUS_PWRFAULT : in STD_LOGIC;
+ SRAM_INTIN : in STD_LOGIC;
+ M_AXI_GP0_ARESETN : out STD_LOGIC;
+ M_AXI_GP0_ARVALID : out STD_LOGIC;
+ M_AXI_GP0_AWVALID : out STD_LOGIC;
+ M_AXI_GP0_BREADY : out STD_LOGIC;
+ M_AXI_GP0_RREADY : out STD_LOGIC;
+ M_AXI_GP0_WLAST : out STD_LOGIC;
+ M_AXI_GP0_WVALID : out STD_LOGIC;
+ M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ACLK : in STD_LOGIC;
+ M_AXI_GP0_ARREADY : in STD_LOGIC;
+ M_AXI_GP0_AWREADY : in STD_LOGIC;
+ M_AXI_GP0_BVALID : in STD_LOGIC;
+ M_AXI_GP0_RLAST : in STD_LOGIC;
+ M_AXI_GP0_RVALID : in STD_LOGIC;
+ M_AXI_GP0_WREADY : in STD_LOGIC;
+ M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP1_ARESETN : out STD_LOGIC;
+ M_AXI_GP1_ARVALID : out STD_LOGIC;
+ M_AXI_GP1_AWVALID : out STD_LOGIC;
+ M_AXI_GP1_BREADY : out STD_LOGIC;
+ M_AXI_GP1_RREADY : out STD_LOGIC;
+ M_AXI_GP1_WLAST : out STD_LOGIC;
+ M_AXI_GP1_WVALID : out STD_LOGIC;
+ M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP1_ACLK : in STD_LOGIC;
+ M_AXI_GP1_ARREADY : in STD_LOGIC;
+ M_AXI_GP1_AWREADY : in STD_LOGIC;
+ M_AXI_GP1_BVALID : in STD_LOGIC;
+ M_AXI_GP1_RLAST : in STD_LOGIC;
+ M_AXI_GP1_RVALID : in STD_LOGIC;
+ M_AXI_GP1_WREADY : in STD_LOGIC;
+ M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP0_ARESETN : out STD_LOGIC;
+ S_AXI_GP0_ARREADY : out STD_LOGIC;
+ S_AXI_GP0_AWREADY : out STD_LOGIC;
+ S_AXI_GP0_BVALID : out STD_LOGIC;
+ S_AXI_GP0_RLAST : out STD_LOGIC;
+ S_AXI_GP0_RVALID : out STD_LOGIC;
+ S_AXI_GP0_WREADY : out STD_LOGIC;
+ S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP0_ACLK : in STD_LOGIC;
+ S_AXI_GP0_ARVALID : in STD_LOGIC;
+ S_AXI_GP0_AWVALID : in STD_LOGIC;
+ S_AXI_GP0_BREADY : in STD_LOGIC;
+ S_AXI_GP0_RREADY : in STD_LOGIC;
+ S_AXI_GP0_WLAST : in STD_LOGIC;
+ S_AXI_GP0_WVALID : in STD_LOGIC;
+ S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP1_ARESETN : out STD_LOGIC;
+ S_AXI_GP1_ARREADY : out STD_LOGIC;
+ S_AXI_GP1_AWREADY : out STD_LOGIC;
+ S_AXI_GP1_BVALID : out STD_LOGIC;
+ S_AXI_GP1_RLAST : out STD_LOGIC;
+ S_AXI_GP1_RVALID : out STD_LOGIC;
+ S_AXI_GP1_WREADY : out STD_LOGIC;
+ S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP1_ACLK : in STD_LOGIC;
+ S_AXI_GP1_ARVALID : in STD_LOGIC;
+ S_AXI_GP1_AWVALID : in STD_LOGIC;
+ S_AXI_GP1_BREADY : in STD_LOGIC;
+ S_AXI_GP1_RREADY : in STD_LOGIC;
+ S_AXI_GP1_WLAST : in STD_LOGIC;
+ S_AXI_GP1_WVALID : in STD_LOGIC;
+ S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_ACP_ARESETN : out STD_LOGIC;
+ S_AXI_ACP_ARREADY : out STD_LOGIC;
+ S_AXI_ACP_AWREADY : out STD_LOGIC;
+ S_AXI_ACP_BVALID : out STD_LOGIC;
+ S_AXI_ACP_RLAST : out STD_LOGIC;
+ S_AXI_ACP_RVALID : out STD_LOGIC;
+ S_AXI_ACP_WREADY : out STD_LOGIC;
+ S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_ACP_ACLK : in STD_LOGIC;
+ S_AXI_ACP_ARVALID : in STD_LOGIC;
+ S_AXI_ACP_AWVALID : in STD_LOGIC;
+ S_AXI_ACP_BREADY : in STD_LOGIC;
+ S_AXI_ACP_RREADY : in STD_LOGIC;
+ S_AXI_ACP_WLAST : in STD_LOGIC;
+ S_AXI_ACP_WVALID : in STD_LOGIC;
+ S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP0_ARESETN : out STD_LOGIC;
+ S_AXI_HP0_ARREADY : out STD_LOGIC;
+ S_AXI_HP0_AWREADY : out STD_LOGIC;
+ S_AXI_HP0_BVALID : out STD_LOGIC;
+ S_AXI_HP0_RLAST : out STD_LOGIC;
+ S_AXI_HP0_RVALID : out STD_LOGIC;
+ S_AXI_HP0_WREADY : out STD_LOGIC;
+ S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_ACLK : in STD_LOGIC;
+ S_AXI_HP0_ARVALID : in STD_LOGIC;
+ S_AXI_HP0_AWVALID : in STD_LOGIC;
+ S_AXI_HP0_BREADY : in STD_LOGIC;
+ S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP0_RREADY : in STD_LOGIC;
+ S_AXI_HP0_WLAST : in STD_LOGIC;
+ S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP0_WVALID : in STD_LOGIC;
+ S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP1_ARESETN : out STD_LOGIC;
+ S_AXI_HP1_ARREADY : out STD_LOGIC;
+ S_AXI_HP1_AWREADY : out STD_LOGIC;
+ S_AXI_HP1_BVALID : out STD_LOGIC;
+ S_AXI_HP1_RLAST : out STD_LOGIC;
+ S_AXI_HP1_RVALID : out STD_LOGIC;
+ S_AXI_HP1_WREADY : out STD_LOGIC;
+ S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_ACLK : in STD_LOGIC;
+ S_AXI_HP1_ARVALID : in STD_LOGIC;
+ S_AXI_HP1_AWVALID : in STD_LOGIC;
+ S_AXI_HP1_BREADY : in STD_LOGIC;
+ S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP1_RREADY : in STD_LOGIC;
+ S_AXI_HP1_WLAST : in STD_LOGIC;
+ S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP1_WVALID : in STD_LOGIC;
+ S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP2_ARESETN : out STD_LOGIC;
+ S_AXI_HP2_ARREADY : out STD_LOGIC;
+ S_AXI_HP2_AWREADY : out STD_LOGIC;
+ S_AXI_HP2_BVALID : out STD_LOGIC;
+ S_AXI_HP2_RLAST : out STD_LOGIC;
+ S_AXI_HP2_RVALID : out STD_LOGIC;
+ S_AXI_HP2_WREADY : out STD_LOGIC;
+ S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_ACLK : in STD_LOGIC;
+ S_AXI_HP2_ARVALID : in STD_LOGIC;
+ S_AXI_HP2_AWVALID : in STD_LOGIC;
+ S_AXI_HP2_BREADY : in STD_LOGIC;
+ S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP2_RREADY : in STD_LOGIC;
+ S_AXI_HP2_WLAST : in STD_LOGIC;
+ S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP2_WVALID : in STD_LOGIC;
+ S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP3_ARESETN : out STD_LOGIC;
+ S_AXI_HP3_ARREADY : out STD_LOGIC;
+ S_AXI_HP3_AWREADY : out STD_LOGIC;
+ S_AXI_HP3_BVALID : out STD_LOGIC;
+ S_AXI_HP3_RLAST : out STD_LOGIC;
+ S_AXI_HP3_RVALID : out STD_LOGIC;
+ S_AXI_HP3_WREADY : out STD_LOGIC;
+ S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_ACLK : in STD_LOGIC;
+ S_AXI_HP3_ARVALID : in STD_LOGIC;
+ S_AXI_HP3_AWVALID : in STD_LOGIC;
+ S_AXI_HP3_BREADY : in STD_LOGIC;
+ S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP3_RREADY : in STD_LOGIC;
+ S_AXI_HP3_WLAST : in STD_LOGIC;
+ S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
+ S_AXI_HP3_WVALID : in STD_LOGIC;
+ S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
+ IRQ_P2F_DMAC0 : out STD_LOGIC;
+ IRQ_P2F_DMAC1 : out STD_LOGIC;
+ IRQ_P2F_DMAC2 : out STD_LOGIC;
+ IRQ_P2F_DMAC3 : out STD_LOGIC;
+ IRQ_P2F_DMAC4 : out STD_LOGIC;
+ IRQ_P2F_DMAC5 : out STD_LOGIC;
+ IRQ_P2F_DMAC6 : out STD_LOGIC;
+ IRQ_P2F_DMAC7 : out STD_LOGIC;
+ IRQ_P2F_SMC : out STD_LOGIC;
+ IRQ_P2F_QSPI : out STD_LOGIC;
+ IRQ_P2F_CTI : out STD_LOGIC;
+ IRQ_P2F_GPIO : out STD_LOGIC;
+ IRQ_P2F_USB0 : out STD_LOGIC;
+ IRQ_P2F_ENET0 : out STD_LOGIC;
+ IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
+ IRQ_P2F_SDIO0 : out STD_LOGIC;
+ IRQ_P2F_I2C0 : out STD_LOGIC;
+ IRQ_P2F_SPI0 : out STD_LOGIC;
+ IRQ_P2F_UART0 : out STD_LOGIC;
+ IRQ_P2F_CAN0 : out STD_LOGIC;
+ IRQ_P2F_USB1 : out STD_LOGIC;
+ IRQ_P2F_ENET1 : out STD_LOGIC;
+ IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
+ IRQ_P2F_SDIO1 : out STD_LOGIC;
+ IRQ_P2F_I2C1 : out STD_LOGIC;
+ IRQ_P2F_SPI1 : out STD_LOGIC;
+ IRQ_P2F_UART1 : out STD_LOGIC;
+ IRQ_P2F_CAN1 : out STD_LOGIC;
+ IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Core0_nFIQ : in STD_LOGIC;
+ Core0_nIRQ : in STD_LOGIC;
+ Core1_nFIQ : in STD_LOGIC;
+ Core1_nIRQ : in STD_LOGIC;
+ DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA0_DAVALID : out STD_LOGIC;
+ DMA0_DRREADY : out STD_LOGIC;
+ DMA0_RSTN : out STD_LOGIC;
+ DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA1_DAVALID : out STD_LOGIC;
+ DMA1_DRREADY : out STD_LOGIC;
+ DMA1_RSTN : out STD_LOGIC;
+ DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA2_DAVALID : out STD_LOGIC;
+ DMA2_DRREADY : out STD_LOGIC;
+ DMA2_RSTN : out STD_LOGIC;
+ DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA3_DAVALID : out STD_LOGIC;
+ DMA3_DRREADY : out STD_LOGIC;
+ DMA3_RSTN : out STD_LOGIC;
+ DMA0_ACLK : in STD_LOGIC;
+ DMA0_DAREADY : in STD_LOGIC;
+ DMA0_DRLAST : in STD_LOGIC;
+ DMA0_DRVALID : in STD_LOGIC;
+ DMA1_ACLK : in STD_LOGIC;
+ DMA1_DAREADY : in STD_LOGIC;
+ DMA1_DRLAST : in STD_LOGIC;
+ DMA1_DRVALID : in STD_LOGIC;
+ DMA2_ACLK : in STD_LOGIC;
+ DMA2_DAREADY : in STD_LOGIC;
+ DMA2_DRLAST : in STD_LOGIC;
+ DMA2_DRVALID : in STD_LOGIC;
+ DMA3_ACLK : in STD_LOGIC;
+ DMA3_DAREADY : in STD_LOGIC;
+ DMA3_DRLAST : in STD_LOGIC;
+ DMA3_DRVALID : in STD_LOGIC;
+ DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ FCLK_CLK3 : out STD_LOGIC;
+ FCLK_CLK2 : out STD_LOGIC;
+ FCLK_CLK1 : out STD_LOGIC;
+ FCLK_CLK0 : out STD_LOGIC;
+ FCLK_CLKTRIG3_N : in STD_LOGIC;
+ FCLK_CLKTRIG2_N : in STD_LOGIC;
+ FCLK_CLKTRIG1_N : in STD_LOGIC;
+ FCLK_CLKTRIG0_N : in STD_LOGIC;
+ FCLK_RESET3_N : out STD_LOGIC;
+ FCLK_RESET2_N : out STD_LOGIC;
+ FCLK_RESET1_N : out STD_LOGIC;
+ FCLK_RESET0_N : out STD_LOGIC;
+ FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ FTMD_TRACEIN_VALID : in STD_LOGIC;
+ FTMD_TRACEIN_CLK : in STD_LOGIC;
+ FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ FTMT_F2P_TRIG_0 : in STD_LOGIC;
+ FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
+ FTMT_F2P_TRIG_1 : in STD_LOGIC;
+ FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
+ FTMT_F2P_TRIG_2 : in STD_LOGIC;
+ FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
+ FTMT_F2P_TRIG_3 : in STD_LOGIC;
+ FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
+ FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
+ FTMT_P2F_TRIG_0 : out STD_LOGIC;
+ FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
+ FTMT_P2F_TRIG_1 : out STD_LOGIC;
+ FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
+ FTMT_P2F_TRIG_2 : out STD_LOGIC;
+ FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
+ FTMT_P2F_TRIG_3 : out STD_LOGIC;
+ FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ FPGA_IDLE_N : in STD_LOGIC;
+ EVENT_EVENTO : out STD_LOGIC;
+ EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ EVENT_EVENTI : in STD_LOGIC;
+ DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ DDR_CAS_n : inout STD_LOGIC;
+ DDR_CKE : inout STD_LOGIC;
+ DDR_Clk_n : inout STD_LOGIC;
+ DDR_Clk : inout STD_LOGIC;
+ DDR_CS_n : inout STD_LOGIC;
+ DDR_DRSTB : inout STD_LOGIC;
+ DDR_ODT : inout STD_LOGIC;
+ DDR_RAS_n : inout STD_LOGIC;
+ DDR_WEB : inout STD_LOGIC;
+ DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_VRN : inout STD_LOGIC;
+ DDR_VRP : inout STD_LOGIC;
+ DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ PS_SRSTB : inout STD_LOGIC;
+ PS_CLK : inout STD_LOGIC;
+ PS_PORB : inout STD_LOGIC
+ );
+ attribute C_DM_WIDTH : integer;
+ attribute C_DM_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
+ attribute C_DQS_WIDTH : integer;
+ attribute C_DQS_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
+ attribute C_DQ_WIDTH : integer;
+ attribute C_DQ_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
+ attribute C_EMIO_GPIO_WIDTH : integer;
+ attribute C_EMIO_GPIO_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
+ attribute C_EN_EMIO_ENET0 : integer;
+ attribute C_EN_EMIO_ENET0 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_EN_EMIO_ENET1 : integer;
+ attribute C_EN_EMIO_ENET1 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_EN_EMIO_PJTAG : integer;
+ attribute C_EN_EMIO_PJTAG of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_EN_EMIO_TRACE : integer;
+ attribute C_EN_EMIO_TRACE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_FCLK_CLK0_BUF : string;
+ attribute C_FCLK_CLK0_BUF of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
+ attribute C_FCLK_CLK1_BUF : string;
+ attribute C_FCLK_CLK1_BUF of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
+ attribute C_FCLK_CLK2_BUF : string;
+ attribute C_FCLK_CLK2_BUF of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
+ attribute C_FCLK_CLK3_BUF : string;
+ attribute C_FCLK_CLK3_BUF of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
+ attribute C_GP0_EN_MODIFIABLE_TXN : integer;
+ attribute C_GP0_EN_MODIFIABLE_TXN of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
+ attribute C_GP1_EN_MODIFIABLE_TXN : integer;
+ attribute C_GP1_EN_MODIFIABLE_TXN of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
+ attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
+ attribute C_INCLUDE_ACP_TRANS_CHECK of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_INCLUDE_TRACE_BUFFER : integer;
+ attribute C_INCLUDE_TRACE_BUFFER of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_IRQ_F2P_MODE : string;
+ attribute C_IRQ_F2P_MODE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
+ attribute C_MIO_PRIMITIVE : integer;
+ attribute C_MIO_PRIMITIVE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
+ attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
+ attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_M_AXI_GP0_ID_WIDTH : integer;
+ attribute C_M_AXI_GP0_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
+ attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
+ attribute C_M_AXI_GP0_THREAD_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
+ attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
+ attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_M_AXI_GP1_ID_WIDTH : integer;
+ attribute C_M_AXI_GP1_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
+ attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
+ attribute C_M_AXI_GP1_THREAD_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
+ attribute C_NUM_F2P_INTR_INPUTS : integer;
+ attribute C_NUM_F2P_INTR_INPUTS of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
+ attribute C_PACKAGE_NAME : string;
+ attribute C_PACKAGE_NAME of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
+ attribute C_PS7_SI_REV : string;
+ attribute C_PS7_SI_REV of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
+ attribute C_S_AXI_ACP_ARUSER_VAL : integer;
+ attribute C_S_AXI_ACP_ARUSER_VAL of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
+ attribute C_S_AXI_ACP_AWUSER_VAL : integer;
+ attribute C_S_AXI_ACP_AWUSER_VAL of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
+ attribute C_S_AXI_ACP_ID_WIDTH : integer;
+ attribute C_S_AXI_ACP_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
+ attribute C_S_AXI_GP0_ID_WIDTH : integer;
+ attribute C_S_AXI_GP0_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_S_AXI_GP1_ID_WIDTH : integer;
+ attribute C_S_AXI_GP1_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_S_AXI_HP0_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP0_DATA_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
+ attribute C_S_AXI_HP0_ID_WIDTH : integer;
+ attribute C_S_AXI_HP0_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_S_AXI_HP1_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP1_DATA_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
+ attribute C_S_AXI_HP1_ID_WIDTH : integer;
+ attribute C_S_AXI_HP1_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_S_AXI_HP2_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP2_DATA_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
+ attribute C_S_AXI_HP2_ID_WIDTH : integer;
+ attribute C_S_AXI_HP2_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_S_AXI_HP3_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP3_DATA_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
+ attribute C_S_AXI_HP3_ID_WIDTH : integer;
+ attribute C_S_AXI_HP3_ID_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
+ attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
+ attribute C_TRACE_BUFFER_CLOCK_DELAY of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
+ attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
+ attribute C_TRACE_BUFFER_FIFO_SIZE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
+ attribute C_TRACE_INTERNAL_WIDTH : integer;
+ attribute C_TRACE_INTERNAL_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
+ attribute C_TRACE_PIPELINE_WIDTH : integer;
+ attribute C_TRACE_PIPELINE_WIDTH of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
+ attribute C_USE_AXI_NONSECURE : integer;
+ attribute C_USE_AXI_NONSECURE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
+ attribute C_USE_DEFAULT_ACP_USER_VAL of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_M_AXI_GP0 : integer;
+ attribute C_USE_M_AXI_GP0 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
+ attribute C_USE_M_AXI_GP1 : integer;
+ attribute C_USE_M_AXI_GP1 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_ACP : integer;
+ attribute C_USE_S_AXI_ACP of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_GP0 : integer;
+ attribute C_USE_S_AXI_GP0 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_GP1 : integer;
+ attribute C_USE_S_AXI_GP1 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_HP0 : integer;
+ attribute C_USE_S_AXI_HP0 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_HP1 : integer;
+ attribute C_USE_S_AXI_HP1 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_HP2 : integer;
+ attribute C_USE_S_AXI_HP2 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute C_USE_S_AXI_HP3 : integer;
+ attribute C_USE_S_AXI_HP3 of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+ attribute HW_HANDOFF : string;
+ attribute HW_HANDOFF of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TopLevel_processing_system7_0_0.hwdef";
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
+ attribute POWER : string;
+ attribute POWER of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
+ attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
+ attribute USE_TRACE_DATA_EDGE_DETECTOR of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
+end TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7;
+
+architecture STRUCTURE of TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
+ signal \<const0>\ : STD_LOGIC;
+ signal \<const1>\ : STD_LOGIC;
+ signal ENET0_MDIO_T_n : STD_LOGIC;
+ signal ENET1_MDIO_T_n : STD_LOGIC;
+ signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal I2C0_SCL_T_n : STD_LOGIC;
+ signal I2C0_SDA_T_n : STD_LOGIC;
+ signal I2C1_SCL_T_n : STD_LOGIC;
+ signal I2C1_SDA_T_n : STD_LOGIC;
+ signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal SDIO0_CMD_T_n : STD_LOGIC;
+ signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal SDIO1_CMD_T_n : STD_LOGIC;
+ signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal SPI0_MISO_T_n : STD_LOGIC;
+ signal SPI0_MOSI_T_n : STD_LOGIC;
+ signal SPI0_SCLK_T_n : STD_LOGIC;
+ signal SPI0_SS_T_n : STD_LOGIC;
+ signal SPI1_MISO_T_n : STD_LOGIC;
+ signal SPI1_MOSI_T_n : STD_LOGIC;
+ signal SPI1_SCLK_T_n : STD_LOGIC;
+ signal SPI1_SS_T_n : STD_LOGIC;
+ signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
+ signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
+ attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
+ signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
+ signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
+ signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal buffered_DDR_CAS_n : STD_LOGIC;
+ signal buffered_DDR_CKE : STD_LOGIC;
+ signal buffered_DDR_CS_n : STD_LOGIC;
+ signal buffered_DDR_Clk : STD_LOGIC;
+ signal buffered_DDR_Clk_n : STD_LOGIC;
+ signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal buffered_DDR_DRSTB : STD_LOGIC;
+ signal buffered_DDR_ODT : STD_LOGIC;
+ signal buffered_DDR_RAS_n : STD_LOGIC;
+ signal buffered_DDR_VRN : STD_LOGIC;
+ signal buffered_DDR_VRP : STD_LOGIC;
+ signal buffered_DDR_WEB : STD_LOGIC;
+ signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
+ signal buffered_PS_CLK : STD_LOGIC;
+ signal buffered_PS_PORB : STD_LOGIC;
+ signal buffered_PS_SRSTB : STD_LOGIC;
+ signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
+ signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
+ attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
+ attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
+begin
+ ENET0_GMII_TXD(7) <= \<const0>\;
+ ENET0_GMII_TXD(6) <= \<const0>\;
+ ENET0_GMII_TXD(5) <= \<const0>\;
+ ENET0_GMII_TXD(4) <= \<const0>\;
+ ENET0_GMII_TXD(3) <= \<const0>\;
+ ENET0_GMII_TXD(2) <= \<const0>\;
+ ENET0_GMII_TXD(1) <= \<const0>\;
+ ENET0_GMII_TXD(0) <= \<const0>\;
+ ENET0_GMII_TX_EN <= \<const0>\;
+ ENET0_GMII_TX_ER <= \<const0>\;
+ ENET1_GMII_TXD(7) <= \<const0>\;
+ ENET1_GMII_TXD(6) <= \<const0>\;
+ ENET1_GMII_TXD(5) <= \<const0>\;
+ ENET1_GMII_TXD(4) <= \<const0>\;
+ ENET1_GMII_TXD(3) <= \<const0>\;
+ ENET1_GMII_TXD(2) <= \<const0>\;
+ ENET1_GMII_TXD(1) <= \<const0>\;
+ ENET1_GMII_TXD(0) <= \<const0>\;
+ ENET1_GMII_TX_EN <= \<const0>\;
+ ENET1_GMII_TX_ER <= \<const0>\;
+ M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
+ M_AXI_GP0_ARCACHE(1) <= \<const1>\;
+ M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
+ M_AXI_GP0_ARSIZE(2) <= \<const0>\;
+ M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
+ M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
+ M_AXI_GP0_AWCACHE(1) <= \<const1>\;
+ M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
+ M_AXI_GP0_AWSIZE(2) <= \<const0>\;
+ M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
+ M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
+ M_AXI_GP1_ARCACHE(1) <= \<const1>\;
+ M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
+ M_AXI_GP1_ARSIZE(2) <= \<const0>\;
+ M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
+ M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
+ M_AXI_GP1_AWCACHE(1) <= \<const1>\;
+ M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
+ M_AXI_GP1_AWSIZE(2) <= \<const0>\;
+ M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
+ PJTAG_TDO <= \<const0>\;
+ TRACE_CLK_OUT <= \<const0>\;
+ TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
+ TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
+DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_CAS_n,
+ PAD => DDR_CAS_n
+ );
+DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_CKE,
+ PAD => DDR_CKE
+ );
+DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_CS_n,
+ PAD => DDR_CS_n
+ );
+DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Clk,
+ PAD => DDR_Clk
+ );
+DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Clk_n,
+ PAD => DDR_Clk_n
+ );
+DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DRSTB,
+ PAD => DDR_DRSTB
+ );
+DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_ODT,
+ PAD => DDR_ODT
+ );
+DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_RAS_n,
+ PAD => DDR_RAS_n
+ );
+DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_VRN,
+ PAD => DDR_VRN
+ );
+DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_VRP,
+ PAD => DDR_VRP
+ );
+DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_WEB,
+ PAD => DDR_WEB
+ );
+ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => ENET0_MDIO_T_n,
+ O => ENET0_MDIO_T
+ );
+ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => ENET1_MDIO_T_n,
+ O => ENET1_MDIO_T
+ );
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(0),
+ O => GPIO_T(0)
+ );
+\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(10),
+ O => GPIO_T(10)
+ );
+\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(11),
+ O => GPIO_T(11)
+ );
+\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(12),
+ O => GPIO_T(12)
+ );
+\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(13),
+ O => GPIO_T(13)
+ );
+\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(14),
+ O => GPIO_T(14)
+ );
+\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(15),
+ O => GPIO_T(15)
+ );
+\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(16),
+ O => GPIO_T(16)
+ );
+\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(17),
+ O => GPIO_T(17)
+ );
+\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(18),
+ O => GPIO_T(18)
+ );
+\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(19),
+ O => GPIO_T(19)
+ );
+\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(1),
+ O => GPIO_T(1)
+ );
+\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(20),
+ O => GPIO_T(20)
+ );
+\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(21),
+ O => GPIO_T(21)
+ );
+\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(22),
+ O => GPIO_T(22)
+ );
+\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(23),
+ O => GPIO_T(23)
+ );
+\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(24),
+ O => GPIO_T(24)
+ );
+\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(25),
+ O => GPIO_T(25)
+ );
+\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(26),
+ O => GPIO_T(26)
+ );
+\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(27),
+ O => GPIO_T(27)
+ );
+\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(28),
+ O => GPIO_T(28)
+ );
+\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(29),
+ O => GPIO_T(29)
+ );
+\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(2),
+ O => GPIO_T(2)
+ );
+\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(30),
+ O => GPIO_T(30)
+ );
+\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(31),
+ O => GPIO_T(31)
+ );
+\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(32),
+ O => GPIO_T(32)
+ );
+\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(33),
+ O => GPIO_T(33)
+ );
+\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(34),
+ O => GPIO_T(34)
+ );
+\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(35),
+ O => GPIO_T(35)
+ );
+\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(36),
+ O => GPIO_T(36)
+ );
+\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(37),
+ O => GPIO_T(37)
+ );
+\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(38),
+ O => GPIO_T(38)
+ );
+\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(39),
+ O => GPIO_T(39)
+ );
+\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(3),
+ O => GPIO_T(3)
+ );
+\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(40),
+ O => GPIO_T(40)
+ );
+\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(41),
+ O => GPIO_T(41)
+ );
+\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(42),
+ O => GPIO_T(42)
+ );
+\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(43),
+ O => GPIO_T(43)
+ );
+\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(44),
+ O => GPIO_T(44)
+ );
+\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(45),
+ O => GPIO_T(45)
+ );
+\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(46),
+ O => GPIO_T(46)
+ );
+\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(47),
+ O => GPIO_T(47)
+ );
+\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(48),
+ O => GPIO_T(48)
+ );
+\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(49),
+ O => GPIO_T(49)
+ );
+\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(4),
+ O => GPIO_T(4)
+ );
+\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(50),
+ O => GPIO_T(50)
+ );
+\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(51),
+ O => GPIO_T(51)
+ );
+\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(52),
+ O => GPIO_T(52)
+ );
+\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(53),
+ O => GPIO_T(53)
+ );
+\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(54),
+ O => GPIO_T(54)
+ );
+\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(55),
+ O => GPIO_T(55)
+ );
+\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(56),
+ O => GPIO_T(56)
+ );
+\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(57),
+ O => GPIO_T(57)
+ );
+\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(58),
+ O => GPIO_T(58)
+ );
+\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(59),
+ O => GPIO_T(59)
+ );
+\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(5),
+ O => GPIO_T(5)
+ );
+\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(60),
+ O => GPIO_T(60)
+ );
+\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(61),
+ O => GPIO_T(61)
+ );
+\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(62),
+ O => GPIO_T(62)
+ );
+\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(63),
+ O => GPIO_T(63)
+ );
+\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(6),
+ O => GPIO_T(6)
+ );
+\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(7),
+ O => GPIO_T(7)
+ );
+\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(8),
+ O => GPIO_T(8)
+ );
+\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => gpio_out_t_n(9),
+ O => GPIO_T(9)
+ );
+I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => I2C0_SCL_T_n,
+ O => I2C0_SCL_T
+ );
+I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => I2C0_SDA_T_n,
+ O => I2C0_SDA_T
+ );
+I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => I2C1_SCL_T_n,
+ O => I2C1_SCL_T
+ );
+I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => I2C1_SDA_T_n,
+ O => I2C1_SDA_T
+ );
+PS7_i: unisim.vcomponents.PS7
+ port map (
+ DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
+ DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
+ DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
+ DDRCASB => buffered_DDR_CAS_n,
+ DDRCKE => buffered_DDR_CKE,
+ DDRCKN => buffered_DDR_Clk_n,
+ DDRCKP => buffered_DDR_Clk,
+ DDRCSB => buffered_DDR_CS_n,
+ DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
+ DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
+ DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
+ DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
+ DDRDRSTB => buffered_DDR_DRSTB,
+ DDRODT => buffered_DDR_ODT,
+ DDRRASB => buffered_DDR_RAS_n,
+ DDRVRN => buffered_DDR_VRN,
+ DDRVRP => buffered_DDR_VRP,
+ DDRWEB => buffered_DDR_WEB,
+ DMA0ACLK => DMA0_ACLK,
+ DMA0DAREADY => DMA0_DAREADY,
+ DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
+ DMA0DAVALID => DMA0_DAVALID,
+ DMA0DRLAST => DMA0_DRLAST,
+ DMA0DRREADY => DMA0_DRREADY,
+ DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
+ DMA0DRVALID => DMA0_DRVALID,
+ DMA0RSTN => DMA0_RSTN,
+ DMA1ACLK => DMA1_ACLK,
+ DMA1DAREADY => DMA1_DAREADY,
+ DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
+ DMA1DAVALID => DMA1_DAVALID,
+ DMA1DRLAST => DMA1_DRLAST,
+ DMA1DRREADY => DMA1_DRREADY,
+ DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
+ DMA1DRVALID => DMA1_DRVALID,
+ DMA1RSTN => DMA1_RSTN,
+ DMA2ACLK => DMA2_ACLK,
+ DMA2DAREADY => DMA2_DAREADY,
+ DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
+ DMA2DAVALID => DMA2_DAVALID,
+ DMA2DRLAST => DMA2_DRLAST,
+ DMA2DRREADY => DMA2_DRREADY,
+ DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
+ DMA2DRVALID => DMA2_DRVALID,
+ DMA2RSTN => DMA2_RSTN,
+ DMA3ACLK => DMA3_ACLK,
+ DMA3DAREADY => DMA3_DAREADY,
+ DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
+ DMA3DAVALID => DMA3_DAVALID,
+ DMA3DRLAST => DMA3_DRLAST,
+ DMA3DRREADY => DMA3_DRREADY,
+ DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
+ DMA3DRVALID => DMA3_DRVALID,
+ DMA3RSTN => DMA3_RSTN,
+ EMIOCAN0PHYRX => CAN0_PHY_RX,
+ EMIOCAN0PHYTX => CAN0_PHY_TX,
+ EMIOCAN1PHYRX => CAN1_PHY_RX,
+ EMIOCAN1PHYTX => CAN1_PHY_TX,
+ EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
+ EMIOENET0GMIICOL => '0',
+ EMIOENET0GMIICRS => '0',
+ EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
+ EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
+ EMIOENET0GMIIRXDV => '0',
+ EMIOENET0GMIIRXER => '0',
+ EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
+ EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
+ EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
+ EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
+ EMIOENET0MDIOI => ENET0_MDIO_I,
+ EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
+ EMIOENET0MDIOO => ENET0_MDIO_O,
+ EMIOENET0MDIOTN => ENET0_MDIO_T_n,
+ EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
+ EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
+ EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
+ EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
+ EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
+ EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
+ EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
+ EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
+ EMIOENET0SOFRX => ENET0_SOF_RX,
+ EMIOENET0SOFTX => ENET0_SOF_TX,
+ EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
+ EMIOENET1GMIICOL => '0',
+ EMIOENET1GMIICRS => '0',
+ EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
+ EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
+ EMIOENET1GMIIRXDV => '0',
+ EMIOENET1GMIIRXER => '0',
+ EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
+ EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
+ EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
+ EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
+ EMIOENET1MDIOI => ENET1_MDIO_I,
+ EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
+ EMIOENET1MDIOO => ENET1_MDIO_O,
+ EMIOENET1MDIOTN => ENET1_MDIO_T_n,
+ EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
+ EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
+ EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
+ EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
+ EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
+ EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
+ EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
+ EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
+ EMIOENET1SOFRX => ENET1_SOF_RX,
+ EMIOENET1SOFTX => ENET1_SOF_TX,
+ EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
+ EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
+ EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
+ EMIOI2C0SCLI => I2C0_SCL_I,
+ EMIOI2C0SCLO => I2C0_SCL_O,
+ EMIOI2C0SCLTN => I2C0_SCL_T_n,
+ EMIOI2C0SDAI => I2C0_SDA_I,
+ EMIOI2C0SDAO => I2C0_SDA_O,
+ EMIOI2C0SDATN => I2C0_SDA_T_n,
+ EMIOI2C1SCLI => I2C1_SCL_I,
+ EMIOI2C1SCLO => I2C1_SCL_O,
+ EMIOI2C1SCLTN => I2C1_SCL_T_n,
+ EMIOI2C1SDAI => I2C1_SDA_I,
+ EMIOI2C1SDAO => I2C1_SDA_O,
+ EMIOI2C1SDATN => I2C1_SDA_T_n,
+ EMIOPJTAGTCK => PJTAG_TCK,
+ EMIOPJTAGTDI => PJTAG_TDI,
+ EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
+ EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
+ EMIOPJTAGTMS => PJTAG_TMS,
+ EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
+ EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
+ EMIOSDIO0CDN => SDIO0_CDN,
+ EMIOSDIO0CLK => SDIO0_CLK,
+ EMIOSDIO0CLKFB => SDIO0_CLK_FB,
+ EMIOSDIO0CMDI => SDIO0_CMD_I,
+ EMIOSDIO0CMDO => SDIO0_CMD_O,
+ EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
+ EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
+ EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
+ EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
+ EMIOSDIO0LED => SDIO0_LED,
+ EMIOSDIO0WP => SDIO0_WP,
+ EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
+ EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
+ EMIOSDIO1CDN => SDIO1_CDN,
+ EMIOSDIO1CLK => SDIO1_CLK,
+ EMIOSDIO1CLKFB => SDIO1_CLK_FB,
+ EMIOSDIO1CMDI => SDIO1_CMD_I,
+ EMIOSDIO1CMDO => SDIO1_CMD_O,
+ EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
+ EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
+ EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
+ EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
+ EMIOSDIO1LED => SDIO1_LED,
+ EMIOSDIO1WP => SDIO1_WP,
+ EMIOSPI0MI => SPI0_MISO_I,
+ EMIOSPI0MO => SPI0_MOSI_O,
+ EMIOSPI0MOTN => SPI0_MOSI_T_n,
+ EMIOSPI0SCLKI => SPI0_SCLK_I,
+ EMIOSPI0SCLKO => SPI0_SCLK_O,
+ EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
+ EMIOSPI0SI => SPI0_MOSI_I,
+ EMIOSPI0SO => SPI0_MISO_O,
+ EMIOSPI0SSIN => SPI0_SS_I,
+ EMIOSPI0SSNTN => SPI0_SS_T_n,
+ EMIOSPI0SSON(2) => SPI0_SS2_O,
+ EMIOSPI0SSON(1) => SPI0_SS1_O,
+ EMIOSPI0SSON(0) => SPI0_SS_O,
+ EMIOSPI0STN => SPI0_MISO_T_n,
+ EMIOSPI1MI => SPI1_MISO_I,
+ EMIOSPI1MO => SPI1_MOSI_O,
+ EMIOSPI1MOTN => SPI1_MOSI_T_n,
+ EMIOSPI1SCLKI => SPI1_SCLK_I,
+ EMIOSPI1SCLKO => SPI1_SCLK_O,
+ EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
+ EMIOSPI1SI => SPI1_MOSI_I,
+ EMIOSPI1SO => SPI1_MISO_O,
+ EMIOSPI1SSIN => SPI1_SS_I,
+ EMIOSPI1SSNTN => SPI1_SS_T_n,
+ EMIOSPI1SSON(2) => SPI1_SS2_O,
+ EMIOSPI1SSON(1) => SPI1_SS1_O,
+ EMIOSPI1SSON(0) => SPI1_SS_O,
+ EMIOSPI1STN => SPI1_MISO_T_n,
+ EMIOSRAMINTIN => SRAM_INTIN,
+ EMIOTRACECLK => TRACE_CLK,
+ EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
+ EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
+ EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
+ EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
+ EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
+ EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
+ EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
+ EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
+ EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
+ EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
+ EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
+ EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
+ EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
+ EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
+ EMIOUART0CTSN => UART0_CTSN,
+ EMIOUART0DCDN => UART0_DCDN,
+ EMIOUART0DSRN => UART0_DSRN,
+ EMIOUART0DTRN => UART0_DTRN,
+ EMIOUART0RIN => UART0_RIN,
+ EMIOUART0RTSN => UART0_RTSN,
+ EMIOUART0RX => UART0_RX,
+ EMIOUART0TX => UART0_TX,
+ EMIOUART1CTSN => UART1_CTSN,
+ EMIOUART1DCDN => UART1_DCDN,
+ EMIOUART1DSRN => UART1_DSRN,
+ EMIOUART1DTRN => UART1_DTRN,
+ EMIOUART1RIN => UART1_RIN,
+ EMIOUART1RTSN => UART1_RTSN,
+ EMIOUART1RX => UART1_RX,
+ EMIOUART1TX => UART1_TX,
+ EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
+ EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
+ EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
+ EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
+ EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
+ EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
+ EMIOWDTCLKI => WDT_CLK_IN,
+ EMIOWDTRSTO => WDT_RST_OUT,
+ EVENTEVENTI => EVENT_EVENTI,
+ EVENTEVENTO => EVENT_EVENTO,
+ EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
+ EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
+ FCLKCLK(3) => FCLK_CLK3,
+ FCLKCLK(2) => FCLK_CLK2,
+ FCLKCLK(1) => FCLK_CLK1,
+ FCLKCLK(0) => FCLK_CLK_unbuffered(0),
+ FCLKCLKTRIGN(3 downto 0) => B"0000",
+ FCLKRESETN(3) => FCLK_RESET3_N,
+ FCLKRESETN(2) => FCLK_RESET2_N,
+ FCLKRESETN(1) => FCLK_RESET1_N,
+ FCLKRESETN(0) => FCLK_RESET0_N,
+ FPGAIDLEN => FPGA_IDLE_N,
+ FTMDTRACEINATID(3 downto 0) => B"0000",
+ FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
+ FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
+ FTMDTRACEINVALID => '0',
+ FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
+ FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
+ FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
+ FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
+ FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
+ FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
+ FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
+ FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
+ FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
+ FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
+ FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
+ FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
+ FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
+ FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
+ FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
+ FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
+ FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
+ FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
+ IRQF2P(19) => Core1_nFIQ,
+ IRQF2P(18) => Core0_nFIQ,
+ IRQF2P(17) => Core1_nIRQ,
+ IRQF2P(16) => Core0_nIRQ,
+ IRQF2P(15 downto 1) => B"000000000000000",
+ IRQF2P(0) => IRQ_F2P(0),
+ IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
+ IRQP2F(27) => IRQ_P2F_DMAC7,
+ IRQP2F(26) => IRQ_P2F_DMAC6,
+ IRQP2F(25) => IRQ_P2F_DMAC5,
+ IRQP2F(24) => IRQ_P2F_DMAC4,
+ IRQP2F(23) => IRQ_P2F_DMAC3,
+ IRQP2F(22) => IRQ_P2F_DMAC2,
+ IRQP2F(21) => IRQ_P2F_DMAC1,
+ IRQP2F(20) => IRQ_P2F_DMAC0,
+ IRQP2F(19) => IRQ_P2F_SMC,
+ IRQP2F(18) => IRQ_P2F_QSPI,
+ IRQP2F(17) => IRQ_P2F_CTI,
+ IRQP2F(16) => IRQ_P2F_GPIO,
+ IRQP2F(15) => IRQ_P2F_USB0,
+ IRQP2F(14) => IRQ_P2F_ENET0,
+ IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
+ IRQP2F(12) => IRQ_P2F_SDIO0,
+ IRQP2F(11) => IRQ_P2F_I2C0,
+ IRQP2F(10) => IRQ_P2F_SPI0,
+ IRQP2F(9) => IRQ_P2F_UART0,
+ IRQP2F(8) => IRQ_P2F_CAN0,
+ IRQP2F(7) => IRQ_P2F_USB1,
+ IRQP2F(6) => IRQ_P2F_ENET1,
+ IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
+ IRQP2F(4) => IRQ_P2F_SDIO1,
+ IRQP2F(3) => IRQ_P2F_I2C1,
+ IRQP2F(2) => IRQ_P2F_SPI1,
+ IRQP2F(1) => IRQ_P2F_UART1,
+ IRQP2F(0) => IRQ_P2F_CAN1,
+ MAXIGP0ACLK => M_AXI_GP0_ACLK,
+ MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
+ MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
+ MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
+ MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
+ MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
+ MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
+ MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
+ MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
+ MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
+ MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
+ MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
+ MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
+ MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
+ MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
+ MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
+ MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
+ MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
+ MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
+ MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
+ MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
+ MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
+ MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
+ MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
+ MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
+ MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
+ MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
+ MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
+ MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
+ MAXIGP0BREADY => M_AXI_GP0_BREADY,
+ MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
+ MAXIGP0BVALID => M_AXI_GP0_BVALID,
+ MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
+ MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
+ MAXIGP0RLAST => M_AXI_GP0_RLAST,
+ MAXIGP0RREADY => M_AXI_GP0_RREADY,
+ MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
+ MAXIGP0RVALID => M_AXI_GP0_RVALID,
+ MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
+ MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
+ MAXIGP0WLAST => M_AXI_GP0_WLAST,
+ MAXIGP0WREADY => M_AXI_GP0_WREADY,
+ MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
+ MAXIGP0WVALID => M_AXI_GP0_WVALID,
+ MAXIGP1ACLK => M_AXI_GP1_ACLK,
+ MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
+ MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
+ MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
+ MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
+ MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
+ MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
+ MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
+ MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
+ MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
+ MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
+ MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
+ MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
+ MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
+ MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
+ MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
+ MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
+ MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
+ MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
+ MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
+ MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
+ MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
+ MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
+ MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
+ MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
+ MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
+ MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
+ MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
+ MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
+ MAXIGP1BREADY => M_AXI_GP1_BREADY,
+ MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
+ MAXIGP1BVALID => M_AXI_GP1_BVALID,
+ MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
+ MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
+ MAXIGP1RLAST => M_AXI_GP1_RLAST,
+ MAXIGP1RREADY => M_AXI_GP1_RREADY,
+ MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
+ MAXIGP1RVALID => M_AXI_GP1_RVALID,
+ MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
+ MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
+ MAXIGP1WLAST => M_AXI_GP1_WLAST,
+ MAXIGP1WREADY => M_AXI_GP1_WREADY,
+ MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
+ MAXIGP1WVALID => M_AXI_GP1_WVALID,
+ MIO(53 downto 0) => buffered_MIO(53 downto 0),
+ PSCLK => buffered_PS_CLK,
+ PSPORB => buffered_PS_PORB,
+ PSSRSTB => buffered_PS_SRSTB,
+ SAXIACPACLK => S_AXI_ACP_ACLK,
+ SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
+ SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
+ SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
+ SAXIACPARESETN => S_AXI_ACP_ARESETN,
+ SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
+ SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
+ SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
+ SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
+ SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
+ SAXIACPARREADY => S_AXI_ACP_ARREADY,
+ SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
+ SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
+ SAXIACPARVALID => S_AXI_ACP_ARVALID,
+ SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
+ SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
+ SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
+ SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
+ SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
+ SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
+ SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
+ SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
+ SAXIACPAWREADY => S_AXI_ACP_AWREADY,
+ SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
+ SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
+ SAXIACPAWVALID => S_AXI_ACP_AWVALID,
+ SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
+ SAXIACPBREADY => S_AXI_ACP_BREADY,
+ SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
+ SAXIACPBVALID => S_AXI_ACP_BVALID,
+ SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
+ SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
+ SAXIACPRLAST => S_AXI_ACP_RLAST,
+ SAXIACPRREADY => S_AXI_ACP_RREADY,
+ SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
+ SAXIACPRVALID => S_AXI_ACP_RVALID,
+ SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
+ SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
+ SAXIACPWLAST => S_AXI_ACP_WLAST,
+ SAXIACPWREADY => S_AXI_ACP_WREADY,
+ SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
+ SAXIACPWVALID => S_AXI_ACP_WVALID,
+ SAXIGP0ACLK => S_AXI_GP0_ACLK,
+ SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
+ SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
+ SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
+ SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
+ SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
+ SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
+ SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
+ SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
+ SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
+ SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
+ SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
+ SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
+ SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
+ SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
+ SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
+ SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
+ SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
+ SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
+ SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
+ SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
+ SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
+ SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
+ SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
+ SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
+ SAXIGP0BREADY => S_AXI_GP0_BREADY,
+ SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
+ SAXIGP0BVALID => S_AXI_GP0_BVALID,
+ SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
+ SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
+ SAXIGP0RLAST => S_AXI_GP0_RLAST,
+ SAXIGP0RREADY => S_AXI_GP0_RREADY,
+ SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
+ SAXIGP0RVALID => S_AXI_GP0_RVALID,
+ SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
+ SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
+ SAXIGP0WLAST => S_AXI_GP0_WLAST,
+ SAXIGP0WREADY => S_AXI_GP0_WREADY,
+ SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
+ SAXIGP0WVALID => S_AXI_GP0_WVALID,
+ SAXIGP1ACLK => S_AXI_GP1_ACLK,
+ SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
+ SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
+ SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
+ SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
+ SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
+ SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
+ SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
+ SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
+ SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
+ SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
+ SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
+ SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
+ SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
+ SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
+ SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
+ SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
+ SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
+ SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
+ SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
+ SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
+ SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
+ SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
+ SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
+ SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
+ SAXIGP1BREADY => S_AXI_GP1_BREADY,
+ SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
+ SAXIGP1BVALID => S_AXI_GP1_BVALID,
+ SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
+ SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
+ SAXIGP1RLAST => S_AXI_GP1_RLAST,
+ SAXIGP1RREADY => S_AXI_GP1_RREADY,
+ SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
+ SAXIGP1RVALID => S_AXI_GP1_RVALID,
+ SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
+ SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
+ SAXIGP1WLAST => S_AXI_GP1_WLAST,
+ SAXIGP1WREADY => S_AXI_GP1_WREADY,
+ SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
+ SAXIGP1WVALID => S_AXI_GP1_WVALID,
+ SAXIHP0ACLK => S_AXI_HP0_ACLK,
+ SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
+ SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
+ SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
+ SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
+ SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
+ SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
+ SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
+ SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
+ SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
+ SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
+ SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
+ SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
+ SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
+ SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
+ SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
+ SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
+ SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
+ SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
+ SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
+ SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
+ SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
+ SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
+ SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
+ SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
+ SAXIHP0BREADY => S_AXI_HP0_BREADY,
+ SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
+ SAXIHP0BVALID => S_AXI_HP0_BVALID,
+ SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
+ SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
+ SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
+ SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
+ SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
+ SAXIHP0RLAST => S_AXI_HP0_RLAST,
+ SAXIHP0RREADY => S_AXI_HP0_RREADY,
+ SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
+ SAXIHP0RVALID => S_AXI_HP0_RVALID,
+ SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
+ SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
+ SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
+ SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
+ SAXIHP0WLAST => S_AXI_HP0_WLAST,
+ SAXIHP0WREADY => S_AXI_HP0_WREADY,
+ SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
+ SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
+ SAXIHP0WVALID => S_AXI_HP0_WVALID,
+ SAXIHP1ACLK => S_AXI_HP1_ACLK,
+ SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
+ SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
+ SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
+ SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
+ SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
+ SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
+ SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
+ SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
+ SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
+ SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
+ SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
+ SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
+ SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
+ SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
+ SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
+ SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
+ SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
+ SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
+ SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
+ SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
+ SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
+ SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
+ SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
+ SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
+ SAXIHP1BREADY => S_AXI_HP1_BREADY,
+ SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
+ SAXIHP1BVALID => S_AXI_HP1_BVALID,
+ SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
+ SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
+ SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
+ SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
+ SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
+ SAXIHP1RLAST => S_AXI_HP1_RLAST,
+ SAXIHP1RREADY => S_AXI_HP1_RREADY,
+ SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
+ SAXIHP1RVALID => S_AXI_HP1_RVALID,
+ SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
+ SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
+ SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
+ SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
+ SAXIHP1WLAST => S_AXI_HP1_WLAST,
+ SAXIHP1WREADY => S_AXI_HP1_WREADY,
+ SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
+ SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
+ SAXIHP1WVALID => S_AXI_HP1_WVALID,
+ SAXIHP2ACLK => S_AXI_HP2_ACLK,
+ SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
+ SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
+ SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
+ SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
+ SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
+ SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
+ SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
+ SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
+ SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
+ SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
+ SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
+ SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
+ SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
+ SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
+ SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
+ SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
+ SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
+ SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
+ SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
+ SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
+ SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
+ SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
+ SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
+ SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
+ SAXIHP2BREADY => S_AXI_HP2_BREADY,
+ SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
+ SAXIHP2BVALID => S_AXI_HP2_BVALID,
+ SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
+ SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
+ SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
+ SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
+ SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
+ SAXIHP2RLAST => S_AXI_HP2_RLAST,
+ SAXIHP2RREADY => S_AXI_HP2_RREADY,
+ SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
+ SAXIHP2RVALID => S_AXI_HP2_RVALID,
+ SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
+ SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
+ SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
+ SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
+ SAXIHP2WLAST => S_AXI_HP2_WLAST,
+ SAXIHP2WREADY => S_AXI_HP2_WREADY,
+ SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
+ SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
+ SAXIHP2WVALID => S_AXI_HP2_WVALID,
+ SAXIHP3ACLK => S_AXI_HP3_ACLK,
+ SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
+ SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
+ SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
+ SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
+ SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
+ SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
+ SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
+ SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
+ SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
+ SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
+ SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
+ SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
+ SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
+ SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
+ SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
+ SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
+ SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
+ SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
+ SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
+ SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
+ SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
+ SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
+ SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
+ SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
+ SAXIHP3BREADY => S_AXI_HP3_BREADY,
+ SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
+ SAXIHP3BVALID => S_AXI_HP3_BVALID,
+ SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
+ SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
+ SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
+ SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
+ SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
+ SAXIHP3RLAST => S_AXI_HP3_RLAST,
+ SAXIHP3RREADY => S_AXI_HP3_RREADY,
+ SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
+ SAXIHP3RVALID => S_AXI_HP3_RVALID,
+ SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
+ SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
+ SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
+ SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
+ SAXIHP3WLAST => S_AXI_HP3_WLAST,
+ SAXIHP3WREADY => S_AXI_HP3_WREADY,
+ SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
+ SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
+ SAXIHP3WVALID => S_AXI_HP3_WVALID
+ );
+PS_CLK_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_PS_CLK,
+ PAD => PS_CLK
+ );
+PS_PORB_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_PS_PORB,
+ PAD => PS_PORB
+ );
+PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_PS_SRSTB,
+ PAD => PS_SRSTB
+ );
+SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO0_CMD_T_n,
+ O => SDIO0_CMD_T
+ );
+\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO0_DATA_T_n(0),
+ O => SDIO0_DATA_T(0)
+ );
+\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO0_DATA_T_n(1),
+ O => SDIO0_DATA_T(1)
+ );
+\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO0_DATA_T_n(2),
+ O => SDIO0_DATA_T(2)
+ );
+\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO0_DATA_T_n(3),
+ O => SDIO0_DATA_T(3)
+ );
+SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO1_CMD_T_n,
+ O => SDIO1_CMD_T
+ );
+\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO1_DATA_T_n(0),
+ O => SDIO1_DATA_T(0)
+ );
+\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO1_DATA_T_n(1),
+ O => SDIO1_DATA_T(1)
+ );
+\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO1_DATA_T_n(2),
+ O => SDIO1_DATA_T(2)
+ );
+\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SDIO1_DATA_T_n(3),
+ O => SDIO1_DATA_T(3)
+ );
+SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI0_MISO_T_n,
+ O => SPI0_MISO_T
+ );
+SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI0_MOSI_T_n,
+ O => SPI0_MOSI_T
+ );
+SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI0_SCLK_T_n,
+ O => SPI0_SCLK_T
+ );
+SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI0_SS_T_n,
+ O => SPI0_SS_T
+ );
+SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI1_MISO_T_n,
+ O => SPI1_MISO_T
+ );
+SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI1_MOSI_T_n,
+ O => SPI1_MOSI_T
+ );
+SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI1_SCLK_T_n,
+ O => SPI1_SCLK_T
+ );
+SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => SPI1_SS_T_n,
+ O => SPI1_SS_T
+ );
+VCC: unisim.vcomponents.VCC
+ port map (
+ P => \<const1>\
+ );
+\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
+ port map (
+ I => FCLK_CLK_unbuffered(0),
+ O => FCLK_CLK0
+ );
+\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(0),
+ PAD => MIO(0)
+ );
+\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(10),
+ PAD => MIO(10)
+ );
+\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(11),
+ PAD => MIO(11)
+ );
+\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(12),
+ PAD => MIO(12)
+ );
+\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(13),
+ PAD => MIO(13)
+ );
+\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(14),
+ PAD => MIO(14)
+ );
+\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(15),
+ PAD => MIO(15)
+ );
+\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(16),
+ PAD => MIO(16)
+ );
+\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(17),
+ PAD => MIO(17)
+ );
+\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(18),
+ PAD => MIO(18)
+ );
+\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(19),
+ PAD => MIO(19)
+ );
+\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(1),
+ PAD => MIO(1)
+ );
+\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(20),
+ PAD => MIO(20)
+ );
+\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(21),
+ PAD => MIO(21)
+ );
+\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(22),
+ PAD => MIO(22)
+ );
+\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(23),
+ PAD => MIO(23)
+ );
+\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(24),
+ PAD => MIO(24)
+ );
+\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(25),
+ PAD => MIO(25)
+ );
+\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(26),
+ PAD => MIO(26)
+ );
+\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(27),
+ PAD => MIO(27)
+ );
+\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(28),
+ PAD => MIO(28)
+ );
+\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(29),
+ PAD => MIO(29)
+ );
+\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(2),
+ PAD => MIO(2)
+ );
+\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(30),
+ PAD => MIO(30)
+ );
+\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(31),
+ PAD => MIO(31)
+ );
+\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(32),
+ PAD => MIO(32)
+ );
+\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(33),
+ PAD => MIO(33)
+ );
+\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(34),
+ PAD => MIO(34)
+ );
+\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(35),
+ PAD => MIO(35)
+ );
+\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(36),
+ PAD => MIO(36)
+ );
+\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(37),
+ PAD => MIO(37)
+ );
+\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(38),
+ PAD => MIO(38)
+ );
+\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(39),
+ PAD => MIO(39)
+ );
+\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(3),
+ PAD => MIO(3)
+ );
+\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(40),
+ PAD => MIO(40)
+ );
+\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(41),
+ PAD => MIO(41)
+ );
+\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(42),
+ PAD => MIO(42)
+ );
+\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(43),
+ PAD => MIO(43)
+ );
+\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(44),
+ PAD => MIO(44)
+ );
+\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(45),
+ PAD => MIO(45)
+ );
+\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(46),
+ PAD => MIO(46)
+ );
+\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(47),
+ PAD => MIO(47)
+ );
+\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(48),
+ PAD => MIO(48)
+ );
+\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(49),
+ PAD => MIO(49)
+ );
+\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(4),
+ PAD => MIO(4)
+ );
+\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(50),
+ PAD => MIO(50)
+ );
+\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(51),
+ PAD => MIO(51)
+ );
+\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(52),
+ PAD => MIO(52)
+ );
+\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(53),
+ PAD => MIO(53)
+ );
+\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(5),
+ PAD => MIO(5)
+ );
+\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(6),
+ PAD => MIO(6)
+ );
+\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(7),
+ PAD => MIO(7)
+ );
+\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(8),
+ PAD => MIO(8)
+ );
+\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_MIO(9),
+ PAD => MIO(9)
+ );
+\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_BankAddr(0),
+ PAD => DDR_BankAddr(0)
+ );
+\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_BankAddr(1),
+ PAD => DDR_BankAddr(1)
+ );
+\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_BankAddr(2),
+ PAD => DDR_BankAddr(2)
+ );
+\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(0),
+ PAD => DDR_Addr(0)
+ );
+\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(10),
+ PAD => DDR_Addr(10)
+ );
+\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(11),
+ PAD => DDR_Addr(11)
+ );
+\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(12),
+ PAD => DDR_Addr(12)
+ );
+\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(13),
+ PAD => DDR_Addr(13)
+ );
+\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(14),
+ PAD => DDR_Addr(14)
+ );
+\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(1),
+ PAD => DDR_Addr(1)
+ );
+\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(2),
+ PAD => DDR_Addr(2)
+ );
+\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(3),
+ PAD => DDR_Addr(3)
+ );
+\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(4),
+ PAD => DDR_Addr(4)
+ );
+\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(5),
+ PAD => DDR_Addr(5)
+ );
+\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(6),
+ PAD => DDR_Addr(6)
+ );
+\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(7),
+ PAD => DDR_Addr(7)
+ );
+\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(8),
+ PAD => DDR_Addr(8)
+ );
+\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_Addr(9),
+ PAD => DDR_Addr(9)
+ );
+\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DM(0),
+ PAD => DDR_DM(0)
+ );
+\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DM(1),
+ PAD => DDR_DM(1)
+ );
+\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DM(2),
+ PAD => DDR_DM(2)
+ );
+\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DM(3),
+ PAD => DDR_DM(3)
+ );
+\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(0),
+ PAD => DDR_DQ(0)
+ );
+\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(10),
+ PAD => DDR_DQ(10)
+ );
+\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(11),
+ PAD => DDR_DQ(11)
+ );
+\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(12),
+ PAD => DDR_DQ(12)
+ );
+\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(13),
+ PAD => DDR_DQ(13)
+ );
+\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(14),
+ PAD => DDR_DQ(14)
+ );
+\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(15),
+ PAD => DDR_DQ(15)
+ );
+\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(16),
+ PAD => DDR_DQ(16)
+ );
+\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(17),
+ PAD => DDR_DQ(17)
+ );
+\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(18),
+ PAD => DDR_DQ(18)
+ );
+\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(19),
+ PAD => DDR_DQ(19)
+ );
+\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(1),
+ PAD => DDR_DQ(1)
+ );
+\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(20),
+ PAD => DDR_DQ(20)
+ );
+\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(21),
+ PAD => DDR_DQ(21)
+ );
+\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(22),
+ PAD => DDR_DQ(22)
+ );
+\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(23),
+ PAD => DDR_DQ(23)
+ );
+\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(24),
+ PAD => DDR_DQ(24)
+ );
+\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(25),
+ PAD => DDR_DQ(25)
+ );
+\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(26),
+ PAD => DDR_DQ(26)
+ );
+\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(27),
+ PAD => DDR_DQ(27)
+ );
+\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(28),
+ PAD => DDR_DQ(28)
+ );
+\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(29),
+ PAD => DDR_DQ(29)
+ );
+\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(2),
+ PAD => DDR_DQ(2)
+ );
+\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(30),
+ PAD => DDR_DQ(30)
+ );
+\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(31),
+ PAD => DDR_DQ(31)
+ );
+\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(3),
+ PAD => DDR_DQ(3)
+ );
+\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(4),
+ PAD => DDR_DQ(4)
+ );
+\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(5),
+ PAD => DDR_DQ(5)
+ );
+\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(6),
+ PAD => DDR_DQ(6)
+ );
+\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(7),
+ PAD => DDR_DQ(7)
+ );
+\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(8),
+ PAD => DDR_DQ(8)
+ );
+\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQ(9),
+ PAD => DDR_DQ(9)
+ );
+\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS_n(0),
+ PAD => DDR_DQS_n(0)
+ );
+\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS_n(1),
+ PAD => DDR_DQS_n(1)
+ );
+\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS_n(2),
+ PAD => DDR_DQS_n(2)
+ );
+\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS_n(3),
+ PAD => DDR_DQS_n(3)
+ );
+\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS(0),
+ PAD => DDR_DQS(0)
+ );
+\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS(1),
+ PAD => DDR_DQS(1)
+ );
+\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS(2),
+ PAD => DDR_DQS(2)
+ );
+\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
+ port map (
+ IO => buffered_DDR_DQS(3),
+ PAD => DDR_DQS(3)
+ );
+i_0: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[0]\
+ );
+i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[0]\(1)
+ );
+i_10: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[7]\(1)
+ );
+i_11: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[7]\(0)
+ );
+i_12: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[6]\(1)
+ );
+i_13: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[6]\(0)
+ );
+i_14: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[5]\(1)
+ );
+i_15: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[5]\(0)
+ );
+i_16: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[4]\(1)
+ );
+i_17: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[4]\(0)
+ );
+i_18: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[3]\(1)
+ );
+i_19: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[3]\(0)
+ );
+i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[0]\(0)
+ );
+i_20: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[2]\(1)
+ );
+i_21: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[2]\(0)
+ );
+i_22: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[1]\(1)
+ );
+i_23: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_DATA_PIPE[1]\(0)
+ );
+i_3: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[7]\
+ );
+i_4: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[6]\
+ );
+i_5: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[5]\
+ );
+i_6: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[4]\
+ );
+i_7: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[3]\
+ );
+i_8: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[2]\
+ );
+i_9: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => '0',
+ O => \TRACE_CTL_PIPE[1]\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity TopLevel_processing_system7_0_0 is
+ port (
+ TTC0_WAVE0_OUT : out STD_LOGIC;
+ TTC0_WAVE1_OUT : out STD_LOGIC;
+ TTC0_WAVE2_OUT : out STD_LOGIC;
+ USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ USB0_VBUS_PWRSELECT : out STD_LOGIC;
+ USB0_VBUS_PWRFAULT : in STD_LOGIC;
+ M_AXI_GP0_ARVALID : out STD_LOGIC;
+ M_AXI_GP0_AWVALID : out STD_LOGIC;
+ M_AXI_GP0_BREADY : out STD_LOGIC;
+ M_AXI_GP0_RREADY : out STD_LOGIC;
+ M_AXI_GP0_WLAST : out STD_LOGIC;
+ M_AXI_GP0_WVALID : out STD_LOGIC;
+ M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ACLK : in STD_LOGIC;
+ M_AXI_GP0_ARREADY : in STD_LOGIC;
+ M_AXI_GP0_AWREADY : in STD_LOGIC;
+ M_AXI_GP0_BVALID : in STD_LOGIC;
+ M_AXI_GP0_RLAST : in STD_LOGIC;
+ M_AXI_GP0_RVALID : in STD_LOGIC;
+ M_AXI_GP0_WREADY : in STD_LOGIC;
+ M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
+ FCLK_CLK0 : out STD_LOGIC;
+ FCLK_RESET0_N : out STD_LOGIC;
+ MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ DDR_CAS_n : inout STD_LOGIC;
+ DDR_CKE : inout STD_LOGIC;
+ DDR_Clk_n : inout STD_LOGIC;
+ DDR_Clk : inout STD_LOGIC;
+ DDR_CS_n : inout STD_LOGIC;
+ DDR_DRSTB : inout STD_LOGIC;
+ DDR_ODT : inout STD_LOGIC;
+ DDR_RAS_n : inout STD_LOGIC;
+ DDR_WEB : inout STD_LOGIC;
+ DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_VRN : inout STD_LOGIC;
+ DDR_VRP : inout STD_LOGIC;
+ DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ PS_SRSTB : inout STD_LOGIC;
+ PS_CLK : inout STD_LOGIC;
+ PS_PORB : inout STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of TopLevel_processing_system7_0_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of TopLevel_processing_system7_0_0 : entity is "TopLevel_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of TopLevel_processing_system7_0_0 : entity is "yes";
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of TopLevel_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2019.1";
+end TopLevel_processing_system7_0_0;
+
+architecture STRUCTURE of TopLevel_processing_system7_0_0 is
+ signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute C_DM_WIDTH : integer;
+ attribute C_DM_WIDTH of inst : label is 4;
+ attribute C_DQS_WIDTH : integer;
+ attribute C_DQS_WIDTH of inst : label is 4;
+ attribute C_DQ_WIDTH : integer;
+ attribute C_DQ_WIDTH of inst : label is 32;
+ attribute C_EMIO_GPIO_WIDTH : integer;
+ attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
+ attribute C_EN_EMIO_ENET0 : integer;
+ attribute C_EN_EMIO_ENET0 of inst : label is 0;
+ attribute C_EN_EMIO_ENET1 : integer;
+ attribute C_EN_EMIO_ENET1 of inst : label is 0;
+ attribute C_EN_EMIO_PJTAG : integer;
+ attribute C_EN_EMIO_PJTAG of inst : label is 0;
+ attribute C_EN_EMIO_TRACE : integer;
+ attribute C_EN_EMIO_TRACE of inst : label is 0;
+ attribute C_FCLK_CLK0_BUF : string;
+ attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
+ attribute C_FCLK_CLK1_BUF : string;
+ attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
+ attribute C_FCLK_CLK2_BUF : string;
+ attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
+ attribute C_FCLK_CLK3_BUF : string;
+ attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
+ attribute C_GP0_EN_MODIFIABLE_TXN : integer;
+ attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
+ attribute C_GP1_EN_MODIFIABLE_TXN : integer;
+ attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
+ attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
+ attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
+ attribute C_INCLUDE_TRACE_BUFFER : integer;
+ attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
+ attribute C_IRQ_F2P_MODE : string;
+ attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
+ attribute C_MIO_PRIMITIVE : integer;
+ attribute C_MIO_PRIMITIVE of inst : label is 54;
+ attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
+ attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
+ attribute C_M_AXI_GP0_ID_WIDTH : integer;
+ attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
+ attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
+ attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
+ attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
+ attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
+ attribute C_M_AXI_GP1_ID_WIDTH : integer;
+ attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
+ attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
+ attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
+ attribute C_NUM_F2P_INTR_INPUTS : integer;
+ attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
+ attribute C_PACKAGE_NAME : string;
+ attribute C_PACKAGE_NAME of inst : label is "clg400";
+ attribute C_PS7_SI_REV : string;
+ attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
+ attribute C_S_AXI_ACP_ARUSER_VAL : integer;
+ attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
+ attribute C_S_AXI_ACP_AWUSER_VAL : integer;
+ attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
+ attribute C_S_AXI_ACP_ID_WIDTH : integer;
+ attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
+ attribute C_S_AXI_GP0_ID_WIDTH : integer;
+ attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
+ attribute C_S_AXI_GP1_ID_WIDTH : integer;
+ attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
+ attribute C_S_AXI_HP0_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
+ attribute C_S_AXI_HP0_ID_WIDTH : integer;
+ attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
+ attribute C_S_AXI_HP1_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
+ attribute C_S_AXI_HP1_ID_WIDTH : integer;
+ attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
+ attribute C_S_AXI_HP2_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
+ attribute C_S_AXI_HP2_ID_WIDTH : integer;
+ attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
+ attribute C_S_AXI_HP3_DATA_WIDTH : integer;
+ attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
+ attribute C_S_AXI_HP3_ID_WIDTH : integer;
+ attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
+ attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
+ attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
+ attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
+ attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
+ attribute C_TRACE_INTERNAL_WIDTH : integer;
+ attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
+ attribute C_TRACE_PIPELINE_WIDTH : integer;
+ attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
+ attribute C_USE_AXI_NONSECURE : integer;
+ attribute C_USE_AXI_NONSECURE of inst : label is 0;
+ attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
+ attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
+ attribute C_USE_M_AXI_GP0 : integer;
+ attribute C_USE_M_AXI_GP0 of inst : label is 1;
+ attribute C_USE_M_AXI_GP1 : integer;
+ attribute C_USE_M_AXI_GP1 of inst : label is 0;
+ attribute C_USE_S_AXI_ACP : integer;
+ attribute C_USE_S_AXI_ACP of inst : label is 0;
+ attribute C_USE_S_AXI_GP0 : integer;
+ attribute C_USE_S_AXI_GP0 of inst : label is 0;
+ attribute C_USE_S_AXI_GP1 : integer;
+ attribute C_USE_S_AXI_GP1 of inst : label is 0;
+ attribute C_USE_S_AXI_HP0 : integer;
+ attribute C_USE_S_AXI_HP0 of inst : label is 0;
+ attribute C_USE_S_AXI_HP1 : integer;
+ attribute C_USE_S_AXI_HP1 of inst : label is 0;
+ attribute C_USE_S_AXI_HP2 : integer;
+ attribute C_USE_S_AXI_HP2 of inst : label is 0;
+ attribute C_USE_S_AXI_HP3 : integer;
+ attribute C_USE_S_AXI_HP3 of inst : label is 0;
+ attribute HW_HANDOFF : string;
+ attribute HW_HANDOFF of inst : label is "TopLevel_processing_system7_0_0.hwdef";
+ attribute POWER : string;
+ attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
+ attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
+ attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
+ attribute X_INTERFACE_INFO : string;
+ attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
+ attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
+ attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
+ attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
+ attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
+ attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
+ attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
+ attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
+ attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
+ attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
+ attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
+ attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
+ attribute X_INTERFACE_PARAMETER : string;
+ attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
+ attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
+ attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
+ attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
+ attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
+ attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
+ attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
+ attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
+ attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
+ attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
+ attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
+ attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
+ attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
+ attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
+ attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
+ attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
+ attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
+ attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
+ attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
+ attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN TopLevel_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
+ attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
+ attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
+begin
+inst: entity work.TopLevel_processing_system7_0_0_processing_system7_v5_5_processing_system7
+ port map (
+ CAN0_PHY_RX => '0',
+ CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
+ CAN1_PHY_RX => '0',
+ CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
+ Core0_nFIQ => '0',
+ Core0_nIRQ => '0',
+ Core1_nFIQ => '0',
+ Core1_nIRQ => '0',
+ DDR_ARB(3 downto 0) => B"0000",
+ DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
+ DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
+ DDR_CAS_n => DDR_CAS_n,
+ DDR_CKE => DDR_CKE,
+ DDR_CS_n => DDR_CS_n,
+ DDR_Clk => DDR_Clk,
+ DDR_Clk_n => DDR_Clk_n,
+ DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
+ DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
+ DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
+ DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
+ DDR_DRSTB => DDR_DRSTB,
+ DDR_ODT => DDR_ODT,
+ DDR_RAS_n => DDR_RAS_n,
+ DDR_VRN => DDR_VRN,
+ DDR_VRP => DDR_VRP,
+ DDR_WEB => DDR_WEB,
+ DMA0_ACLK => '0',
+ DMA0_DAREADY => '0',
+ DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
+ DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
+ DMA0_DRLAST => '0',
+ DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
+ DMA0_DRTYPE(1 downto 0) => B"00",
+ DMA0_DRVALID => '0',
+ DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
+ DMA1_ACLK => '0',
+ DMA1_DAREADY => '0',
+ DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
+ DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
+ DMA1_DRLAST => '0',
+ DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
+ DMA1_DRTYPE(1 downto 0) => B"00",
+ DMA1_DRVALID => '0',
+ DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
+ DMA2_ACLK => '0',
+ DMA2_DAREADY => '0',
+ DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
+ DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
+ DMA2_DRLAST => '0',
+ DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
+ DMA2_DRTYPE(1 downto 0) => B"00",
+ DMA2_DRVALID => '0',
+ DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
+ DMA3_ACLK => '0',
+ DMA3_DAREADY => '0',
+ DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
+ DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
+ DMA3_DRLAST => '0',
+ DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
+ DMA3_DRTYPE(1 downto 0) => B"00",
+ DMA3_DRVALID => '0',
+ DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
+ ENET0_EXT_INTIN => '0',
+ ENET0_GMII_COL => '0',
+ ENET0_GMII_CRS => '0',
+ ENET0_GMII_RXD(7 downto 0) => B"00000000",
+ ENET0_GMII_RX_CLK => '0',
+ ENET0_GMII_RX_DV => '0',
+ ENET0_GMII_RX_ER => '0',
+ ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
+ ENET0_GMII_TX_CLK => '0',
+ ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
+ ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
+ ENET0_MDIO_I => '0',
+ ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
+ ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
+ ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
+ ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
+ ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
+ ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
+ ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
+ ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
+ ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
+ ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
+ ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
+ ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
+ ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
+ ENET1_EXT_INTIN => '0',
+ ENET1_GMII_COL => '0',
+ ENET1_GMII_CRS => '0',
+ ENET1_GMII_RXD(7 downto 0) => B"00000000",
+ ENET1_GMII_RX_CLK => '0',
+ ENET1_GMII_RX_DV => '0',
+ ENET1_GMII_RX_ER => '0',
+ ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
+ ENET1_GMII_TX_CLK => '0',
+ ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
+ ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
+ ENET1_MDIO_I => '0',
+ ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
+ ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
+ ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
+ ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
+ ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
+ ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
+ ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
+ ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
+ ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
+ ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
+ ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
+ ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
+ ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
+ EVENT_EVENTI => '0',
+ EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
+ EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
+ EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
+ FCLK_CLK0 => FCLK_CLK0,
+ FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
+ FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
+ FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
+ FCLK_CLKTRIG0_N => '0',
+ FCLK_CLKTRIG1_N => '0',
+ FCLK_CLKTRIG2_N => '0',
+ FCLK_CLKTRIG3_N => '0',
+ FCLK_RESET0_N => FCLK_RESET0_N,
+ FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
+ FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
+ FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
+ FPGA_IDLE_N => '0',
+ FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
+ FTMD_TRACEIN_CLK => '0',
+ FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
+ FTMD_TRACEIN_VALID => '0',
+ FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
+ FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
+ FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
+ FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
+ FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
+ FTMT_F2P_TRIG_0 => '0',
+ FTMT_F2P_TRIG_1 => '0',
+ FTMT_F2P_TRIG_2 => '0',
+ FTMT_F2P_TRIG_3 => '0',
+ FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
+ FTMT_P2F_TRIGACK_0 => '0',
+ FTMT_P2F_TRIGACK_1 => '0',
+ FTMT_P2F_TRIGACK_2 => '0',
+ FTMT_P2F_TRIGACK_3 => '0',
+ FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
+ FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
+ FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
+ FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
+ GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
+ GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
+ I2C0_SCL_I => '0',
+ I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
+ I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
+ I2C0_SDA_I => '0',
+ I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
+ I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
+ I2C1_SCL_I => '0',
+ I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
+ I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
+ I2C1_SDA_I => '0',
+ I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
+ I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
+ IRQ_F2P(0) => IRQ_F2P(0),
+ IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
+ IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
+ IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
+ IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
+ IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
+ IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
+ IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
+ IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
+ IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
+ IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
+ IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
+ IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
+ IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
+ IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
+ IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
+ IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
+ IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
+ IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
+ IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
+ IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
+ IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
+ IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
+ IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
+ IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
+ IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
+ IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
+ IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
+ IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
+ IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
+ MIO(53 downto 0) => MIO(53 downto 0),
+ M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
+ M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
+ M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
+ M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
+ M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
+ M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
+ M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
+ M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
+ M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
+ M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
+ M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
+ M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
+ M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
+ M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
+ M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
+ M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
+ M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
+ M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
+ M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
+ M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
+ M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
+ M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
+ M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
+ M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
+ M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
+ M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
+ M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
+ M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
+ M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
+ M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
+ M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
+ M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
+ M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
+ M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
+ M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
+ M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
+ M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
+ M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
+ M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
+ M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
+ M_AXI_GP1_ACLK => '0',
+ M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
+ M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
+ M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
+ M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
+ M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
+ M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
+ M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_ARREADY => '0',
+ M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
+ M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
+ M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
+ M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
+ M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
+ M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
+ M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
+ M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_AWREADY => '0',
+ M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
+ M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
+ M_AXI_GP1_BID(11 downto 0) => B"000000000000",
+ M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
+ M_AXI_GP1_BRESP(1 downto 0) => B"00",
+ M_AXI_GP1_BVALID => '0',
+ M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
+ M_AXI_GP1_RID(11 downto 0) => B"000000000000",
+ M_AXI_GP1_RLAST => '0',
+ M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
+ M_AXI_GP1_RRESP(1 downto 0) => B"00",
+ M_AXI_GP1_RVALID => '0',
+ M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
+ M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
+ M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
+ M_AXI_GP1_WREADY => '0',
+ M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
+ M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
+ PJTAG_TCK => '0',
+ PJTAG_TDI => '0',
+ PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
+ PJTAG_TMS => '0',
+ PS_CLK => PS_CLK,
+ PS_PORB => PS_PORB,
+ PS_SRSTB => PS_SRSTB,
+ SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
+ SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
+ SDIO0_CDN => '0',
+ SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
+ SDIO0_CLK_FB => '0',
+ SDIO0_CMD_I => '0',
+ SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
+ SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
+ SDIO0_DATA_I(3 downto 0) => B"0000",
+ SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
+ SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
+ SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
+ SDIO0_WP => '0',
+ SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
+ SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
+ SDIO1_CDN => '0',
+ SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
+ SDIO1_CLK_FB => '0',
+ SDIO1_CMD_I => '0',
+ SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
+ SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
+ SDIO1_DATA_I(3 downto 0) => B"0000",
+ SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
+ SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
+ SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
+ SDIO1_WP => '0',
+ SPI0_MISO_I => '0',
+ SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
+ SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
+ SPI0_MOSI_I => '0',
+ SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
+ SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
+ SPI0_SCLK_I => '0',
+ SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
+ SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
+ SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
+ SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
+ SPI0_SS_I => '0',
+ SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
+ SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
+ SPI1_MISO_I => '0',
+ SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
+ SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
+ SPI1_MOSI_I => '0',
+ SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
+ SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
+ SPI1_SCLK_I => '0',
+ SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
+ SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
+ SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
+ SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
+ SPI1_SS_I => '0',
+ SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
+ SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
+ SRAM_INTIN => '0',
+ S_AXI_ACP_ACLK => '0',
+ S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_ACP_ARBURST(1 downto 0) => B"00",
+ S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
+ S_AXI_ACP_ARID(2 downto 0) => B"000",
+ S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
+ S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
+ S_AXI_ACP_ARPROT(2 downto 0) => B"000",
+ S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
+ S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
+ S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
+ S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
+ S_AXI_ACP_ARVALID => '0',
+ S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_ACP_AWBURST(1 downto 0) => B"00",
+ S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_ACP_AWID(2 downto 0) => B"000",
+ S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
+ S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
+ S_AXI_ACP_AWPROT(2 downto 0) => B"000",
+ S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
+ S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
+ S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
+ S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
+ S_AXI_ACP_AWVALID => '0',
+ S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
+ S_AXI_ACP_BREADY => '0',
+ S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
+ S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
+ S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
+ S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
+ S_AXI_ACP_RREADY => '0',
+ S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
+ S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ S_AXI_ACP_WID(2 downto 0) => B"000",
+ S_AXI_ACP_WLAST => '0',
+ S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
+ S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
+ S_AXI_ACP_WVALID => '0',
+ S_AXI_GP0_ACLK => '0',
+ S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP0_ARBURST(1 downto 0) => B"00",
+ S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
+ S_AXI_GP0_ARID(5 downto 0) => B"000000",
+ S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
+ S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
+ S_AXI_GP0_ARPROT(2 downto 0) => B"000",
+ S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
+ S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
+ S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
+ S_AXI_GP0_ARVALID => '0',
+ S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP0_AWBURST(1 downto 0) => B"00",
+ S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_GP0_AWID(5 downto 0) => B"000000",
+ S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
+ S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
+ S_AXI_GP0_AWPROT(2 downto 0) => B"000",
+ S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
+ S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
+ S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
+ S_AXI_GP0_AWVALID => '0',
+ S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
+ S_AXI_GP0_BREADY => '0',
+ S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
+ S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
+ S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
+ S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
+ S_AXI_GP0_RREADY => '0',
+ S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
+ S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP0_WID(5 downto 0) => B"000000",
+ S_AXI_GP0_WLAST => '0',
+ S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
+ S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
+ S_AXI_GP0_WVALID => '0',
+ S_AXI_GP1_ACLK => '0',
+ S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP1_ARBURST(1 downto 0) => B"00",
+ S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
+ S_AXI_GP1_ARID(5 downto 0) => B"000000",
+ S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
+ S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
+ S_AXI_GP1_ARPROT(2 downto 0) => B"000",
+ S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
+ S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
+ S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
+ S_AXI_GP1_ARVALID => '0',
+ S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP1_AWBURST(1 downto 0) => B"00",
+ S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_GP1_AWID(5 downto 0) => B"000000",
+ S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
+ S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
+ S_AXI_GP1_AWPROT(2 downto 0) => B"000",
+ S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
+ S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
+ S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
+ S_AXI_GP1_AWVALID => '0',
+ S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
+ S_AXI_GP1_BREADY => '0',
+ S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
+ S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
+ S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
+ S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
+ S_AXI_GP1_RREADY => '0',
+ S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
+ S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_GP1_WID(5 downto 0) => B"000000",
+ S_AXI_GP1_WLAST => '0',
+ S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
+ S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
+ S_AXI_GP1_WVALID => '0',
+ S_AXI_HP0_ACLK => '0',
+ S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP0_ARBURST(1 downto 0) => B"00",
+ S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
+ S_AXI_HP0_ARID(5 downto 0) => B"000000",
+ S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
+ S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
+ S_AXI_HP0_ARPROT(2 downto 0) => B"000",
+ S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
+ S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
+ S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
+ S_AXI_HP0_ARVALID => '0',
+ S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP0_AWBURST(1 downto 0) => B"00",
+ S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_HP0_AWID(5 downto 0) => B"000000",
+ S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
+ S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
+ S_AXI_HP0_AWPROT(2 downto 0) => B"000",
+ S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
+ S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
+ S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
+ S_AXI_HP0_AWVALID => '0',
+ S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
+ S_AXI_HP0_BREADY => '0',
+ S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
+ S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
+ S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
+ S_AXI_HP0_RDISSUECAP1_EN => '0',
+ S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
+ S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
+ S_AXI_HP0_RREADY => '0',
+ S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
+ S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
+ S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ S_AXI_HP0_WID(5 downto 0) => B"000000",
+ S_AXI_HP0_WLAST => '0',
+ S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
+ S_AXI_HP0_WRISSUECAP1_EN => '0',
+ S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
+ S_AXI_HP0_WVALID => '0',
+ S_AXI_HP1_ACLK => '0',
+ S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP1_ARBURST(1 downto 0) => B"00",
+ S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
+ S_AXI_HP1_ARID(5 downto 0) => B"000000",
+ S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
+ S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
+ S_AXI_HP1_ARPROT(2 downto 0) => B"000",
+ S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
+ S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
+ S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
+ S_AXI_HP1_ARVALID => '0',
+ S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP1_AWBURST(1 downto 0) => B"00",
+ S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_HP1_AWID(5 downto 0) => B"000000",
+ S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
+ S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
+ S_AXI_HP1_AWPROT(2 downto 0) => B"000",
+ S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
+ S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
+ S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
+ S_AXI_HP1_AWVALID => '0',
+ S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
+ S_AXI_HP1_BREADY => '0',
+ S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
+ S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
+ S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
+ S_AXI_HP1_RDISSUECAP1_EN => '0',
+ S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
+ S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
+ S_AXI_HP1_RREADY => '0',
+ S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
+ S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
+ S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ S_AXI_HP1_WID(5 downto 0) => B"000000",
+ S_AXI_HP1_WLAST => '0',
+ S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
+ S_AXI_HP1_WRISSUECAP1_EN => '0',
+ S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
+ S_AXI_HP1_WVALID => '0',
+ S_AXI_HP2_ACLK => '0',
+ S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP2_ARBURST(1 downto 0) => B"00",
+ S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
+ S_AXI_HP2_ARID(5 downto 0) => B"000000",
+ S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
+ S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
+ S_AXI_HP2_ARPROT(2 downto 0) => B"000",
+ S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
+ S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
+ S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
+ S_AXI_HP2_ARVALID => '0',
+ S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP2_AWBURST(1 downto 0) => B"00",
+ S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_HP2_AWID(5 downto 0) => B"000000",
+ S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
+ S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
+ S_AXI_HP2_AWPROT(2 downto 0) => B"000",
+ S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
+ S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
+ S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
+ S_AXI_HP2_AWVALID => '0',
+ S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
+ S_AXI_HP2_BREADY => '0',
+ S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
+ S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
+ S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
+ S_AXI_HP2_RDISSUECAP1_EN => '0',
+ S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
+ S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
+ S_AXI_HP2_RREADY => '0',
+ S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
+ S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
+ S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ S_AXI_HP2_WID(5 downto 0) => B"000000",
+ S_AXI_HP2_WLAST => '0',
+ S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
+ S_AXI_HP2_WRISSUECAP1_EN => '0',
+ S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
+ S_AXI_HP2_WVALID => '0',
+ S_AXI_HP3_ACLK => '0',
+ S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP3_ARBURST(1 downto 0) => B"00",
+ S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
+ S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
+ S_AXI_HP3_ARID(5 downto 0) => B"000000",
+ S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
+ S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
+ S_AXI_HP3_ARPROT(2 downto 0) => B"000",
+ S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
+ S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
+ S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
+ S_AXI_HP3_ARVALID => '0',
+ S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
+ S_AXI_HP3_AWBURST(1 downto 0) => B"00",
+ S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
+ S_AXI_HP3_AWID(5 downto 0) => B"000000",
+ S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
+ S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
+ S_AXI_HP3_AWPROT(2 downto 0) => B"000",
+ S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
+ S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
+ S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
+ S_AXI_HP3_AWVALID => '0',
+ S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
+ S_AXI_HP3_BREADY => '0',
+ S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
+ S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
+ S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
+ S_AXI_HP3_RDISSUECAP1_EN => '0',
+ S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
+ S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
+ S_AXI_HP3_RREADY => '0',
+ S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
+ S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
+ S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
+ S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
+ S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ S_AXI_HP3_WID(5 downto 0) => B"000000",
+ S_AXI_HP3_WLAST => '0',
+ S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
+ S_AXI_HP3_WRISSUECAP1_EN => '0',
+ S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
+ S_AXI_HP3_WVALID => '0',
+ TRACE_CLK => '0',
+ TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
+ TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
+ TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
+ TTC0_CLK0_IN => '0',
+ TTC0_CLK1_IN => '0',
+ TTC0_CLK2_IN => '0',
+ TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
+ TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
+ TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
+ TTC1_CLK0_IN => '0',
+ TTC1_CLK1_IN => '0',
+ TTC1_CLK2_IN => '0',
+ TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
+ TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
+ TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
+ UART0_CTSN => '0',
+ UART0_DCDN => '0',
+ UART0_DSRN => '0',
+ UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
+ UART0_RIN => '0',
+ UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
+ UART0_RX => '1',
+ UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
+ UART1_CTSN => '0',
+ UART1_DCDN => '0',
+ UART1_DSRN => '0',
+ UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
+ UART1_RIN => '0',
+ UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
+ UART1_RX => '1',
+ UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
+ USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
+ USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
+ USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
+ USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
+ USB1_VBUS_PWRFAULT => '0',
+ USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
+ WDT_CLK_IN => '0',
+ WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
+ );
+end STRUCTURE;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.v b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.v
new file mode 100644
index 0000000..7eb28ba
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.v
@@ -0,0 +1,100 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+// Date : Tue Oct 15 10:07:06 2019
+// Host : carl-pc running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub
+// /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.v
+// Design : TopLevel_processing_system7_0_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.1" *)
+module TopLevel_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
+ TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
+ M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
+ M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
+ M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
+ M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
+ M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
+ M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
+ M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
+ M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
+ M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
+ DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
+ DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
+ output TTC0_WAVE0_OUT;
+ output TTC0_WAVE1_OUT;
+ output TTC0_WAVE2_OUT;
+ output [1:0]USB0_PORT_INDCTL;
+ output USB0_VBUS_PWRSELECT;
+ input USB0_VBUS_PWRFAULT;
+ output M_AXI_GP0_ARVALID;
+ output M_AXI_GP0_AWVALID;
+ output M_AXI_GP0_BREADY;
+ output M_AXI_GP0_RREADY;
+ output M_AXI_GP0_WLAST;
+ output M_AXI_GP0_WVALID;
+ output [11:0]M_AXI_GP0_ARID;
+ output [11:0]M_AXI_GP0_AWID;
+ output [11:0]M_AXI_GP0_WID;
+ output [1:0]M_AXI_GP0_ARBURST;
+ output [1:0]M_AXI_GP0_ARLOCK;
+ output [2:0]M_AXI_GP0_ARSIZE;
+ output [1:0]M_AXI_GP0_AWBURST;
+ output [1:0]M_AXI_GP0_AWLOCK;
+ output [2:0]M_AXI_GP0_AWSIZE;
+ output [2:0]M_AXI_GP0_ARPROT;
+ output [2:0]M_AXI_GP0_AWPROT;
+ output [31:0]M_AXI_GP0_ARADDR;
+ output [31:0]M_AXI_GP0_AWADDR;
+ output [31:0]M_AXI_GP0_WDATA;
+ output [3:0]M_AXI_GP0_ARCACHE;
+ output [3:0]M_AXI_GP0_ARLEN;
+ output [3:0]M_AXI_GP0_ARQOS;
+ output [3:0]M_AXI_GP0_AWCACHE;
+ output [3:0]M_AXI_GP0_AWLEN;
+ output [3:0]M_AXI_GP0_AWQOS;
+ output [3:0]M_AXI_GP0_WSTRB;
+ input M_AXI_GP0_ACLK;
+ input M_AXI_GP0_ARREADY;
+ input M_AXI_GP0_AWREADY;
+ input M_AXI_GP0_BVALID;
+ input M_AXI_GP0_RLAST;
+ input M_AXI_GP0_RVALID;
+ input M_AXI_GP0_WREADY;
+ input [11:0]M_AXI_GP0_BID;
+ input [11:0]M_AXI_GP0_RID;
+ input [1:0]M_AXI_GP0_BRESP;
+ input [1:0]M_AXI_GP0_RRESP;
+ input [31:0]M_AXI_GP0_RDATA;
+ input [0:0]IRQ_F2P;
+ output FCLK_CLK0;
+ output FCLK_RESET0_N;
+ inout [53:0]MIO;
+ inout DDR_CAS_n;
+ inout DDR_CKE;
+ inout DDR_Clk_n;
+ inout DDR_Clk;
+ inout DDR_CS_n;
+ inout DDR_DRSTB;
+ inout DDR_ODT;
+ inout DDR_RAS_n;
+ inout DDR_WEB;
+ inout [2:0]DDR_BankAddr;
+ inout [14:0]DDR_Addr;
+ inout DDR_VRN;
+ inout DDR_VRP;
+ inout [3:0]DDR_DM;
+ inout [31:0]DDR_DQ;
+ inout [3:0]DDR_DQS_n;
+ inout [3:0]DDR_DQS;
+ inout PS_SRSTB;
+ inout PS_CLK;
+ inout PS_PORB;
+endmodule
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.vhdl b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.vhdl
new file mode 100644
index 0000000..48e6896
--- /dev/null
+++ b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.vhdl
@@ -0,0 +1,98 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
+-- Date : Tue Oct 15 10:07:06 2019
+-- Host : carl-pc running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /home/kkrizka/firmware/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/TopLevel_processing_system7_0_0_stub.vhdl
+-- Design : TopLevel_processing_system7_0_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg400-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity TopLevel_processing_system7_0_0 is
+ Port (
+ TTC0_WAVE0_OUT : out STD_LOGIC;
+ TTC0_WAVE1_OUT : out STD_LOGIC;
+ TTC0_WAVE2_OUT : out STD_LOGIC;
+ USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ USB0_VBUS_PWRSELECT : out STD_LOGIC;
+ USB0_VBUS_PWRFAULT : in STD_LOGIC;
+ M_AXI_GP0_ARVALID : out STD_LOGIC;
+ M_AXI_GP0_AWVALID : out STD_LOGIC;
+ M_AXI_GP0_BREADY : out STD_LOGIC;
+ M_AXI_GP0_RREADY : out STD_LOGIC;
+ M_AXI_GP0_WLAST : out STD_LOGIC;
+ M_AXI_GP0_WVALID : out STD_LOGIC;
+ M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_GP0_ACLK : in STD_LOGIC;
+ M_AXI_GP0_ARREADY : in STD_LOGIC;
+ M_AXI_GP0_AWREADY : in STD_LOGIC;
+ M_AXI_GP0_BVALID : in STD_LOGIC;
+ M_AXI_GP0_RLAST : in STD_LOGIC;
+ M_AXI_GP0_RVALID : in STD_LOGIC;
+ M_AXI_GP0_WREADY : in STD_LOGIC;
+ M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
+ FCLK_CLK0 : out STD_LOGIC;
+ FCLK_RESET0_N : out STD_LOGIC;
+ MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ DDR_CAS_n : inout STD_LOGIC;
+ DDR_CKE : inout STD_LOGIC;
+ DDR_Clk_n : inout STD_LOGIC;
+ DDR_Clk : inout STD_LOGIC;
+ DDR_CS_n : inout STD_LOGIC;
+ DDR_DRSTB : inout STD_LOGIC;
+ DDR_ODT : inout STD_LOGIC;
+ DDR_RAS_n : inout STD_LOGIC;
+ DDR_WEB : inout STD_LOGIC;
+ DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_VRN : inout STD_LOGIC;
+ DDR_VRP : inout STD_LOGIC;
+ DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ PS_SRSTB : inout STD_LOGIC;
+ PS_CLK : inout STD_LOGIC;
+ PS_PORB : inout STD_LOGIC
+ );
+
+end TopLevel_processing_system7_0_0;
+
+architecture stub of TopLevel_processing_system7_0_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2019.1";
+begin
+end;
diff --git a/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/hdl/verilog/TopLevel_processing_system7_0_0.hwdef b/pbv3_mass_test_adapter_firmware.srcs/sources_1/bd/TopLevel/ip/TopLevel_processing_system7_0_0/hdl/verilog/TopLevel_processing_system7_0_0.hwdef
new file mode 100644
index 0000000000000000000000000000000000000000..c205eddb39d989950f5b04921fd6dd0652483a98
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