From 3476e30ed254bc3b27d9a3a519e431402d6bb8a0 Mon Sep 17 00:00:00 2001 From: Tom Levens <tom.levens@cern.ch> Date: Wed, 1 Aug 2018 10:22:13 +0200 Subject: [PATCH] Add QIP file for core --- VfcDdr3.qip | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 VfcDdr3.qip diff --git a/VfcDdr3.qip b/VfcDdr3.qip new file mode 100644 index 0000000..321be71 --- /dev/null +++ b/VfcDdr3.qip @@ -0,0 +1,7 @@ +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "VfcDdr3.sv"] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "VfcDdr3Interface.sv"] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "VfcDdr3WbToAvl.sv"] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "VfcDdr3WbToAvlWithFetch.sv"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "Ddr3M/Ddr3M.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "Ddr3S/Ddr3S.qip"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "../BI_HDL_Cores/cores_for_synthesis/WbBus2M1S.v"] -- GitLab