Merge branch 'IntelSimART_21.0' into '21.0'

Simulation ART jobs should only run on Intel nodes See merge request atlas/athena!53467

Merge branch 'IntelSimART_21.0' into '21.0'
Simulation ART jobs should only run on Intel nodes See merge request atlas/athena!53467
da06cb49 · Julien Maurer · 699dc10f · d1120b9f · da06cb49 · da06cb49
Commit da06cb49 authored May 19, 2022 by Julien Maurer
--- a/Event/EventOverlay/OverlayMonitoringRTT/test/test_BSFilter.sh
+++ b/Event/EventOverlay/OverlayMonitoringRTT/test/test_BSFilter.sh
@@ -2,6 +2,7 @@

 # art-description: BSOverlayFilter_tf legacy test
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: master/Athena

--- a/Event/EventOverlay/OverlayMonitoringRTT/test/test_DataOverlayMC16.sh
+++ b/Event/EventOverlay/OverlayMonitoringRTT/test/test_DataOverlayMC16.sh
 #!/bin/sh

 # art-description: OverlayChain+Reco test for data16.
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-include: 21.0/Athena                                                    
 # art-include: 21.3/Athena                                                    

--- a/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_singlemu.sh
+++ b/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_singlemu.sh
@@ -2,6 +2,7 @@

 # art-description: MC+MC Overlay for MC16, single mu, no trigger
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena                                
 # art-include: 21.3/Athena                                        
 # art-include: master/Athena 

--- a/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_ttbar.sh
+++ b/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_ttbar.sh
 #!/bin/sh

 # art-description: MC+MC Overlay for MC16, ttbar, no trigger
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-include: 21.0/Athena                
 # art-include: 21.3/Athena           

--- a/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_ttbar_L1Calo.sh
+++ b/Event/EventOverlay/OverlayMonitoringRTT/test/test_MCOverlayMC16_ttbar_L1Calo.sh
@@ -2,6 +2,7 @@

 # art-description: MC+MC Overlay for MC16, ttbar, with L1Calo, no reco
 # art-type: grid
+# art-architecture:  '#x86_64-intel'
 # art-include: 21.0/Athena
 # art-include: 21.3/Athena
 # art-include: master/Athena

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFAST3_QS_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFAST3_QS_ttbar.sh
@@ -3,6 +3,7 @@
 # art-description: MC16-style simulation using ATLFAST3 with Quasi-stable particles
 # art-include: 21.0/Athena
 # art-athena-mt: 8
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFAST3_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFAST3_ttbar.sh
@@ -3,6 +3,7 @@
 # art-description: MC16-style simulation using ATLFAST3
 # art-include: 21.0/Athena
 # art-athena-mt: 8
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFASTIIF_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFASTIIF_ttbar.sh
@@ -4,6 +4,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFASTII_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_ATLFASTII_ttbar.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_QS_ZPrimebb_ExtraParticles.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_QS_ZPrimebb_ExtraParticles.sh
@@ -7,6 +7,7 @@
 # art-include: 21.9/Athena
 # art-include: master/Athena
 # art-include: master/AthSimulation
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_QS_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_QS_ttbar.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_MC16_FullG4_ttbar.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_ReSimulation.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_ReSimulation.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: log.*
 # art-output: original.HITS.pool.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTIIF_minbias.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTIIF_minbias.sh
@@ -4,6 +4,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTIIF_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTIIF_ttbar.sh
@@ -4,6 +4,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTII_ReproducibilityTest.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTII_ReproducibilityTest.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: hitsFull.ttbar.pool.root
 # art-output: hitsHalf1.ttbar.pool.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTII_ttbar.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_ATLFASTII_ttbar.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CalibrationHits_pions.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CalibrationHits_pions.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: truth.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CosmicSim.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CosmicSim.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root
 # art-output: test.TR.pool.root

--- a/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CosmicSimTR.sh
+++ b/Simulation/ISF/ISF_Validation/test/test_Sim_FullG4_CosmicSimTR.sh
@@ -5,6 +5,7 @@
 # art-include: 21.3/Athena
 # art-include: 21.9/Athena
 # art-include: master/Athena
+# art-architecture:  '#x86_64-intel'
 # art-type: grid
 # art-output: test.HITS.pool.root