diff --git a/ci/.launch_vivado.yml b/ci/.launch_vivado.yml index 04e1f053223f698045af9cf15e03c03703600814..a89d248a582d783732dd25c7e621900234b27e83 100644 --- a/ci/.launch_vivado.yml +++ b/ci/.launch_vivado.yml @@ -11,28 +11,28 @@ variables: EMPHUB_TAG: ${EMPHUB_TAG} IPBB_VERSION: "dev/2024e" -Generate Declaration Files: - stage: Generate Files - image: registry.cern.ch/docker.io/library/python - before_script: - - pip install --extra-index-url https://gitlab.cern.ch/api/v4/projects/186983/packages/pypi/simple dtcgenerator==0.0.6 - - apt-get update && apt-get install -y tree - script: - - cd ci - - dtcgenerator configs/b186-vu13p.yml - - tree generated-files - - find generated-files -name "*.vhd" | xargs cat - artifacts: - when: always - paths: - - ci/generated-files +# Generate Declaration Files: +# stage: Generate Files +# image: python +# before_script: +# - pip install --extra-index-url https://gitlab.cern.ch/api/v4/projects/186983/packages/pypi/simple dtcgenerator==0.0.6 +# - apt-get update && apt-get install -y tree +# script: +# - cd ci +# - dtcgenerator configs/b186-vu13p.yml +# - tree generated-files +# - find generated-files -name "*.vhd" | xargs cat +# artifacts: +# when: always +# paths: +# - ci/generated-files Make Project: needs: - Check Dependencies - Generate Declaration Files script: - - rsync -rv --ignore-missing-args ci/generated-files/* ./ci/builds/work/src/dtc/ # Move generated files to their correct locations + # - rsync -rv --ignore-missing-args ci/generated-files/* ./ci/builds/work/src/dtc/ # Move generated files to their correct locations - cd ci/builds/work - ipbb proj create vivado $PROJECT_NAME $BUILD_REPO:$PROJECT_ALGORITHM $PROJECT_DEPFILE - cd proj/$PROJECT_NAME diff --git a/dtc-fe/firmware/hdl/L1DataDecoder_PS10G.vhd b/dtc-fe/firmware/hdl/L1DataDecoder_PS10G.vhd index ae466ffdc27fd828287516eecfd7fbecd15ce75b..d2d2d7d7e9cd857b5a9c39560a56cbfaf862ade0 100644 --- a/dtc-fe/firmware/hdl/L1DataDecoder_PS10G.vhd +++ b/dtc-fe/firmware/hdl/L1DataDecoder_PS10G.vhd @@ -21,7 +21,7 @@ signal last_word : std_logic_vector(cL1DataFifoWidth-1 downto 0) := ( othe signal start_counter : integer range 0 to 31 := cL1StartSequenceThresh; signal header_counter : integer range -1 to 35; -signal payload_counter : integer range -1 to 4500; +signal payload_counter : integer range -3 to 4500; signal bit_counter : integer range -1 to cL1DataFifoWidth - 1; signal extra_word : std_logic := '0'; @@ -240,6 +240,11 @@ begin end if; + elsif payload_counter < -1 then -- payload_counter is -2 or -3 when Sclust = 0 and Pclust = 0 ie. no stub in the payload + + decoder <= store_event; + extra_word <= '0'; + else --payload_counter = -1, only one bit of the last two bits added to payload word is good decoder <= store_event; diff --git a/top/dtc-mini/b186-vu13p/firmware/hdl/emp_project_decl.vhd b/top/dtc-mini/b186-vu13p/firmware/hdl/emp_project_decl.vhd index 38a8bfd76980ee3edfce9bb6a1cea2622df88b18..ac732f5eb170ee2ac012467a9be3376ac6c419da 100644 --- a/top/dtc-mini/b186-vu13p/firmware/hdl/emp_project_decl.vhd +++ b/top/dtc-mini/b186-vu13p/firmware/hdl/emp_project_decl.vhd @@ -48,6 +48,9 @@ package emp_project_decl is -- 11 => (gty25, buf, no_fmt, buf, gty25), -- 12 => (gty25, buf, no_fmt, buf, gty25), -- 13 => (gty25, buf, no_fmt, buf, gty25), + 11 => (no_mgt, buf, no_fmt, buf, no_mgt), + 12 => (no_mgt, buf, no_fmt, buf, no_mgt), + 13 => (no_mgt, buf, no_fmt, buf, no_mgt), -- 14 => (gty25, buf, no_fmt, buf, gty25), -- 15 => kDummyRegion, -- Unconnected -- -- Cross-chip diff --git a/top/dtc-mini/b186-vu13p/firmware/hdl/link_maps.vhd b/top/dtc-mini/b186-vu13p/firmware/hdl/link_maps.vhd index ebbe9630527a426dee9243fe72907ffb733ffd9c..6fd32bf1c611a199c845fe0eec057615fa7aa8a8 100644 --- a/top/dtc-mini/b186-vu13p/firmware/hdl/link_maps.vhd +++ b/top/dtc-mini/b186-vu13p/firmware/hdl/link_maps.vhd @@ -6,7 +6,7 @@ use work.dtc_link_maps_func.all; package dtc_link_maps is constant cNumberOfFEModules : integer := 12; - constant cNumberOfOutputLinks : integer := 4; + constant cNumberOfOutputLinks : integer := 12; type tDTCInputLinkMap is array(0 to cNumberOfFEModules - 1) of tDTCInputLinkConfig; constant cDTCInputLinkMap : tDTCInputLinkMap := ( @@ -26,7 +26,7 @@ package dtc_link_maps is type tDTCOutputLinkMap is array(0 to cNumberOfOutputLinks - 1) of integer; constant cDTCOutputLinkMap : tDTCOutputLinkMap := ( - 12, 13, 14, 15 + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55 ); -end package dtc_link_maps; \ No newline at end of file +end package dtc_link_maps;