diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..fe8a2d349b0ebba9c78a67268559c9cfb20ce53b
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+ipbus_decode**
\ No newline at end of file
diff --git a/dtc-fe/firmware/cfg/sim.dep b/dtc-fe/firmware/cfg/sim.dep
new file mode 100644
index 0000000000000000000000000000000000000000..266e487c059bcccc88d62b3e3201ffc08403edf0
--- /dev/null
+++ b/dtc-fe/firmware/cfg/sim.dep
@@ -0,0 +1,40 @@
+src sim/LinkInterfaceSim.vhd
+
+src HeaderAligner.vhd
+
+src HeaderFingerprintChecker.vhd
+src HeaderFingerprintChecker_2S.vhd
+src HeaderFingerprintChecker_PS5G.vhd
+src HeaderFingerprintChecker_PS10G.vhd
+
+src HeaderExtractor.vhd
+src HeaderExtractor_2S.vhd
+src HeaderExtractor_PS5G.vhd
+src HeaderExtractor_PS10G.vhd
+
+src L1DataDecoder.vhd
+src L1DataDecoder_2S_CIC1.vhd
+src L1DataDecoder_2S_CIC2.vhd
+src L1DataDecoder_PS5G.vhd
+src L1DataDecoder_PS10G.vhd
+
+src StubInterleaver.vhd
+src StubExtractor.vhd
+src L1DataExtractor.vhd
+#src FrameAligner.vhd
+src StubConverter.vhd
+src HealthMonitor.vhd
+src LocalFastCommand.vhd
+src data_types.vhd
+src ipbus_decode_dtc_link_interface.vhd
+src module_constants.vhd
+src link_maps_func.vhd
+
+#src ../cgn/fifo_ctrl_16b_bram.xci
+#src ../cgn/fifo_data_32b_bram.xci
+
+addrtab -t dtc_link_interface.xml
+addrtab dtc_link_l1daq.xml
+addrtab dtc_link_fastcmd.xml
+addrtab dtc_link_fectrl.xml
+addrtab dtc_link_health_mon.xml
diff --git a/dtc-fe/firmware/hdl/sim/LinkInterfaceSim.vhd b/dtc-fe/firmware/hdl/sim/LinkInterfaceSim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..107ef4fffda7bc9f543ebab8aecfbf92cd7871cd
--- /dev/null
+++ b/dtc-fe/firmware/hdl/sim/LinkInterfaceSim.vhd
@@ -0,0 +1,161 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.emp_data_types.all;
+
+use work.module_constants.all;
+use work.front_end_data_types.all;
+use work.dtc_constants.all;
+use work.dtc_data_types.all;
+
+
+entity LinkInterface is
+generic (
+ module_type : string;
+ bandwidth : integer;
+ cic_type : string;
+ enable_monitoring : boolean := true;
+ emp_channel : integer := 0
+);
+port (
+ --- Input Ports ---
+ clk_p : in std_logic;
+ clk40 : in std_logic;
+ link_in : in lword := LWORD_NULL;
+ aligner_reset : in std_logic;
+ --- Output Ports ---
+ stub_out : out lword := LWORD_NULL;
+ header_out : out tCICHeaderArray(cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ --- Debug Ports ---
+ debug_header_start : out std_logic_vector(1 downto 0);
+ debug_header_match : out std_logic_vector(1 downto 0);
+ debug_aligner_state : out std_logic_vector(7 downto 0)
+);
+end LinkInterface;
+
+architecture rtl of LinkInterface is
+
+ -- Link decoding and module readout
+
+ signal headers : tCICHeaderArray(cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ signal stubs : ldata(cNumberOfCICs - 1 downto 0) := (others => LWORD_NULL);
+ signal stubs_interleaved : lword := LWORD_NULL;
+
+ signal aligner_state : tAlignerArray(cNumberOfCICs - 1 downto 0) := (others => (others => '0'));
+ signal header_start : std_logic_vector(cNumberOfCICs - 1 downto 0) := (others => '0');
+ signal sync_loss : std_logic_vector(cNumberOfCICs - 1 downto 0) := (others => '0');
+
+
+
+begin
+
+
+ header_out <= headers;
+
+ debug_header_start <= header_start;
+ debug_header_match <= sync_loss;
+ debug_aligner_state <= aligner_state(1) & aligner_state(0);
+
+
+
+ --==============================--
+ -- Link decoding and module readout
+ --==============================--
+
+
+ --==============================--
+ CicInterface: for i in 0 to cNumberOfCICs - 1 generate
+ --==============================--
+
+ signal stream_in : lword := LWORD_NULL;
+ signal stream_in_aligned : lword := LWORD_NULL;
+
+ signal l1_data_in : std_logic_vector(cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth)) -1 downto 0) := (Others=>'0');
+
+ begin
+
+ stream_in.valid <= link_in.valid;
+ stream_in.strobe <= '1';
+ stream_in.data(cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0) <= link_in.data(32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 32*i);
+
+ l1_data_in <= link_in.data(32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) + cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth))-1 downto 32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)));
+
+ --==============================--
+ HeaderAligner: entity work.HeaderAligner
+ --==============================--
+ generic map (
+ module_type => module_type,
+ bandwidth => bandwidth
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ data_in => stream_in,
+ reset => aligner_reset,
+ --- Output Ports ---
+ header_start => header_start(i),
+ state => aligner_state(i),
+ sync_loss => sync_loss(i)
+ );
+
+ --==============================--
+ StubExtractor: entity work.StubExtractor
+ --==============================--
+ generic map(
+ cic_index => i,
+ module_type => module_type,
+ bandwidth => bandwidth
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ data_in => stream_in,
+ header_start => header_start(i),
+ aligner_state => aligner_state(i),
+ --- Output Ports ---
+ stub_out => stubs(i),
+ header_out => headers(i)
+ );
+
+ end generate CicInterface;
+
+
+ --==============================--
+ -- Stub interleaving
+ --==============================--
+
+ --==============================--
+ StubInterleaver: entity work.StubInterleaver
+ --==============================--
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ stub_in_0 => stubs(0),
+ stub_in_1 => stubs(0),
+ --- Output Ports ---
+ stub_out => stubs_interleaved
+ );
+
+
+ --==============================--
+ -- Stub conversion for input to router
+ --==============================--
+
+ --==============================--
+ StubConverter: entity work.StubConverter
+ --==============================--
+ generic map (
+ module_type => module_type,
+ bandwidth => bandwidth
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ stub_in => stubs_interleaved,
+ --- Output Ports ---
+ stub_out => stub_out
+ );
+
+
+end rtl;
diff --git a/dtc-fe/testbenches/HeaderAligner/firmware/cfg/top.dep b/dtc-fe/testbenches/HeaderAligner/firmware/cfg/top.dep
new file mode 100644
index 0000000000000000000000000000000000000000..78b687d099a1f6f85b3e7691236bbfb08fe1b04e
--- /dev/null
+++ b/dtc-fe/testbenches/HeaderAligner/firmware/cfg/top.dep
@@ -0,0 +1,21 @@
+setup --cd ../ucf sim.tcl
+
+src TestBench.vhd
+src -c sim/common TestBenchIO.vhd
+
+src -c dtc-fe HeaderAligner.vhd
+src -c dtc-fe HeaderFingerprintChecker_2S.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS10G.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS5G.vhd
+src -c dtc-fe HeaderFingerprintChecker.vhd
+
+src -c dtc-fe module_constants.vhd
+
+src -c dtc-be/common data_types.vhd
+src -c dtc-be/common dtc_constants.vhd
+src -c emp-fwk:components/datapath emp_data_types.vhd
+
+@device_generation = "UltraScalePlus"
+@device_name = "xcku15p"
+@device_package = "-ffva1760"
+@device_speed = "-2-e"
\ No newline at end of file
diff --git a/dtc-fe/testbenches/HeaderAligner/firmware/hdl/TestBench.vhd b/dtc-fe/testbenches/HeaderAligner/firmware/hdl/TestBench.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fc197b6fbc072ed931eb5baacffdff82ec8bb123
--- /dev/null
+++ b/dtc-fe/testbenches/HeaderAligner/firmware/hdl/TestBench.vhd
@@ -0,0 +1,85 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.emp_data_types.all;
+use work.dtc_data_types.all;
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+ -- Clocks
+ signal clk_p : std_logic := '0';
+ signal clk40 : std_logic := '0';
+
+ -- Counters
+ signal global_counter : integer := 0;
+ signal boxcar_counter : integer := 0;
+
+ -- I/O streams
+ signal stream_in : lword := LWORD_NULL;
+ signal stubs : lword := LWORD_NULL;
+
+ -- Link Interface
+ signal aligner_reset : std_logic := '0';
+
+begin
+
+ -- Clocks
+ clk_p <= not clk_p after 3.125 ns;
+ clk40 <= not clk40 after 25 ns;
+
+ -- Counters
+ pIncrementCounter : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ global_counter <= global_counter + 1;
+ end if;
+ end process pIncrementCounter;
+
+ -- Resets
+ pReset : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ aligner_reset <= '0';
+ if global_counter = 10 then
+ aligner_reset <= '1';
+ end if;
+ end if;
+ end process pReset;
+
+ -- I/O
+ --==============================--
+ TestBenchIOInstance : entity work.TestBenchIO
+ --==============================--
+ generic map (
+ input_filename => "framed_stream.txt",
+ output_filename => "result.txt"
+ )
+ port map (
+ clk => clk_p,
+ data_out => stream_in
+ -- data_in => stubs
+ );
+
+ --==============================--
+ HeaderAligner: entity work.HeaderAligner
+ --==============================--
+ generic map (
+ module_type => "2S",
+ bandwidth => 5
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ data_in => stream_in,
+ reset => aligner_reset
+ --- Output Ports ---
+ -- header_start => header_start(i),
+ -- state => aligner_state(i),
+ -- sync_loss => sync_loss(i)
+ );
+
+end Behavioral;
diff --git a/dtc-fe/testbenches/HeaderAligner/firmware/ucf/sim.tcl b/dtc-fe/testbenches/HeaderAligner/firmware/ucf/sim.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..81a36fbafe277dcc20b2df16b65dbd7d2622e091
--- /dev/null
+++ b/dtc-fe/testbenches/HeaderAligner/firmware/ucf/sim.tcl
@@ -0,0 +1,6 @@
+set_property top testbench [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+update_compile_order -fileset sources_1
+set_property source_mgmt_mode DisplayOnly [current_project]
+
+import_files -fileset sim_1 -norecurse ../../src/dtc/dtc-fe/testbenches/HeaderAligner/framed_stream.txt
\ No newline at end of file
diff --git a/dtc-fe/testbenches/HeaderAligner/framed_stream.txt b/dtc-fe/testbenches/HeaderAligner/framed_stream.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7833ec6ca94fca2b7d25454fdc423fabd265aa84
--- /dev/null
+++ b/dtc-fe/testbenches/HeaderAligner/framed_stream.txt
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diff --git a/dtc-fe/testbenches/StubExtractor/firmware/cfg/top.dep b/dtc-fe/testbenches/StubExtractor/firmware/cfg/top.dep
new file mode 100644
index 0000000000000000000000000000000000000000..9aef382b665c88d9fda03f35792f8d1d233a2c29
--- /dev/null
+++ b/dtc-fe/testbenches/StubExtractor/firmware/cfg/top.dep
@@ -0,0 +1,28 @@
+setup --cd ../ucf sim.tcl
+
+src TestBench.vhd
+src -c sim/common TestBenchIO.vhd
+
+src -c dtc-fe StubExtractor.vhd
+src -c dtc-fe HeaderExtractor_2S.vhd
+src -c dtc-fe HeaderExtractor_PS5G.vhd
+src -c dtc-fe HeaderExtractor_PS10G.vhd
+src -c dtc-fe HeaderExtractor.vhd
+
+src -c dtc-fe HeaderAligner.vhd
+src -c dtc-fe HeaderFingerprintChecker_2S.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS10G.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS5G.vhd
+src -c dtc-fe HeaderFingerprintChecker.vhd
+
+src -c dtc-fe data_types.vhd
+src -c dtc-fe module_constants.vhd
+
+src -c dtc-be/common data_types.vhd
+src -c dtc-be/common dtc_constants.vhd
+src -c emp-fwk:components/datapath emp_data_types.vhd
+
+@device_generation = "UltraScalePlus"
+@device_name = "xcku15p"
+@device_package = "-ffva1760"
+@device_speed = "-2-e"
\ No newline at end of file
diff --git a/dtc-fe/testbenches/StubExtractor/firmware/hdl/TestBench.vhd b/dtc-fe/testbenches/StubExtractor/firmware/hdl/TestBench.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb3723a73ecd3b96f5f376c6f75949bea6ca45fc
--- /dev/null
+++ b/dtc-fe/testbenches/StubExtractor/firmware/hdl/TestBench.vhd
@@ -0,0 +1,106 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.emp_data_types.all;
+use work.dtc_data_types.all;
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+ -- Clocks
+ signal clk_p : std_logic := '0';
+ signal clk40 : std_logic := '0';
+
+ -- Counters
+ signal global_counter : integer := 0;
+ signal boxcar_counter : integer := 0;
+
+ -- I/O streams
+ signal stream_in : lword := LWORD_NULL;
+ signal stubs : lword := LWORD_NULL;
+
+ -- Link Interface
+ signal aligner_reset : std_logic := '0';
+ signal header_start : std_logic := '0';
+ signal aligner_state : std_logic_vector(3 downto 0) := (others => '0');
+
+begin
+
+ -- Clocks
+ clk_p <= not clk_p after 3.125 ns;
+ clk40 <= not clk40 after 25 ns;
+
+ -- Counters
+ pIncrementCounter : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ global_counter <= global_counter + 1;
+ end if;
+ end process pIncrementCounter;
+
+ -- Resets
+ pReset : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ aligner_reset <= '0';
+ if global_counter = 10 then
+ aligner_reset <= '1';
+ end if;
+ end if;
+ end process pReset;
+
+ -- I/O
+ --==============================--
+ TestBenchIOInstance : entity work.TestBenchIO
+ --==============================--
+ generic map (
+ input_filename => "framed_stream.txt",
+ output_filename => "result.txt"
+ )
+ port map (
+ clk => clk_p,
+ data_out => stream_in
+ -- data_in => stubs
+ );
+
+ --==============================--
+ HeaderAligner: entity work.HeaderAligner
+ --==============================--
+ generic map (
+ module_type => "2S",
+ bandwidth => 5
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ data_in => stream_in,
+ reset => aligner_reset,
+ --- Output Ports ---
+ header_start => header_start,
+ state => aligner_state
+ -- sync_loss => sync_loss(i)
+ );
+
+ --==============================--
+ StubExtractor: entity work.StubExtractor
+ --==============================--
+ generic map(
+ cic_index => 0,
+ module_type => "2S",
+ bandwidth => 5
+ )
+ port map(
+ --- Input Ports ---
+ clk => clk_p,
+ data_in => stream_in,
+ header_start => header_start,
+ aligner_state => aligner_state
+ --- Output Ports ---
+ -- stub_out => stubs(i),
+ -- header_out => headers(i)
+ );
+
+end Behavioral;
diff --git a/dtc-fe/testbenches/StubExtractor/firmware/ucf/sim.tcl b/dtc-fe/testbenches/StubExtractor/firmware/ucf/sim.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..81a36fbafe277dcc20b2df16b65dbd7d2622e091
--- /dev/null
+++ b/dtc-fe/testbenches/StubExtractor/firmware/ucf/sim.tcl
@@ -0,0 +1,6 @@
+set_property top testbench [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+update_compile_order -fileset sources_1
+set_property source_mgmt_mode DisplayOnly [current_project]
+
+import_files -fileset sim_1 -norecurse ../../src/dtc/dtc-fe/testbenches/HeaderAligner/framed_stream.txt
\ No newline at end of file
diff --git a/dtc-fe/testbenches/StubExtractor/framed_stream.txt b/dtc-fe/testbenches/StubExtractor/framed_stream.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7833ec6ca94fca2b7d25454fdc423fabd265aa84
--- /dev/null
+++ b/dtc-fe/testbenches/StubExtractor/framed_stream.txt
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diff --git a/dtc-fe/testbenches/StubInterleaver/firmware/cfg/top.dep b/dtc-fe/testbenches/StubInterleaver/firmware/cfg/top.dep
new file mode 100644
index 0000000000000000000000000000000000000000..27c4524ce93eb7ddcfee1a31d716c10390b634c8
--- /dev/null
+++ b/dtc-fe/testbenches/StubInterleaver/firmware/cfg/top.dep
@@ -0,0 +1,14 @@
+setup --cd ../ucf sim.tcl
+
+src TestBench.vhd
+
+src -c dtc-fe StubInterleaver.vhd
+
+src -c dtc-be/common data_types.vhd
+src -c dtc-be/common dtc_constants.vhd
+src -c emp-fwk:components/datapath emp_data_types.vhd
+
+@device_generation = "UltraScalePlus"
+@device_name = "xcku15p"
+@device_package = "-ffva1760"
+@device_speed = "-2-e"
\ No newline at end of file
diff --git a/dtc-fe/testbenches/StubInterleaver/firmware/hdl/TestBench.vhd b/dtc-fe/testbenches/StubInterleaver/firmware/hdl/TestBench.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..07c29bc82fd8b828ea9ada6fd81eb592d9a7004f
--- /dev/null
+++ b/dtc-fe/testbenches/StubInterleaver/firmware/hdl/TestBench.vhd
@@ -0,0 +1,60 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.emp_data_types.all;
+use work.dtc_data_types.all;
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+ -- Clocks
+ signal clk_p : std_logic := '0';
+ signal clk40 : std_logic := '0';
+
+ -- Counters
+ signal global_counter : integer := 0;
+ signal boxcar_counter : integer := 0;
+
+ -- I/O streams
+ signal stream_in : lword := LWORD_NULL;
+ signal stubs : lword := LWORD_NULL;
+
+ -- Link Interface
+ signal aligner_reset : std_logic := '0';
+ signal header_start_array : std_logic_vector(2 - 1 downto 0) := (others => '0');
+ signal header_start_array_buffered : std_logic_vector(2 - 1 downto 0) := (others => '0');
+ signal header_array : tCICHeaderArray(2 - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+
+begin
+
+ -- Clocks
+ clk_p <= not clk_p after 3.125 ns;
+ clk40 <= not clk40 after 25 ns;
+
+ -- Counters
+ pIncrementCounter : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ global_counter <= global_counter + 1;
+
+ if header_start_array(0) = '1' then
+ boxcar_counter <= boxcar_counter + 1;
+ end if;
+ end if;
+ end process pIncrementCounter;
+
+ -- Resets
+ pReset : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ aligner_reset <= '0';
+ if global_counter = 10 then
+ aligner_reset <= '1';
+ end if;
+ end if;
+ end process pReset;
+
+end Behavioral;
diff --git a/dtc-fe/testbenches/StubInterleaver/firmware/ucf/sim.tcl b/dtc-fe/testbenches/StubInterleaver/firmware/ucf/sim.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..55a402c6143007c396e5386ecaf2a13fd340c715
--- /dev/null
+++ b/dtc-fe/testbenches/StubInterleaver/firmware/ucf/sim.tcl
@@ -0,0 +1,2 @@
+set_property top testbench [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
\ No newline at end of file
diff --git a/sim/LinkInterface/firmware/cfg/top.dep b/sim/LinkInterface/firmware/cfg/top.dep
new file mode 100644
index 0000000000000000000000000000000000000000..d9a4acfa776c070141a36f51915603e4d8aa0914
--- /dev/null
+++ b/sim/LinkInterface/firmware/cfg/top.dep
@@ -0,0 +1,24 @@
+src TestBench.vhd
+src TestBenchIO.vhd
+
+src -c emp-fwk:components/datapath emp_data_types.vhd
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
+
+src -c ipbus-firmware:components/ipbus_slaves ipbus_dpram.vhd
+src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_v.vhd
+src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
+src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
+src -c ipbus-firmware:components/ipbus_core ipbus_dc_node.vhd
+src -c ipbus-firmware:components/ipbus_core ipbus_dc_fabric_sel.vhd
+
+include -c histogram:top histogram.dep
+include -c dtc-stub-processing:common tools.dep
+
+include -c dtc-fe sim.dep
+include -c dtc-be/common daqpath.dep
+include -c dtc-be/common common.dep
+
+@device_generation = "UltraScalePlus"
+@device_name = "xcku15p"
+@device_package = "-ffva1760"
+@device_speed = "-2-e"
diff --git a/sim/LinkInterface/firmware/hdl/TestBench.vhd b/sim/LinkInterface/firmware/hdl/TestBench.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..421f57061a6529bdad56758e9647e2b54f0f1354
--- /dev/null
+++ b/sim/LinkInterface/firmware/hdl/TestBench.vhd
@@ -0,0 +1,102 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.emp_data_types.all;
+use work.dtc_data_types.all;
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+ -- Clocks
+ signal clk_p : std_logic := '0';
+ signal clk40 : std_logic := '0';
+
+ -- Counters
+ signal global_counter : integer := 0;
+ signal boxcar_counter : integer := 0;
+
+ -- I/O streams
+ signal stream_in : lword := LWORD_NULL;
+ signal stubs : lword := LWORD_NULL;
+
+ -- Link Interface
+ signal aligner_reset : std_logic := '0';
+ signal header_start_array : std_logic_vector(2 - 1 downto 0) := (others => '0');
+ signal header_start_array_buffered : std_logic_vector(2 - 1 downto 0) := (others => '0');
+ signal header_array : tCICHeaderArray(2 - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+
+begin
+
+ -- Clocks
+ clk_p <= not clk_p after 3.125 ns;
+ clk40 <= not clk40 after 25 ns;
+
+ -- Counters
+ pIncrementCounter : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ global_counter <= global_counter + 1;
+
+ if header_start_array(0) = '1' then
+ boxcar_counter <= boxcar_counter + 1;
+ end if;
+ end if;
+ end process pIncrementCounter;
+
+ -- Resets
+ pReset : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ aligner_reset <= '0';
+ if global_counter = 10 then
+ aligner_reset <= '1';
+ end if;
+ end if;
+ end process pReset;
+
+ -- Buffers
+ pBuffer : process(clk_p)
+ begin
+ if rising_edge(clk_p) then
+ header_start_array_buffered <= header_start_array;
+ end if;
+ end process pBuffer;
+
+ -- I/O
+ TestBenchIOInstance : entity work.TestBenchIO
+ generic map (
+ input_filename => "framed_stream.txt",
+ output_filename => "result.txt"
+ )
+ port map (
+ clk => clk_p,
+ data_out => stream_in,
+ data_in => stubs
+ );
+
+ -- Link Interface
+ --==============================--
+ LinkInterfaceInstance: entity work.LinkInterface
+ --==============================--
+ generic map(
+ module_type => "2S",
+ bandwidth => 5,
+ cic_type => "CIC2"
+ )
+ port map(
+ --- Input Ports ---
+ clk_p => clk_p,
+ clk40 => clk40,
+ link_in => stream_in,
+ aligner_reset => aligner_reset,
+ --- Output Ports ---
+ stub_out => stubs,
+ header_out => header_array,
+ --- Debug Ports ---
+ debug_header_start => header_start_array
+ );
+
+end Behavioral;
diff --git a/sim/common/firmware/hdl/TestBenchIO.vhd b/sim/common/firmware/hdl/TestBenchIO.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9181a73028528f6dd45cf4660d0cdbe7eb4daae0
--- /dev/null
+++ b/sim/common/firmware/hdl/TestBenchIO.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 31.08.2022 10:20:55
+-- Design Name:
+-- Module Name: TestBenchIO - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_textio.all;
+use std.textio.all;
+use work.emp_data_types.all;
+
+
+entity TestBenchIO is
+ generic (
+ input_filename : string;
+ output_filename : string;
+ input_line_width : integer := 16;
+ output_line_width : integer := 32
+ );
+ port (
+ clk : in std_logic;
+ data_out : out lword := LWORD_NULL;
+ data_in : in lword := LWORD_NULL
+ );
+end TestBenchIO;
+
+architecture Behavioral of TestBenchIO is
+begin
+ -- Process that reads file and outputs a line each clock cycle as a logic
+ -- vector. NOTE: Option to also write to file is commented out but kept for
+ -- future reference.
+ process is
+ variable line_v : line;
+ variable line_v_w : line;
+ file read_file : text;
+ file write_file : text;
+ variable slv_v : std_logic_vector(input_line_width - 1 downto 0);
+ variable slv_v_w : std_logic_vector(output_line_width - 1 downto 0);
+ begin
+ file_open(read_file, input_filename, read_mode);
+ file_open(write_file, output_filename, write_mode);
+ while not endfile(read_file) loop
+ wait until clk = '1' and clk'event;
+ readline(read_file, line_v);
+ hread(line_v, slv_v);
+ data_out.data(input_line_width - 1 downto 0) <= slv_v;
+ data_out.valid <= '1';
+ data_out.strobe <= '1';
+ slv_v_w := data_in.data(output_line_width - 1 downto 0);
+ hwrite(line_v_w, slv_v_w);
+ writeline(write_file, line_v_w);
+ end loop;
+ file_close(read_file);
+ data_out.valid <= '0';
+ file_close(write_file);
+ wait;
+ end process;
+end Behavioral;