diff --git a/ci/.launch_vivado.yml b/ci/.launch_vivado.yml
index c605ae9b8901878e7274eda6aa587e9e7e649e79..2a7f37691b61ac821e999bd685cd8cca92fd9386 100644
--- a/ci/.launch_vivado.yml
+++ b/ci/.launch_vivado.yml
@@ -5,12 +5,12 @@ include:
 
 variables:
   IPBB_OS: "c8"
-  VIVADO_VER: "2022.2"
+  VIVADO_VER: "2023.2"
   PROJECT_DEPFILE: ${PROJECT_DEPFILE}
   PROJECT_ALGORITHM: ${PROJECT_ALGORITHM}
   PROJECT_NAME: "dtc"
   EMPHUB_TAG: ${EMPHUB_TAG}
-  IPBB_VER: "dev-2023a-v1.3"
+  IPBB_VER: "dev-2024b-v1.5"
 
 .vivado-job-build:
   tags:
@@ -38,7 +38,6 @@ Make Project:
     - source /opt/Xilinx/Vivado/$VIVADO_VER/settings64.sh
     - rsync -rv --ignore-missing-args ci/generated-files/* ./ # Move generated files to their correct locations
     - python3 /ci-tools/setup_project.py $CI_PROJECT_DIR/dependencies.yml
-#    - cp -r $CI_PROJECT_DIR/replacements/* $CI_PROJECT_DIR/ci/builds/work/src/
   script:
     - cd ci/builds/work
     - ipbb proj create vivado $PROJECT_NAME $BUILD_REPO:$PROJECT_ALGORITHM $PROJECT_DEPFILE
diff --git a/dependencies.yml b/dependencies.yml
index 4f15d5b7ed45aada2f54967ceee172a699fcf3d4..0ecc2dd32787c81a3facc9b8490a6febeb1ba721 100644
--- a/dependencies.yml
+++ b/dependencies.yml
@@ -1,7 +1,7 @@
 ---
 sources:
     emp-fwk:
-        tag: v0.9.0-alpha2
+        tag: v0.9.0-alpha3
         url: https://gitlab.cern.ch/p2-xware/firmware/emp-fwk.git
 
     ttc_legacy:
@@ -25,7 +25,7 @@ sources:
         url: https://gitlab.cern.ch/cms-tcds/cms-tcds2-firmware.git
 
     tclink:
-        commit: fda0bcf
+        commit: fda0bcf07c501f81daeec1421ffdfb46f828f823
         url: https://gitlab.cern.ch/HPTD/tclink.git
 
     slink-ip:
@@ -55,5 +55,3 @@ sources:
     daqpath-toolkit:
         branch: master
         url: https://gitlab.cern.ch/dmonk/daqpath-toolkit.git
-
-
diff --git a/dtc-fe/firmware/cfg/common.dep b/dtc-fe/firmware/cfg/common.dep
index 638af2a455437e453b5add665909e24241dc78b1..ee436e2cc14cf07a7cc703a7fc52f430b6e3131c 100644
--- a/dtc-fe/firmware/cfg/common.dep
+++ b/dtc-fe/firmware/cfg/common.dep
@@ -24,7 +24,7 @@ src L1DataExtractor.vhd
 #src FrameAligner.vhd
 src StubConverter.vhd
 src HealthMonitor.vhd
-src LocalFastCommand.vhd
+src --vhdl2008 LocalFastCommand.vhd
 src data_types.vhd
 src ipbus_decode_dtc_link_interface.vhd
 src module_constants.vhd
diff --git a/dtc-fe/firmware/hdl/LinkInterface.vhd b/dtc-fe/firmware/hdl/LinkInterface.vhd
index 32438e57214288c08817becbafb3834e6feadfdb..b9bf487538b5d4a88b43df8d72656e98b49317f0 100644
--- a/dtc-fe/firmware/hdl/LinkInterface.vhd
+++ b/dtc-fe/firmware/hdl/LinkInterface.vhd
@@ -21,6 +21,7 @@ generic (
     module_type : string;
     bandwidth   : integer;
     cic_type    : string;
+    enable_monitoring : boolean := true;
     emp_channel : integer := 0
 );
 port (
@@ -306,27 +307,32 @@ port map(
 -- Health Monitoring
 --==============================--
 
+genMonitoring : if enable_monitoring = true generate
 
---==============================--
-HealthMonitor: entity work.HealthMonitor
---==============================--
-port map(
-        --- Input Ports ---
-        clk_p                 => clk_p,
-        header_start          => header_start,
-        sync_loss             => sync_loss,
-        header_in             => headers,
-        aligner_state         => aligner_state,
-        counter_reset         => fe_control_registers(0)(2),
-        uplink_rdy_i          => link_in.data(62),
-        --- Output Ports ---
+begin
 
-        --- IPBus Ports ---
-        clk                   => clk,                       
-        rst                   => rst,                       
-        ipb_in                => ipb_to_slaves(N_SLV_HEALTH_MON),  
-        ipb_out               => ipb_from_slaves(N_SLV_HEALTH_MON)
-    );
+    --==============================--
+    HealthMonitor: entity work.HealthMonitor
+    --==============================--
+    port map(
+            --- Input Ports ---
+            clk_p                 => clk_p,
+            header_start          => header_start,
+            sync_loss             => sync_loss,
+            header_in             => headers,
+            aligner_state         => aligner_state,
+            counter_reset         => fe_control_registers(0)(2),
+            uplink_rdy_i          => link_in.data(62),
+            --- Output Ports ---
+
+            --- IPBus Ports ---
+            clk                   => clk,                       
+            rst                   => rst,                       
+            ipb_in                => ipb_to_slaves(N_SLV_HEALTH_MON),  
+            ipb_out               => ipb_from_slaves(N_SLV_HEALTH_MON)
+        );
+
+end generate genMonitoring;
 
 
 end rtl;
diff --git a/dtc-fe/firmware/hdl/LocalFastCommand.vhd b/dtc-fe/firmware/hdl/LocalFastCommand.vhd
index abcf15a51bfc28af672131957c34372fd5a5ef34..a2a5e7803c0bb7ca6e9ea57057a810eb00c3dcc7 100644
--- a/dtc-fe/firmware/hdl/LocalFastCommand.vhd
+++ b/dtc-fe/firmware/hdl/LocalFastCommand.vhd
@@ -38,8 +38,9 @@ constant PIPE_WIDTH             : integer := 8;
 
 -- IPBus registers
 
-signal fast_cmd_status          : ipb_reg_v(3 downto 0) := (others => (others => '0'));
-signal fast_cmd_ctrl            : ipb_reg_v(3 downto 0) := (others => (others => '0'));
+signal fast_cmd_status          : ipb_reg_v(3 downto 0);
+signal fast_cmd_ctrl            : ipb_reg_v(3 downto 0);
+signal fast_cmd_ctrl_latched    : ipb_reg_v(3 downto 0);
 
 signal source_mask              : std_logic_vector(3 downto 0) := (others => '0');
 signal gen_run                  : std_logic := '0';
@@ -119,22 +120,22 @@ begin
     if rising_edge(clk40) then
 
         -- latch IPBus control registers in payload clock domain
-        source_mask     <= fast_cmd_ctrl(0)(3 downto 0);
-        gen_run         <= fast_cmd_ctrl(0)(4);
-        gen_cntr_mode   <= fast_cmd_ctrl(0)(5);
-        gen_repeat      <= to_integer(unsigned(fast_cmd_ctrl(0)(15 downto 6)));
+        source_mask     <= fast_cmd_ctrl_latched(0)(3 downto 0);
+        gen_run         <= fast_cmd_ctrl_latched(0)(4);
+        gen_cntr_mode   <= fast_cmd_ctrl_latched(0)(5);
+        gen_repeat      <= to_integer(unsigned(fast_cmd_ctrl_latched(0)(15 downto 6)));
 
-        tap_select      <= to_integer(unsigned(fast_cmd_ctrl(0)(18 downto 16)));
+        tap_select      <= to_integer(unsigned(fast_cmd_ctrl_latched(0)(18 downto 16)));
 
         -- 16b fast command generator commands : instruction [2b] + wait counter [10b] + fast command [4b]
         -- instructions : 0 = return to first word; 1 = move to next word; 2 = stop at this word; 3 = undefined
         -- fast commands: bit3 = fast_reset; bit2 = l1a_trigger; bit1 = cal_pulse; bit0 = counter_reset
-        gen_buffer(0) <= fast_cmd_ctrl(1)(15 downto 0);
-        gen_buffer(1) <= fast_cmd_ctrl(1)(31 downto 16);
-        gen_buffer(2) <= fast_cmd_ctrl(2)(15 downto 0);
-        gen_buffer(3) <= fast_cmd_ctrl(2)(31 downto 16);
-        gen_buffer(4) <= fast_cmd_ctrl(3)(15 downto 0);
-        gen_buffer(5) <= fast_cmd_ctrl(3)(31 downto 16);
+        gen_buffer(0) <= fast_cmd_ctrl_latched(1)(15 downto 0);
+        gen_buffer(1) <= fast_cmd_ctrl_latched(1)(31 downto 16);
+        gen_buffer(2) <= fast_cmd_ctrl_latched(2)(15 downto 0);
+        gen_buffer(3) <= fast_cmd_ctrl_latched(2)(31 downto 16);
+        gen_buffer(4) <= fast_cmd_ctrl_latched(3)(15 downto 0);
+        gen_buffer(5) <= fast_cmd_ctrl_latched(3)(31 downto 16);
         gen_buffer(6) <= (others => '0');   --null buffer
 
         -- only run fast command generator when gen_run enabled
@@ -295,6 +296,8 @@ begin
 
     if rising_edge(clk_p) then
 
+        fast_cmd_ctrl_latched <= fast_cmd_ctrl;
+
         -- latch delayed commands into clk_p domain and hold
         data_out_cache2.data(15 downto 0)  <= fastCommandToSLV(cmd_fe);
         data_out_cache2.data(31 downto 16) <= fastCommandToSLV(cmd_cic);
@@ -305,7 +308,7 @@ begin
 
 end process to_clkp;
 
-data_out.valid  <= '1';
-data_out.strobe <= '1';
+data_out_cache.valid  <= '1';
+data_out_cache.strobe <= '1';
 
 end rtl;
diff --git a/replacements/.gitkeep b/replacements/.gitkeep
deleted file mode 100644
index 8b137891791fe96927ad78e64b0aad7bded08bdc..0000000000000000000000000000000000000000
--- a/replacements/.gitkeep
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl b/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl
deleted file mode 100644
index 70dc8b777be9b89fd7f23a74b341dea9b087f851..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl
+++ /dev/null
@@ -1,51 +0,0 @@
-# 40MHz & payload I/O clocks derived from board-local source (for tests without external clock source)
-create_generated_clock -name clk_40_pseudo_i [get_pins ttc/bufgce_clk_40_rx/O]
-create_generated_clock -name clk_40_pseudo   -source [get_pins ttc/clocks/mmcm/CLKIN2] [get_pins ttc/clocks/mmcm/CLKOUT1]
-create_generated_clock -name clk_payload_pseudo -source [get_pins ttc/clocks/mmcm/CLKIN2] [get_pins ttc/clocks/mmcm/CLKOUT3]
-
-# Names of the LHC-synchronised derived clocks that are used by payload and infra (outside of TTC block)
-lappend lMainInternalClocks clk_40_pseudo clk_payload_pseudo
-
-
-if {[llength [get_pins -quiet ttc/gen_master_legacy.osc_clock/mmcm/CLKOUT1]] != 0} {
-    create_generated_clock -name clk_40_extern_i0 [get_pins ttc/gen_master_legacy.osc_clock/gen_mmcm/mmcm/CLKOUT1]
-}
-
-if {[llength [get_pins -quiet ttc/gen_master_tcds2.tcds2/tcds2_interface/bufgce_clk_40_rx/O]] != 0} {
-    create_generated_clock -name clk_40_extern_i1 [get_pins ttc/gen_master_tcds2.tcds2/tcds2_interface/bufgce_clk_40_rx/O]
-}
-
-foreach i [list 0 1] {
-    if {[llength [get_clocks -quiet clk_40_extern_i$i]] != 0 } {
-        create_generated_clock -name clk_40_extern$i -master_clock [get_clocks clk_40_extern_i$i] [get_pins ttc/clocks/mmcm/CLKOUT1]
-        # Payload I/O clock derived from external oscillator
-        create_generated_clock -name clk_payload_extern$i -master_clock [get_clocks clk_40_extern_i$i] [get_pins ttc/clocks/mmcm/CLKOUT3]
-
-        lappend lMainInternalClocks clk_40_extern_i$i clk_40_extern$i clk_payload_extern$i
-    }
-}
-
-
-# Clock groups: Asynchronous
-puts "lMainInternalClocks = $lMainInternalClocks"
-set_clock_groups -asynch -group [get_clocks axi_clk] -group [get_clocks -include_generated_clocks ipbus_clk]
-set_clock_groups -asynch -group [get_clocks -include_generated_clocks ipbus_clk] -group $lMainInternalClocks
-
-# Clock groups: Logically exclusive
-# The 40MHz, 160MHz and payload clocks used across the chip are generated by an MMCM with two clock sources:
-#  * an externally-provided LHC clock (typically from TCDS), which itself could come from one of two interfaces (clk_40_externN); and
-#  * an internally-generated 'pseudo-LHC' clock (clk_40_pseudo)
-# Must set the copies of the clocks generated from those sources as logically exclusive
-foreach lMasterA [list clk_40_pseudo_i clk_40_pseudo_i clk_40_extern_i0] lMasterB [list clk_40_extern_i0 clk_40_extern_i1 clk_40_extern_i1] {
-    if {[llength [get_clocks -quiet [list $lMasterA $lMasterB]]] == 2} {
-        puts "Declaring clocks derived from $lMasterA and $lMasterB as logically exclusive"
-        set_clock_groups -logically_exclusive -group [get_clocks -filter "MASTER_CLOCK == $lMasterA"] -group [get_clocks -filter "MASTER_CLOCK == $lMasterB"]
-    }
-}
-
-
-# Remove timing constraints for heartbeat LED output port
-set_false_path -to [get_ports -regexp "(.+_led|led_.+)"]
-
-# Print clock report for the record (in case build fails, or need to debug clock-related issues)
-report_clocks
diff --git a/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl b/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl
deleted file mode 100644
index e49c9d01bf70044ca92097b07f2b08af5d7cfb57..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl
+++ /dev/null
@@ -1,12 +0,0 @@
-
-# 100 Mhz PCIe system clock
-create_clock -period 10.000 -name pcie_sys_clk [get_ports pcie_sys_clk_p]
-
-# IPbus clock
-create_generated_clock -name ipbus_clk -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT1]
-
-# AXI clock
-create_generated_clock -name axi_clk [get_pins -hierarchical -filter {NAME =~infra/dma/xdma/*/phy_clk_i/bufg_gt_userclk/O}]
-
-# Approx 40MHz clock derived from AXI clock (for tests without external clock source)
-#create_generated_clock -name clk_40_pseudo_i [get_pins infra/clocks/mmcm/CLKOUT2]
diff --git a/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd b/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd
deleted file mode 100644
index bf1c409c13f1737afb61e6a7174fac6e8e9c0552..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd
+++ /dev/null
@@ -1,589 +0,0 @@
--- ttc
---
--- TTC decoder, counters, LHC clock distribution, etc
---
--- Dave Newbold, June 2013
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.VComponents.all;
-
-use work.ipbus.all;
-use work.ipbus_reg_types.all;
-use work.ipbus_decode_emp_ttc.all;
-use work.emp_ttc_decl.all;
-use work.emp_ttc_utils;
-
-use work.emp_device_decl;
-use work.emp_project_decl.all;
-
-use work.tcds2_interface_pkg;
-use work.tcds2_streams_pkg;
-
-
--------------------------------------------------------------------------------
-entity emp_ttc is
-  generic(
-    ENABLE_LEGACY_TTC : boolean;
-    ENABLE_TCDS2      : boolean;
-    EXT_CLK_FREQ      : real
-    );
-  port(
-    -- ipbus clock & rst
-    clk_ipb      : in  std_logic;
-    rst_ipb      : in  std_logic;
-    -- IPBus
-    ipb_in       : in  ipb_wbus;
-    ipb_out      : out ipb_rbus;
-    -- 125MHz clock
-    clk125       : in  std_logic;
-    -- internal pseudo-40MHz clock
-    clk40ish_in  : in  std_logic;
-    -- clock outputs
-    clk40        : out std_logic;
-    -- clock domain reset outputs
-    rst40        : out std_logic;
-    clk_p        : out std_logic;
-    rst_p        : out std_logic;
-    clks_aux     : out std_logic_vector(2 downto 0);
-    rsts_aux     : out std_logic_vector(2 downto 0);
-    -- Legacy TTC interface
-    ttc_clk_p    : in  std_logic;
-    ttc_clk_n    : in  std_logic;
-    ttc_rx_p     : in  std_logic;
-    ttc_rx_n     : in  std_logic;
-    -- TCDS2 interface
-    tcds_clk_p   : in  std_logic;
-    tcds_clk_n   : in  std_logic;
-    tcds_rx_p    : in  std_logic;
-    tcds_rx_n    : in  std_logic;
-    tcds_tx_p    : out std_logic;
-    tcds_tx_n    : out std_logic;
-    -- TTC b command output
-    ttc_cmd      : out ttc_cmd_t;
-    ttc_cmd_dist : out ttc_cmd_t;
-    -- L1A output
-    ttc_l1a      : out std_logic;
-    -- L1A qualifier output
-    ttc_l1a_dist : out std_logic;
-    dist_lock    : in  std_logic;
-    bunch_ctr    : out bctr_t;
-    evt_ctr      : in  eoctr_t;
-    orb_ctr      : out eoctr_t;
-    oc_flag      : out std_logic;
-    ec_flag      : out std_logic;
-    -- clock monitoring inputs from MGTs
-    monclk       : in  std_logic_vector(3 downto 0);
-    clk125_o     : out std_logic
-    );
-
-end emp_ttc;
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
-architecture rtl of emp_ttc is
-
-  signal clk40_ext, clk40_ext_legacy, clk40_ext_tcds2                                     : std_logic;
-  signal tcds_refclk_b, tcds_refclk_div                                                   : std_logic;
-  signal clk40_i, rst40_i, clk160s, clk40_div, rsti, rsti_40, clk40_a, rst40_a, clk_p_i, rst_p_i   : std_logic;
-  signal lock, stop                                                                       : std_logic;
-  signal clks_aux_i, rsts_aux_i                                                           : std_logic_vector(2 downto 0);
-  signal l1a_ext_legacy, l1a_ext_tcds2                                                    : std_logic;
-  signal l1a, l1a_ttc, l1a_del, l1a_ext, l1a_pend, cmd_bx, cmd_pend, l1a_issue, cmd_issue : std_logic;
-  signal cmd, cmd_ttc, cmd_del, cmd_ext_tcds2, cmd_ext_legacy                             : ttc_cmd_t;
-  signal psok, bc0_fr, ctr_clr                                                            : std_logic;
-  signal bunch_ctr_i                                                                      : bctr_t;
-  signal req_bx                                                                           : unsigned(bctr_t'range);
-  signal orb_ctr_i                                                                        : eoctr_t;
-  signal clk40_mmcm_sel                                                                   : std_logic;
-
-  signal stat_clk40 : ipb_reg_v(0 downto 0);
-  signal ctrl_clk40 : ipb_reg_v(0 downto 0);
-
-  signal stat_common : ipb_reg_v(2 downto 0);
-  signal ctrl_common : ipb_reg_v(0 downto 0);
-  signal stb_common  : std_logic_vector(0 downto 0);
-
-  signal bc0_lock : std_logic;
-  signal ipbw     : ipb_wbus_array(N_SLAVES - 1 downto 0);
-  signal ipbr     : ipb_rbus_array(N_SLAVES - 1 downto 0);
-  
-  signal clk_40_to_mmcm : std_logic;
-
-begin
-
-
-
--- ipbus address decode
-
-  fabric : entity work.ipbus_fabric_sel
-    generic map(
-      NSLV      => N_SLAVES,
-      SEL_WIDTH => IPBUS_SEL_WIDTH)
-    port map(
-      ipb_in          => ipb_in,
-      ipb_out         => ipb_out,
-      sel             => ipbus_sel_emp_ttc(ipb_in.ipb_addr),
-      ipb_to_slaves   => ipbw,
-      ipb_from_slaves => ipbr
-      );
-
--- TTC control registers
-
-  reg_clk40 : entity work.ipbus_ctrlreg_v
-    generic map (
-      N_CTRL => 1,
-      N_STAT => 1
-      )
-    port map (
-      clk       => clk_ipb,
-      reset     => rst_ipb,
-      ipbus_in  => ipbw(N_SLV_CLK40),
-      ipbus_out => ipbr(N_SLV_CLK40),
-      d         => stat_clk40,
-      q         => ctrl_clk40,
-      stb       => open
-      );
-
-  stat_clk40(0)(0) <= lock;
-  stat_clk40(0)(1) <= stop;
-
-  reg_common : entity work.ipbus_syncreg_v
-    generic map(
-      N_CTRL => 1,
-      N_STAT => 3
-      )
-    port map(
-      clk     => clk_ipb,
-      rst     => rst_ipb,
-      ipb_in  => ipbw(N_SLV_MASTER_COMMON),
-      ipb_out => ipbr(N_SLV_MASTER_COMMON),
-      slv_clk => clk40_a,
-      d       => stat_common,
-      q       => ctrl_common,
-      stb     => stb_common
-      );
-
-  stat_common(0)(0) <= '1' when ENABLE_LEGACY_TTC else '0';
-  stat_common(0)(1) <= '1' when ENABLE_TCDS2      else '0';
-
-
-  -- Mux for external clocks
-  gen_ext_mux : if ENABLE_TCDS2 and ENABLE_LEGACY_TTC generate
-
-    signal sel_pipeline : std_logic_vector(3 downto 0);
- 
-  begin
-
-    process (clk_ipb)
-    begin
-      if rising_edge(clk_ipb) then
-        sel_pipeline(0) <= ctrl_clk40(0)(2);
-        sel_pipeline(1) <= sel_pipeline(0);
-        sel_pipeline(2) <= sel_pipeline(1);
-        sel_pipeline(3) <= sel_pipeline(2);
-      end if;
-    end process;
-
-    clk40mux : BUFGMUX
-      port map (
-        S  => sel_pipeline(3),
-        I0 => clk40_ext_legacy,
-        I1 => clk40_ext_tcds2,
-        O  => clk40_ext
-        );
-
-  elsif ENABLE_TCDS2 generate
-
-    clk40_ext <= clk40_ext_tcds2;
-
-  else generate
-
-    clk40_ext <= clk40_ext_legacy;
-
-  end generate;
-
-
--- MMCM for clock multiplication / phase adjustment
-
-  rsti           <= rst_ipb or ctrl_common(0)(2);
-  clk40_mmcm_sel <= ctrl_clk40(0)(1) or ctrl_clk40(0)(2);
-  
-  bufgce_clk_40_rx : bufgce_div
-    generic map (
-      BUFGCE_DIVIDE => 8
-    )
-    port map (
-      i   => tcds_refclk_b,
-      o   => clk_40_to_mmcm,
-      ce  => '1',
-      clr => '0'
-    );  
-
-  clocks : entity work.emp_ttc_clocks
-    port map(
-      clk_40       => clk40_ext,
-      clk_40pseudo => clk_40_to_mmcm,
-      clko_40      => clk40_i,
-      clko_p       => clk_p_i,
-      clko_aux     => clks_aux_i,
-      rsto_40      => rst40_i,
-      rsto_p       => rst_p_i,
-      rsto_aux     => rsts_aux_i,
-      clko_160s    => clk160s,
-      stopped      => stop,
-      locked       => lock,
-      rst_mmcm     => ctrl_clk40(0)(0),
-      rsti         => rsti_40,
-      clksel       => clk40_mmcm_sel,
-      psval        => ctrl_common(0)(23 downto 12),
-      psok         => psok,
-      psen         => ctrl_common(0)(24)
-      );
-
-  clk40_a  <= clk40_i;  -- Needed to make sure delta delays line up in simulation!
-  rst40_a  <= rst40_i;
-  clk40    <= clk40_i;
-  rst40    <= rst40_i;
-  clk_p    <= clk_p_i;
-  rst_p    <= rst_p_i;
-  clks_aux <= clks_aux_i;
-  rsts_aux <= rsts_aux_i;
-
--- TTC protocol decoder
-
-  gen_master_tcds2 : if ENABLE_TCDS2 generate
-
-    signal clk125_i, clk125_b : std_logic;
-    signal tcds_refclk        : std_logic;
-    signal tcds_refclk_i      : std_logic;
-    signal tcds_orbit_pulse   : std_logic;
-
-    signal channel0_ttc2, channel1_ttc2 : tcds2_streams_pkg.tcds2_ttc2;
-    signal tcds2_interface_ctrl : tcds2_interface_pkg.tcds2_interface_ctrl_t;
-    signal tcds2_interface_stat : tcds2_interface_pkg.tcds2_interface_stat_t;
-
-  begin
-
-    clk125_o <= clk125_b;
-
-    ibufds_gt : IBUFDS_GTE4
-      port map (
-        i     => tcds_clk_p,
-        ib    => tcds_clk_n,
-        o     => tcds_refclk,
-        odiv2 => tcds_refclk_i,
-        ceb   => '0'
-        );
-
-    ibuf_osc : IBUF
-      port map (
-        O => clk125_i,
-        I => clk125
-        );
-
-    bufg_osc : BUFG
-      port map (
-        I => clk125_i,
-        O => clk125_b
-        );
-
-    bufg_ref : BUFG_GT
-      port map (
-        i       => tcds_refclk_i,
-        o       => tcds_refclk_b,
-        ce      => '1',
-        clr     => '0',
-        div     => "000",
-        cemask  => '1',
-        clrmask => '0'
-        );
-
-    tcds2 : entity work.tcds2_interface_with_mgt
-      generic map (
-        G_MGT_TYPE => emp_ttc_utils.get_tcds2_mgt_type(emp_device_decl.TCDS2_MGT_TYPE),
-        G_LINK_SPEED => emp_ttc_utils.get_tcds2_link_speed(emp_device_decl.TCDS2_SPEED),
-        G_INCLUDE_PRBS_LINK_TEST => true
-        )
-      port map (
-        ctrl_i => tcds2_interface_ctrl,
-        stat_o => tcds2_interface_stat,
-
-        clk_sys_125mhz => clk125_b,
-
-        mgt_tx_p_o => tcds_tx_p,
-        mgt_tx_n_o => tcds_tx_n,
-        mgt_rx_p_i => tcds_rx_n,
-        mgt_rx_n_i => tcds_rx_p,
-
-        clk_320_mgt_ref_i => tcds_refclk,
-
-        clk_40_o => clk40_ext_tcds2,
-
-        orbit_o => tcds_orbit_pulse,
-
-        channel0_ttc2_o    => channel0_ttc2,
-        channel0_tts2_i(0) => tcds2_streams_pkg.C_TCDS2_TTS2_VALUE_IGNORED,
-        channel1_ttc2_o    => channel1_ttc2,
-        channel1_tts2_i(0) => tcds2_streams_pkg.C_TCDS2_TTS2_VALUE_IGNORED
-        );
-
-    process (clk40_a)
-    begin
-      if rising_edge(clk40_a) then
-        -- Only consider a BC0 signal to be received if I see it on both of those channels in the same BX
-        -- Reason: Improve robustness against bitflips in TTC path for Serenity
-        -- TODO: Set this behvaviour using SW-settable register in v0.7.0, rather than hardcoding
-        if (channel0_ttc2.sync_flags_and_commands(0) = '1') and (channel1_ttc2.sync_flags_and_commands(0) = '1') then
-          cmd_ext_tcds2 <= TTC_BCMD_BC0;
-        else
-          cmd_ext_tcds2 <= TTC_BCMD_NULL;
-        end if;
-
-        rsti_40 <= rsti;
-
-      end if;
-    end process;
-
-    l1a_ext_tcds2 <= '0';
-
-    csr : entity work.ipbus_tcds2_interface_accessor
-      port map (
-        clk_ipb => clk_ipb,
-        rst_ipb => rst_ipb,
-        ipb_in  => ipbw(N_SLV_MASTER_TCDS2),
-        ipb_out => ipbr(N_SLV_MASTER_TCDS2),
-
-        ctrl_o => tcds2_interface_ctrl,
-        stat_i => tcds2_interface_stat
-        );
-
-  else generate
-
-    tcds_tx_p <= '0';
-    tcds_tx_n <= '0';
-
-    tcds_refclk_b   <= '0';
-    clk40_ext_tcds2 <= '0';
-    cmd_ext_tcds2   <= TTC_BCMD_NULL;
-    l1a_ext_tcds2   <= '0';
-
-    ipbr(N_SLV_MASTER_TCDS2).ipb_ack   <= '0';
-    ipbr(N_SLV_MASTER_TCDS2).ipb_err   <= ipbw(N_SLV_MASTER_TCDS2).ipb_strobe;
-    ipbr(N_SLV_MASTER_TCDS2).ipb_rdata <= (others => '0');
-
-  end generate;
-
-
-  gen_master_legacy : if ENABLE_LEGACY_TTC generate
-
-    signal err_rst                : std_logic;
-    signal sinerr_ctr, dblerr_ctr : std_logic_vector(15 downto 0);
-    signal stat_legacy            : ipb_reg_v(0 downto 0);
-    signal ctrl_legacy            : ipb_reg_v(0 downto 0);
-    signal stb_legacy             : std_logic_vector(0 downto 0);
-
-  begin
-
-    osc_clock : entity work.emp_oscclk
-      generic map (
-        OSC_FREQ => EXT_CLK_FREQ
-        )
-      port map (
-        clk_p => ttc_clk_p,
-        clk_n => ttc_clk_n,
-        clk40 => clk40_ext_legacy
-        );
-
-    reg : entity work.ipbus_syncreg_v
-      generic map(
-        N_CTRL => 1,
-        N_STAT => 1
-        )
-      port map(
-        clk     => clk_ipb,
-        rst     => rst_ipb,
-        ipb_in  => ipbw(N_SLV_MASTER_LEGACY),
-        ipb_out => ipbr(N_SLV_MASTER_LEGACY),
-        slv_clk => clk40_a,
-        d       => stat_legacy,
-        q       => ctrl_legacy,
-        stb     => stb_legacy
-        );
-
-    interface : entity work.emp_ttc_legacy
-      port map(
-        clk         => clk40_a,
-        rst         => rst40_a,
-        sclk        => clk160s,
-        sclk_locked => lock,
-        ttc_in_p    => ttc_rx_p,
-        ttc_in_n    => ttc_rx_n,
-        l1a         => l1a_ext_legacy,
-        cmd         => cmd_ext_legacy,
-        sinerr_ctr  => sinerr_ctr,
-        dblerr_ctr  => dblerr_ctr,
-        err_rst     => err_rst
-        );
-
-    err_rst        <= ctrl_legacy(0)(0) and stb_legacy(0);
-    stat_legacy(0) <= dblerr_ctr & sinerr_ctr;
-
-
-  else generate
-
-    clk40_ext_legacy <= '0';
-    cmd_ext_legacy   <= TTC_BCMD_NULL;
-    l1a_ext_legacy   <= '0';
-
-    ipbr(N_SLV_MASTER_LEGACY).ipb_ack   <= '0';
-    ipbr(N_SLV_MASTER_LEGACY).ipb_err   <= ipbw(N_SLV_MASTER_LEGACY).ipb_strobe;
-    ipbr(N_SLV_MASTER_LEGACY).ipb_rdata <= (others => '0');
-
-  end generate;
-
-
-  -- FIXME: Select between each of two external sources and internal
-  with ctrl_common(0)(1 downto 0) select cmd_ttc <=
-    cmd_ext_legacy when "01",
-    cmd_ext_tcds2  when "10",
-    TTC_BCMD_NULL  when others;
-
-  with ctrl_common(0)(1 downto 0) select l1a_ttc <=
-    l1a_ext_legacy when "01",
-    l1a_ext_tcds2  when "10",
-    '0'            when others;
-
-  -- L1A generation
-  l1a       <= l1a_ttc or l1a_pend;
-  l1a_issue <= l1a and not l1a_ttc;
-
-  -- TTC command generation
-  req_bx <= to_unsigned(LHC_BUNCH_COUNT, req_bx'length) - to_unsigned(TTC_DEL, req_bx'length) - 1;
-  cmd_bx <= '1' when std_logic_vector(req_bx) = bunch_ctr_i else '0';
-
-  process(cmd_ttc, bc0_fr, cmd_pend, cmd_bx)
-  begin
-    cmd_issue <= '0';
-    if cmd_ttc /= TTC_BCMD_NULL then
-      cmd <= cmd_ttc;
-    elsif bc0_fr = '1' then
-      cmd <= TTC_BCMD_BC0;
-    elsif cmd_pend = '1' then
-      cmd       <= ctrl_common(0)(15 downto 8);
-      cmd_issue <= '1';
-    else
-      cmd <= TTC_BCMD_NULL;
-    end if;
-  end process;
-
-  process(clk40_a)
-  begin
-    if rising_edge(clk40_a) then
-      cmd_pend     <= (cmd_pend or (ctrl_common(0)(5) and stb_common(0))) and not (rst40_a or cmd_issue);
-      l1a_pend     <= l1a_pend and not (rst40_a or l1a_issue);
-      ttc_cmd_dist <= cmd;
-    end if;
-  end process;
-
-  ttc_l1a_dist <= l1a;
-
--- Counters
-
-  ctr_clr <= ctrl_common(0)(4) and stb_common(0);
-
-  ttcctr : entity work.ttc_ctrs
-    port map(
-      clk         => clk40_a,
-      rst         => rst40_a,
-      ttc_cmd     => cmd,
-      l1a         => l1a,
-      clr         => '0',
-      en_int_bc0  => ctrl_common(0)(3),
-      bc0_lock    => bc0_lock,
-      bc0_fr      => bc0_fr,
-      ttc_cmd_out => cmd_del,
-      l1a_out     => l1a_del,
-      bunch_ctr   => bunch_ctr_i,
-      orb_ctr     => orb_ctr_i
-      );
-
-  ttc_cmd   <= cmd_del;
-  ttc_l1a   <= l1a_del;
-  bunch_ctr <= bunch_ctr_i;
-  orb_ctr   <= orb_ctr_i;
-  oc_flag   <= '1' when orb_ctr_i(13 downto 0) = (13 downto 0 => '0') and bc0_lock = '1' else '0';
-  ec_flag   <= '1' when evt_ctr(16 downto 0) = (16 downto 0   => '0')                    else '0';
-
--- Status reg
-
-  stat_common(0)(7 downto 2)   <= (l1a_pend or cmd_pend) & psok & dist_lock & bc0_lock & "00";
-  stat_common(0)(19 downto 8)  <= bunch_ctr_i;
-  stat_common(0)(31 downto 20) <= std_logic_vector(to_unsigned(LHC_BUNCH_COUNT, 12));
-  stat_common(1)               <= evt_ctr;
-  stat_common(2)               <= orb_ctr_i;
-
--- clk40 frequency monitoring   
-
-  div : entity work.freq_ctr_div
-    generic map(
-      N_CLK => 2
-      )
-    port map(
-      clk(0)    => clk40_a,
-      clk(1)    => tcds_refclk_b,
-      clkdiv(0) => clk40_div,
-      clkdiv(1) => tcds_refclk_div
-      );
-
--- Clock frequency monitor
-
-  ctr : entity work.ipbus_freq_ctr
-    generic map(
-      N_CLK => 6
-      )
-    port map(
-      clk                => clk_ipb,
-      rst                => rst_ipb,
-      ipb_in             => ipbw(N_SLV_FREQ),
-      ipb_out            => ipbr(N_SLV_FREQ),
-      clkdiv(0)          => clk40_div,
-      clkdiv(1)          => tcds_refclk_div,
-      clkdiv(5 downto 2) => monclk
-      );
-
--- TTC history buffer
-
-  hist : entity work.ttc_history_new
-    port map(
-      clk     => clk_ipb,
-      rst     => rst_ipb,
-      ipb_in  => ipbw(N_SLV_HIST),
-      ipb_out => ipbr(N_SLV_HIST),
-      ttc_clk => clk40_a,
-      ttc_rst => rst40_a,
-      ttc_l1a => l1a_del,
-      ttc_cmd => cmd_del,
-      ttc_bx  => bunch_ctr_i,
-      ttc_orb => orb_ctr_i,
-      ttc_evt => evt_ctr
-      );
-
--- Command counters
-
-  cmdctrs : entity work.ttc_cmd_ctrs
-    port map(
-      clk     => clk_ipb,
-      rst     => rst_ipb,
-      ipb_in  => ipbw(N_SLV_CMD_CTRS),
-      ipb_out => ipbr(N_SLV_CMD_CTRS),
-      ttc_clk => clk40_a,
-      clr     => ctr_clr,
-      ttc_cmd => cmd_del
-      );
-
-end rtl;
--------------------------------------------------------------------------------
diff --git a/top/common/designs/vu13p_s1/firmware/cfg/vu13p_s1.dep b/top/common/designs/vu13p_s1/firmware/cfg/vu13p_s1.dep
index 77eca81585b7a7defdbadce31240f1ed5c42c4a9..09076aa70cc8654047ce3aecb815af478e5bcc36 100644
--- a/top/common/designs/vu13p_s1/firmware/cfg/vu13p_s1.dep
+++ b/top/common/designs/vu13p_s1/firmware/cfg/vu13p_s1.dep
@@ -3,7 +3,8 @@ include device.dep
 @boardname = "serenity-s1-vu13p"
 @tcds2_link_type = "gty10g"
 
-src --cd ../ucf area_constraints.tcl
+# src --cd ../ucf custom_pblock.tcl
+src --cd ../ucf --usefor implementation area_constraints.tcl
 
 # Top level
 include -c emp-fwk:components/top top_pcie_both_ttc.dep
@@ -15,11 +16,11 @@ include -c emp-fwk:boards/serenity/common
 # (Note: Must set loc before changing to CPLL - otherwise core will revert back to QPLL)
 setup -f -c emp-fwk:boards/serenity/common xdma_downgrade_pcie2_and_cpll.tcl
 setup -f xdma_loc.tcl
-src --cd ../ucf xdma_constraints.tcl
+src --cd ../ucf --usefor implementation xdma_constraints.tcl
 
 # Pin constraints
-src --cd ../ucf pins_general.tcl
-src --cd ../ucf pins_refclks.tcl
+src --cd ../ucf --usefor implementation pins_general.tcl
+src --cd ../ucf --usefor implementation pins_refclks.tcl
 
 # Include links
 include -c emp-fwk:components/links/be_mgt/interface interface_gty.dep
diff --git a/top/common/designs/vu13p_s1/firmware/ucf/custom_pblock.tcl b/top/common/designs/vu13p_s1/firmware/ucf/custom_pblock.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3fec7aaac573b2c166db5c8d574e96e9d16e4686
--- /dev/null
+++ b/top/common/designs/vu13p_s1/firmware/ucf/custom_pblock.tcl
@@ -0,0 +1,81 @@
+create_pblock pblock_1
+resize_pblock pblock_1 -add {SLICE_X26Y600:SLICE_X206Y959 DSP48E2_X2Y240:DSP48E2_X29Y383 RAMB18_X2Y240:RAMB18_X11Y383 RAMB36_X2Y120:RAMB36_X11Y191 URAM288_X0Y160:URAM288_X4Y255}
+add_cells_to_pblock pblock_1 [get_cells [list payload/StubProcessor/MuxInstance payload/StubProcessor/RouteInstance]] -clear_locs
+
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[0].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[1].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[2].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[3].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[4].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[5].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[6].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[7].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[8].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[9].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[10].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[11].LinkInterface]
+
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[12].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[13].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[14].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[15].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[16].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[17].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[18].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[19].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[20].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[21].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[22].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[23].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[24].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[25].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[26].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[27].LinkInterface]
+
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[28].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[29].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[30].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[31].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[32].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[33].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[34].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[35].LinkInterface]
+
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[36].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[37].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[38].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[39].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[40].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[41].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[42].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR2 [get_cells payload/module[43].LinkInterface]
+
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[44].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[45].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[46].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[47].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[48].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[49].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[50].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[51].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[52].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[53].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[54].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[55].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[56].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[57].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[58].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR1 [get_cells payload/module[59].LinkInterface]
+
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[60].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[61].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[62].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[63].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[64].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[65].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[66].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[67].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[68].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[69].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[70].LinkInterface]
+set_property USER_SLR_ASSIGNMENT SLR0 [get_cells payload/module[71].LinkInterface]
diff --git a/top/common/firmware/cfg/payload.dep b/top/common/firmware/cfg/payload.dep
index d7b881779d9003476d7fcca81e8a46b62abf350f..70467c462b560915f7342b7f294319bec4f39d04 100644
--- a/top/common/firmware/cfg/payload.dep
+++ b/top/common/firmware/cfg/payload.dep
@@ -4,7 +4,7 @@ include -c emp-fwk:components/links/slink generator.dep
 src -c emp-fwk:components/datapath emp_data_types.vhd
 src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
 src -c emp-fwk:components/ttc emp_ttc_decl.vhd
-src -c emp-fwk:components/payload ../ucf/emp_simple_payload.tcl
+src -c emp-fwk:components/payload --usefor implementation ../ucf/emp_simple_payload.tcl
 
 ? toolset.lower() == "vivado" ? setup -c emp-fwk:components/payload emp_simple_payload_msg_suppressions.tcl
 
diff --git a/top/dtc-full/2S-5G/firmware/cfg/vu13p_s1/top.dep b/top/dtc-full/2S-5G/firmware/cfg/vu13p_s1/top.dep
index 17bfd35f53a55222ab62c20907117cfc75e65857..22c4b6d6795af5ca41a74d852c203eb666e6af49 100644
--- a/top/dtc-full/2S-5G/firmware/cfg/vu13p_s1/top.dep
+++ b/top/dtc-full/2S-5G/firmware/cfg/vu13p_s1/top.dep
@@ -1,5 +1,10 @@
 src emp_payload.vhd
 src ipbus_decode_emp_payload.vhd
+
+src -c top/common/designs/vu13p_s1 --cd ../ucf --usefor implementation custom_pblock.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_left.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_right.tcl
+
 include -c top/common payload.dep
 
 addrtab -t emp_payload.xml
diff --git a/top/dtc-full/2S-5G/firmware/hdl/emp_payload.vhd b/top/dtc-full/2S-5G/firmware/hdl/emp_payload.vhd
index ecc10d119cb5190a899d696fdfb00a555c6ad4db..18484b4afef592711bcadc53ca16caf4f07efee6 100644
--- a/top/dtc-full/2S-5G/firmware/hdl/emp_payload.vhd
+++ b/top/dtc-full/2S-5G/firmware/hdl/emp_payload.vhd
@@ -77,6 +77,9 @@ architecture rtl of emp_payload is
 
   signal router_output              : ldata(cNumberOfOutputLinks - 1 downto 0) := (others => LWORD_NULL);
   signal stub_processor_input       : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache2: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache3: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
 
 
   -- TCDS & Fast commands
@@ -162,7 +165,7 @@ begin
     generic map (
       I_SLV     => i,
       SEL_WIDTH => 7,
-      PIPELINE  => false
+      PIPELINE  => true
     )
     port map (
       clk       => clk,
@@ -179,7 +182,8 @@ begin
     generic map (
       module_type => cDTCInputLinkMap(i).module_type,
       bandwidth   => cDTCInputLinkMap(i).bandwidth,
-      cic_type    => cDTCInputLinkMap(i).cic_type
+      cic_type    => cDTCInputLinkMap(i).cic_type,
+      enable_monitoring => true
     )
     port map (
       --- Input Ports ---
@@ -424,7 +428,10 @@ begin
       data_in <= d;
       q <= data_out;
 
-      stub_processor_input <= stubs;
+      stub_processor_input_cache <= stubs;
+      stub_processor_input_cache3 <= stub_processor_input_cache2;
+      stub_processor_input_cache2 <= stub_processor_input_cache;
+      stub_processor_input <= stub_processor_input_cache3;
     end if;
   end process;
 
diff --git a/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_left.tcl b/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_left.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2e805be41fb83976e4a14535376a3dee79ca5093
--- /dev/null
+++ b/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_left.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_22
+resize_pblock pblock_p_quad_22 -add CLOCKREGION_X1Y9:CLOCKREGION_X2Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[36].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[37].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[38].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[39].LinkInterface}]]
+
+create_pblock pblock_p_quad_23
+resize_pblock pblock_p_quad_23 -add CLOCKREGION_X1Y8:CLOCKREGION_X2Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[40].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[41].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[42].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[43].LinkInterface}]]
+
+create_pblock pblock_p_quad_24
+resize_pblock pblock_p_quad_24 -add CLOCKREGION_X1Y7:CLOCKREGION_X2Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[44].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[45].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[46].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[47].LinkInterface}]]
+
+create_pblock pblock_p_quad_25
+resize_pblock pblock_p_quad_25 -add CLOCKREGION_X1Y6:CLOCKREGION_X2Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[48].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[49].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[50].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[51].LinkInterface}]]
+
+create_pblock pblock_p_quad_26
+resize_pblock pblock_p_quad_26 -add CLOCKREGION_X1Y5:CLOCKREGION_X2Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[52].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[53].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[54].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[55].LinkInterface}]]
+
+create_pblock pblock_p_quad_27
+resize_pblock pblock_p_quad_27 -add CLOCKREGION_X1Y4:CLOCKREGION_X2Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[56].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[57].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[58].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[59].LinkInterface}]]
+
+create_pblock pblock_p_quad_28
+resize_pblock pblock_p_quad_28 -add CLOCKREGION_X1Y3:CLOCKREGION_X2Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[60].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[61].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[62].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[63].LinkInterface}]]
+
+create_pblock pblock_p_quad_29
+resize_pblock pblock_p_quad_29 -add CLOCKREGION_X1Y2:CLOCKREGION_X2Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[64].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[65].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[66].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[67].LinkInterface}]]
+
+create_pblock pblock_p_quad_30
+resize_pblock pblock_p_quad_30 -add CLOCKREGION_X1Y1:CLOCKREGION_X2Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[68].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[69].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[70].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[71].LinkInterface}]]
diff --git a/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_right.tcl b/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_right.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3ce96c39bc6aa56468dfd0825b5577feceac6111
--- /dev/null
+++ b/top/dtc-full/2S-5G/firmware/ucf/linkinterface_pblocks_right.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_1
+resize_pblock pblock_p_quad_1 -add CLOCKREGION_X5Y1:CLOCKREGION_X6Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
+
+create_pblock pblock_p_quad_2
+resize_pblock pblock_p_quad_2 -add CLOCKREGION_X5Y2:CLOCKREGION_X6Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[4].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[5].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[6].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[7].LinkInterface}]]
+
+create_pblock pblock_p_quad_3
+resize_pblock pblock_p_quad_3 -add CLOCKREGION_X5Y3:CLOCKREGION_X6Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[8].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[9].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[10].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[11].LinkInterface}]]
+
+create_pblock pblock_p_quad_4
+resize_pblock pblock_p_quad_4 -add CLOCKREGION_X5Y4:CLOCKREGION_X6Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[12].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[13].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[14].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[15].LinkInterface}]]
+
+create_pblock pblock_p_quad_5
+resize_pblock pblock_p_quad_5 -add CLOCKREGION_X5Y5:CLOCKREGION_X6Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[16].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[17].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[18].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[19].LinkInterface}]]
+
+create_pblock pblock_p_quad_6
+resize_pblock pblock_p_quad_6 -add CLOCKREGION_X5Y6:CLOCKREGION_X6Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[20].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[21].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[22].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[23].LinkInterface}]]
+
+create_pblock pblock_p_quad_7
+resize_pblock pblock_p_quad_7 -add CLOCKREGION_X5Y7:CLOCKREGION_X6Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[24].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[25].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[26].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[27].LinkInterface}]]
+
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[28].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[29].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[30].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[31].LinkInterface}]]
+
+create_pblock pblock_p_quad_9
+resize_pblock pblock_p_quad_9 -add CLOCKREGION_X5Y9:CLOCKREGION_X6Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[32].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[33].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[34].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[35].LinkInterface}]]
diff --git a/top/dtc-full/PS-10G/firmware/cfg/vu13p_s1/top.dep b/top/dtc-full/PS-10G/firmware/cfg/vu13p_s1/top.dep
index 17bfd35f53a55222ab62c20907117cfc75e65857..22c4b6d6795af5ca41a74d852c203eb666e6af49 100644
--- a/top/dtc-full/PS-10G/firmware/cfg/vu13p_s1/top.dep
+++ b/top/dtc-full/PS-10G/firmware/cfg/vu13p_s1/top.dep
@@ -1,5 +1,10 @@
 src emp_payload.vhd
 src ipbus_decode_emp_payload.vhd
+
+src -c top/common/designs/vu13p_s1 --cd ../ucf --usefor implementation custom_pblock.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_left.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_right.tcl
+
 include -c top/common payload.dep
 
 addrtab -t emp_payload.xml
diff --git a/top/dtc-full/PS-10G/firmware/hdl/emp_payload.vhd b/top/dtc-full/PS-10G/firmware/hdl/emp_payload.vhd
index ecc10d119cb5190a899d696fdfb00a555c6ad4db..f0fa59b96f7f6301c2e52a72bdb205ba4b063bdb 100644
--- a/top/dtc-full/PS-10G/firmware/hdl/emp_payload.vhd
+++ b/top/dtc-full/PS-10G/firmware/hdl/emp_payload.vhd
@@ -77,6 +77,9 @@ architecture rtl of emp_payload is
 
   signal router_output              : ldata(cNumberOfOutputLinks - 1 downto 0) := (others => LWORD_NULL);
   signal stub_processor_input       : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache2: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache3: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
 
 
   -- TCDS & Fast commands
@@ -162,7 +165,7 @@ begin
     generic map (
       I_SLV     => i,
       SEL_WIDTH => 7,
-      PIPELINE  => false
+      PIPELINE  => true
     )
     port map (
       clk       => clk,
@@ -179,7 +182,8 @@ begin
     generic map (
       module_type => cDTCInputLinkMap(i).module_type,
       bandwidth   => cDTCInputLinkMap(i).bandwidth,
-      cic_type    => cDTCInputLinkMap(i).cic_type
+      cic_type    => cDTCInputLinkMap(i).cic_type,
+      enable_monitoring => false
     )
     port map (
       --- Input Ports ---
@@ -424,7 +428,10 @@ begin
       data_in <= d;
       q <= data_out;
 
-      stub_processor_input <= stubs;
+      stub_processor_input_cache <= stubs;
+      stub_processor_input_cache3 <= stub_processor_input_cache2;
+      stub_processor_input_cache2 <= stub_processor_input_cache;
+      stub_processor_input <= stub_processor_input_cache3;
     end if;
   end process;
 
diff --git a/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_left.tcl b/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_left.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2e805be41fb83976e4a14535376a3dee79ca5093
--- /dev/null
+++ b/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_left.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_22
+resize_pblock pblock_p_quad_22 -add CLOCKREGION_X1Y9:CLOCKREGION_X2Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[36].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[37].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[38].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[39].LinkInterface}]]
+
+create_pblock pblock_p_quad_23
+resize_pblock pblock_p_quad_23 -add CLOCKREGION_X1Y8:CLOCKREGION_X2Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[40].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[41].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[42].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[43].LinkInterface}]]
+
+create_pblock pblock_p_quad_24
+resize_pblock pblock_p_quad_24 -add CLOCKREGION_X1Y7:CLOCKREGION_X2Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[44].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[45].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[46].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[47].LinkInterface}]]
+
+create_pblock pblock_p_quad_25
+resize_pblock pblock_p_quad_25 -add CLOCKREGION_X1Y6:CLOCKREGION_X2Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[48].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[49].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[50].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[51].LinkInterface}]]
+
+create_pblock pblock_p_quad_26
+resize_pblock pblock_p_quad_26 -add CLOCKREGION_X1Y5:CLOCKREGION_X2Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[52].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[53].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[54].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[55].LinkInterface}]]
+
+create_pblock pblock_p_quad_27
+resize_pblock pblock_p_quad_27 -add CLOCKREGION_X1Y4:CLOCKREGION_X2Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[56].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[57].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[58].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[59].LinkInterface}]]
+
+create_pblock pblock_p_quad_28
+resize_pblock pblock_p_quad_28 -add CLOCKREGION_X1Y3:CLOCKREGION_X2Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[60].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[61].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[62].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[63].LinkInterface}]]
+
+create_pblock pblock_p_quad_29
+resize_pblock pblock_p_quad_29 -add CLOCKREGION_X1Y2:CLOCKREGION_X2Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[64].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[65].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[66].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[67].LinkInterface}]]
+
+create_pblock pblock_p_quad_30
+resize_pblock pblock_p_quad_30 -add CLOCKREGION_X1Y1:CLOCKREGION_X2Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[68].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[69].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[70].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[71].LinkInterface}]]
diff --git a/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_right.tcl b/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_right.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3ce96c39bc6aa56468dfd0825b5577feceac6111
--- /dev/null
+++ b/top/dtc-full/PS-10G/firmware/ucf/linkinterface_pblocks_right.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_1
+resize_pblock pblock_p_quad_1 -add CLOCKREGION_X5Y1:CLOCKREGION_X6Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
+
+create_pblock pblock_p_quad_2
+resize_pblock pblock_p_quad_2 -add CLOCKREGION_X5Y2:CLOCKREGION_X6Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[4].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[5].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[6].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[7].LinkInterface}]]
+
+create_pblock pblock_p_quad_3
+resize_pblock pblock_p_quad_3 -add CLOCKREGION_X5Y3:CLOCKREGION_X6Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[8].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[9].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[10].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[11].LinkInterface}]]
+
+create_pblock pblock_p_quad_4
+resize_pblock pblock_p_quad_4 -add CLOCKREGION_X5Y4:CLOCKREGION_X6Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[12].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[13].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[14].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[15].LinkInterface}]]
+
+create_pblock pblock_p_quad_5
+resize_pblock pblock_p_quad_5 -add CLOCKREGION_X5Y5:CLOCKREGION_X6Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[16].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[17].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[18].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[19].LinkInterface}]]
+
+create_pblock pblock_p_quad_6
+resize_pblock pblock_p_quad_6 -add CLOCKREGION_X5Y6:CLOCKREGION_X6Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[20].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[21].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[22].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[23].LinkInterface}]]
+
+create_pblock pblock_p_quad_7
+resize_pblock pblock_p_quad_7 -add CLOCKREGION_X5Y7:CLOCKREGION_X6Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[24].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[25].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[26].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[27].LinkInterface}]]
+
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[28].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[29].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[30].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[31].LinkInterface}]]
+
+create_pblock pblock_p_quad_9
+resize_pblock pblock_p_quad_9 -add CLOCKREGION_X5Y9:CLOCKREGION_X6Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[32].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[33].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[34].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[35].LinkInterface}]]
diff --git a/top/dtc-full/PS-5G/firmware/cfg/vu13p_s1/top.dep b/top/dtc-full/PS-5G/firmware/cfg/vu13p_s1/top.dep
index 17bfd35f53a55222ab62c20907117cfc75e65857..22c4b6d6795af5ca41a74d852c203eb666e6af49 100644
--- a/top/dtc-full/PS-5G/firmware/cfg/vu13p_s1/top.dep
+++ b/top/dtc-full/PS-5G/firmware/cfg/vu13p_s1/top.dep
@@ -1,5 +1,10 @@
 src emp_payload.vhd
 src ipbus_decode_emp_payload.vhd
+
+src -c top/common/designs/vu13p_s1 --cd ../ucf --usefor implementation custom_pblock.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_left.tcl
+src --cd ../ucf --usefor implementation linkinterface_pblocks_right.tcl
+
 include -c top/common payload.dep
 
 addrtab -t emp_payload.xml
diff --git a/top/dtc-full/PS-5G/firmware/hdl/emp_payload.vhd b/top/dtc-full/PS-5G/firmware/hdl/emp_payload.vhd
index ecc10d119cb5190a899d696fdfb00a555c6ad4db..f0fa59b96f7f6301c2e52a72bdb205ba4b063bdb 100644
--- a/top/dtc-full/PS-5G/firmware/hdl/emp_payload.vhd
+++ b/top/dtc-full/PS-5G/firmware/hdl/emp_payload.vhd
@@ -77,6 +77,9 @@ architecture rtl of emp_payload is
 
   signal router_output              : ldata(cNumberOfOutputLinks - 1 downto 0) := (others => LWORD_NULL);
   signal stub_processor_input       : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache2: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
+  signal stub_processor_input_cache3: ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
 
 
   -- TCDS & Fast commands
@@ -162,7 +165,7 @@ begin
     generic map (
       I_SLV     => i,
       SEL_WIDTH => 7,
-      PIPELINE  => false
+      PIPELINE  => true
     )
     port map (
       clk       => clk,
@@ -179,7 +182,8 @@ begin
     generic map (
       module_type => cDTCInputLinkMap(i).module_type,
       bandwidth   => cDTCInputLinkMap(i).bandwidth,
-      cic_type    => cDTCInputLinkMap(i).cic_type
+      cic_type    => cDTCInputLinkMap(i).cic_type,
+      enable_monitoring => false
     )
     port map (
       --- Input Ports ---
@@ -424,7 +428,10 @@ begin
       data_in <= d;
       q <= data_out;
 
-      stub_processor_input <= stubs;
+      stub_processor_input_cache <= stubs;
+      stub_processor_input_cache3 <= stub_processor_input_cache2;
+      stub_processor_input_cache2 <= stub_processor_input_cache;
+      stub_processor_input <= stub_processor_input_cache3;
     end if;
   end process;
 
diff --git a/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_left.tcl b/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_left.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2e805be41fb83976e4a14535376a3dee79ca5093
--- /dev/null
+++ b/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_left.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_22
+resize_pblock pblock_p_quad_22 -add CLOCKREGION_X1Y9:CLOCKREGION_X2Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[36].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[37].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[38].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_22] [get_cells -quiet [list {payload/module[39].LinkInterface}]]
+
+create_pblock pblock_p_quad_23
+resize_pblock pblock_p_quad_23 -add CLOCKREGION_X1Y8:CLOCKREGION_X2Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[40].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[41].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[42].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_23] [get_cells -quiet [list {payload/module[43].LinkInterface}]]
+
+create_pblock pblock_p_quad_24
+resize_pblock pblock_p_quad_24 -add CLOCKREGION_X1Y7:CLOCKREGION_X2Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[44].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[45].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[46].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_24] [get_cells -quiet [list {payload/module[47].LinkInterface}]]
+
+create_pblock pblock_p_quad_25
+resize_pblock pblock_p_quad_25 -add CLOCKREGION_X1Y6:CLOCKREGION_X2Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[48].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[49].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[50].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_25] [get_cells -quiet [list {payload/module[51].LinkInterface}]]
+
+create_pblock pblock_p_quad_26
+resize_pblock pblock_p_quad_26 -add CLOCKREGION_X1Y5:CLOCKREGION_X2Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[52].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[53].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[54].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_26] [get_cells -quiet [list {payload/module[55].LinkInterface}]]
+
+create_pblock pblock_p_quad_27
+resize_pblock pblock_p_quad_27 -add CLOCKREGION_X1Y4:CLOCKREGION_X2Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[56].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[57].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[58].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_27] [get_cells -quiet [list {payload/module[59].LinkInterface}]]
+
+create_pblock pblock_p_quad_28
+resize_pblock pblock_p_quad_28 -add CLOCKREGION_X1Y3:CLOCKREGION_X2Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[60].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[61].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[62].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_28] [get_cells -quiet [list {payload/module[63].LinkInterface}]]
+
+create_pblock pblock_p_quad_29
+resize_pblock pblock_p_quad_29 -add CLOCKREGION_X1Y2:CLOCKREGION_X2Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[64].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[65].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[66].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_29] [get_cells -quiet [list {payload/module[67].LinkInterface}]]
+
+create_pblock pblock_p_quad_30
+resize_pblock pblock_p_quad_30 -add CLOCKREGION_X1Y1:CLOCKREGION_X2Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[68].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[69].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[70].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_30] [get_cells -quiet [list {payload/module[71].LinkInterface}]]
diff --git a/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_right.tcl b/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_right.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3ce96c39bc6aa56468dfd0825b5577feceac6111
--- /dev/null
+++ b/top/dtc-full/PS-5G/firmware/ucf/linkinterface_pblocks_right.tcl
@@ -0,0 +1,62 @@
+create_pblock pblock_p_quad_1
+resize_pblock pblock_p_quad_1 -add CLOCKREGION_X5Y1:CLOCKREGION_X6Y1
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_1] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
+
+create_pblock pblock_p_quad_2
+resize_pblock pblock_p_quad_2 -add CLOCKREGION_X5Y2:CLOCKREGION_X6Y2
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[4].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[5].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[6].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_2] [get_cells -quiet [list {payload/module[7].LinkInterface}]]
+
+create_pblock pblock_p_quad_3
+resize_pblock pblock_p_quad_3 -add CLOCKREGION_X5Y3:CLOCKREGION_X6Y3
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[8].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[9].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[10].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_3] [get_cells -quiet [list {payload/module[11].LinkInterface}]]
+
+create_pblock pblock_p_quad_4
+resize_pblock pblock_p_quad_4 -add CLOCKREGION_X5Y4:CLOCKREGION_X6Y4
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[12].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[13].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[14].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_4] [get_cells -quiet [list {payload/module[15].LinkInterface}]]
+
+create_pblock pblock_p_quad_5
+resize_pblock pblock_p_quad_5 -add CLOCKREGION_X5Y5:CLOCKREGION_X6Y5
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[16].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[17].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[18].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_5] [get_cells -quiet [list {payload/module[19].LinkInterface}]]
+
+create_pblock pblock_p_quad_6
+resize_pblock pblock_p_quad_6 -add CLOCKREGION_X5Y6:CLOCKREGION_X6Y6
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[20].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[21].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[22].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_6] [get_cells -quiet [list {payload/module[23].LinkInterface}]]
+
+create_pblock pblock_p_quad_7
+resize_pblock pblock_p_quad_7 -add CLOCKREGION_X5Y7:CLOCKREGION_X6Y7
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[24].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[25].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[26].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_7] [get_cells -quiet [list {payload/module[27].LinkInterface}]]
+
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[28].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[29].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[30].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[31].LinkInterface}]]
+
+create_pblock pblock_p_quad_9
+resize_pblock pblock_p_quad_9 -add CLOCKREGION_X5Y9:CLOCKREGION_X6Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[32].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[33].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[34].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[35].LinkInterface}]]
diff --git a/top/dtc-mini/2S-5G/firmware/cfg/vu13p_so2_v1/top.dep b/top/dtc-mini/2S-5G/firmware/cfg/vu13p_so2_v1/top.dep
index fd02a64bdc2addbe9ec4396e5be13713618f1598..90e5d7dba06bc6355974119807bb40e2c40b6a0c 100644
--- a/top/dtc-mini/2S-5G/firmware/cfg/vu13p_so2_v1/top.dep
+++ b/top/dtc-mini/2S-5G/firmware/cfg/vu13p_so2_v1/top.dep
@@ -1,5 +1,9 @@
+src --cd ../ucf --usefor implementation linkinterface_pblocks.tcl
+
 include -c top/dtc-mini/common payload.dep
 
+
+
 include -c emp-fwk:boards/serenity/dc_vu13p dc_vu13p_so2.dep
 include -c top/common fe_mgt.dep
 
diff --git a/top/dtc-mini/2S-5G/firmware/ucf/linkinterface_pblocks.tcl b/top/dtc-mini/2S-5G/firmware/ucf/linkinterface_pblocks.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6d57ed05df1d8e5c8d9699e2be4b544de6cc72cd
--- /dev/null
+++ b/top/dtc-mini/2S-5G/firmware/ucf/linkinterface_pblocks.tcl
@@ -0,0 +1,20 @@
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
+
+create_pblock pblock_p_quad_9
+resize_pblock pblock_p_quad_9 -add CLOCKREGION_X5Y9:CLOCKREGION_X6Y9
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[4].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[5].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[6].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_9] [get_cells -quiet [list {payload/module[7].LinkInterface}]]
+
+create_pblock pblock_p_quad_10
+resize_pblock pblock_p_quad_10 -add CLOCKREGION_X5Y10:CLOCKREGION_X6Y10
+add_cells_to_pblock [get_pblocks pblock_p_quad_10] [get_cells -quiet [list {payload/module[8].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_10] [get_cells -quiet [list {payload/module[9].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_10] [get_cells -quiet [list {payload/module[10].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_10] [get_cells -quiet [list {payload/module[11].LinkInterface}]]
\ No newline at end of file
diff --git a/top/dtc-mini/PS-10G/firmware/cfg/vu13p_so2_v1/top.dep b/top/dtc-mini/PS-10G/firmware/cfg/vu13p_so2_v1/top.dep
index fd02a64bdc2addbe9ec4396e5be13713618f1598..5f8dc890a33d353daaa2119ecbe363e948124e0f 100644
--- a/top/dtc-mini/PS-10G/firmware/cfg/vu13p_so2_v1/top.dep
+++ b/top/dtc-mini/PS-10G/firmware/cfg/vu13p_so2_v1/top.dep
@@ -1,3 +1,5 @@
+src --cd ../ucf --usefor implementation linkinterface_pblocks.tcl
+
 include -c top/dtc-mini/common payload.dep
 
 include -c emp-fwk:boards/serenity/dc_vu13p dc_vu13p_so2.dep
diff --git a/top/dtc-mini/PS-10G/firmware/ucf/linkinterface_pblocks.tcl b/top/dtc-mini/PS-10G/firmware/ucf/linkinterface_pblocks.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..777a9145c3206850668ff9cf983daa0829a6b709
--- /dev/null
+++ b/top/dtc-mini/PS-10G/firmware/ucf/linkinterface_pblocks.tcl
@@ -0,0 +1,6 @@
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
diff --git a/top/dtc-mini/PS-5G/firmware/cfg/vu13p_so2_v1/top.dep b/top/dtc-mini/PS-5G/firmware/cfg/vu13p_so2_v1/top.dep
index fd02a64bdc2addbe9ec4396e5be13713618f1598..5f8dc890a33d353daaa2119ecbe363e948124e0f 100644
--- a/top/dtc-mini/PS-5G/firmware/cfg/vu13p_so2_v1/top.dep
+++ b/top/dtc-mini/PS-5G/firmware/cfg/vu13p_so2_v1/top.dep
@@ -1,3 +1,5 @@
+src --cd ../ucf --usefor implementation linkinterface_pblocks.tcl
+
 include -c top/dtc-mini/common payload.dep
 
 include -c emp-fwk:boards/serenity/dc_vu13p dc_vu13p_so2.dep
diff --git a/top/dtc-mini/PS-5G/firmware/ucf/linkinterface_pblocks.tcl b/top/dtc-mini/PS-5G/firmware/ucf/linkinterface_pblocks.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..777a9145c3206850668ff9cf983daa0829a6b709
--- /dev/null
+++ b/top/dtc-mini/PS-5G/firmware/ucf/linkinterface_pblocks.tcl
@@ -0,0 +1,6 @@
+create_pblock pblock_p_quad_8
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X5Y8:CLOCKREGION_X6Y8
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[2].LinkInterface}]]
+add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[3].LinkInterface}]]
diff --git a/top/dtc-mini/b186-vu13p/firmware/cfg/top.dep b/top/dtc-mini/b186-vu13p/firmware/cfg/top.dep
index c791c625f980430a6422d9ac0dabdce5519168d8..8c18ab856052fdfa7f11a0bd5532c90524e79cba 100644
--- a/top/dtc-mini/b186-vu13p/firmware/cfg/top.dep
+++ b/top/dtc-mini/b186-vu13p/firmware/cfg/top.dep
@@ -1,3 +1,5 @@
+src --cd ../ucf --usefor implementation SLRs.tcl
+
 include -c top/dtc-mini/common payload.dep
 
 include -c emp-fwk:boards/serenity/dc_vu13p dc_vu13p_so2.dep
@@ -6,5 +8,4 @@ include -c top/common fe_mgt.dep
 src emp_project_decl.vhd
 src link_maps.vhd
 
-src --cd ../ucf SLRs.tcl
 setup --cd ../ucf strategy.tcl
diff --git a/top/dtc-mini/b186-vu13p/firmware/ucf/SLRs.tcl b/top/dtc-mini/b186-vu13p/firmware/ucf/SLRs.tcl
index c8f770597fd5a046eb93f023ac541921d2a7c854..e183cbe0adc9820017407d2a5db35a36d564c4e0 100644
--- a/top/dtc-mini/b186-vu13p/firmware/ucf/SLRs.tcl
+++ b/top/dtc-mini/b186-vu13p/firmware/ucf/SLRs.tcl
@@ -18,7 +18,7 @@ set_property USER_SLR_ASSIGNMENT quad_10 [get_cells {datapath/rgen[10].region}]
 
 
 create_pblock pblock_p_quad_8
-resize_pblock pblock_p_quad_8 -add CLOCKREGION_X4Y9:CLOCKREGION_X6Y9
+resize_pblock pblock_p_quad_8 -add CLOCKREGION_X4Y9:CLOCKREGION_X6Y8
 add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[0].LinkInterface}]]
 add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[1].LinkInterface}]]
 add_cells_to_pblock [get_pblocks pblock_p_quad_8] [get_cells -quiet [list {payload/module[2].LinkInterface}]]