diff --git a/CODE_STYLE.md b/CODE_STYLE.md
index 350f2a09835634b30f4850b5245f7e9b5f714f52..de4df681d16e0ee012124b0de700b2da9c7f2cbd 100644
--- a/CODE_STYLE.md
+++ b/CODE_STYLE.md
@@ -3,7 +3,11 @@
#### Name conventions:
- Constants should have a `c` prefix and be in camel case
- Types should have a `t` prefix and be in came case
+- Entity names should be in camel case, beginning with a capital letter. They should also end with `Instance` and be descriptive
+- Processes should be named, beginning with a lowercase `p` and be descriptive
+- Generate statements should be named, beginning with `gen` and be descriptive
#### File structure
- Use entities in place of components
- Inputs and outputs of an entity should be grouped under a specific header. IPbus ports should be placed under their own header
+- Any new block should be indented relative to its parent (including architectures, generate statements, processes and if statements).
diff --git a/dtc-be/firmware/hdl/FormatOutput.vhd b/dtc-be/firmware/hdl/FormatOutput.vhd
index abaaf99a30b92bd6ea960b9c256fc35549de320d..4d98e091169729a83cb7471b0b40308196e4bc02 100644
--- a/dtc-be/firmware/hdl/FormatOutput.vhd
+++ b/dtc-be/firmware/hdl/FormatOutput.vhd
@@ -5,42 +5,34 @@ use work.config.all;
use work.dtc_stubs.all;
entity dtc_formatOutput is
-port (
- clk: in std_logic;
- formatOutput_din: in t_stubsDTC( numLinksDTC - 1 downto 0 );
- formatOutput_dout: out ldata( numLinksDTC - 1 downto 0 )
-);
+ port (
+ --- Input Ports ---
+ clk : in std_logic;
+ formatOutput_din : in t_stubsDTC( numLinksDTC - 1 downto 0 );
+ --- Output Ports ---
+ formatOutput_dout : out ldata( numLinksDTC - 1 downto 0 )
+ );
end;
architecture rtl of dtc_formatOutput is
-
-component dtc_formatOutput_node
-port (
- clk: in std_logic;
- node_din: in t_stubDTC;
- node_dout: out lword
-);
-end component;
-
begin
-
-g: for k in numLinksDTC - 1 downto 0 generate
-
-signal node_din: t_stubDTC := nullStub;
-signal node_dout: lword := ( ( others => '0' ), '0', '0', '1' );
-
-begin
-
-node_din <= formatOutput_din( k );
-formatOutput_dout( k ) <= node_dout;
-
-c: dtc_formatOutput_node port map ( clk, node_din, node_dout );
-
-end generate;
-
+ genFormatOutputNodes : for k in numLinksDTC - 1 downto 0 generate
+ begin
+ --==============================--
+ FormatOutputNodeInstance : entity work.dtc_formatOutput_node
+ --==============================--
+ port map (
+ --- Input Ports ---
+ clk => clk,
+ node_din => formatOutput_din(k),
+ --- Output Ports ---
+ node_dout => formatOutput_dout(k)
+ );
+ end generate;
end;
+
library ieee;
use ieee.std_logic_1164.all;
use work.emp_data_types.all;
@@ -51,53 +43,53 @@ use work.dtc_config.all;
entity dtc_formatOutput_node is
port (
- clk: in std_logic;
- node_din: in t_stubDTC;
- node_dout: out lword
+ --- Input Ports ---
+ clk : in std_logic;
+ node_din : in t_stubDTC;
+ --- Input Ports ---
+ node_dout : out lword
);
end;
architecture rtl of dtc_formatOutput_node is
-signal din: t_stubDTC := nullStub;
-signal dout: lword := ( ( others => '0' ), '0', '0', '1' );
-
-signal reset: std_logic := '0';
-signal counter: std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
+ signal din : t_stubDTC := nullStub;
+ signal dout : lword := ( ( others => '0' ), '0', '0', '1' );
+ signal reset : std_logic := '0';
+ signal counter : std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
begin
-node_dout <= dout;
-din <= node_din;
-
-process ( clk ) is
-begin
-if rising_edge( clk ) then
+ node_dout <= dout;
+ din <= node_din;
+ process ( clk ) is
+ begin
+ if rising_edge( clk ) then
- dout.data <= ( others => '0' );
- if dout.valid = '1' then
- if din.valid = '1' then
- dout.data <= conv( din );
- end if;
- counter <= incr( counter );
- if uint( counter ) = numStubs - downTime - 1 then
- dout.valid <= '0';
dout.data <= ( others => '0' );
- end if;
- end if;
+ if dout.valid = '1' then
+ if din.valid = '1' then
+ dout.data <= conv( din );
+ end if;
+ counter <= incr( counter );
+ if uint( counter ) = numStubs - downTime - 1 then
+ dout.valid <= '0';
+ dout.data <= ( others => '0' );
+ end if;
+ end if;
+
+ reset <= din.reset;
+ if reset = '1' then
+ dout.valid <= '1';
+ if din.valid = '1' then
+ dout.data <= conv( din );
+ end if;
+ counter <= ( others => '0' );
+ end if;
- reset <= din.reset;
- if reset = '1' then
- dout.valid <= '1';
- if din.valid = '1' then
- dout.data <= conv( din );
end if;
- counter <= ( others => '0' );
- end if;
-
-end if;
-end process;
+ end process;
end;
diff --git a/dtc-be/firmware/hdl/mux.vhd b/dtc-be/firmware/hdl/mux.vhd
index a81e612599dea05ef4e7605f3df0cf2b8812b7b5..5612f280bb715bdff33a365c2ec447c830126fcf 100644
--- a/dtc-be/firmware/hdl/mux.vhd
+++ b/dtc-be/firmware/hdl/mux.vhd
@@ -6,10 +6,10 @@ use work.dtc_config.all;
entity dtc_mux is
port (
- -- Input Ports ---
+ --- Input Ports ---
clk : in std_logic;
mux_din : in t_stubsRoute( routeStubs - 1 downto 0 );
- -- Output Ports ---
+ --- Output Ports ---
mux_dout : out t_stubsDTC( numLinksDTC - 1 downto 0 )
);
end;
@@ -35,10 +35,10 @@ begin
MuxNodeInstance : entity work.dtc_mux_node
--==============================--
port map (
- -- Input Ports ---
+ --- Input Ports ---
clk => clk,
node_din => linkMapping(mux_din),
- -- Output Ports ---
+ --- Output Ports ---
node_dout => node_dout
);
@@ -49,10 +49,10 @@ begin
latency => k + 1
)
port map (
- -- Input Ports ---
+ --- Input Ports ---
clk => clk,
resync_din => node_dout,
- -- Output Ports ---
+ --- Output Ports ---
resync_dout => mux_dout( numOverlap * ( k + 1 ) - 1 downto numOverlap * k )
);
end generate;
@@ -72,10 +72,10 @@ entity dtc_mux_resync is
latency: natural
);
port (
- -- Input Ports ---
+ --- Input Ports ---
clk : in std_logic;
resync_din : in t_stubsDTC( numOverlap - 1 downto 0 );
- -- Output Ports ---
+ --- Output Ports ---
resync_dout : out t_stubsDTC( numOverlap - 1 downto 0 )
);
end;
@@ -112,10 +112,10 @@ begin
latency => latency
)
port map (
- -- Input Ports ---
+ --- Input Ports ---
clk => clk,
node_din => node_din,
- -- Output Ports ---
+ --- Output Ports ---
node_dout => node_dout
);
@@ -139,10 +139,10 @@ entity dtc_resync_node is
latency: natural
);
port (
- -- Input Ports ---
+ --- Input Ports ---
clk : in std_logic;
node_din : in t_stubDTC;
- -- Output Ports ---
+ --- Output Ports ---
node_dout : out t_stubDTC
);
attribute ram_style: string;
@@ -203,6 +203,7 @@ begin
end;
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -212,201 +213,204 @@ use work.dtc_stubs.all;
use work.dtc_config.all;
entity dtc_mux_node is
-port (
- clk: in std_logic;
- node_din: in t_stubsRoute( routeBlocks - 1 downto 0 );
- node_dout: out t_stubsDTC( numOverlap - 1 downto 0 )
-);
-attribute ram_style: string;
+ port (
+ --- Input Ports ---
+ clk : in std_logic;
+ node_din : in t_stubsRoute( routeBlocks - 1 downto 0 );
+ --- Ouput Ports ---
+ node_dout : out t_stubsDTC( numOverlap - 1 downto 0 )
+ );
+ attribute ram_style: string;
end;
architecture rtl of dtc_mux_node is
-constant widthStub: natural := widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer;
-constant widthPattern: natural := numOverlap;
-constant widthRam: natural := widthPattern + widthStub;
-subtype rangeStub is natural range widthStub - 1 downto 0;
-subtype rangePattern is natural range widthPattern + widthStub - 1 downto widthStub;
-type t_pattern is array ( natural range <> ) of std_logic_vector( widthPattern - 1 downto 0 );
-type t_ram is array ( natural range <> ) of std_logic_vector( widthRam - 1 downto 0 );
-type t_vStubs is array ( natural range <> ) of std_logic_vector( widthStub - 1 downto 0 );
-
-signal patterns: t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
-signal stubs: t_vStubs( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
-signal enablesOut: t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
-
-function set_enables( patterns: t_pattern ) return t_pattern is
- variable enables: t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
-begin
- for k in numOverlap - 1 downto 0 loop
- for l in routeBlocks - 1 downto 0 loop
- if patterns( l )( k ) = '1' then
- enables( l )( k ) := '1';
- exit;
- end if;
+ constant widthStub : natural := widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer;
+ constant widthPattern : natural := numOverlap;
+ constant widthRam : natural := widthPattern + widthStub;
+
+ subtype rangeStub is natural range widthStub - 1 downto 0;
+ subtype rangePattern is natural range widthPattern + widthStub - 1 downto widthStub;
+ type t_pattern is array ( natural range <> ) of std_logic_vector( widthPattern - 1 downto 0 );
+ type t_ram is array ( natural range <> ) of std_logic_vector( widthRam - 1 downto 0 );
+ type t_vStubs is array ( natural range <> ) of std_logic_vector( widthStub - 1 downto 0 );
+
+ signal patterns : t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
+ signal stubs : t_vStubs( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
+ signal enablesOut : t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
+
+ function set_enables( patterns: t_pattern ) return t_pattern is
+ variable enables: t_pattern( routeBlocks - 1 downto 0 ) := ( others => ( others => '0' ) );
+ begin
+ for k in numOverlap - 1 downto 0 loop
+ for l in routeBlocks - 1 downto 0 loop
+ if patterns( l )( k ) = '1' then
+ enables( l )( k ) := '1';
+ exit;
+ end if;
+ end loop;
end loop;
- end loop;
- return enables;
-end function;
+ return enables;
+ end function;
-function lconv( s: t_stubRoute ) return std_logic_vector is begin return s.r & s.phi & s.z & s.mMin & s.mMax & s.etaMin & s.etaMax & s.layer; end function;
+ function lconv( s: t_stubRoute ) return std_logic_vector is begin return s.r & s.phi & s.z & s.mMin & s.mMax & s.etaMin & s.etaMax & s.layer; end function;
begin
-enablesOut <= set_enables( patterns );
+ enablesOut <= set_enables( patterns );
-gOuts: for k in numOverlap - 1 downto 0 generate
+ gOuts: for k in numOverlap - 1 downto 0 generate
-signal stub: t_stubDTC := nullStub;
-signal reset: std_logic_vector( 3 downto 0 ) := ( others => '0' );
+ signal stub : t_stubDTC := nullStub;
+ signal reset : std_logic_vector( 3 downto 0 ) := ( others => '0' );
-function lconv( s: std_logic_vector ) return t_stubDTC is
- variable stub: t_stubDTC := nullStub;
-begin
- stub.r := s( widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.phi := s( widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.z := s( widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.mMin := s( widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.mMax := s( widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthSectorEta + widthLayer );
- stub.etaMin := s( widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthLayer );
- stub.etaMax := s( widthSectorEta + widthLayer - 1 downto widthLayer );
- stub.layer := s( widthLayer - 1 downto 0 );
- if k = 0 then
- stub.phi := std_logic_vector( signed( stub.phi ) + 2 ** ( widthPhiDTC - 2 ) );
- else
- stub.phi := std_logic_vector( signed( stub.phi ) - 2 ** ( widthPhiDTC - 2 ) );
- end if;
- return stub;
-end function;
+ function lconv( s: std_logic_vector ) return t_stubDTC is
+ variable stub: t_stubDTC := nullStub;
+ begin
+ stub.r := s( widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.phi := s( widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.z := s( widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.mMin := s( widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.mMax := s( widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthSectorEta + widthLayer );
+ stub.etaMin := s( widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthLayer );
+ stub.etaMax := s( widthSectorEta + widthLayer - 1 downto widthLayer );
+ stub.layer := s( widthLayer - 1 downto 0 );
+ if k = 0 then
+ stub.phi := std_logic_vector( signed( stub.phi ) + 2 ** ( widthPhiDTC - 2 ) );
+ else
+ stub.phi := std_logic_vector( signed( stub.phi ) - 2 ** ( widthPhiDTC - 2 ) );
+ end if;
+ return stub;
+ end function;
-begin
+ begin
-node_dout( k ) <= stub;
+ node_dout( k ) <= stub;
-process( clk ) is
-begin
-if rising_edge( clk ) then
-
- reset <= reset( reset'high - 1 downto 0 ) & node_din( 0 ).reset;
- stub <= nullStub;
- for l in routeBlocks - 1 downto 0 loop
- if enablesOut( l )( k ) = '1' then
- stub <= lconv( stubs( l ) );
- stub.valid <= '1';
- exit;
- end if;
- end loop;
- if reset( reset'high ) = '1' then
- stub <= nullStub;
- stub.reset <= '1';
- end if;
+ process( clk ) is
+ begin
+ if rising_edge( clk ) then
+
+ reset <= reset( reset'high - 1 downto 0 ) & node_din( 0 ).reset;
+ stub <= nullStub;
+ for l in routeBlocks - 1 downto 0 loop
+ if enablesOut( l )( k ) = '1' then
+ stub <= lconv( stubs( l ) );
+ stub.valid <= '1';
+ exit;
+ end if;
+ end loop;
+ if reset( reset'high ) = '1' then
+ stub <= nullStub;
+ stub.reset <= '1';
+ end if;
-end if;
-end process;
+ end if;
+ end process;
-end generate;
+ end generate;
-gIn: for k in routeBlocks - 1 downto 0 generate
+ gIn: for k in routeBlocks - 1 downto 0 generate
-signal din: t_stubRoute := nullStub;
+ signal din : t_stubRoute := nullStub;
-signal ram: t_ram( 2 ** widthStubs - 1 downto 0 ) := ( others => ( others => '0' ) );
-signal ramReg: std_logic_vector( widthRam - 1 downto 0 ) := ( others => '0' );
-signal waddr, raddr, addr: std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
-signal reset, enableIn, valid, validIn, protect, resetIn: std_logic := '0';
-signal loaded: std_logic_vector( 1 downto 0 ) := ( others => '0' );
-signal patternIn: std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
-signal ramPattern: std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
-signal ramStub: std_logic_vector( widthStub - 1 downto 0 ) := ( others => '0' );
-signal ramStubStub, stubStub: t_stubDTC := nullStub;
+ signal ram : t_ram( 2 ** widthStubs - 1 downto 0 ) := ( others => ( others => '0' ) );
+ signal ramReg : std_logic_vector( widthRam - 1 downto 0 ) := ( others => '0' );
+ signal waddr, raddr, addr : std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
+ signal reset, enableIn, valid, validIn, protect, resetIn : std_logic := '0';
+ signal loaded : std_logic_vector( 1 downto 0 ) := ( others => '0' );
+ signal patternIn : std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
+ signal ramPattern : std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
+ signal ramStub : std_logic_vector( widthStub - 1 downto 0 ) := ( others => '0' );
+ signal ramStubStub, stubStub : t_stubDTC := nullStub;
-signal stub: std_logic_vector( widthStub - 1 downto 0 ) := ( others => '0' );
-signal pattern: std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
-signal enableOut: std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
+ signal stub : std_logic_vector( widthStub - 1 downto 0 ) := ( others => '0' );
+ signal pattern : std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
+ signal enableOut : std_logic_vector( widthPattern - 1 downto 0 ) := ( others => '0' );
-attribute ram_style of ram: signal is "block";
+ attribute ram_style of ram: signal is "block";
-function lconv( s: std_logic_vector ) return t_stubDTC is
- variable stub: t_stubDTC := nullStub;
-begin
- stub.r := s( widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.phi := s( widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.z := s( widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.mMin := s( widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthSectorEta + widthSectorEta + widthLayer );
- stub.mMax := s( widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthSectorEta + widthLayer );
- stub.etaMin := s( widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthLayer );
- stub.etaMax := s( widthSectorEta + widthLayer - 1 downto widthLayer );
- stub.layer := s( widthLayer - 1 downto 0 );
- return stub;
-end function;
+ function lconv( s: std_logic_vector ) return t_stubDTC is
+ variable stub: t_stubDTC := nullStub;
+ begin
+ stub.r := s( widthR + widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.phi := s( widthPhiDTC + widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.z := s( widthZ + widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.mMin := s( widthMBin + widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthMBin + widthSectorEta + widthSectorEta + widthLayer );
+ stub.mMax := s( widthMBin + widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthSectorEta + widthLayer );
+ stub.etaMin := s( widthSectorEta + widthSectorEta + widthLayer - 1 downto widthSectorEta + widthLayer );
+ stub.etaMax := s( widthSectorEta + widthLayer - 1 downto widthLayer );
+ stub.layer := s( widthLayer - 1 downto 0 );
+ return stub;
+ end function;
-begin
+ begin
-enableOut <= enablesOut( k );
-stubs( k ) <= stub;
-patterns( k ) <= pattern;
+ enableOut <= enablesOut( k );
+ stubs( k ) <= stub;
+ patterns( k ) <= pattern;
-patternIn <= din.nonant;
-ramPattern <= ramReg( rangePattern );
-ramStub <= ramReg( rangeStub );
-ramStubStub <= lconv( ramStub );
-stubStub <= lconv( stub );
-enableIn <= '1' when uint( enableOut ) > 0 and enableOut = pattern else '0';
-protect <= '1' when ( addr = waddr ) or ( incr( addr ) = waddr and valid = '1' ) else '0';
-raddr <= incr( addr ) when ( enableIn = '1' or loaded( 1 ) = '0' or loaded( 0 ) = '0' ) and protect = '0' else addr;
+ patternIn <= din.nonant;
+ ramPattern <= ramReg( rangePattern );
+ ramStub <= ramReg( rangeStub );
+ ramStubStub <= lconv( ramStub );
+ stubStub <= lconv( stub );
+ enableIn <= '1' when uint( enableOut ) > 0 and enableOut = pattern else '0';
+ protect <= '1' when ( addr = waddr ) or ( incr( addr ) = waddr and valid = '1' ) else '0';
+ raddr <= incr( addr ) when ( enableIn = '1' or loaded( 1 ) = '0' or loaded( 0 ) = '0' ) and protect = '0' else addr;
-process( clk ) is
-begin
-if rising_edge( clk ) then
-
- din <= node_din( k );
-
- reset <= din.reset;
- valid <= din.valid;
- ramReg <= ram( uint( raddr ) );
- ram( uint( waddr ) ) <= patternIn & lconv( din );
- if din.valid = '1' then
- waddr <= incr( waddr );
- end if;
- if din.reset = '1' then
- valid <= '0';
- waddr <= ( others => '0' );
- end if;
-
- validIn <= valid;
- pattern <= pattern xor enableOut;
- addr <= raddr;
- resetIn <= reset;
- if resetIn = '1' then
- pattern <= ( others => '0' );
- end if;
- if enableIn = '1' or loaded( 1 ) = '0' then
- loaded( 1 ) <= loaded( 0 );
- pattern <= ramPattern;
- stub <= ramStub;
- end if;
- if ( enableIn = '1' or loaded( 1 ) = '0' ) and ( ( validIn = '0' and addr = waddr ) or ( valid = '0' and incr( addr ) = waddr ) ) then
- loaded( 0 ) <= '0';
- end if;
- if ( validIn = '1' and addr = waddr ) or ( valid = '1' and incr( addr ) = waddr ) then
- loaded( 0 ) <= '1';
- end if;
- if enableIn = '1' and loaded( 0 ) = '0' then
- pattern <= ( others => '0' );
- end if;
- if reset = '1' then
- validIn <= '0';
- --pattern <= ( others => '0' );
- loaded <= ( others => '0' );
- addr <= ( others => '0' );
- end if;
-
-end if;
-end process;
-
-end generate;
+ process( clk ) is
+ begin
+ if rising_edge( clk ) then
+
+ din <= node_din( k );
+
+ reset <= din.reset;
+ valid <= din.valid;
+ ramReg <= ram( uint( raddr ) );
+ ram( uint( waddr ) ) <= patternIn & lconv( din );
+ if din.valid = '1' then
+ waddr <= incr( waddr );
+ end if;
+ if din.reset = '1' then
+ valid <= '0';
+ waddr <= ( others => '0' );
+ end if;
+
+ validIn <= valid;
+ pattern <= pattern xor enableOut;
+ addr <= raddr;
+ resetIn <= reset;
+ if resetIn = '1' then
+ pattern <= ( others => '0' );
+ end if;
+ if enableIn = '1' or loaded( 1 ) = '0' then
+ loaded( 1 ) <= loaded( 0 );
+ pattern <= ramPattern;
+ stub <= ramStub;
+ end if;
+ if ( enableIn = '1' or loaded( 1 ) = '0' ) and ( ( validIn = '0' and addr = waddr ) or ( valid = '0' and incr( addr ) = waddr ) ) then
+ loaded( 0 ) <= '0';
+ end if;
+ if ( validIn = '1' and addr = waddr ) or ( valid = '1' and incr( addr ) = waddr ) then
+ loaded( 0 ) <= '1';
+ end if;
+ if enableIn = '1' and loaded( 0 ) = '0' then
+ pattern <= ( others => '0' );
+ end if;
+ if reset = '1' then
+ validIn <= '0';
+ --pattern <= ( others => '0' );
+ loaded <= ( others => '0' );
+ addr <= ( others => '0' );
+ end if;
+
+ end if;
+ end process;
+
+ end generate;
end;
diff --git a/dtc-be/firmware/hdl/top.vhd b/dtc-be/firmware/hdl/top.vhd
index f1ff1c61aa776da870a139df7dda167b7d8922ee..faaa10947acf76d3a9287408f202265880b61124 100644
--- a/dtc-be/firmware/hdl/top.vhd
+++ b/dtc-be/firmware/hdl/top.vhd
@@ -9,7 +9,7 @@ use work.dtc_config.all;
entity dtc_top is
port (
- -- Input Ports ---
+ --- Input Ports ---
clk : in std_logic;
dtc_din : in ldata( 4 * N_REGION - 1 downto 0 );
--- Output Ports ---
@@ -78,7 +78,7 @@ begin
transform_din => transform_din,
--- Input Ports ---
transform_dout => transform_dout,
- -- IPbus Ports ---
+ --- IPbus Ports ---
transform_ipbus => transform_ipbus
);