From 2670831491068dbbd381c8d90f50a2355bdf496f Mon Sep 17 00:00:00 2001
From: Marco Riggirello <marco.riggirello@cern.ch>
Date: Tue, 23 Jul 2024 15:16:11 +0200
Subject: [PATCH] Updated dependencies: using 'dev' version of daqpath-toolkit
---
dependencies.yml | 2 +-
.../common/firmware/hdl/L1DataAggregator.vhd | 98 ++++++++-----------
.../firmware/hdl/emp_daqpath_user_package.vhd | 8 +-
3 files changed, 48 insertions(+), 60 deletions(-)
diff --git a/dependencies.yml b/dependencies.yml
index ef253d77..e19a1e46 100644
--- a/dependencies.yml
+++ b/dependencies.yml
@@ -65,5 +65,5 @@ sources:
url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/10gb-ethernet.git
daqpath-toolkit:
- branch: master
+ branch: dev
url: https://gitlab.cern.ch/dmonk/daqpath-toolkit.git
diff --git a/replacements/dtc/dtc-be/common/firmware/hdl/L1DataAggregator.vhd b/replacements/dtc/dtc-be/common/firmware/hdl/L1DataAggregator.vhd
index 53de7f90..a0c607f9 100644
--- a/replacements/dtc/dtc-be/common/firmware/hdl/L1DataAggregator.vhd
+++ b/replacements/dtc/dtc-be/common/firmware/hdl/L1DataAggregator.vhd
@@ -50,15 +50,9 @@ architecture rtl of L1DataAggregator is
constant cNUM_CHANNELS : integer := INPUT_LINKS * cNumberOfCICs;
- signal word_fifo_rdata : generic_data_fifo_data_array(cNUM_CHANNELS - 1 downto 0);
- signal id_fifo_rdata : ctrl_fifo_data_array(cNUM_CHANNELS - 1 downto 0);
- signal nw_fifo_rdata : ctrl_fifo_data_array(cNUM_CHANNELS - 1 downto 0);
- signal word_fifo_re : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
- signal id_fifo_re : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
- signal nw_fifo_re : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
- signal word_fifo_empty : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
- signal id_fifo_empty : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
- signal nw_fifo_empty : std_logic_vector(cNUM_CHANNELS - 1 downto 0);
+ signal daqpath_data_in : emp_daqpath_data_in_array(cNUM_CHANNELS - 1 downto 0);
+ signal daqpath_empty : emp_daqpath_flags_array(cNUM_CHANNELS - 1 downto 0);
+ signal daqpath_read_en : emp_daqpath_flags_array(cNUM_CHANNELS - 1 downto 0);
signal daqpath_en : std_logic;
signal daqpath_rst : std_logic;
signal daqpath_ext_creg : ipb_reg_v(3 downto 0) := (others => (others => '0'));
@@ -67,11 +61,8 @@ architecture rtl of L1DataAggregator is
-- Daqpath core
- signal int_data_out : std_logic_vector(63 downto 0);
- signal int_data_we_out : std_logic;
- signal int_idnw_out : std_logic_vector(31 downto 0);
- signal int_idnw_we_out : std_logic;
- signal slink : lword;
+ signal daqpath_data_out : emp_daqpath_data_out;
+ signal daqpath_slink_out : emp_daqpath_slink_out;
-- Output IPBus FIFO interface
@@ -133,9 +124,9 @@ begin
status_registers_i : for i in 0 to cNUM_CHANNELS - 1 generate
--==============================--
- daqpath_ext_sreg(1)(i) <= word_fifo_empty(i);
- daqpath_ext_sreg(2)(i) <= id_fifo_empty(i);
- daqpath_ext_sreg(3)(i) <= nw_fifo_empty(i);
+ daqpath_ext_sreg(1)(i) <= daqpath_empty(i).data_word;
+ daqpath_ext_sreg(2)(i) <= daqpath_empty(i).event_id;
+ daqpath_ext_sreg(3)(i) <= daqpath_empty(i).n_words;
end generate status_registers_i;
@@ -174,16 +165,17 @@ begin
map_channels : for j in 0 to cNumberOfCICs - 1 generate
--==============================--
- word_fifo_rdata (i * cNumberOfCICs + j) <= daq_in(i)(j).data_word;
- id_fifo_rdata (i * cNumberOfCICs + j) <= daq_in(i)(j).event_id;
- nw_fifo_rdata (i * cNumberOfCICs + j) <= daq_in(i)(j).n_words;
- word_fifo_empty (i * cNumberOfCICs + j) <= empty(i)(j).data_word;
- id_fifo_empty (i * cNumberOfCICs + j) <= empty(i)(j).event_id;
- nw_fifo_empty (i * cNumberOfCICs + j) <= empty(i)(j).n_words;
+ daqpath_data_in(i * cNumberOfCICs + j).data_word <= daq_in(i)(j).data_word;
+ daqpath_data_in(i * cNumberOfCICs + j).event_id <= daq_in(i)(j).event_id;
+ daqpath_data_in(i * cNumberOfCICs + j).n_words <= daq_in(i)(j).n_words;
+
+ daqpath_empty(i * cNumberOfCICs + j).data_word <= empty(i)(j).data_word;
+ daqpath_empty(i * cNumberOfCICs + j).event_id <= empty(i)(j).event_id;
+ daqpath_empty(i * cNumberOfCICs + j).n_words <= empty(i)(j).n_words;
- read(i)(j).data_word <= word_fifo_re (i * cNumberOfCICs + j);
- read(i)(j).event_id <= id_fifo_re (i * cNumberOfCICs + j);
- read(i)(j).n_words <= nw_fifo_re (i * cNumberOfCICs + j);
+ read(i)(j).data_word <= daqpath_read_en(i * cNumberOfCICs + j).data_word;
+ read(i)(j).event_id <= daqpath_read_en(i * cNumberOfCICs + j).event_id;
+ read(i)(j).n_words <= daqpath_read_en(i * cNumberOfCICs + j).n_words;
end generate map_channels;
@@ -204,35 +196,29 @@ begin
N_CHAN_PER_GROUP => N_CHAN_PER_GROUP
)
port map (
- ipb_clk => clk,
- ipb_rst => rst,
- ipb_in => ipb_to_slaves(N_SLV_DAQPATH_CSR),
- ipb_out => ipb_from_slaves(N_SLV_DAQPATH_CSR),
- clk => clk_p,
- rst => daqpath_rst,
- en => daqpath_en,
- pause => backpressure,
- data_out => int_data_out,
- data_we_out => int_data_we_out,
- idnw_out => int_idnw_out,
- idnw_we_out => int_idnw_we_out,
- slink_data => slink.data,
- slink_dv => slink.valid,
- slink_start => slink.start,
- slink_end => slink.strobe,
- word_fifo_rdata => word_fifo_rdata,
- nw_fifo_rdata => nw_fifo_rdata,
- id_fifo_rdata => id_fifo_rdata,
- id_fifo_re => id_fifo_re,
- nw_fifo_re => nw_fifo_re,
- word_fifo_re => word_fifo_re,
- word_fifo_empty => word_fifo_empty,
- id_fifo_empty => id_fifo_empty,
- nw_fifo_empty => nw_fifo_empty
+ ipb_clk => clk,
+ ipb_rst => rst,
+ ipb_in => ipb_to_slaves(N_SLV_DAQPATH_CSR),
+ ipb_out => ipb_from_slaves(N_SLV_DAQPATH_CSR),
+ clk => clk_p,
+ rst => daqpath_rst,
+ en => daqpath_en,
+ pause => backpressure,
+ empty => daqpath_empty,
+ daqpath_data_in => daqpath_data_in,
+ read_en => daqpath_read_en,
+ daqpath_slink_out => daqpath_slink_out,
+ daqpath_data_out => daqpath_data_out
);
+
-- daqpath stream exposed 'as is'
- data_out <= slink;
+
+ data_out.data <= daqpath_slink_out.data;
+ data_out.valid <= daqpath_slink_out.valid;
+ data_out.start <= daqpath_slink_out.start;
+ data_out.strobe <= daqpath_slink_out.last;
+
--==============================--
-- IPBus Output FIFO
@@ -242,10 +228,10 @@ begin
map_output : for i in 0 to cNUM_LINKS - 1 generate
--==============================--
- output_data_fifo_wdata(i) <= int_data_out;
- output_data_fifo_we(i) <= int_data_we_out;
- output_idnw_fifo_wdata(i) <= int_idnw_out;
- output_idnw_fifo_we(i) <= int_idnw_we_out;
+ output_data_fifo_wdata(i) <= daqpath_data_out.data_out;
+ output_data_fifo_we(i) <= daqpath_data_out.data_out_we;
+ output_idnw_fifo_wdata(i) <= daqpath_data_out.idnw_data;
+ output_idnw_fifo_we(i) <= daqpath_data_out.idnw_data_we;
end generate map_output;
diff --git a/replacements/dtc/dtc-be/common/firmware/hdl/emp_daqpath_user_package.vhd b/replacements/dtc/dtc-be/common/firmware/hdl/emp_daqpath_user_package.vhd
index 0021ba53..e444d7f7 100644
--- a/replacements/dtc/dtc-be/common/firmware/hdl/emp_daqpath_user_package.vhd
+++ b/replacements/dtc/dtc-be/common/firmware/hdl/emp_daqpath_user_package.vhd
@@ -7,9 +7,11 @@ package emp_daqpath_user_package is
-- DAQPATH settings
- --constant N_CHAN : integer := 8; -- total number of channnels (commented out cause channels number is calculated in payload with number fo FE modules/CICs constants)
- constant N_CHAN_PER_GROUP : integer := 8; -- number of channels per pipeline group (number of group is then = ceil(N_CHAN/N_CHAN_PER_GROUP))
- constant DW_BYTES : integer := 4; -- 32 bit words for DTC
+ --constant N_CHAN : integer := 8; -- total number of channnels (commented out cause channels number is calculated in payload with number fo FE modules/CICs constants)
+ constant N_CHAN_PER_GROUP : integer := 8; -- number of channels per pipeline group (number of group is then = ceil(N_CHAN/N_CHAN_PER_GROUP))
+ constant DW_BYTES : integer := 4; -- 32 bit words for DTC
+
+ constant emp_daqpath_ctrl_FIFOs_width : integer := 16; -- Width of the record/event-id input FIFOs words
end package emp_daqpath_user_package;
--
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