diff --git a/common/firmware/hdl/EcalDataAggregator.vhd b/common/firmware/hdl/EcalDataAggregator.vhd
index 367aaca7a81da91459c5b32104b131ef7d3a72f1..a323d7e2e85fb5d0df587da11d89f311c1597f8c 100644
--- a/common/firmware/hdl/EcalDataAggregator.vhd
+++ b/common/firmware/hdl/EcalDataAggregator.vhd
@@ -29,6 +29,7 @@ architecture rtl of EcalDataAggregator is
   
   type tBcIdPipe is array (integer range 0 to 8) of std_logic_vector(11 downto 0);
   signal bcid_p : tBcIdPipe;
+  signal last_valid_bcid : std_logic_vector(11 downto 0);
   
 begin
 
@@ -80,10 +81,19 @@ begin
             data_out(0).start <= '1';         
           end if;
                     
-         if unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) then
-            timer := 0;
-            ecal_data_reg <= ecal_data_p;
-            valid_reg <= '1';
+          if unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) then
+            if not ( valid_reg = '1' and (bcid_p(8) /= last_valid_bcid) ) then
+              timer := 0;
+              ecal_data_reg <= ecal_data_p;
+              last_valid_bcid <= bcid_p(0);
+              valid_reg <= '1';
+            else
+              if timer = 7 then
+                 timer := 0;
+              else 
+                 timer := timer + 1;
+              end if;
+            end if;
           elsif timer = 7 then
             timer :=0;
             valid_reg <= '0';