diff --git a/common/addr_table/mprocessor.xml b/common/addr_table/mprocessor.xml
index 3075dce5e54dad2556a4ab30b501be3f7c8afb67..9a988f46d8112a295d7d6f728a376d50f4327c0f 100644
--- a/common/addr_table/mprocessor.xml
+++ b/common/addr_table/mprocessor.xml
@@ -10,9 +10,14 @@
<node id="header_user_bits" address="0x1"/>
</node>
- <node id="csr" address="0x24" description="MProcessor control and status" fwinfo="endpoint;width=2">
+ <node id="csr" address="0x30" description="MProcessor control and status" fwinfo="endpoint;width=3">
<node id="header_start_select" address="0x0" mask="0x7"/>
- <node id="lff" address="0x2" mask="0x0001"/>
- <node id="super_id" address="0x3"/>
+ <node id="occupancy_windowL" address="0x1"/>
+ <node id="occupancy_windowH" address="0x2" mask="0x000f"/>
+ <node id="lff" address="0x4" mask="0x0001"/>
+ <node id="super_id" address="0x5"/>
+ <node id="occupancy_max_value" address="0x6"/>
</node>
+
+ <node id="occupancy_mem" address="0x400" size="0x100" mode="incremental" fwinfo="endpoint;width=8"/>
</node>
diff --git a/common/firmware/cfg/module.dep b/common/firmware/cfg/module.dep
index 63dca63d46d330ed4792961e7454240fdf91a9a5..7975c1d2b46da0c23b15a492d62dc535d3f42bf2 100644
--- a/common/firmware/cfg/module.dep
+++ b/common/firmware/cfg/module.dep
@@ -11,6 +11,7 @@ src LinkCombinerCore.vhd
src LinkCombinerIPBus.vhd
src --vhdl2008 TrackReconstructor.vhd
src mprocessor_data_types.vhd
+src PayloadHeaderGenerator.vhd
src ipbus_decode_link_aggregator.vhd
src ipbus_decode_mprocessor.vhd
diff --git a/common/firmware/hdl/LinkAggregatorCore.vhd b/common/firmware/hdl/LinkAggregatorCore.vhd
index 495ec9e43733f85e40ecb19296bc93560510f620..c6544ff89d00a359389539e677b43e673f04099a 100644
--- a/common/firmware/hdl/LinkAggregatorCore.vhd
+++ b/common/firmware/hdl/LinkAggregatorCore.vhd
@@ -11,7 +11,8 @@ use work.mprocessor_data_types.all;
entity LinkAggregatorCore is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
@@ -171,7 +172,7 @@ begin
if rising_edge(clk_p) then
wr_en_array_cache <= (others => '0');
wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid;
- data_in <= std_logic_vector(to_unsigned(i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
+ data_in <= std_logic_vector(to_unsigned(INDEX*N_LINKS + i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
end if;
end process pRouteInputData;
diff --git a/common/firmware/hdl/LinkAggregatorIPBus.vhd b/common/firmware/hdl/LinkAggregatorIPBus.vhd
index a17e22aec64e00becb670dc9243fa59dac4f8578..4f1664f19f6bee1b6c80f96ba88602a217af5168 100644
--- a/common/firmware/hdl/LinkAggregatorIPBus.vhd
+++ b/common/firmware/hdl/LinkAggregatorIPBus.vhd
@@ -12,7 +12,8 @@ use work.ipbus_decode_link_aggregator.all;
entity LinkAggregatorIPBus is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
@@ -201,7 +202,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorCore
--==============================--
generic map (
- N_LINKS => N_LINKS
+ N_LINKS => N_LINKS,
+ INDEX => INDEX
)
port map (
--- Input Ports ---
diff --git a/common/firmware/hdl/LinkCombinerCore.vhd b/common/firmware/hdl/LinkCombinerCore.vhd
index 0a217957fc6033307fa14499388c2bbae45ddff3..66086644dccc63c58fd09e47e4c28ba0cd4acc5e 100644
--- a/common/firmware/hdl/LinkCombinerCore.vhd
+++ b/common/firmware/hdl/LinkCombinerCore.vhd
@@ -5,6 +5,7 @@ use work.emp_data_types.all;
use work.dtc_link_maps.all;
use work.dtc_constants.all;
use work.dtc_data_types.all;
+use IEEE.std_logic_misc.all;
entity LinkCombinerCore is
@@ -19,14 +20,14 @@ entity LinkCombinerCore is
output_enable : in std_logic := '0';
links_in : in ldata(N_INPUT_LINKS - 1 downto 0);
packet_start : in std_logic;
- header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
- header_user_bits : in std_logic_vector(31 downto 0) := (others => '0');
+ payload_header : in std_logic_vector(127 downto 0) := (others => '0');
--- Ouput Ports ---
link_out : out lword := LWORD_NULL;
--- Debug Ports ---
debug : out lword := LWORD_NULL;
debug_super_id : out std_logic_vector(31 downto 0);
- debug_fifo : out std_logic_vector(31 downto 0) := (others => '0')
+ debug_fifo : out std_logic_vector(31 downto 0) := (others => '0');
+ debug_packet_size : out lword := LWORD_NULL
);
end LinkCombinerCore;
@@ -87,7 +88,7 @@ architecture Behavioral of LinkCombinerCore is
constant cNullValidArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
constant cFullEmptyArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '1');
- -- Signals
+ -- Signals
signal input_dout_array : tWordArray(0 to N_INPUT_LINKS - 1) := (others => (others => '0'));
signal input_rd_en_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
signal input_almost_empty_array, input_valid_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
@@ -113,7 +114,6 @@ architecture Behavioral of LinkCombinerCore is
signal output_rd_en : std_logic := '0';
signal counter : integer := 0;
- signal status_sr : tStatusShiftRegister := (others => (others => '0'));
signal bcid_sr : tBCIDShiftRegister := (others => (others => '0'));
signal super_id : unsigned(32 - 1 downto 0) := (others => '0');
@@ -124,6 +124,7 @@ architecture Behavioral of LinkCombinerCore is
begin
+
--==============================--
genInputLinkBuffers : for i in 0 to N_INPUT_LINKS - 1 generate
--==============================--
@@ -193,6 +194,8 @@ begin
variable data_count : unsigned(7 downto 0);
begin
if rising_edge(clk_p) then
+ debug_packet_size <= LWORD_NULL;
+
output_valid_previous <= output_valid;
if output_valid = '1' and output_rd_en_check = '1' then
link_out.valid <= '1';
@@ -212,6 +215,9 @@ begin
if data_count >= 2 and output_readout_countdown = 0 then
output_rd_en_check <= output_enable;
output_readout_countdown <= to_integer(data_count);
+
+ debug_packet_size.valid <= '1';
+ debug_packet_size.data(7 downto 0) <= output_data_count;
elsif output_almost_full = '1' and output_readout_countdown = 0 then
output_rd_en_check <= output_enable;
output_readout_countdown <= to_integer(data_count);
@@ -266,7 +272,7 @@ begin
begin
if rising_edge(clk_p) then
-- Iterate pointer to successively empty the input FIFOs
- if input_data_valid = '1' and counter = 4 then
+ if input_data_valid = '1' and counter = 3 then
if input_almost_empty_array(output_pointer) = '0' then
input_rd_en_array(output_pointer) <= '1';
else
@@ -284,6 +290,8 @@ begin
end if;
end if;
else
+ output_pointer <= 0;
+ next_pointer_location := 0;
input_rd_en_array(output_pointer) <= '0';
end if;
@@ -291,7 +299,7 @@ begin
if packet_start = '1' then
counter <= 0;
else
- if counter < 4 then
+ if counter < 3 then
counter <= counter + 1;
else
counter <= counter;
@@ -299,83 +307,27 @@ begin
end if;
output_pointer_buffered <= output_pointer;
output_din <= input_dout_array(output_pointer_buffered);
- output_wr_en <= input_valid_array(output_pointer_buffered);
-
-
- if reset = '1' then
- packet_stub_count <= (others => '0');
- packet_stub_count_previous <= packet_stub_count;
- packet_stub_counter_pointer <= 0;
- packet_stub_count_done <= '0';
- else
- if packet_stub_count_done = '0' then
- if packet_stub_counter_pointer = (cNumberOfFEModules - 1) * cNumberOfCICs then
- packet_stub_count_done <= '1';
- end if;
- packet_stub_count <= packet_stub_count + unsigned(header_in(packet_stub_counter_pointer).stub_count) + unsigned(header_in(packet_stub_counter_pointer + 1).stub_count);
- packet_stub_counter_pointer <= packet_stub_counter_pointer + cNumberOfCICs;
- end if;
- end if;
+ output_wr_en <= input_valid_array(output_pointer_buffered) and (not reset);
if counter = 1 then
- output_wr_en_buf <= '1';
- output_din_buf(63 downto 32) <= header_user_bits;
- output_din_buf(31 downto 0) <= std_logic_vector(super_id);
- elsif counter = 2 then
- output_din_buf <= (others => '0');
- output_din_buf(63 downto 56) <= std_logic_vector(packet_stub_count_previous);
- output_din_buf(47 downto 36) <= bcid_sr(bcid_sr'high);
output_wr_en_buf <= '1';
- if cNumberOfFEModules < 3 then
- output_din_buf(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high);
- else
- output_din_buf(2 * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(2 * cNumberOfCICs * 9 - 1 downto 0);
- end if;
- elsif counter = 3 then
+ output_din_buf <= payload_header(63 downto 0);
+ elsif counter = 2 then
output_din_buf <= (others => '0');
+ output_din_buf(19 downto 0) <= payload_header(83 downto 64);
output_wr_en_buf <= '1';
- if cNumberOfFEModules >= 3 and cNumberOfFEModules < 6 then
- output_din_buf((cNumberOfFEModules - 2) * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 2 * cNumberOfCICs * 9);
- end if;
else
- output_wr_en_buf <= output_wr_en;
+ output_wr_en_buf <= output_wr_en and (not reset);
output_din_buf <= output_din;
end if;
end if;
end process pCombineBuffers;
-
- --==============================--
- pBufferHeader: process(clk_p)
- --==============================--
- variable status : std_logic_vector(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) := (others => '0');
- variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
- begin
- if rising_edge(clk_p) then
- if output_reset = '1' then
- super_id <= (others => '0');
- else
- if packet_start = '1' then
- for i in cNumberOfFEModules - 1 downto 0 loop
- status(i*cNumberOfCICs*9 + 8 downto i*cNumberOfCICs*9) := std_logic_vector(header_in(i*cNumberOfCICs).status);
- status(i*cNumberOfCICs*9 + 17 downto i*cNumberOfCICs*9 + 9) := std_logic_vector(header_in(i*cNumberOfCICs + 1).status);
- end loop;
- status_sr <= status_sr(status_sr'high - 1 downto 0) & status;
- bcid := std_logic_vector(header_in(0).bcid);
- bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
- if unsigned(bcid_sr(bcid_sr'high)) > unsigned(bcid_sr(bcid_sr'high - 1)) then
- super_id <= super_id + 1;
- end if;
- end if;
- end if;
- end if;
- end process pBufferHeader;
-
--==============================--
-- Debug
--==============================--
- debug.data(31 downto 0) <= std_logic_vector(super_id);
+ debug.data(31 downto 0) <= payload_header(31 downto 0);
debug.data(39 downto 32) <= output_data_count;
debug.data(47 downto 40) <= "00" & input_data_count(0);
debug.data(51 downto 48) <= std_logic_vector(to_unsigned(counter, 4));
@@ -385,7 +337,7 @@ begin
debug.data(58) <= input_data_valid;
debug.valid <= '1';
debug.strobe <= '1';
- debug_super_id <= std_logic_vector(super_id);
+ debug_super_id <= payload_header(31 downto 0);
debug_fifo(7 downto 0) <= output_data_count;
debug_fifo(8) <= output_full;
debug_fifo(9) <= output_rd_en;
diff --git a/common/firmware/hdl/LinkCombinerIPBus.vhd b/common/firmware/hdl/LinkCombinerIPBus.vhd
index c813671602e388933f2dc4c4e6396c822b895f3f..47ce10783312434bb69d77950bc6bf5868e5dc6f 100644
--- a/common/firmware/hdl/LinkCombinerIPBus.vhd
+++ b/common/firmware/hdl/LinkCombinerIPBus.vhd
@@ -21,7 +21,7 @@ entity LinkCombinerIPBus is
reset : in std_logic;
links_in : in ldata(N_INPUT_LINKS - 1 downto 0);
packet_start : in std_logic;
- header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ payload_header : in std_logic_vector(127 downto 0) := (others => '0');
lff : in std_logic;
output_srst : in std_logic := '0';
--- Ouput Ports ---
@@ -32,7 +32,8 @@ entity LinkCombinerIPBus is
ipb_in : in ipb_wbus;
ipb_out : out ipb_rbus;
--- Debug Ports ---
- super_id : out std_logic_vector(31 downto 0)
+ super_id : out std_logic_vector(31 downto 0);
+ debug_packet_size : out lword := LWORD_NULL
);
end LinkCombinerIPBus;
@@ -108,14 +109,13 @@ begin
output_enable => link_combiner_rd_en,
links_in => masked_input,
packet_start => packet_start,
- header_in => header_in,
- header_user_bits => control_registers(1),
+ payload_header => payload_header,
--- Output Ports ---
link_out => link_out,
--- Debug Ports ---
-- debug => link_combiner_debug,
- debug_super_id => super_id
- -- debug_fifo => link_aggregator_status_registers(2)
+ debug_super_id => super_id,
+ debug_packet_size => debug_packet_size
);
end Behavioral;
diff --git a/common/firmware/hdl/MProcessor.vhd b/common/firmware/hdl/MProcessor.vhd
index 29ee4cceee6bfcc72d86875a30dded83fe00f02a..d8a4465b88679e5360010cb7e0c050db9409db70 100644
--- a/common/firmware/hdl/MProcessor.vhd
+++ b/common/firmware/hdl/MProcessor.vhd
@@ -16,14 +16,15 @@ use work.dtc_data_types.all;
entity MProcessor is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
clk_p : in std_logic;
links_in : in ldata(N_LINKS - 1 downto 0);
- header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
header_start_array : in tHeaderStartArray := (others => (others => '0'));
+ payload_header : in std_logic_vector(127 downto 0) := (others => '0');
gbe_backpressure : in std_logic := '0';
srst : in std_logic := '0';
--- Output Ports ---
@@ -32,7 +33,9 @@ entity MProcessor is
ipb_clk : in std_logic;
ipb_rst : in std_logic;
ipb_in : in ipb_wbus;
- ipb_out : out ipb_rbus
+ ipb_out : out ipb_rbus;
+ --- Debug Ports ---
+ debug_readout_reset : out std_logic := '0'
);
end MProcessor;
@@ -47,11 +50,20 @@ architecture Behavorial of MProcessor is
signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL);
signal link_aggregator_input : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
- signal status_registers : ipb_reg_v(2 - 1 downto 0) := (others => (others => '0'));
- signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal status_registers : ipb_reg_v(3 - 1 downto 0) := (others => (others => '0'));
+ signal control_registers : ipb_reg_v(3 - 1 downto 0) := (others => (others => '0'));
signal super_id : std_logic_vector(31 downto 0) := (others => '0');
+ signal occupancy_trigger_window_lower : std_logic_vector(31 downto 0) := (others => '0');
+ signal occupancy_trigger_window_upper : std_logic_vector(3 downto 0) := (others => '0');
+ signal occupancy_trigger_window : std_logic_vector(36 - 1 downto 0) := X"0ffffffff";
+ signal occupancy_max_value : std_logic_vector(32 - 1 downto 0) := (others => '0');
+ signal occupancy_histogram_reset : std_logic := '0';
+ signal debug_packet_size : lword := LWORD_NULL;
+
+
+
begin
--==============================--
@@ -78,8 +90,8 @@ begin
MProcessorControlInstance: entity work.ipbus_ctrlreg_v
--==============================--
generic map(
- N_CTRL => 1,
- N_STAT => 2
+ N_CTRL => 3,
+ N_STAT => 3
)
port map(
clk => ipb_clk,
@@ -94,7 +106,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorIPBus
--==============================--
generic map (
- N_LINKS => N_LINKS
+ N_LINKS => N_LINKS,
+ INDEX => INDEX
)
port map (
--- Input Ports ---
@@ -123,7 +136,7 @@ begin
reset => readout_reset,
links_in => aggregated_stubs,
packet_start => packet_start,
- header_in => header_in,
+ payload_header => payload_header,
lff => gbe_backpressure,
output_srst => srst,
--- Output Ports ---
@@ -134,7 +147,8 @@ begin
ipb_in => ipb_to_slaves(N_SLV_LINK_COMBINER),
ipb_out => ipb_from_slaves(N_SLV_LINK_COMBINER),
--- Debug Ports ---
- super_id => super_id
+ super_id => super_id,
+ debug_packet_size => debug_packet_size
);
-- --==============================--
@@ -151,5 +165,47 @@ begin
status_registers(0)(0) <= gbe_backpressure;
status_registers(1) <= super_id;
packet_start <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0);
+ debug_readout_reset <= readout_reset;
+
+
+ --==============================--
+ PacketSizeHistogramInstance : entity work.IPBusHistogram
+ --==============================--
+ generic map (
+ input_width => 8,
+ bin_width => 32,
+ data_offset => 0
+ )
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ data_in => debug_packet_size,
+ histogram_reset => occupancy_histogram_reset,
+ --- Output Ports ---
+ max_bin_value => occupancy_max_value,
+ --- IPBus Ports ---
+ clk => ipb_clk,
+ rst => ipb_rst,
+ ipb_in => ipb_to_slaves(N_SLV_OCCUPANCY_MEM),
+ ipb_out => ipb_from_slaves(N_SLV_OCCUPANCY_MEM)
+ );
+
+ --==============================--
+ OccupancyHistogramResetter : entity work.HistogramResetter
+ --==============================--
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ trigger_window => occupancy_trigger_window,
+ --- Output Ports ---
+ histogram_reset => occupancy_histogram_reset
+ );
+
+ occupancy_trigger_window_lower <= control_registers(1);
+ occupancy_trigger_window_upper <= control_registers(2)(3 downto 0);
+ occupancy_trigger_window <= occupancy_trigger_window_upper & occupancy_trigger_window_lower;
+
+ status_registers(2)(32 - 1 downto 0) <= occupancy_max_value;
+
end Behavorial;
diff --git a/common/firmware/hdl/PayloadHeaderGenerator.vhd b/common/firmware/hdl/PayloadHeaderGenerator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c36d580d6bbeaf4bd4591e3a0bab52ac591526a9
--- /dev/null
+++ b/common/firmware/hdl/PayloadHeaderGenerator.vhd
@@ -0,0 +1,109 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.emp_data_types.all;
+use work.dtc_link_maps.all;
+use work.dtc_constants.all;
+use work.dtc_data_types.all;
+use IEEE.std_logic_misc.all;
+use work.mprocessor_constants.all;
+
+
+entity PayloadHeaderGenerator is
+ port (
+ --- Input Ports ---
+ clk_p : in std_logic;
+ reset : in std_logic;
+ readout_reset : in std_logic;
+ header_start : in std_logic;
+ module_header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ user_bits : in std_logic_vector(31 downto 0);
+ --- Ouput Ports ---
+ header_out : out tPayloadHeaderArray := (others => (others => '0'));
+ --- Debug Ports ---
+ debug_super_id : out std_logic_vector(31 downto 0) := (others => '0')
+ );
+end PayloadHeaderGenerator;
+
+architecture Behavioral of PayloadHeaderGenerator is
+
+ type tBCIDShiftRegister is array(1 downto 0) of std_logic_vector(12 - 1 downto 0);
+ type tInputDataCountArray is array(integer range <>) of std_logic_vector(5 downto 0);
+
+ signal bcid_sr : tBCIDShiftRegister := (others => (others => '0'));
+ signal super_id : unsigned(32 - 1 downto 0) := (others => '0');
+
+ signal packet_stub_count, packet_stub_count_previous : unsigned(7 downto 0) := (others => '0');
+ signal packet_stub_counter_pointer : integer := 0;
+ signal packet_stub_count_done : std_logic := '0';
+
+ signal header_word : std_logic_vector(127 downto 0) := (others => '0');
+
+begin
+
+ --==============================--
+ pBufferHeader: process(clk_p)
+ --==============================--
+ variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_p) then
+ if reset = '1' then
+ super_id <= (others => '0');
+ header_word <= (others => '0');
+ else
+ if header_start = '1' then
+ bcid := std_logic_vector(module_header_in(0).bcid);
+ bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
+ if unsigned(bcid_sr(bcid_sr'high)) > unsigned(bcid_sr(bcid_sr'high - 1)) then
+ super_id <= super_id + 1;
+ end if;
+ end if;
+
+ -- header_word <= (others => '0');
+ header_word(31 downto 0) <= std_logic_vector(super_id);
+ header_word(63 downto 32) <= user_bits;
+ header_word(75 downto 64) <= bcid_sr(bcid_sr'high);
+ end if;
+ end if;
+ end process pBufferHeader;
+
+
+ --==============================--
+ genOutput : for i in 0 to 2 - 1 generate
+ --==============================--
+
+ signal packet_stub_count, packet_stub_count_previous : unsigned(7 downto 0) := (others => '0');
+ signal packet_stub_counter_pointer : integer := 0;
+ signal packet_stub_count_done : std_logic := '0';
+
+ begin
+ --==============================--
+ pCountStubs : process(clk_p)
+ --==============================--
+ begin
+ if rising_edge(clk_p) then
+ if readout_reset = '1' then
+ packet_stub_count <= (others => '0');
+ packet_stub_count_previous <= packet_stub_count;
+ packet_stub_counter_pointer <= 0;
+ packet_stub_count_done <= '0';
+ else
+ if packet_stub_count_done = '0' then
+ if packet_stub_counter_pointer = (6 - 1) * cNumberOfCICs then
+ packet_stub_count_done <= '1';
+ end if;
+ packet_stub_count <= packet_stub_count + unsigned(module_header_in((6*i) + packet_stub_counter_pointer).stub_count) + unsigned(module_header_in((6*i) + packet_stub_counter_pointer + 1).stub_count);
+ packet_stub_counter_pointer <= packet_stub_counter_pointer + cNumberOfCICs;
+ end if;
+ end if;
+
+ header_out(i)(75 downto 0 ) <= header_word(75 downto 0);
+ header_out(i)(83 downto 76) <= std_logic_vector(packet_stub_count_previous);
+ end if;
+ end process pCountStubs;
+
+ end generate ; -- genOutput
+
+ debug_super_id <= std_logic_vector(super_id);
+
+end Behavioral;
diff --git a/common/firmware/hdl/mprocessor_constants.vhd b/common/firmware/hdl/mprocessor_constants.vhd
index 367eb0996372120aec21e2d4da72d9240ed3ce45..00f1e166419cd2b27b16c3659cd4a115d2b202f6 100644
--- a/common/firmware/hdl/mprocessor_constants.vhd
+++ b/common/firmware/hdl/mprocessor_constants.vhd
@@ -7,6 +7,7 @@ use work.dtc_link_maps.all;
package mprocessor_constants is
type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
+ type tPayloadHeaderArray is array(2 - 1 downto 0) of std_logic_vector(127 downto 0);
function convertSLVtoHeaderStartArray (input_vector : in std_logic_vector(2*cNumberOfFEModules - 1 downto 0)) return tHeaderStartArray;
diff --git a/top/addr_table/emp_payload.xml b/top/addr_table/emp_payload.xml
index 0eb42100fd332c0aed71be24da0468b27c36a703..04a81abafb5a6e2ad8be1906fc3d36f38b0bb744 100644
--- a/top/addr_table/emp_payload.xml
+++ b/top/addr_table/emp_payload.xml
@@ -7,17 +7,19 @@
<node id="fe_chan" address="0x200" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=9"/>
-
- <node id="mprocessor" address="0x400" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
- <node id="mproc_ctrl" address="0x4ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
- <node id="chan_sel" mask="0x7f"/>
- <node id="srst" mask="0x80"/>
- <node id="sync_fastreset" mask="0x100"/>
- </node>
-
<node id="tcds_fast_cmd" address="0x600" module="file://dtc_tcds_fastcmd.xml"/>
<node id="link_monitor" address="0x10000" module="file://LinkMonitorInterface.xml"/>
+
+ <node id="mprocessor" address="0x40000" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=12"/>
+ <node id="mproc_ctrl" address="0x4fff0" description="MProcessor channel control" fwinfo="endpoint;width=1">
+ <node id="control" address="0x0">
+ <node id="chan_sel" mask="0x7f"/>
+ <node id="srst" mask="0x80"/>
+ <node id="sync_fastreset" mask="0x100"/>
+ </node>
+ <node id="header_user_bits" address="0x1"/>
+ </node>
<node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>
</node>
diff --git a/top/firmware/hdl/emp_payload.vhd b/top/firmware/hdl/emp_payload.vhd
index cfc5b2217899511711c56c1255cbaf60cfbc3dc6..68d7fe6234f324906c70cfdedd5bb923dd230c14 100644
--- a/top/firmware/hdl/emp_payload.vhd
+++ b/top/firmware/hdl/emp_payload.vhd
@@ -60,7 +60,8 @@ architecture rtl of emp_payload is
signal fe_control_registers : ipb_reg_v(0 downto 0);
signal fe_status_registers : ipb_reg_v(0 downto 0);
- signal mproc_channel_sel : ipb_reg_v(0 downto 0);
+ signal mproc_control_registers : ipb_reg_v(1 downto 0);
+ signal mproc_status_registers : ipb_reg_v(0 downto 0);
signal link_aggr_control : ipb_reg_v(0 downto 0);
@@ -84,6 +85,8 @@ architecture rtl of emp_payload is
signal orbit_counter : unsigned(31 downto 0) := to_unsigned(0 , 32);
signal bunch_counter : unsigned(11 downto 0) := to_unsigned(3564, 12);
+ signal readout_reset : std_logic_vector(cNumberOfMProcessors - 1 downto 0) := (others => '0');
+ signal payload_headers : tPayloadHeaderArray := (others => (others => '0'));
-- Daqpath
@@ -157,18 +160,17 @@ begin
);
--==============================--
- mproc_channel_ctrl: entity work.ipbus_reg_v
+ mproc_ctrl: entity work.ipbus_ctrlreg_v
--==============================--
generic map(
- N_REG => 1
+ N_CTRL => 2
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipb_to_slaves(N_SLV_MPROC_CTRL),
ipbus_out => ipb_from_slaves(N_SLV_MPROC_CTRL),
- q => mproc_channel_sel,
- qmask => (0 => X"00000fff")
+ q => mproc_control_registers
);
@@ -339,7 +341,7 @@ begin
port map(
clk => clk,
rst => rst,
- sel => mproc_channel_sel(0)(6 downto 0),
+ sel => mproc_control_registers(0)(6 downto 0),
ipb_in => ipb_to_slaves(N_SLV_MPROCESSOR),
ipb_out => ipb_from_slaves(N_SLV_MPROCESSOR),
ipbdc_out => mprocessor_ipb_chain(0),
@@ -378,14 +380,15 @@ begin
MProcessorInstance: entity work.MProcessor
--==============================--
generic map(
- N_LINKS => cNumberofInputLinks
+ N_LINKS => cNumberofInputLinks,
+ INDEX => i
)
port map(
--- Input Ports ---
clk_p => clk_p,
links_in => stubs(cNumberofInputLinks*i + (cNumberofInputLinks - 1) downto cNumberofInputLinks*i),
- header_in => header_array,
header_start_array => convertSLVtoHeaderStartArray(header_start_array_buffered),
+ payload_header => payload_headers(i),
gbe_backpressure => gbe_backpressure(i),
srst => srst,
--- Output Ports ---
@@ -394,10 +397,28 @@ begin
ipb_clk => clk,
ipb_rst => rst,
ipb_in => ipb_to_channel,
- ipb_out => ipb_from_channel
+ ipb_out => ipb_from_channel,
+ --- Debug Ports ---
+ debug_readout_reset => readout_reset(i)
);
end generate genMProcessors;
+ --==============================--
+ PayloadHeadeGeneratorInstance : entity work.PayloadHeaderGenerator
+ --==============================--
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ reset => srst,
+ readout_reset => readout_reset(0),
+ header_start => header_start_array_buffered(0),
+ module_header_in => header_array,
+ user_bits => mproc_control_registers(1),
+ --- Ouput Ports ---
+ header_out => payload_headers
+ );
+
+
gbe_q <= eth_link_out;
q(5) <= eth_link_out(0);
@@ -443,8 +464,8 @@ begin
end if;
end process;
- ttc_resync_reset <= mproc_channel_sel(0)(8);
- srst <= mproc_channel_sel(0)(7) or ttc_oc0;
+ ttc_resync_reset <= mproc_control_registers(0)(8);
+ srst <= mproc_control_registers(0)(7) or ttc_oc0;
q(4).valid <= '1';
q(4).data <= "0000" & std_logic_vector(bunch_counter) & "0000000000000000" & std_logic_vector(orbit_counter);