From 44b955bc46179052363179f26ae77ff3ca995999 Mon Sep 17 00:00:00 2001
From: Kirika Uchida <kirika.uchida@gmail.com>
Date: Sun, 10 Sep 2023 09:21:28 +0200
Subject: [PATCH] added pipeline on EcalDataAggregator output
---
common/firmware/hdl/EcalDataAggregator.vhd | 23 +++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/common/firmware/hdl/EcalDataAggregator.vhd b/common/firmware/hdl/EcalDataAggregator.vhd
index 65ee6c27..a6c216db 100644
--- a/common/firmware/hdl/EcalDataAggregator.vhd
+++ b/common/firmware/hdl/EcalDataAggregator.vhd
@@ -28,6 +28,10 @@ architecture rtl of EcalDataAggregator is
signal ecal_data_p : std_logic_vector(28 * 16 -1 downto 0);
alias padding_p is ecal_data(ecal_data'high downto ecal_data'high-2);
+ signal data_out_s : std_logic_vector(28 * 16 -1 downto 0) := (others => '0');
+ signal data_out_s_start : std_logic := '0';
+ signal data_out_s_last : std_logic := '0';
+
signal sync : std_logic := '0';
type tBcIdPipe is array (integer range 0 to 8) of std_logic_vector(11 downto 0);
@@ -67,14 +71,19 @@ begin
bcid_p(i+1) <= bcid_p(i);
end loop;
+ -- data_out pipeline
+ data_out <= data_out_s;
+ data_out_start <= data_out_s_start;
+ data_out_last <= data_out_s_last;
+
-- capturing frames
- data_out_start <= '0';
- data_out_last <= '0';
+ data_out_s_start <= '0';
+ data_out_s_last <= '0';
if sync = '0' then
if padding_p = "111" and (unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) ) then
timer := 0;
- data_out <= ecal_data_p;
- data_out_start <= '1';
+ data_out_s <= ecal_data_p;
+ data_out_s_start <= '1';
last_valid_bcid <= bcid_p(0);
sync <= '1';
elsif timer = 7 then
@@ -86,8 +95,8 @@ begin
if timer = 7 then
timer := 0;
if padding_p = "111" and (unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) ) then
- data_out <= ecal_data_p;
- data_out_start <= '1';
+ data_out_s <= ecal_data_p;
+ data_out_s_start <= '1';
last_valid_bcid <= bcid_p(0);
else
sync <= '0';
@@ -95,7 +104,7 @@ begin
else
timer := timer + 1;
if timer = 7 then
- data_out_last <= '1';
+ data_out_s_last <= '1';
end if;
end if;
end if;
--
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