diff --git a/common/addr_table/link_aggregator.xml b/common/addr_table/link_aggregator.xml
index 9d2ff0d7d08f4d76ac63dd24280b155e41880179..b2374be343a69f693532cee057b6af5ee420c251 100644
--- a/common/addr_table/link_aggregator.xml
+++ b/common/addr_table/link_aggregator.xml
@@ -1,14 +1,24 @@
<node description="Link Aggregator control and status" fwinfo="endpoint">
<node id="chan_sel" address="0x000" description="Bx channel select" fwinfo="endpoint;width=0"/>
- <node id="control" address="0x001" fwinfo="endpoint;width=0">
- <node id="input_link_mask" mask="0x03f"/>
- <node id="reset" mask="0x40"/>
- <node id="trigger_threshold_0" mask="0x00000780"/>
- <node id="trigger_threshold_1" mask="0x00007800"/>
- <node id="trigger_threshold_2" mask="0x00078000"/>
- <node id="trigger_threshold_3" mask="0x00780000"/>
- <node id="trigger_threshold_4" mask="0x07800000"/>
- <node id="trigger_threshold_5" mask="0x78000000"/>
+ <node id="control" address="0x002" fwinfo="endpoint;width=1">
+ <node id="control_l" address="0x0">
+ <node id="input_link_mask" mask="0x03f"/>
+ <node id="reset" mask="0x40"/>
+ <node id="trigger_threshold_l_0" mask="0x00000780"/>
+ <node id="trigger_threshold_l_1" mask="0x00007800"/>
+ <node id="trigger_threshold_l_2" mask="0x00078000"/>
+ <node id="trigger_threshold_l_3" mask="0x00780000"/>
+ <node id="trigger_threshold_l_4" mask="0x07800000"/>
+ <node id="trigger_threshold_l_5" mask="0x78000000"/>
+ <node/>
+ <node id="control_u" address="0x1">
+ <node id="trigger_threshold_u_0" mask="0x0000000f"/>
+ <node id="trigger_threshold_u_1" mask="0x000000f0"/>
+ <node id="trigger_threshold_u_2" mask="0x00000f00"/>
+ <node id="trigger_threshold_u_3" mask="0x0000f000"/>
+ <node id="trigger_threshold_u_4" mask="0x000f0000"/>
+ <node id="trigger_threshold_u_5" mask="0x00f00000"/>
+ <node/>
</node>
<node id="rate_monitoring" address="0x004" fwinfo="endpoint;width=2">
<node id="bx_valid_count" address="0x0"/>
diff --git a/common/firmware/hdl/LinkAggregatorCore.vhd b/common/firmware/hdl/LinkAggregatorCore.vhd
index 067214054469b0e1cc4fbf0b3fbfd8ac9f97f1ff..7f139d05e22a69b964ba7c385a0fc6ef3d9c9c12 100644
--- a/common/firmware/hdl/LinkAggregatorCore.vhd
+++ b/common/firmware/hdl/LinkAggregatorCore.vhd
@@ -19,7 +19,8 @@ entity LinkAggregatorCore is
reset : in std_logic;
packet_start : in std_logic;
links_in : in ldata(N_LINKS - 1 downto 0);
- thresholds : in tIntegerArray := (others => 0);
+ thresholds_l : in tIntegerArray := (others => 0);
+ thresholds_u : in tIntegerArray := (others => 0);
--- Output Ports ---
links_out : out ldata(7 downto 0) := (others => LWORD_NULL);
uncompressed_stubs : out ldata(N_LINKS * 8 - 1 downto 0) := (others => LWORD_NULL);
@@ -230,7 +231,7 @@ begin
begin
if rising_edge(clk_p) then
if packet_start_buffered = '1' then
- if unsigned(count_cache) >= thresholds(i) then
+ if unsigned(count_cache) >= thresholds_l(i) and (unsigned(count_cache) <= thresholds_u(i) or thresholds_u(i) = "0000") then
bx_valid_array(N_LINKS*j + i) <= '1';
else
bx_valid_array(N_LINKS*j + i) <= '0';
diff --git a/common/firmware/hdl/LinkAggregatorIPBus.vhd b/common/firmware/hdl/LinkAggregatorIPBus.vhd
index 628cedc9abf1e223b0f692122347b4f77c94e1b6..a17e22aec64e00becb670dc9243fa59dac4f8578 100644
--- a/common/firmware/hdl/LinkAggregatorIPBus.vhd
+++ b/common/firmware/hdl/LinkAggregatorIPBus.vhd
@@ -40,13 +40,14 @@ architecture Behavorial of LinkAggregatorIPBus is
signal ipb_chain : ipbdc_bus_array(8 downto 0);
-- signal link_aggregator_status_registers : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
- signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal control_registers : ipb_reg_v(1 downto 0) := (others => (others => '0'));
signal mprocessor_monitoring_registers : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
signal rate_monitoring_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal bx_valid_count : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal masked_links : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
- signal thresholds : tIntegerArray := (others => 0);
+ signal thresholds_l : tIntegerArray := (others => 0);
+ signal thresholds_u : tIntegerArray := (others => 0);
begin
@@ -88,7 +89,7 @@ begin
ControlInstance: entity work.ipbus_ctrlreg_v
--==============================--
generic map(
- N_CTRL => 1,
+ N_CTRL => 2,
N_STAT => 0
)
port map(
@@ -191,7 +192,8 @@ begin
genThresholds: for i in 0 to N_LINKS - 1 generate
begin
- thresholds(i) <= to_integer(unsigned(control_registers(0)(4*(i+1) - 1 + 7 downto 4*i + 7)));
+ thresholds_l(i) <= to_integer(unsigned(control_registers(0)(4*(i+1) - 1 + 7 downto 4*i + 7)));
+ thresholds_u(i) <= to_integer(unsigned(control_registers(1)(4*(i+1) - 1 downto 4*i)));
end generate;
@@ -207,7 +209,8 @@ begin
reset => control_registers(0)(6),
packet_start => packet_start,
links_in => masked_links,
- thresholds => thresholds,
+ thresholds_l => thresholds_l,
+ thresholds_u => thresholds_u,
--- Output Ports ---
links_out => links_out,
readout_reset => readout_reset,