diff --git a/common/firmware/hdl/LinkAggregatorCore.vhd b/common/firmware/hdl/LinkAggregatorCore.vhd
index ad9f1d4a7c5a78d7b48af465a9eb6138356f5f1c..022d0d211248d155b79c9a46d47e743e06143f31 100644
--- a/common/firmware/hdl/LinkAggregatorCore.vhd
+++ b/common/firmware/hdl/LinkAggregatorCore.vhd
@@ -10,7 +10,8 @@ use work.ipbus_reg_types.all;
 
 entity LinkAggregatorCore is
     generic (
-        N_LINKS : integer
+        N_LINKS : integer;
+        INDEX   : integer := 0
     );
     port (
         --- Input Ports ---
@@ -169,7 +170,7 @@ begin
             if rising_edge(clk_p) then
                 wr_en_array_cache <= (others => '0');
                 wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid;
-                data_in <= std_logic_vector(to_unsigned(i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
+                data_in <= std_logic_vector(to_unsigned(INDEX*N_LINKS + i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
             end if;
         end process pRouteInputData;
 
diff --git a/common/firmware/hdl/LinkAggregatorIPBus.vhd b/common/firmware/hdl/LinkAggregatorIPBus.vhd
index 43b94dd07529d7d179376fdc4eae9e5cd1505d03..ddf90b771683fd0956a9c2630305333aca081a7b 100644
--- a/common/firmware/hdl/LinkAggregatorIPBus.vhd
+++ b/common/firmware/hdl/LinkAggregatorIPBus.vhd
@@ -11,7 +11,8 @@ use work.ipbus_decode_link_aggregator.all;
 
 entity LinkAggregatorIPBus is
     generic (
-        N_LINKS : integer
+        N_LINKS : integer;
+        INDEX   : integer := 0
     );
     port (
         --- Input Ports ---
@@ -191,7 +192,8 @@ begin
     LinkAggregatorInstance: entity work.LinkAggregatorCore
     --==============================--
     generic map (
-        N_LINKS => N_LINKS
+        N_LINKS => N_LINKS,
+        INDEX   => INDEX
     )
     port map (
         --- Input Ports ---
diff --git a/common/firmware/hdl/LinkCombinerCore.vhd b/common/firmware/hdl/LinkCombinerCore.vhd
index ba692877270912c89311cd8e7b501d249b7d3550..149185a722d69959d692ff3b056bf7ee1e777dbd 100644
--- a/common/firmware/hdl/LinkCombinerCore.vhd
+++ b/common/firmware/hdl/LinkCombinerCore.vhd
@@ -89,11 +89,6 @@ architecture Behavioral of LinkCombinerCore is
     constant cFullEmptyArray                                              : std_logic_vector(N_INPUT_LINKS - 1 downto 0)       := (others => '1');
 
     -- Signals
-    signal input_links_valid                                              : std_logic_vector(N_INPUT_LINKS - 1 downto 0)       := (others => '0');
-    signal all_input_links_valid                                          : std_logic                                          := '0';
-    signal all_input_links_valid_previous                                 : std_logic                                          := '0';
-    signal start_output                                                   : std_logic                                          := '0';
-    
     signal input_dout_array                                               : tWordArray(0 to N_INPUT_LINKS - 1)                 := (others => (others => '0'));
     signal input_rd_en_array                                              : std_logic_vector(N_INPUT_LINKS - 1 downto 0)       := (others => '0');
     signal input_almost_empty_array, input_valid_array                    : std_logic_vector(N_INPUT_LINKS - 1 downto 0)       := (others => '0');
@@ -254,21 +249,13 @@ begin
     --==============================--
     begin
         if rising_edge(clk_p) then
-            if start_output = '1' then
+            if packet_start = '1' then
                 input_data_valid <= '1';
             else
                 if reset = '1' then
                     input_data_valid <= '0';
                 end if;
             end if;
-            
-            all_input_links_valid <= and_reduce(input_links_valid);
-            all_input_links_valid_previous <= all_input_links_valid;
-            if all_input_links_valid = '0' and all_input_links_valid_previous = '1' then
-                start_output <= '1';
-            else
-                start_output <= '0';
-            end if;
         end if;
     end process pValidDataChecker;
     
@@ -306,7 +293,7 @@ begin
             end if;
             
             -- Packet control bits logic
-            if start_output = '1' then
+            if packet_start = '1' then
                 counter <= 0;
             else
                 if counter < 3 then
diff --git a/common/firmware/hdl/MProcessor.vhd b/common/firmware/hdl/MProcessor.vhd
index 29ee4cceee6bfcc72d86875a30dded83fe00f02a..d15baa4a5ee1515b2248c7c4bf88016aa9af4ed5 100644
--- a/common/firmware/hdl/MProcessor.vhd
+++ b/common/firmware/hdl/MProcessor.vhd
@@ -16,7 +16,8 @@ use work.dtc_data_types.all;
 
 entity MProcessor is
     generic (
-        N_LINKS : integer
+        N_LINKS : integer;
+        INDEX   : integer := 0
     );
     port (
         --- Input Ports ---
@@ -94,7 +95,8 @@ begin
     LinkAggregatorInstance: entity work.LinkAggregatorIPBus
     --==============================--
     generic map (
-        N_LINKS       => N_LINKS
+        N_LINKS       => N_LINKS,
+        INDEX         => INDEX
     )
     port map (
         --- Input Ports ---
diff --git a/top/firmware/hdl/emp_payload.vhd b/top/firmware/hdl/emp_payload.vhd
index cfc5b2217899511711c56c1255cbaf60cfbc3dc6..413cdb06f7fbb3e5dd273caea2bc3e67d1bceb28 100644
--- a/top/firmware/hdl/emp_payload.vhd
+++ b/top/firmware/hdl/emp_payload.vhd
@@ -378,7 +378,8 @@ begin
         MProcessorInstance: entity work.MProcessor
         --==============================--
         generic map(
-            N_LINKS => cNumberofInputLinks
+            N_LINKS => cNumberofInputLinks,
+            INDEX   => i
         )
         port map(
             --- Input Ports ---