From 74580161597bc2963372e547fb04d0b6ff6a6de7 Mon Sep 17 00:00:00 2001
From: David Gabriel Monk <david.gabriel.monk@cern.ch>
Date: Thu, 31 Aug 2023 12:29:34 +0200
Subject: [PATCH] Reverted change that had lead to a bug in the readout
---
common/firmware/hdl/LinkAggregatorCore.vhd | 5 +++--
common/firmware/hdl/LinkAggregatorIPBus.vhd | 6 ++++--
common/firmware/hdl/LinkCombinerCore.vhd | 17 ++---------------
common/firmware/hdl/MProcessor.vhd | 6 ++++--
top/firmware/hdl/emp_payload.vhd | 3 ++-
5 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/common/firmware/hdl/LinkAggregatorCore.vhd b/common/firmware/hdl/LinkAggregatorCore.vhd
index ad9f1d4a..022d0d21 100644
--- a/common/firmware/hdl/LinkAggregatorCore.vhd
+++ b/common/firmware/hdl/LinkAggregatorCore.vhd
@@ -10,7 +10,8 @@ use work.ipbus_reg_types.all;
entity LinkAggregatorCore is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
@@ -169,7 +170,7 @@ begin
if rising_edge(clk_p) then
wr_en_array_cache <= (others => '0');
wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid;
- data_in <= std_logic_vector(to_unsigned(i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
+ data_in <= std_logic_vector(to_unsigned(INDEX*N_LINKS + i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
end if;
end process pRouteInputData;
diff --git a/common/firmware/hdl/LinkAggregatorIPBus.vhd b/common/firmware/hdl/LinkAggregatorIPBus.vhd
index 43b94dd0..ddf90b77 100644
--- a/common/firmware/hdl/LinkAggregatorIPBus.vhd
+++ b/common/firmware/hdl/LinkAggregatorIPBus.vhd
@@ -11,7 +11,8 @@ use work.ipbus_decode_link_aggregator.all;
entity LinkAggregatorIPBus is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
@@ -191,7 +192,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorCore
--==============================--
generic map (
- N_LINKS => N_LINKS
+ N_LINKS => N_LINKS,
+ INDEX => INDEX
)
port map (
--- Input Ports ---
diff --git a/common/firmware/hdl/LinkCombinerCore.vhd b/common/firmware/hdl/LinkCombinerCore.vhd
index ba692877..149185a7 100644
--- a/common/firmware/hdl/LinkCombinerCore.vhd
+++ b/common/firmware/hdl/LinkCombinerCore.vhd
@@ -89,11 +89,6 @@ architecture Behavioral of LinkCombinerCore is
constant cFullEmptyArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '1');
-- Signals
- signal input_links_valid : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
- signal all_input_links_valid : std_logic := '0';
- signal all_input_links_valid_previous : std_logic := '0';
- signal start_output : std_logic := '0';
-
signal input_dout_array : tWordArray(0 to N_INPUT_LINKS - 1) := (others => (others => '0'));
signal input_rd_en_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
signal input_almost_empty_array, input_valid_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
@@ -254,21 +249,13 @@ begin
--==============================--
begin
if rising_edge(clk_p) then
- if start_output = '1' then
+ if packet_start = '1' then
input_data_valid <= '1';
else
if reset = '1' then
input_data_valid <= '0';
end if;
end if;
-
- all_input_links_valid <= and_reduce(input_links_valid);
- all_input_links_valid_previous <= all_input_links_valid;
- if all_input_links_valid = '0' and all_input_links_valid_previous = '1' then
- start_output <= '1';
- else
- start_output <= '0';
- end if;
end if;
end process pValidDataChecker;
@@ -306,7 +293,7 @@ begin
end if;
-- Packet control bits logic
- if start_output = '1' then
+ if packet_start = '1' then
counter <= 0;
else
if counter < 3 then
diff --git a/common/firmware/hdl/MProcessor.vhd b/common/firmware/hdl/MProcessor.vhd
index 29ee4cce..d15baa4a 100644
--- a/common/firmware/hdl/MProcessor.vhd
+++ b/common/firmware/hdl/MProcessor.vhd
@@ -16,7 +16,8 @@ use work.dtc_data_types.all;
entity MProcessor is
generic (
- N_LINKS : integer
+ N_LINKS : integer;
+ INDEX : integer := 0
);
port (
--- Input Ports ---
@@ -94,7 +95,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorIPBus
--==============================--
generic map (
- N_LINKS => N_LINKS
+ N_LINKS => N_LINKS,
+ INDEX => INDEX
)
port map (
--- Input Ports ---
diff --git a/top/firmware/hdl/emp_payload.vhd b/top/firmware/hdl/emp_payload.vhd
index cfc5b221..413cdb06 100644
--- a/top/firmware/hdl/emp_payload.vhd
+++ b/top/firmware/hdl/emp_payload.vhd
@@ -378,7 +378,8 @@ begin
MProcessorInstance: entity work.MProcessor
--==============================--
generic map(
- N_LINKS => cNumberofInputLinks
+ N_LINKS => cNumberofInputLinks,
+ INDEX => i
)
port map(
--- Input Ports ---
--
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