From 77aa0a36c28d09f483a3f58b4186d0da9df1b8af Mon Sep 17 00:00:00 2001
From: David Gabriel Monk <david.gabriel.monk@cern.ch>
Date: Sat, 1 Oct 2022 23:31:58 +0200
Subject: [PATCH] Update top/firmware/hdl/LinkAggregatorCore.vhd
---
top/firmware/hdl/LinkAggregatorCore.vhd | 41 ++++++++++++++++++++++---
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/top/firmware/hdl/LinkAggregatorCore.vhd b/top/firmware/hdl/LinkAggregatorCore.vhd
index fbf08994..8c2c46aa 100644
--- a/top/firmware/hdl/LinkAggregatorCore.vhd
+++ b/top/firmware/hdl/LinkAggregatorCore.vhd
@@ -127,7 +127,8 @@ architecture compressed of LinkAggregatorCore is
signal output_overflow_array : std_logic_vector(cBoxcarBx - 1 downto 0) := (others => '0');
signal route_overflow_array : tEnableArray := cNullEnableArray;
signal cache_overflow_array : tEnableArray := cNullEnableArray;
-
+
+ signal bx_valid_array : std_logic_vector(N_LINKS * cBoxcarBx - 1 downto 0) := (others => '0');
signal non_empty_fifo_count : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
@@ -168,6 +169,7 @@ begin
signal din_route, dout_route : std_logic_vector(cFIFOWidth - 1 downto 0) := (others => '0');
signal count_route : std_logic_vector(4 downto 0);
signal route_reset : std_logic := '0';
+ signal countdown_iterator : unsigned(3 downto 0) := (others => '0');
begin
@@ -181,11 +183,13 @@ begin
if packet_start = '1' then
if empty_cache = '0' then
rd_en_cache <= '1';
+ countdown_iterator <= unsigned(count_cache) - 1;
end if;
- end if;
- if rd_en_cache = '1' then
- -- Use almost empty flag to avoid underflow
- if almost_empty_cache = '1' then
+ else
+ if countdown_iterator > 0 then
+ countdown_iterator <= countdown_iterator - 1;
+ else
+ countdown_iterator <= countdown_iterator;
rd_en_cache <= '0';
end if;
end if;
@@ -198,6 +202,22 @@ begin
end if;
end process pTransferToRoutingFIFO;
+ --==============================--
+ pCheckBxValidConditionPerLink : process(clk_p)
+ --==============================--
+ begin
+ if rising_edge(clk_p) then
+ if packet_start = '1' then
+ if unsigned(count_cache) > 0 then
+ bx_valid_array(N_LINKS*j + i) <= '1';
+ else
+ bx_valid_array(N_LINKS*j + i) <= '0';
+ end if;
+ end if;
+ end if;
+ end process pCheckBxValidConditionPerLink;
+
+
-- Enable writing of routing FIFO using the valid flag of the cache FIFO
wr_en_route <= valid_cache;
din_route <= dout_cache;
@@ -266,6 +286,8 @@ begin
signal compressed_stub_pointer : integer range 0 to 1 := 0;
signal previous_valid_row : std_logic_vector(N_LINKS - 1 downto 0) := (others => '0');
signal all_links_reset : std_logic := '0';
+
+ signal bx_valid : std_logic := '0';
begin
--==============================--
@@ -273,6 +295,9 @@ begin
-- Process to iterate of the link FIFOs and route the data to the output FIFO, if data is present on a given link.
-- The process uses a rotating pointer to repeatedly iterate over all links, taking one stub per iteration, until all link FIFOs are empty.
--==============================--
+
+ variable bx_valid_variable : std_logic := '0';
+
begin
if rising_edge(clk_p) then
@@ -312,6 +337,12 @@ begin
wr_en <= '0';
end if;
+ -- Check if Bx is valid
+ bx_valid_variable := '1';
+ for j in 0 to N_LINKS - 1 loop
+ bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*i + j);
+ end loop;
+ bx_valid <= bx_valid_variable;
-- If counter is at the end of a packet, then start to readout the contents of the aggregated FIFOs
if counter = 47 and empty = '0' then
--
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