diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..1bb46147d7feb65673794f3a0c412fb42fdff549
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.code-workspace
\ No newline at end of file
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d8cc2f13f84cd9f5972ccb5978882eb4f65fc8d3..8fe1eba72dc0d40bd1487ec04e8051687700043a 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -3,7 +3,7 @@ include:
file: "/ci/templates/vivado-jobs.yml"
variables:
- VIVADO_VER: "2020.2"
+ VIVADO_VER: "2022.2"
PROJECT_DEPFILE: top.dep
PROJECT_ALGORITHM: top
PROJECT_NAME: mprocessor
diff --git a/top/addr_table/link_aggregator.xml b/common/addr_table/link_aggregator.xml
similarity index 79%
rename from top/addr_table/link_aggregator.xml
rename to common/addr_table/link_aggregator.xml
index a6ab3964ed27d2a1a7dfae821b7f8819e3b06e2a..ce2c72808222577139aaf0aeca6cfb7895965644 100644
--- a/top/addr_table/link_aggregator.xml
+++ b/common/addr_table/link_aggregator.xml
@@ -3,6 +3,10 @@
<node id="control" address="0x001" fwinfo="endpoint;width=0">
<node id="input_link_mask" mask="0x03f"/>
<node id="reset" mask="0x40"/>
+ <node id="trigger_threshold" mask="0x780"/>
+ </node>
+ <node id="rate_monitoring" address="0x004" fwinfo="endpoint;width=2">
+ <node id="bx_valid_count" address="0x0"/>
</node>
<node id="monitoring" address="0x008" fwinfo="endpoint;width=3">
<node id="non_empty_count_0" address="0x0"/>
diff --git a/top/addr_table/mprocessor.xml b/common/addr_table/mprocessor.xml
similarity index 77%
rename from top/addr_table/mprocessor.xml
rename to common/addr_table/mprocessor.xml
index 57de74f4a685f1dfc83ce13ac3df042663237bb8..3075dce5e54dad2556a4ab30b501be3f7c8afb67 100644
--- a/top/addr_table/mprocessor.xml
+++ b/common/addr_table/mprocessor.xml
@@ -10,8 +10,9 @@
<node id="header_user_bits" address="0x1"/>
</node>
- <node id="csr" address="0x22" description="MProcessor control and status" fwinfo="endpoint;width=1">
+ <node id="csr" address="0x24" description="MProcessor control and status" fwinfo="endpoint;width=2">
<node id="header_start_select" address="0x0" mask="0x7"/>
- <node id="lff" address="0x1" mask="0x0001"/>
+ <node id="lff" address="0x2" mask="0x0001"/>
+ <node id="super_id" address="0x3"/>
</node>
</node>
diff --git a/common/firmware/cfg/module.dep b/common/firmware/cfg/module.dep
new file mode 100644
index 0000000000000000000000000000000000000000..f8a06571bcd54844ef87fc64bc6df49d81c00ff4
--- /dev/null
+++ b/common/firmware/cfg/module.dep
@@ -0,0 +1,31 @@
+setup -f --cd ../cfg settings.tcl
+
+src fixed_pkg_2008.vhd
+
+src mprocessor_constants.vhd
+
+src MProcessor.vhd
+src LinkAggregatorCore.vhd
+src LinkAggregatorIPBus.vhd
+src LinkCombinerCore.vhd
+src LinkCombinerIPBus.vhd
+src --vhdl2008 TrackReconstructor.vhd
+
+src ipbus_decode_link_aggregator.vhd
+src ipbus_decode_mprocessor.vhd
+
+addrtab -t mprocessor.xml
+addrtab -t link_aggregator.xml
+
+# IP Cores
+src --cd ../cgn link_agg_single_link_fifo.xci
+setup -f --cd ../cgn link_agg_single_link_fifo.tcl
+
+src --cd ../cgn link_agg_single_link_fifo_fwft.xci
+setup -f --cd ../cgn link_agg_single_link_fifo_fwft.tcl
+
+src --cd ../cgn link_agg_all_links_fifo.xci
+setup -f --cd ../cgn link_agg_all_links_fifo.tcl
+
+src --cd ../cgn link_combin_buffer.xci
+setup -f --cd ../cgn link_combin_buffer.tcl
\ No newline at end of file
diff --git a/top/firmware/cfg/settings.tcl b/common/firmware/cfg/settings.tcl
similarity index 100%
rename from top/firmware/cfg/settings.tcl
rename to common/firmware/cfg/settings.tcl
diff --git a/top/firmware/cgn/link_agg_all_links_fifo.tcl b/common/firmware/cgn/link_agg_all_links_fifo.tcl
similarity index 100%
rename from top/firmware/cgn/link_agg_all_links_fifo.tcl
rename to common/firmware/cgn/link_agg_all_links_fifo.tcl
diff --git a/top/firmware/cgn/link_agg_all_links_fifo.xci b/common/firmware/cgn/link_agg_all_links_fifo.xci
similarity index 100%
rename from top/firmware/cgn/link_agg_all_links_fifo.xci
rename to common/firmware/cgn/link_agg_all_links_fifo.xci
diff --git a/top/firmware/cgn/link_agg_single_link_fifo.tcl b/common/firmware/cgn/link_agg_single_link_fifo.tcl
similarity index 100%
rename from top/firmware/cgn/link_agg_single_link_fifo.tcl
rename to common/firmware/cgn/link_agg_single_link_fifo.tcl
diff --git a/top/firmware/cgn/link_agg_single_link_fifo.xci b/common/firmware/cgn/link_agg_single_link_fifo.xci
similarity index 100%
rename from top/firmware/cgn/link_agg_single_link_fifo.xci
rename to common/firmware/cgn/link_agg_single_link_fifo.xci
diff --git a/top/firmware/cgn/link_agg_single_link_fifo_fwft.tcl b/common/firmware/cgn/link_agg_single_link_fifo_fwft.tcl
similarity index 100%
rename from top/firmware/cgn/link_agg_single_link_fifo_fwft.tcl
rename to common/firmware/cgn/link_agg_single_link_fifo_fwft.tcl
diff --git a/top/firmware/cgn/link_agg_single_link_fifo_fwft.xci b/common/firmware/cgn/link_agg_single_link_fifo_fwft.xci
similarity index 100%
rename from top/firmware/cgn/link_agg_single_link_fifo_fwft.xci
rename to common/firmware/cgn/link_agg_single_link_fifo_fwft.xci
diff --git a/top/firmware/cgn/link_combin_buffer.tcl b/common/firmware/cgn/link_combin_buffer.tcl
similarity index 100%
rename from top/firmware/cgn/link_combin_buffer.tcl
rename to common/firmware/cgn/link_combin_buffer.tcl
diff --git a/top/firmware/cgn/link_combin_buffer.xci b/common/firmware/cgn/link_combin_buffer.xci
similarity index 100%
rename from top/firmware/cgn/link_combin_buffer.xci
rename to common/firmware/cgn/link_combin_buffer.xci
diff --git a/top/firmware/hdl/LinkAggregatorCore.vhd b/common/firmware/hdl/LinkAggregatorCore.vhd
similarity index 82%
rename from top/firmware/hdl/LinkAggregatorCore.vhd
rename to common/firmware/hdl/LinkAggregatorCore.vhd
index fbf08994a306c4f3ebf078689b7f0ad809e9583a..de44256fa46d86a904347903b91f5215562ac75e 100644
--- a/top/firmware/hdl/LinkAggregatorCore.vhd
+++ b/common/firmware/hdl/LinkAggregatorCore.vhd
@@ -17,6 +17,7 @@ entity LinkAggregatorCore is
reset : in std_logic;
packet_start : in std_logic;
links_in : in ldata(N_LINKS - 1 downto 0);
+ trigger_threshold : in integer := 0;
--- Output Ports ---
links_out : out ldata(7 downto 0) := (others => LWORD_NULL);
uncompressed_stubs : out ldata(N_LINKS * 8 - 1 downto 0) := (others => LWORD_NULL);
@@ -24,7 +25,8 @@ entity LinkAggregatorCore is
--- Debug Ports ---
status_bits : out std_logic_vector(15 downto 0);
--- IPBus Ports ---
- non_empty_counts : out ipb_reg_v(8*N_LINKS - 1 downto 0)
+ non_empty_counts : out ipb_reg_v(8*N_LINKS - 1 downto 0);
+ bx_valid_count_out : out ipb_reg_v(0 downto 0)
);
end LinkAggregatorCore;
@@ -127,9 +129,12 @@ architecture compressed of LinkAggregatorCore is
signal output_overflow_array : std_logic_vector(cBoxcarBx - 1 downto 0) := (others => '0');
signal route_overflow_array : tEnableArray := cNullEnableArray;
signal cache_overflow_array : tEnableArray := cNullEnableArray;
-
+
+ signal bx_valid_array : std_logic_vector(N_LINKS * cBoxcarBx - 1 downto 0) := (others => '0');
signal non_empty_fifo_count : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
+ signal bx_valid_count : ipb_reg_v(0 downto 0) := (others => (others => '0'));
+ signal pBx_counter : integer := 0;
begin
@@ -168,6 +173,7 @@ begin
signal din_route, dout_route : std_logic_vector(cFIFOWidth - 1 downto 0) := (others => '0');
signal count_route : std_logic_vector(4 downto 0);
signal route_reset : std_logic := '0';
+ signal countdown_iterator : unsigned(3 downto 0) := (others => '0');
begin
@@ -181,23 +187,45 @@ begin
if packet_start = '1' then
if empty_cache = '0' then
rd_en_cache <= '1';
+ countdown_iterator <= unsigned(count_cache) - 1;
end if;
- end if;
- if rd_en_cache = '1' then
- -- Use almost empty flag to avoid underflow
- if almost_empty_cache = '1' then
+ else
+ if countdown_iterator > 0 then
+ countdown_iterator <= countdown_iterator - 1;
+ else
+ countdown_iterator <= countdown_iterator;
rd_en_cache <= '0';
end if;
end if;
-- Check for non-empty FIFOs at reset
- if route_reset = '1' then
- if empty_route = '0' then
- non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+ if reset = '1' then
+ non_empty_fifo_count(N_LINKS*j + i) <= (others => '0');
+ else
+ if route_reset = '1' then
+ if empty_route = '0' then
+ non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+ end if;
end if;
end if;
end if;
end process pTransferToRoutingFIFO;
+ --==============================--
+ pCheckBxValidConditionPerLink : process(clk_p)
+ --==============================--
+ begin
+ if rising_edge(clk_p) then
+ if packet_start = '1' then
+ if unsigned(count_cache) >= trigger_threshold then
+ bx_valid_array(N_LINKS*j + i) <= '1';
+ else
+ bx_valid_array(N_LINKS*j + i) <= '0';
+ end if;
+ end if;
+ end if;
+ end process pCheckBxValidConditionPerLink;
+
+
-- Enable writing of routing FIFO using the valid flag of the cache FIFO
wr_en_route <= valid_cache;
din_route <= dout_cache;
@@ -266,6 +294,8 @@ begin
signal compressed_stub_pointer : integer range 0 to 1 := 0;
signal previous_valid_row : std_logic_vector(N_LINKS - 1 downto 0) := (others => '0');
signal all_links_reset : std_logic := '0';
+
+ signal bx_valid : std_logic := '0';
begin
--==============================--
@@ -273,6 +303,8 @@ begin
-- Process to iterate of the link FIFOs and route the data to the output FIFO, if data is present on a given link.
-- The process uses a rotating pointer to repeatedly iterate over all links, taking one stub per iteration, until all link FIFOs are empty.
--==============================--
+ variable bx_valid_variable : std_logic := '0';
+
begin
if rising_edge(clk_p) then
@@ -312,10 +344,18 @@ begin
wr_en <= '0';
end if;
+ -- Check if Bx is valid
+ bx_valid_variable := '1';
+ for j in 0 to N_LINKS - 1 loop
+ bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*i + j);
+ end loop;
+ bx_valid <= bx_valid_variable;
-- If counter is at the end of a packet, then start to readout the contents of the aggregated FIFOs
- if counter = 47 and empty = '0' then
- rd_en <= '1';
+ if counter = 47 then
+ if empty = '0' and bx_valid = '1' then
+ rd_en <= '1';
+ end if;
end if;
if rd_en = '1' then
if almost_empty = '1' then
@@ -331,6 +371,7 @@ begin
links_out(i).data <= (others => '0');
end if;
links_out(i).strobe <= '1';
+
end if;
end process pIteratePointer;
@@ -385,6 +426,40 @@ begin
end if;
end process pReadoutReset;
+ --==============================--
+ pCountValidBits : process(clk_p)
+ --==============================--
+ variable bx_valid_variable : std_logic := '0';
+ begin
+ if rising_edge(clk_p) then
+ if counter = 47 then
+ pBx_counter <= 0;
+ else
+ if pBx_counter = 8 then
+ pBx_counter <= pBx_counter;
+ else
+ pBx_counter <= pBx_counter + 1;
+ end if;
+ end if;
+
+ if pBx_counter < 8 then
+ bx_valid_variable := '1';
+ for j in 0 to N_LINKS - 1 loop
+ bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*pBx_counter + j);
+ end loop;
+ end if;
+
+ -- Increment counter if bx_valid is set high when readout is started
+ if reset = '1' then
+ bx_valid_count(0) <= (others => '0');
+ else
+ if bx_valid_variable = '1' and pBx_counter < 8 then
+ bx_valid_count(0) <= std_logic_vector(unsigned(bx_valid_count(0)) + 1);
+ end if;
+ end if;
+ end if;
+ end process pCountValidBits;
+
--==============================--
-- Debug
--==============================--
@@ -399,5 +474,6 @@ begin
status_bits(8) <= cache_overflow_array(0)(0); -- link_aggregator_cache_0_0_overflow;
status_bits(9) <= route_overflow_array(0)(0); -- link_aggregator_route_0_0_overflow;
non_empty_counts <= non_empty_fifo_count;
+ bx_valid_count_out <= bx_valid_count;
end compressed;
diff --git a/top/firmware/hdl/LinkAggregatorIPBus.vhd b/common/firmware/hdl/LinkAggregatorIPBus.vhd
similarity index 80%
rename from top/firmware/hdl/LinkAggregatorIPBus.vhd
rename to common/firmware/hdl/LinkAggregatorIPBus.vhd
index 25bad0443646df2d35d9865bc63acb5d12653f76..43b94dd07529d7d179376fdc4eae9e5cd1505d03 100644
--- a/top/firmware/hdl/LinkAggregatorIPBus.vhd
+++ b/common/firmware/hdl/LinkAggregatorIPBus.vhd
@@ -38,11 +38,13 @@ architecture Behavorial of LinkAggregatorIPBus is
signal channel_sel : ipb_reg_v(0 downto 0);
signal ipb_chain : ipbdc_bus_array(8 downto 0);
- -- signal link_aggregator_status_registers : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
- signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
- signal mprocessor_monitoring_registers : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
+ -- signal link_aggregator_status_registers : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
+ signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal mprocessor_monitoring_registers : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
+ signal rate_monitoring_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal bx_valid_count : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
- signal masked_links : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
+ signal masked_links : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
begin
@@ -96,6 +98,21 @@ begin
q => control_registers
);
+ --==============================--
+ RateMonitoringInstance: entity work.ipbus_ctrlreg_v
+ --==============================--
+ generic map(
+ N_CTRL => 0,
+ N_STAT => 1
+ )
+ port map(
+ clk => ipb_clk,
+ reset => ipb_rst,
+ ipbus_in => ipb_to_slaves(N_SLV_RATE_MONITORING),
+ ipbus_out => ipb_from_slaves(N_SLV_RATE_MONITORING),
+ d => rate_monitoring_registers
+ );
+
--==============================--
channel_select: entity work.ipbus_dc_fabric_sel
--==============================--
@@ -182,13 +199,16 @@ begin
reset => control_registers(0)(N_LINKS + 1 - 1),
packet_start => packet_start,
links_in => masked_links,
+ trigger_threshold => to_integer(unsigned(control_registers(0)(N_LINKS + 5 - 1 downto N_LINKS + 1))),
--- Output Ports ---
links_out => links_out,
readout_reset => readout_reset,
--- Debug Ports ---
-- status_bits => link_aggregator_status_registers(3)(15 downto 0),
- non_empty_counts => mprocessor_monitoring_registers
+ non_empty_counts => mprocessor_monitoring_registers,
+ bx_valid_count_out => bx_valid_count
);
+ rate_monitoring_registers(0) <= bx_valid_count(0);
end Behavorial;
diff --git a/top/firmware/hdl/LinkAggregatorUncompressed.vhd b/common/firmware/hdl/LinkAggregatorUncompressed.vhd
similarity index 100%
rename from top/firmware/hdl/LinkAggregatorUncompressed.vhd
rename to common/firmware/hdl/LinkAggregatorUncompressed.vhd
diff --git a/top/firmware/hdl/LinkCombinerCore.vhd b/common/firmware/hdl/LinkCombinerCore.vhd
similarity index 100%
rename from top/firmware/hdl/LinkCombinerCore.vhd
rename to common/firmware/hdl/LinkCombinerCore.vhd
diff --git a/top/firmware/hdl/LinkCombinerIPBus.vhd b/common/firmware/hdl/LinkCombinerIPBus.vhd
similarity index 89%
rename from top/firmware/hdl/LinkCombinerIPBus.vhd
rename to common/firmware/hdl/LinkCombinerIPBus.vhd
index e551dd4996b14aa11800c93a01927d4b307ef2ef..18a08325379e68a329f95f0f85b175af2318052c 100644
--- a/top/firmware/hdl/LinkCombinerIPBus.vhd
+++ b/common/firmware/hdl/LinkCombinerIPBus.vhd
@@ -25,13 +25,16 @@ entity LinkCombinerIPBus is
packet_start : in std_logic;
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
lff : in std_logic;
+ output_srst : in std_logic := '0';
--- Ouput Ports ---
link_out : out lword := LWORD_NULL;
--- IPBus Ports ---
ipb_clk : in std_logic;
ipb_rst : in std_logic;
ipb_in : in ipb_wbus;
- ipb_out : out ipb_rbus
+ ipb_out : out ipb_rbus;
+ --- Debug Ports ---
+ super_id : out std_logic_vector(31 downto 0)
);
end LinkCombinerIPBus;
@@ -44,6 +47,7 @@ architecture Behavioral of LinkCombinerIPBus is
signal masked_input : ldata(8 - 1 downto 0) := (others => LWORD_NULL);
signal control_registers : ipb_reg_v(2 - 1 downto 0) := (others => (others => '0'));
+ signal output_reset : std_logic := '0';
begin
@@ -88,6 +92,7 @@ begin
begin
if rising_edge(clk_p) then
link_combiner_rd_en <= not lff and control_registers(0)(N_INPUT_LINKS + 2 - 1);
+ output_reset <= control_registers(0)(N_INPUT_LINKS + 1 - 1) or output_srst;
end if;
end process pReadEnable;
@@ -101,17 +106,17 @@ begin
--- Input Ports ---
clk_p => clk_p,
reset => reset,
- output_reset => control_registers(0)(N_INPUT_LINKS + 1 - 1),
+ output_reset => output_reset,
output_enable => link_combiner_rd_en,
links_in => masked_input,
packet_start => packet_start,
header_in => header_in,
header_user_bits => control_registers(1),
--- Output Ports ---
- link_out => link_out
+ link_out => link_out,
--- Debug Ports ---
-- debug => link_combiner_debug,
- -- debug_super_id => link_combiner_debug_super_id,
+ debug_super_id => super_id
-- debug_fifo => link_aggregator_status_registers(2)
);
diff --git a/top/firmware/hdl/MProcessor.vhd b/common/firmware/hdl/MProcessor.vhd
similarity index 91%
rename from top/firmware/hdl/MProcessor.vhd
rename to common/firmware/hdl/MProcessor.vhd
index f9b3a4d1c3973bb0648bf5e25f3512a039cbbbbd..27f7176539dd8bfff702ee0dea536fafdc2f0dd0 100644
--- a/top/firmware/hdl/MProcessor.vhd
+++ b/common/firmware/hdl/MProcessor.vhd
@@ -27,6 +27,7 @@ entity MProcessor is
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
header_start_array : in tHeaderStartArray := (others => (others => '0'));
gbe_backpressure : in std_logic := '0';
+ srst : in std_logic := '0';
--- Output Ports ---
link_out : out lword := LWORD_NULL;
--- IPBus Ports ---
@@ -48,9 +49,11 @@ architecture Behavorial of MProcessor is
signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL);
signal link_aggregator_input : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
- signal status_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal status_registers : ipb_reg_v(2 - 1 downto 0) := (others => (others => '0'));
signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
+ signal super_id : std_logic_vector(31 downto 0) := (others => '0');
+
begin
--==============================--
@@ -78,7 +81,7 @@ begin
--==============================--
generic map(
N_CTRL => 1,
- N_STAT => 1
+ N_STAT => 2
)
port map(
clk => ipb_clk,
@@ -124,13 +127,16 @@ begin
packet_start => packet_start,
header_in => header_in,
lff => gbe_backpressure,
+ output_srst => srst,
--- Output Ports ---
link_out => link_out,
--- IPBus Ports ---
ipb_clk => ipb_clk,
ipb_rst => ipb_rst,
ipb_in => ipb_to_slaves(N_SLV_LINK_COMBINER),
- ipb_out => ipb_from_slaves(N_SLV_LINK_COMBINER)
+ ipb_out => ipb_from_slaves(N_SLV_LINK_COMBINER),
+ --- Debug Ports ---
+ super_id => super_id
);
-- --==============================--
@@ -145,6 +151,7 @@ begin
link_aggregator_input(N_LINKS - 1 downto 0) <= links_in;
status_registers(0)(0) <= gbe_backpressure;
+ status_registers(1) <= super_id;
packet_start <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0);
end Behavorial;
diff --git a/top/firmware/hdl/TrackReconstructor.vhd b/common/firmware/hdl/TrackReconstructor.vhd
similarity index 100%
rename from top/firmware/hdl/TrackReconstructor.vhd
rename to common/firmware/hdl/TrackReconstructor.vhd
diff --git a/top/firmware/hdl/fixed_pkg_2008.vhd b/common/firmware/hdl/fixed_pkg_2008.vhd
similarity index 100%
rename from top/firmware/hdl/fixed_pkg_2008.vhd
rename to common/firmware/hdl/fixed_pkg_2008.vhd
diff --git a/common/firmware/hdl/mprocessor_constants.vhd b/common/firmware/hdl/mprocessor_constants.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..367eb0996372120aec21e2d4da72d9240ed3ce45
--- /dev/null
+++ b/common/firmware/hdl/mprocessor_constants.vhd
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.dtc_link_maps.all;
+
+package mprocessor_constants is
+
+ type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
+
+ function convertSLVtoHeaderStartArray (input_vector : in std_logic_vector(2*cNumberOfFEModules - 1 downto 0)) return tHeaderStartArray;
+
+end package mprocessor_constants;
+
+package body mprocessor_constants is
+
+ function convertSLVtoHeaderStartArray (input_vector : in std_logic_vector(2*cNumberOfFEModules - 1 downto 0)) return tHeaderStartArray is
+
+ variable output : tHeaderStartArray;
+
+ begin
+
+ for i in 0 to cNumberOfFEModules - 1 loop
+ output(i)(0) := input_vector(2*i);
+ output(i)(1) := input_vector(2*i + 1);
+ end loop;
+
+ return output;
+
+ end;
+
+end package body mprocessor_constants;
\ No newline at end of file
diff --git a/dependencies.yml b/dependencies.yml
index ce05070077fe7a8f2eb206a6deb74ae7877692f4..0cbe131cbe6e15a919fa141564d1e7e6163a8e5b 100644
--- a/dependencies.yml
+++ b/dependencies.yml
@@ -1,7 +1,7 @@
---
sources:
emp-fwk:
- tag: feature/daqpath_v2
+ branch: feature/lpgbtv1_merge_rebase
url: https://gitlab.cern.ch/p2-xware/firmware/emp-fwk.git
ttc_legacy:
@@ -31,9 +31,17 @@ sources:
tclink:
commit: fda0bcf
url: https://gitlab.cern.ch/HPTD/tclink.git
-
+
+ slink-ip:
+ tag: v03.12
+ url: https://gitlab.cern.ch/dth_p1-v2/slinkrocket_ips.git
+
+ slink:
+ tag: v03.12
+ url: https://gitlab.cern.ch/dth_p1-v2/slinkrocket.git
+
gbt-sc:
- tag: gbt_sc_4_1
+ tag: gbt_sc_4_3
url: https://gitlab.cern.ch/gbtsc-fpga-support/gbt-sc.git
dtc:
@@ -43,11 +51,15 @@ sources:
dtc-stub-processing:
branch: master
url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/dtc-stub-processing.git
+
+ dtc-monitoring:
+ branch: master
+ url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/dtc-monitoring.git
verilog-ethernet:
- tag: v1.0.0
+ branch: master
url: https://github.com/KristianHahn/verilog-ethernet.git
10gb-ethernet:
- tag: v2.0.0
+ branch: master
url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/10gb-ethernet.git
diff --git a/replacements/emp-fwk/boards/serenity/common/firmware/ucf/clock_constraints.tcl b/replacements/emp-fwk/boards/serenity/common/firmware/ucf/clock_constraints.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fa7a6a672b8b3297213d026dba8022401f3a6e98
--- /dev/null
+++ b/replacements/emp-fwk/boards/serenity/common/firmware/ucf/clock_constraints.tcl
@@ -0,0 +1,53 @@
+# 40 MHz external oscillator from Artix
+set lLegacyTtcClockPort [get_ports -quiet ttc_clk_p]
+if {[llength $lLegacyTtcClockPort] != 0} {
+ create_clock -name clk_40_extern_i0 -period 25.000 $lLegacyTtcClockPort
+}
+
+# 320 MHz TCDS2 clock
+set lTcdsClockPort [get_ports -quiet tcds_clk_p]
+if {[llength $lTcdsClockPort] != 0} {
+ create_clock -name tcds_clk -period 3.125 $lTcdsClockPort
+}
+
+# KH for slink
+if { [llength [get_cells slink_check.slink]] > 0 } {
+ set index [get_property ref_clock_index [get_cells slink_check.slink]]
+ puts "slink ==> refclk index : $index"
+ set reffreq [get_property ref_clock_freq [get_cells slink_check.slink]]
+ puts "slink ==> refclk freq : $reffreq"
+ set refprd [expr 1000/$reffreq]
+ puts "slink ==> refclk period : $refprd"
+}
+
+# DGM for eth10g
+if { [llength [get_cells eth10g_interface]] > 0 } {
+ set eth10g_index [get_property ref_clock_index [get_cells eth10g_interface]]
+ puts "eth10g ==> refclk index : $eth10g_index"
+ set eth10g_reffreq [get_property ref_clock_freq [get_cells eth10g_interface]]
+ puts "eth10g ==> refclk freq : $eth10g_reffreq"
+ set eth10g_refprd [expr 1000/$eth10g_reffreq]
+ puts "eth10g ==> refclk period : $eth10g_refprd"
+}
+
+# MGT refclks
+set lRefClkSize [llength [get_ports {refclkn[*]}]]
+for {set i 0} {$i < $lRefClkSize} {incr i} {
+ # KH modify for slink
+ if { [llength [get_cells slink_check.slink]] > 0 } {
+ if { $i == $index } {
+ create_clock -name refclk_$i -period $refprd [get_ports refclkn[$i]]
+ } else {
+ create_clock -name refclk_$i -period 3.125 [get_ports refclkn[$i]]
+ }
+ } elseif {[llength [get_cells eth10g_interface]] > 0} {
+ if { $i == $eth10g_index } {
+ # DGM commented out as hack - reason for timing issues when uncommented unclear
+ # create_clock -name refclk_$i -period $eth10g_refprd [get_ports refclkn[$i]]
+ } else {
+ create_clock -name refclk_$i -period 3.125 [get_ports refclkn[$i]]
+ }
+ } else {
+ create_clock -name refclk_$i -period 3.125 [get_ports refclkn[$i]]
+ }
+}
diff --git a/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/hdl/emp_device_decl_sm1_v1.vhd b/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/hdl/emp_device_decl_sm1_v1.vhd
deleted file mode 100644
index 9a9ce1692dc406628ef1f398fc710d00bfa831c0..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/hdl/emp_device_decl_sm1_v1.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
--- emp_device_decl
---
--- Defines constants for the whole device
---
--- Tom Williams, June 2018
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-use work.emp_framework_decl.all;
-
-
-package emp_device_decl is
-
- constant BOARD_DESIGN_ID : std_logic_vector(7 downto 0) := X"41";
-
- constant TCDS2_MGT_TYPE : io_gt_kind_t := io_gty;
- constant TCDS2_SPEED : io_tcds2_speed_t := io_tcds2_10g;
-
-
- constant N_REGION : integer := 18;
- constant N_REFCLK : integer := 14;
- constant CROSS_REGION : integer := 9;
-
- constant IO_REGION_SPEC : io_region_spec_array_t(0 to N_REGION - 1) := (
- 0 => (io_gth, 0, 7), -- Bank 225 -- Right column
- 1 => (io_gth, 0, 8), -- Bank 226
- 2 => (io_gth, 1, 8), -- Bank 227
- 3 => (io_gth, 1, 8), -- Bank 228
- 4 => (io_gth, 2, 9), -- Bank 229
- 5 => (io_gth, 2, 9), -- Bank 230
- 6 => (io_gth, 2, 9), -- Bank 231
- 7 => (io_gth, 3, 10), -- Bank 232
- 8 => (io_gth, 3, 10), -- Bank 233
- 9 => (io_gth, 3, 10), -- Bank 234
- -- Cross-chip
- -- 10 => (io_gty, 4, 11), -- Bank 134 -- Left column
- -- 11 => (io_gty, 4, 11), -- Bank 133
- -- 12 => (io_gty, 4, 11), -- Bank 132
- 13 => (io_gty, 5, 12), -- Bank 131
- 14 => (io_gty, 5, 12), -- Bank 130
- 15 => (io_gty, 5, 12), -- Bank 129
- 16 => kIONoGTRegion, -- Bank 128 (TCDS2 via QSFP)
- 17 => (io_gty, 6, 13), -- Bank 127
- others => kIONoGTRegion
- );
-
-end emp_device_decl;
diff --git a/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/area_constraints.tcl b/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/area_constraints.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f389dfcdad41391a8979b1ba1001726c694c1c91
--- /dev/null
+++ b/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/area_constraints.tcl
@@ -0,0 +1,105 @@
+delete_pblocks -quiet infra ttc clocks payload quad_*
+#-------------------------------------
+
+#KH comment for slink w/o datapath
+#-------------------------------------
+#Infra, ttc, ctrl blocks creation skipped due to the peculiar shape of the DIE.
+#To be revisited later in view of specific ku15p applications.
+#-------------------------------------
+#
+# Constrain infra to the lowest row of clock regions, plus X5Y1 that contains the PCIe MGTs
+# create_pblock infra
+# resize_pblock [get_pblocks infra] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y1}
+# add_cells_to_pblock [get_pblocks infra] [get_cells -quiet [list infra info ctrl]]
+
+# # Constrain TTC to a sub-area of infra
+# create_pblock ttc -parent [get_pblocks infra]
+# resize_pblock [get_pblocks ttc] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y0}
+# add_cells_to_pblock [get_pblocks ttc] [get_cells -quiet ttc]
+
+
+# Except for the clocks, that require a 3 row vertical slice to accommodate 3 MMCMs and the corresponding BUFGs.
+# create_pblock clocks
+# resize_pblock [get_pblocks clocks] -add {CLOCKREGION_X4Y0:CLOCKREGION_X4Y3}
+# add_cells_to_pblock [get_pblocks clocks] [get_cells infra/usp_clocks/*]
+# add_cells_to_pblock [get_pblocks clocks] [get_cells ttc/osc_clock/*]
+# add_cells_to_pblock [get_pblocks clocks] [get_cells ttc/clocks/*]
+
+
+# # TTC MMC assignment
+# # TODO - check the code below
+# create_pblock mmcm_ttc
+# resize_pblock [get_pblocks mmcm_ttc] -add CLOCKREGION_X5Y9
+
+# add_cells_to_pblock [get_pblocks mmcm_ttc] [get_cells ttc/clocks/mmcm]
+# set bufgs { bufg_40 bufg_p bufr_40s cgen\[0\].bufg_aux cgen\[1\].bufg_aux cgen\[2\].bufg_aux }
+# foreach lRegId $bufgs {
+# add_cells_to_pblock [get_pblocks mmcm_ttc] [get_cells -quiet ttc/clocks/${i} ]
+# }
+# # -------------------
+#-------------------------------------
+
+# Parameters
+set lLeftQuadWidth 1330
+set lRightQuadWidth 520
+
+set lClkBounds [get_XY_bounds [get_clock_regions]]
+puts "Clock region boundaries ${lClkBounds}"
+set lRPMBounds [get_fpga_rpm_bounds]
+puts "FPGA boundaries (RPM coords) $lRPMBounds"
+
+lassign [create_quad_pblocks $lLeftQuadWidth $lRightQuadWidth] lNumQuads lLeftBoundary lRightBoundary
+
+# Create the quad p-blocks and store the number of blocks created
+puts "Created $lNumQuads quads"
+
+# Right MGT column, right quads 1 to 10
+for {set lRegId 0} {$lRegId < 10} {incr lRegId} {
+ set q [expr 1 + $lRegId]
+ set lQuadBlock [get_pblocks quad_R$q]
+ puts "Populating $lQuadBlock with region $lRegId"
+
+ add_cells_to_pblock $lQuadBlock datapath/rgen\[$lRegId\].region
+ remove_cells_from_pblock -quiet $lQuadBlock datapath/rgen\[$lRegId\].region/mgt_gen.fe_mgt_gen.fe_mgt_inst
+ constrain_mgts $lRegId $lQuadBlock 1
+}
+
+# Left MGT column, left quads 10 to 3
+for {set lRegId 10} {$lRegId < 18} {incr lRegId} {
+ set q [expr 20 - $lRegId]
+ set lQuadBlock [get_pblocks quad_L$q]
+ puts "Populating $lQuadBlock with region $lRegId"
+
+ add_cells_to_pblock $lQuadBlock datapath/rgen\[$lRegId\].region
+ remove_cells_from_pblock -quiet $lQuadBlock datapath/rgen\[$lRegId\].region/mgt_gen.fe_mgt_gen.fe_mgt_inst
+ constrain_mgts $lRegId $lQuadBlock 0
+}
+
+
+# now the slinks
+set lQuadNumberingOffset 1
+constrain_slinks $lQuadNumberingOffset
+# now the eth10g
+constrain_eth10g $lQuadNumberingOffset
+
+# Payload Area assignment
+set lPayload [create_pblock payload]
+set lPayloadRect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>2}] -f "RPM_X >= $lLeftBoundary && RPM_X <= $lRightBoundary"]]
+add_rects_to_pblock $lPayload $lPayloadRect
+
+
+add_cells_to_pblock [get_pblocks payload] [get_cells -quiet datapath/rgen[*].pgen.*]
+
+
+
+# Add more sites to quad_L10 to alleviate bus skew problems
+# (temporary workaround - permananent solution to follow with Hermes v2)
+resize_pblock -remove SLICE_X25Y180:SLICE_X26Y659 [get_pblocks payload]
+resize_pblock -add SLICE_X25Y600:SLICE_X26Y659 [get_pblocks quad_L10]
+resize_pblock -add SLICE_X25Y540:SLICE_X26Y599 [get_pblocks quad_L9]
+resize_pblock -add SLICE_X25Y480:SLICE_X26Y539 [get_pblocks quad_L8]
+resize_pblock -add SLICE_X25Y420:SLICE_X26Y479 [get_pblocks quad_L7]
+resize_pblock -add SLICE_X25Y360:SLICE_X26Y419 [get_pblocks quad_L6]
+resize_pblock -add SLICE_X25Y300:SLICE_X26Y359 [get_pblocks quad_L5]
+resize_pblock -add SLICE_X25Y240:SLICE_X26Y299 [get_pblocks quad_L4]
+resize_pblock -add SLICE_X25Y180:SLICE_X26Y239 [get_pblocks quad_L3]
diff --git a/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/pins_sm1_common.tcl b/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/pins_sm1_common.tcl
deleted file mode 100644
index 1d3596e953e910fe7674392b01fd111e71881467..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/boards/serenity/dc_ku15p/firmware/ucf/pins_sm1_common.tcl
+++ /dev/null
@@ -1,65 +0,0 @@
-
-# EXTERNAL OSCILLATOR
-set_property IOSTANDARD LVCMOS18 [get_ports clk125]
-set_property PACKAGE_PIN AP29 [get_ports clk125]
-
-# KH comment for tcds only version ...
-# LEGACY TTC - DATA
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports ttc_rx_n]
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports ttc_rx_p]
-set_property PACKAGE_PIN AY10 [get_ports ttc_rx_n]
-set_property PACKAGE_PIN AY11 [get_ports ttc_rx_p]
-
-
-# TCDS2 INTERFACE
-# Bank 128, channel 2, refclk0
-set_property PACKAGE_PIN AD32 [get_ports tcds_clk_p]
-# set_property PACKAGE_PIN AK41 [get_ports tcds_rx_p]
-set_property PACKAGE_PIN AG34 [get_ports tcds_tx_p]
-
-set_property LOC GTYE4_COMMON_X0Y1 [get_cells ttc/gen_master_tcds2.tcds2/mgt/if_usp_gty.if_10g.mgt/inst/gen_gtwizard_gtye4_top.gtye4_slave_timing_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[1].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST]
-set_property LOC GTYE4_CHANNEL_X0Y6 [get_cells ttc/gen_master_tcds2.tcds2/mgt/if_usp_gty.if_10g.mgt/inst/gen_gtwizard_gtye4_top.gtye4_slave_timing_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST]
-
-
-# HEARTBEAT LED
-set_property IOSTANDARD LVCMOS18 [get_ports heartbeat_led]
-set_property PACKAGE_PIN AM23 [get_ports heartbeat_led]
-
-
-# MGT REF CLOCKS - ASYNC
-# Bank 225 refclk0 (interposer: MGT_CLK_09)
-set_property PACKAGE_PIN AJ12 [get_ports {refclkp[0]}]
-# Bank 227 refclk1 (interposer: MGT_CLK_11)
-set_property PACKAGE_PIN AD10 [get_ports {refclkp[1]}]
-# Bank 230 refclk1 (interposer: MGT_CLK_13)
-set_property PACKAGE_PIN V10 [get_ports {refclkp[2]}]
-# Bank 233 refclk1 (interposer: MGT_CLK_15)
-set_property PACKAGE_PIN M10 [get_ports {refclkp[3]}]
-# KH using for 10g eth ...
-# Bank 133 refclk1 (interposer: MGT_CLK_01)
-#set_property PACKAGE_PIN N30 [get_ports {refclkp[4]}]
-# Bank 130 refclk1 (interposer: MGT_CLK_03)
-set_property PACKAGE_PIN W30 [get_ports {refclkp[5]}]
-# # Bank 128 refclk1 (interposer: MGT_CLK_05) -- Now used for TCDS2 (via QSFP)
-# set_property PACKAGE_PIN AC30 [get_ports {refclkp[6]}]
-# BAnk 127 refclk1 (interposer: MGT_CLK_07)
-set_property PACKAGE_PIN AE30 [get_ports {refclkp[6]}]
-
-
-# MGT REF CLOCKS - SYNC
-# Bank 224 refclk1 (interposer: MGT_CLK_08)
-set_property PACKAGE_PIN AK10 [get_ports {refclkp[7]}]
-# Bank 227 refclk0 (interposer: MGT_CLK_10)
-set_property PACKAGE_PIN AE12 [get_ports {refclkp[8]}]
-# Bank 230 refclk0 (interposer: MGT_CLK_12)
-set_property PACKAGE_PIN W12 [get_ports {refclkp[9]}]
-# Bank 233 refclk0 (interposer: MGT_CLK_14)
-set_property PACKAGE_PIN N12 [get_ports {refclkp[10]}]
-# Bank 133 refclk0 (interposer: MGT_CLK_00)
-set_property PACKAGE_PIN P32 [get_ports {refclkp[11]}]
-# Bank 130 refclk0 (interposer: MGT_CLK_02)
-set_property PACKAGE_PIN Y32 [get_ports {refclkp[12]}]
-# # Bank 128 refclk0 (interposer: MGT_CLK_04) -- Quad now used for TCDS2 (via QSFP)
-# set_property PACKAGE_PIN AD32 [get_ports {refclkp[13]}]
-# Bank 127 refclk0 (interposer: MGT_CLK_06)
-set_property PACKAGE_PIN AG30 [get_ports {refclkp[13]}]
diff --git a/replacements/emp-fwk/components/payload/firmware/ucf/emp_simple_payload.tcl b/replacements/emp-fwk/components/payload/firmware/ucf/emp_simple_payload.tcl
deleted file mode 100644
index d2bb3a4f4f797d7c4d498c46840f93d2511a5239..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/payload/firmware/ucf/emp_simple_payload.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Area constraints for MP7 null algo
-#KH cms sep24
-#add_cells_to_pblock [get_pblock payload] payload
diff --git a/replacements/emp-fwk/components/top/addr_table/top_emp.xml b/replacements/emp-fwk/components/top/addr_table/top_emp.xml
index 1dbfd363469346dc91c8246cdb91dd03529efd01..901c6ddd02c71b9f3c1ec717e64fa18a47e05684 100644
--- a/replacements/emp-fwk/components/top/addr_table/top_emp.xml
+++ b/replacements/emp-fwk/components/top/addr_table/top_emp.xml
@@ -4,6 +4,6 @@
<node id="ttc" module="file://emp_ttc.xml" address="0x400"/>
<node id="datapath" module="file://emp_datapath.xml" address="0x2000"/>
<node id="eth10g" module="file://emp_eth10g_interface.xml" address="0x4000"/>
- <node id="freq" module="file://ipbus_freq_ctr.xml" address="0x40000000"/>
+ <node id="slink" module="file://emp_slink.xml" address="0x1000000" />
<node id="payload" module="file://emp_payload.xml" address="0x80000000" fwinfo="endpoint;width=31"/>
</node>
diff --git a/replacements/emp-fwk/components/top/firmware/hdl/emp_top_pcie_both_ttc.vhd b/replacements/emp-fwk/components/top/firmware/hdl/emp_top_pcie_both_ttc.vhd
index 092073ff1e78995b1e4b4baf347c743a645b25ef..2ac77db506624757e959ec1c66b214630cca78cd 100644
--- a/replacements/emp-fwk/components/top/firmware/hdl/emp_top_pcie_both_ttc.vhd
+++ b/replacements/emp-fwk/components/top/firmware/hdl/emp_top_pcie_both_ttc.vhd
@@ -17,6 +17,11 @@ use work.ipbus_decode_top_emp.all;
use work.emp_device_decl.all;
use work.emp_slim_top_decl;
+use work.emp_slink_types.all;
+use work.emp_slink_core_config_decl.all;
+use work.emp_project_decl.all; -- for SLINK_CONF
+use work.emp_eth10g_types.all;
+
library UNISIM;
use UNISIM.VComponents.all;
@@ -56,13 +61,6 @@ entity top is
tcds_rx_n : in std_logic;
tcds_tx_p : out std_logic;
tcds_tx_n : out std_logic;
- -- 10g eth signals
- gbe_rx_p : in std_logic_vector(1 downto 0);
- gbe_rx_n : in std_logic_vector(1 downto 0);
- gbe_tx_p : out std_logic_vector(1 downto 0);
- gbe_tx_n : out std_logic_vector(1 downto 0);
- gbe_mgt_refclk_p : in std_logic;
- gbe_mgt_refclk_n : in std_logic;
-- Transceiver ref-clocks
refclkp : in std_logic_vector(N_REFCLK - 1 downto 0);
refclkn : in std_logic_vector(N_REFCLK - 1 downto 0);
@@ -97,10 +95,10 @@ architecture rtl of top is
signal rsts_aux : std_logic_vector(2 downto 0);
-- TTC signals
- signal ttc_l1a, ttc_l1a_dist, dist_lock, oc_flag, ec_flag, ttc_l1a_throttle : std_logic;
- signal ttc_cmd, ttc_cmd_dist : ttc_cmd_t;
- signal bunch_ctr : bctr_t;
- signal orb_ctr : eoctr_t;
+ signal ttc_l1a, ttc_l1a_dist, dist_lock, oc_flag, ec_flag, ttc_l1a_throttle : std_logic;
+ signal ttc_cmd, ttc_cmd_dist : ttc_cmd_t;
+ signal bunch_ctr : bctr_t;
+ signal orb_ctr : eoctr_t;
-- Others
signal nuke, soft_rst : std_logic;
@@ -113,27 +111,26 @@ architecture rtl of top is
signal ctrs : ttc_stuff_array(N_REGION - 1 downto 0);
signal rst_loc, clken_loc : std_logic_vector(N_REGION - 1 downto 0);
- signal clk125_s : std_logic;
+ signal clk125_s : std_logic;
+
+ -- Slink
+ signal slink_payload_data : slink_input_data_quad_array(SLINK_MAX_QUADS-1 downto 0);
+ signal slink_backpressure : std_logic_vector(SLINK_MAX_QUADS-1 downto 0) := (others => '0');
- -- 10g
- signal gbe_ldata : ldata(1 downto 0);
- signal gbe_lff : std_logic_vector(1 downto 0);
-
- -- KH tmp
- signal clk_40_div, clk_p_div : std_logic;
+ --10g
+ signal gbe_ldata : ldata(ETH10G_MAX_QUADS*ETH10G_MAX_CHANNELS - 1 downto 0) := (others => LWORD_NULL);
+ signal gbe_backpressure : std_logic_vector(ETH10G_MAX_QUADS*ETH10G_MAX_CHANNELS - 1 downto 0) := (others => '0');
begin
-- Infrastructure
- pcie_rst_passthrough : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '0' generate
- pcie_sys_rst_n <= pcie_sys_rst;
- end generate;
-
- pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate
- pcie_sys_rst_n <= not pcie_sys_rst;
- end generate;
+pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate
+pcie_sys_rst_n <= not pcie_sys_rst;
+else generate -- pcie_rst_invert
+pcie_sys_rst_n <= pcie_sys_rst;
+end generate pcie_rst_invert;
infra : entity work.emp_infra_pcie
port map(
@@ -250,7 +247,6 @@ begin
rst => ipb_rst,
ipb_in => ipb_w_array(N_SLV_DATAPATH),
ipb_out => ipb_r_array(N_SLV_DATAPATH),
- board_id => (others => '0'),
clk125 => clk125_s,
clk40 => clk40,
clk_p => clk_p,
@@ -269,91 +265,84 @@ begin
);
-- And finally, the payload
- -- KH ILA_DEBUG for payload defaults to false ...
- -- if desired set generic here and enable include the xci
- -- in the eth dep
payload : entity work.emp_payload
port map(
- clk => ipb_clk,
- rst => ipb_rst,
- ipb_in => ipb_w_array(N_SLV_PAYLOAD),
- ipb_out => ipb_r_array(N_SLV_PAYLOAD),
- clk40 => clk40,
- clk_payload => clks_aux,
- rst_payload => rsts_aux,
- clk_p => clk_p,
- rst_loc => rst_loc,
- clken_loc => clken_loc,
- ctrs => ctrs,
- bc0 => open,
- d => payload_d,
- q => payload_q,
- gpio => open,
- gpio_en => open,
+ clk => ipb_clk,
+ rst => ipb_rst,
+ ipb_in => ipb_w_array(N_SLV_PAYLOAD),
+ ipb_out => ipb_r_array(N_SLV_PAYLOAD),
+ clk40 => clk40,
+ clk_payload => clks_aux,
+ rst_payload => rsts_aux,
+ clk_p => clk_p,
+ rst_loc => rst_loc,
+ clken_loc => clken_loc,
+ ttc_cmd => ttc_cmd_dist,
+ ctrs => ctrs,
+ bc0 => open,
+ d => payload_d,
+ q => payload_q,
+ gpio => open,
+ gpio_en => open,
+ slink_q => slink_payload_data,
+ backpressure => slink_backpressure,
-- 10g
gbe_q => gbe_ldata,
- gbe_backpressure => gbe_lff
- );
+ gbe_backpressure => gbe_backpressure
+
+ );
+
+ slink_check : if slink_quads_enabled(SLINK_CONF) > 0 generate
+ slink : entity work.emp_slink_interface
+ generic map (
+ throughput => SLINK_THROUGHPUT,
+ technology => SLINK_XCVR_TYPE,
+ ref_clock_freq => SLINK_REFCLK_FREQ,
+ ref_clock_index => IO_REGION_SPEC(SLINK_CONF(0).region).io_async_refclk
+ )
+ port map (
+ ipb_clk => ipb_clk,
+ ipb_rst => ipb_rst,
+ ipb_in => ipb_w_array(N_SLV_SLINK),
+ ipb_out => ipb_r_array(N_SLV_SLINK),
+
+ clk_40 => clk40ish,
+ clk_p => clk_p,
+
+ slink_d => slink_payload_data,
+ backpressure => slink_backpressure,
+
+ refclkp => refclkp,
+ refclkn => refclkn
+ );
+ end generate;
--
-- 10g
--
- eth10g : entity work.emp_eth10g_interface
- generic map ( ETH10G_CHANNELS => 2 )
+ eth10g_interface : entity work.emp_eth10g_interface
+ generic map (
+ ref_clock_index => 4
+ )
port map (
- clk_ipb => ipb_clk,
- rst_ipb => ipb_rst,
- ipb_in => ipb_w_array(N_SLV_ETH10G),
- ipb_out => ipb_r_array(N_SLV_ETH10G),
- --
+ --- Input Ports ---
clk_p => clk_p,
rst_p => rst_p,
- clk125 => clk125,
- -- Input from payload
+ clk125 => clk125,
+ refclkp => refclkp,
+ refclkn => refclkn,
ldata_in => gbe_ldata,
- -- backpressure to payload
- lff => gbe_lff,
- --10g
- gbe_rx_p => gbe_rx_p,
- gbe_rx_n => gbe_rx_n,
- gbe_tx_p => gbe_tx_p,
- gbe_tx_n => gbe_tx_n,
- gbe_mgt_refclk_p => gbe_mgt_refclk_p,
- gbe_mgt_refclk_n => gbe_mgt_refclk_n
- );
-
-
-
-
--- KH tmp to check clk_p
- div : entity work.freq_ctr_div
- generic map(
- N_CLK => 2
- )
- port map(
- clk(0) => clk_p,
- clk(1) => clk40,
- clkdiv(0) => clk_p_div,
- clkdiv(1) => clk_40_div
- );
-
--- Clock frequency monitor
-
- ctr : entity work.ipbus_freq_ctr
- generic map(
- N_CLK => 2
- )
- port map(
- clk => ipb_clk,
- rst => ipb_rst,
- ipb_in => ipb_w_array(N_SLV_FREQ),
- ipb_out => ipb_r_array(N_SLV_FREQ),
- clkdiv(0) => clk_p_div,
- clkdiv(1) => clk_40_div
- );
-
-
+ --- Output Ports ---
+ backpressure => gbe_backpressure,
+ --- IPBus Ports ---
+ ipb_clk => ipb_clk,
+ ipb_rst => ipb_rst,
+ ipb_in => ipb_w_array(N_SLV_ETH10G),
+ ipb_out => ipb_r_array(N_SLV_ETH10G)
+ --- Pin Ports ---
+ -- gbe_mgt_refclk_p => gbe_mgt_refclk_p,
+ -- gbe_mgt_refclk_n => gbe_mgt_refclk_n
+ );
end rtl;
-
diff --git a/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl b/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl
deleted file mode 100644
index fb9fdc0fe2a22ed881a0b2d5809858c7e6df4a02..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_common.tcl
+++ /dev/null
@@ -1,52 +0,0 @@
-# 40MHz & payload I/O clocks derived from board-local source (for tests without external clock source)
-create_generated_clock -name clk_40_pseudo_i [get_pins ttc/bufgce_clk_40_rx/O]
-create_generated_clock -name clk_40_pseudo -source [get_pins ttc/clocks/mmcm/CLKIN2] [get_pins ttc/clocks/mmcm/CLKOUT1]
-create_generated_clock -name clk_payload_pseudo -source [get_pins ttc/clocks/mmcm/CLKIN2] [get_pins ttc/clocks/mmcm/CLKOUT3]
-
-# Names of the LHC-synchronised derived clocks that are used by payload and infra (outside of TTC block)
-lappend lMainInternalClocks clk_40_pseudo clk_payload_pseudo
-
-
-if {[llength [get_pins -quiet ttc/gen_master_legacy.osc_clock/mmcm/CLKOUT1]] != 0} {
- create_generated_clock -name clk_40_extern_i0 [get_pins ttc/gen_master_legacy.osc_clock/gen_mmcm/mmcm/CLKOUT1]
-}
-
-if {[llength [get_pins -quiet ttc/gen_master_tcds2.tcds2/tcds2_interface/bufgce_clk_40_rx/O]] != 0} {
- create_generated_clock -name clk_40_extern_i1 [get_pins ttc/gen_master_tcds2.tcds2/tcds2_interface/bufgce_clk_40_rx/O]
-}
-
-foreach i [list 0 1] {
- if {[llength [get_clocks -quiet clk_40_extern_i$i]] != 0 } {
- create_generated_clock -name clk_40_extern$i -master_clock [get_clocks clk_40_extern_i$i] [get_pins ttc/clocks/mmcm/CLKOUT1]
- # Payload I/O clock derived from external oscillator
- create_generated_clock -name clk_payload_extern$i -master_clock [get_clocks clk_40_extern_i$i] [get_pins ttc/clocks/mmcm/CLKOUT3]
-
- lappend lMainInternalClocks clk_40_extern_i$i clk_40_extern$i clk_payload_extern$i
- }
-}
-
-
-# Clock groups: Asynchronous
-puts "lMainInternalClocks = $lMainInternalClocks"
-set_clock_groups -asynch -group [get_clocks axi_clk] -group [get_clocks -include_generated_clocks ipbus_clk]
-set_clock_groups -asynch -group [get_clocks -include_generated_clocks ipbus_clk] -group $lMainInternalClocks
-
-# Clock groups: Logically exclusive
-# The 40MHz, 160MHz and payload clocks used across the chip are generated by an MMCM with two clock sources:
-# * an externally-provided LHC clock (typically from TCDS), which itself could come from one of two interfaces (clk_40_externN); and
-# * an internally-generated 'pseudo-LHC' clock (clk_40_pseudo)
-# Must set the copies of the clocks generated from those sources as logically exclusive
-foreach lMasterA [list clk_40_pseudo_i clk_40_pseudo_i clk_40_extern_i0] lMasterB [list clk_40_extern_i0 clk_40_extern_i1 clk_40_extern_i1] {
- if {[llength [get_clocks -quiet [list $lMasterA $lMasterB]]] == 2} {
- puts "Declaring clocks derived from $lMasterA and $lMasterB as logically exclusive"
- set_clock_groups -logically_exclusive -group [get_clocks -filter "MASTER_CLOCK == $lMasterA"] -group [get_clocks -filter "MASTER_CLOCK == $lMasterB"]
- }
-}
-
-
-# Remove timing constraints for heartbeat LED output port
-set_false_path -to [get_ports -regexp "(.+_led|led_.+)"]
-
-# Print clock report for the record (in case build fails, or need to debug clock-related issues)
-report_clocks
-
diff --git a/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_tcds2.tcl b/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_tcds2.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..606c6caf8b35ccc2b6da32e9c7fc317d2310a392
--- /dev/null
+++ b/replacements/emp-fwk/components/top/firmware/ucf/clock_constraints_tcds2.tcl
@@ -0,0 +1,12 @@
+
+# Define 125MHz clock, and declare as async to other clocks
+#Â Note: In some designs 125MHz clock is top-level port (e.g. Serenity DC),
+# otherwise its a derived clock from the infra block (e.g. Apollo)
+if {[llength [get_ports -quiet clk125]] != 0} {
+ create_clock -period 8.000 -name sys_clk125 [get_ports clk125]
+}
+set_clock_groups -asynch -group [get_clocks -include_generated_clocks sys_clk125]
+
+# Paths from TCDS core to EMP TTC logic: Only perform timing analysis when clk40 in EMP logic comes from TCDS core
+# Commented out as it throws error in Vivado 2022
+# set_false_path -through [get_nets {ttc/*tcds2_interface_stat[channel0_ttc2]*}] -to [get_clocks {clk_40_extern0 clk_40_pseudo}]
diff --git a/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl b/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl
deleted file mode 100644
index e49c9d01bf70044ca92097b07f2b08af5d7cfb57..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/top/firmware/ucf/clock_declarations_pcie.tcl
+++ /dev/null
@@ -1,12 +0,0 @@
-
-# 100 Mhz PCIe system clock
-create_clock -period 10.000 -name pcie_sys_clk [get_ports pcie_sys_clk_p]
-
-# IPbus clock
-create_generated_clock -name ipbus_clk -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT1]
-
-# AXI clock
-create_generated_clock -name axi_clk [get_pins -hierarchical -filter {NAME =~infra/dma/xdma/*/phy_clk_i/bufg_gt_userclk/O}]
-
-# Approx 40MHz clock derived from AXI clock (for tests without external clock source)
-#create_generated_clock -name clk_40_pseudo_i [get_pins infra/clocks/mmcm/CLKOUT2]
diff --git a/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd b/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd
deleted file mode 100644
index bf1c409c13f1737afb61e6a7174fac6e8e9c0552..0000000000000000000000000000000000000000
--- a/replacements/emp-fwk/components/ttc/firmware/hdl/emp_ttc.vhd
+++ /dev/null
@@ -1,589 +0,0 @@
--- ttc
---
--- TTC decoder, counters, LHC clock distribution, etc
---
--- Dave Newbold, June 2013
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.VComponents.all;
-
-use work.ipbus.all;
-use work.ipbus_reg_types.all;
-use work.ipbus_decode_emp_ttc.all;
-use work.emp_ttc_decl.all;
-use work.emp_ttc_utils;
-
-use work.emp_device_decl;
-use work.emp_project_decl.all;
-
-use work.tcds2_interface_pkg;
-use work.tcds2_streams_pkg;
-
-
--------------------------------------------------------------------------------
-entity emp_ttc is
- generic(
- ENABLE_LEGACY_TTC : boolean;
- ENABLE_TCDS2 : boolean;
- EXT_CLK_FREQ : real
- );
- port(
- -- ipbus clock & rst
- clk_ipb : in std_logic;
- rst_ipb : in std_logic;
- -- IPBus
- ipb_in : in ipb_wbus;
- ipb_out : out ipb_rbus;
- -- 125MHz clock
- clk125 : in std_logic;
- -- internal pseudo-40MHz clock
- clk40ish_in : in std_logic;
- -- clock outputs
- clk40 : out std_logic;
- -- clock domain reset outputs
- rst40 : out std_logic;
- clk_p : out std_logic;
- rst_p : out std_logic;
- clks_aux : out std_logic_vector(2 downto 0);
- rsts_aux : out std_logic_vector(2 downto 0);
- -- Legacy TTC interface
- ttc_clk_p : in std_logic;
- ttc_clk_n : in std_logic;
- ttc_rx_p : in std_logic;
- ttc_rx_n : in std_logic;
- -- TCDS2 interface
- tcds_clk_p : in std_logic;
- tcds_clk_n : in std_logic;
- tcds_rx_p : in std_logic;
- tcds_rx_n : in std_logic;
- tcds_tx_p : out std_logic;
- tcds_tx_n : out std_logic;
- -- TTC b command output
- ttc_cmd : out ttc_cmd_t;
- ttc_cmd_dist : out ttc_cmd_t;
- -- L1A output
- ttc_l1a : out std_logic;
- -- L1A qualifier output
- ttc_l1a_dist : out std_logic;
- dist_lock : in std_logic;
- bunch_ctr : out bctr_t;
- evt_ctr : in eoctr_t;
- orb_ctr : out eoctr_t;
- oc_flag : out std_logic;
- ec_flag : out std_logic;
- -- clock monitoring inputs from MGTs
- monclk : in std_logic_vector(3 downto 0);
- clk125_o : out std_logic
- );
-
-end emp_ttc;
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
-architecture rtl of emp_ttc is
-
- signal clk40_ext, clk40_ext_legacy, clk40_ext_tcds2 : std_logic;
- signal tcds_refclk_b, tcds_refclk_div : std_logic;
- signal clk40_i, rst40_i, clk160s, clk40_div, rsti, rsti_40, clk40_a, rst40_a, clk_p_i, rst_p_i : std_logic;
- signal lock, stop : std_logic;
- signal clks_aux_i, rsts_aux_i : std_logic_vector(2 downto 0);
- signal l1a_ext_legacy, l1a_ext_tcds2 : std_logic;
- signal l1a, l1a_ttc, l1a_del, l1a_ext, l1a_pend, cmd_bx, cmd_pend, l1a_issue, cmd_issue : std_logic;
- signal cmd, cmd_ttc, cmd_del, cmd_ext_tcds2, cmd_ext_legacy : ttc_cmd_t;
- signal psok, bc0_fr, ctr_clr : std_logic;
- signal bunch_ctr_i : bctr_t;
- signal req_bx : unsigned(bctr_t'range);
- signal orb_ctr_i : eoctr_t;
- signal clk40_mmcm_sel : std_logic;
-
- signal stat_clk40 : ipb_reg_v(0 downto 0);
- signal ctrl_clk40 : ipb_reg_v(0 downto 0);
-
- signal stat_common : ipb_reg_v(2 downto 0);
- signal ctrl_common : ipb_reg_v(0 downto 0);
- signal stb_common : std_logic_vector(0 downto 0);
-
- signal bc0_lock : std_logic;
- signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0);
- signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0);
-
- signal clk_40_to_mmcm : std_logic;
-
-begin
-
-
-
--- ipbus address decode
-
- fabric : entity work.ipbus_fabric_sel
- generic map(
- NSLV => N_SLAVES,
- SEL_WIDTH => IPBUS_SEL_WIDTH)
- port map(
- ipb_in => ipb_in,
- ipb_out => ipb_out,
- sel => ipbus_sel_emp_ttc(ipb_in.ipb_addr),
- ipb_to_slaves => ipbw,
- ipb_from_slaves => ipbr
- );
-
--- TTC control registers
-
- reg_clk40 : entity work.ipbus_ctrlreg_v
- generic map (
- N_CTRL => 1,
- N_STAT => 1
- )
- port map (
- clk => clk_ipb,
- reset => rst_ipb,
- ipbus_in => ipbw(N_SLV_CLK40),
- ipbus_out => ipbr(N_SLV_CLK40),
- d => stat_clk40,
- q => ctrl_clk40,
- stb => open
- );
-
- stat_clk40(0)(0) <= lock;
- stat_clk40(0)(1) <= stop;
-
- reg_common : entity work.ipbus_syncreg_v
- generic map(
- N_CTRL => 1,
- N_STAT => 3
- )
- port map(
- clk => clk_ipb,
- rst => rst_ipb,
- ipb_in => ipbw(N_SLV_MASTER_COMMON),
- ipb_out => ipbr(N_SLV_MASTER_COMMON),
- slv_clk => clk40_a,
- d => stat_common,
- q => ctrl_common,
- stb => stb_common
- );
-
- stat_common(0)(0) <= '1' when ENABLE_LEGACY_TTC else '0';
- stat_common(0)(1) <= '1' when ENABLE_TCDS2 else '0';
-
-
- -- Mux for external clocks
- gen_ext_mux : if ENABLE_TCDS2 and ENABLE_LEGACY_TTC generate
-
- signal sel_pipeline : std_logic_vector(3 downto 0);
-
- begin
-
- process (clk_ipb)
- begin
- if rising_edge(clk_ipb) then
- sel_pipeline(0) <= ctrl_clk40(0)(2);
- sel_pipeline(1) <= sel_pipeline(0);
- sel_pipeline(2) <= sel_pipeline(1);
- sel_pipeline(3) <= sel_pipeline(2);
- end if;
- end process;
-
- clk40mux : BUFGMUX
- port map (
- S => sel_pipeline(3),
- I0 => clk40_ext_legacy,
- I1 => clk40_ext_tcds2,
- O => clk40_ext
- );
-
- elsif ENABLE_TCDS2 generate
-
- clk40_ext <= clk40_ext_tcds2;
-
- else generate
-
- clk40_ext <= clk40_ext_legacy;
-
- end generate;
-
-
--- MMCM for clock multiplication / phase adjustment
-
- rsti <= rst_ipb or ctrl_common(0)(2);
- clk40_mmcm_sel <= ctrl_clk40(0)(1) or ctrl_clk40(0)(2);
-
- bufgce_clk_40_rx : bufgce_div
- generic map (
- BUFGCE_DIVIDE => 8
- )
- port map (
- i => tcds_refclk_b,
- o => clk_40_to_mmcm,
- ce => '1',
- clr => '0'
- );
-
- clocks : entity work.emp_ttc_clocks
- port map(
- clk_40 => clk40_ext,
- clk_40pseudo => clk_40_to_mmcm,
- clko_40 => clk40_i,
- clko_p => clk_p_i,
- clko_aux => clks_aux_i,
- rsto_40 => rst40_i,
- rsto_p => rst_p_i,
- rsto_aux => rsts_aux_i,
- clko_160s => clk160s,
- stopped => stop,
- locked => lock,
- rst_mmcm => ctrl_clk40(0)(0),
- rsti => rsti_40,
- clksel => clk40_mmcm_sel,
- psval => ctrl_common(0)(23 downto 12),
- psok => psok,
- psen => ctrl_common(0)(24)
- );
-
- clk40_a <= clk40_i; -- Needed to make sure delta delays line up in simulation!
- rst40_a <= rst40_i;
- clk40 <= clk40_i;
- rst40 <= rst40_i;
- clk_p <= clk_p_i;
- rst_p <= rst_p_i;
- clks_aux <= clks_aux_i;
- rsts_aux <= rsts_aux_i;
-
--- TTC protocol decoder
-
- gen_master_tcds2 : if ENABLE_TCDS2 generate
-
- signal clk125_i, clk125_b : std_logic;
- signal tcds_refclk : std_logic;
- signal tcds_refclk_i : std_logic;
- signal tcds_orbit_pulse : std_logic;
-
- signal channel0_ttc2, channel1_ttc2 : tcds2_streams_pkg.tcds2_ttc2;
- signal tcds2_interface_ctrl : tcds2_interface_pkg.tcds2_interface_ctrl_t;
- signal tcds2_interface_stat : tcds2_interface_pkg.tcds2_interface_stat_t;
-
- begin
-
- clk125_o <= clk125_b;
-
- ibufds_gt : IBUFDS_GTE4
- port map (
- i => tcds_clk_p,
- ib => tcds_clk_n,
- o => tcds_refclk,
- odiv2 => tcds_refclk_i,
- ceb => '0'
- );
-
- ibuf_osc : IBUF
- port map (
- O => clk125_i,
- I => clk125
- );
-
- bufg_osc : BUFG
- port map (
- I => clk125_i,
- O => clk125_b
- );
-
- bufg_ref : BUFG_GT
- port map (
- i => tcds_refclk_i,
- o => tcds_refclk_b,
- ce => '1',
- clr => '0',
- div => "000",
- cemask => '1',
- clrmask => '0'
- );
-
- tcds2 : entity work.tcds2_interface_with_mgt
- generic map (
- G_MGT_TYPE => emp_ttc_utils.get_tcds2_mgt_type(emp_device_decl.TCDS2_MGT_TYPE),
- G_LINK_SPEED => emp_ttc_utils.get_tcds2_link_speed(emp_device_decl.TCDS2_SPEED),
- G_INCLUDE_PRBS_LINK_TEST => true
- )
- port map (
- ctrl_i => tcds2_interface_ctrl,
- stat_o => tcds2_interface_stat,
-
- clk_sys_125mhz => clk125_b,
-
- mgt_tx_p_o => tcds_tx_p,
- mgt_tx_n_o => tcds_tx_n,
- mgt_rx_p_i => tcds_rx_n,
- mgt_rx_n_i => tcds_rx_p,
-
- clk_320_mgt_ref_i => tcds_refclk,
-
- clk_40_o => clk40_ext_tcds2,
-
- orbit_o => tcds_orbit_pulse,
-
- channel0_ttc2_o => channel0_ttc2,
- channel0_tts2_i(0) => tcds2_streams_pkg.C_TCDS2_TTS2_VALUE_IGNORED,
- channel1_ttc2_o => channel1_ttc2,
- channel1_tts2_i(0) => tcds2_streams_pkg.C_TCDS2_TTS2_VALUE_IGNORED
- );
-
- process (clk40_a)
- begin
- if rising_edge(clk40_a) then
- -- Only consider a BC0 signal to be received if I see it on both of those channels in the same BX
- -- Reason: Improve robustness against bitflips in TTC path for Serenity
- -- TODO: Set this behvaviour using SW-settable register in v0.7.0, rather than hardcoding
- if (channel0_ttc2.sync_flags_and_commands(0) = '1') and (channel1_ttc2.sync_flags_and_commands(0) = '1') then
- cmd_ext_tcds2 <= TTC_BCMD_BC0;
- else
- cmd_ext_tcds2 <= TTC_BCMD_NULL;
- end if;
-
- rsti_40 <= rsti;
-
- end if;
- end process;
-
- l1a_ext_tcds2 <= '0';
-
- csr : entity work.ipbus_tcds2_interface_accessor
- port map (
- clk_ipb => clk_ipb,
- rst_ipb => rst_ipb,
- ipb_in => ipbw(N_SLV_MASTER_TCDS2),
- ipb_out => ipbr(N_SLV_MASTER_TCDS2),
-
- ctrl_o => tcds2_interface_ctrl,
- stat_i => tcds2_interface_stat
- );
-
- else generate
-
- tcds_tx_p <= '0';
- tcds_tx_n <= '0';
-
- tcds_refclk_b <= '0';
- clk40_ext_tcds2 <= '0';
- cmd_ext_tcds2 <= TTC_BCMD_NULL;
- l1a_ext_tcds2 <= '0';
-
- ipbr(N_SLV_MASTER_TCDS2).ipb_ack <= '0';
- ipbr(N_SLV_MASTER_TCDS2).ipb_err <= ipbw(N_SLV_MASTER_TCDS2).ipb_strobe;
- ipbr(N_SLV_MASTER_TCDS2).ipb_rdata <= (others => '0');
-
- end generate;
-
-
- gen_master_legacy : if ENABLE_LEGACY_TTC generate
-
- signal err_rst : std_logic;
- signal sinerr_ctr, dblerr_ctr : std_logic_vector(15 downto 0);
- signal stat_legacy : ipb_reg_v(0 downto 0);
- signal ctrl_legacy : ipb_reg_v(0 downto 0);
- signal stb_legacy : std_logic_vector(0 downto 0);
-
- begin
-
- osc_clock : entity work.emp_oscclk
- generic map (
- OSC_FREQ => EXT_CLK_FREQ
- )
- port map (
- clk_p => ttc_clk_p,
- clk_n => ttc_clk_n,
- clk40 => clk40_ext_legacy
- );
-
- reg : entity work.ipbus_syncreg_v
- generic map(
- N_CTRL => 1,
- N_STAT => 1
- )
- port map(
- clk => clk_ipb,
- rst => rst_ipb,
- ipb_in => ipbw(N_SLV_MASTER_LEGACY),
- ipb_out => ipbr(N_SLV_MASTER_LEGACY),
- slv_clk => clk40_a,
- d => stat_legacy,
- q => ctrl_legacy,
- stb => stb_legacy
- );
-
- interface : entity work.emp_ttc_legacy
- port map(
- clk => clk40_a,
- rst => rst40_a,
- sclk => clk160s,
- sclk_locked => lock,
- ttc_in_p => ttc_rx_p,
- ttc_in_n => ttc_rx_n,
- l1a => l1a_ext_legacy,
- cmd => cmd_ext_legacy,
- sinerr_ctr => sinerr_ctr,
- dblerr_ctr => dblerr_ctr,
- err_rst => err_rst
- );
-
- err_rst <= ctrl_legacy(0)(0) and stb_legacy(0);
- stat_legacy(0) <= dblerr_ctr & sinerr_ctr;
-
-
- else generate
-
- clk40_ext_legacy <= '0';
- cmd_ext_legacy <= TTC_BCMD_NULL;
- l1a_ext_legacy <= '0';
-
- ipbr(N_SLV_MASTER_LEGACY).ipb_ack <= '0';
- ipbr(N_SLV_MASTER_LEGACY).ipb_err <= ipbw(N_SLV_MASTER_LEGACY).ipb_strobe;
- ipbr(N_SLV_MASTER_LEGACY).ipb_rdata <= (others => '0');
-
- end generate;
-
-
- -- FIXME: Select between each of two external sources and internal
- with ctrl_common(0)(1 downto 0) select cmd_ttc <=
- cmd_ext_legacy when "01",
- cmd_ext_tcds2 when "10",
- TTC_BCMD_NULL when others;
-
- with ctrl_common(0)(1 downto 0) select l1a_ttc <=
- l1a_ext_legacy when "01",
- l1a_ext_tcds2 when "10",
- '0' when others;
-
- -- L1A generation
- l1a <= l1a_ttc or l1a_pend;
- l1a_issue <= l1a and not l1a_ttc;
-
- -- TTC command generation
- req_bx <= to_unsigned(LHC_BUNCH_COUNT, req_bx'length) - to_unsigned(TTC_DEL, req_bx'length) - 1;
- cmd_bx <= '1' when std_logic_vector(req_bx) = bunch_ctr_i else '0';
-
- process(cmd_ttc, bc0_fr, cmd_pend, cmd_bx)
- begin
- cmd_issue <= '0';
- if cmd_ttc /= TTC_BCMD_NULL then
- cmd <= cmd_ttc;
- elsif bc0_fr = '1' then
- cmd <= TTC_BCMD_BC0;
- elsif cmd_pend = '1' then
- cmd <= ctrl_common(0)(15 downto 8);
- cmd_issue <= '1';
- else
- cmd <= TTC_BCMD_NULL;
- end if;
- end process;
-
- process(clk40_a)
- begin
- if rising_edge(clk40_a) then
- cmd_pend <= (cmd_pend or (ctrl_common(0)(5) and stb_common(0))) and not (rst40_a or cmd_issue);
- l1a_pend <= l1a_pend and not (rst40_a or l1a_issue);
- ttc_cmd_dist <= cmd;
- end if;
- end process;
-
- ttc_l1a_dist <= l1a;
-
--- Counters
-
- ctr_clr <= ctrl_common(0)(4) and stb_common(0);
-
- ttcctr : entity work.ttc_ctrs
- port map(
- clk => clk40_a,
- rst => rst40_a,
- ttc_cmd => cmd,
- l1a => l1a,
- clr => '0',
- en_int_bc0 => ctrl_common(0)(3),
- bc0_lock => bc0_lock,
- bc0_fr => bc0_fr,
- ttc_cmd_out => cmd_del,
- l1a_out => l1a_del,
- bunch_ctr => bunch_ctr_i,
- orb_ctr => orb_ctr_i
- );
-
- ttc_cmd <= cmd_del;
- ttc_l1a <= l1a_del;
- bunch_ctr <= bunch_ctr_i;
- orb_ctr <= orb_ctr_i;
- oc_flag <= '1' when orb_ctr_i(13 downto 0) = (13 downto 0 => '0') and bc0_lock = '1' else '0';
- ec_flag <= '1' when evt_ctr(16 downto 0) = (16 downto 0 => '0') else '0';
-
--- Status reg
-
- stat_common(0)(7 downto 2) <= (l1a_pend or cmd_pend) & psok & dist_lock & bc0_lock & "00";
- stat_common(0)(19 downto 8) <= bunch_ctr_i;
- stat_common(0)(31 downto 20) <= std_logic_vector(to_unsigned(LHC_BUNCH_COUNT, 12));
- stat_common(1) <= evt_ctr;
- stat_common(2) <= orb_ctr_i;
-
--- clk40 frequency monitoring
-
- div : entity work.freq_ctr_div
- generic map(
- N_CLK => 2
- )
- port map(
- clk(0) => clk40_a,
- clk(1) => tcds_refclk_b,
- clkdiv(0) => clk40_div,
- clkdiv(1) => tcds_refclk_div
- );
-
--- Clock frequency monitor
-
- ctr : entity work.ipbus_freq_ctr
- generic map(
- N_CLK => 6
- )
- port map(
- clk => clk_ipb,
- rst => rst_ipb,
- ipb_in => ipbw(N_SLV_FREQ),
- ipb_out => ipbr(N_SLV_FREQ),
- clkdiv(0) => clk40_div,
- clkdiv(1) => tcds_refclk_div,
- clkdiv(5 downto 2) => monclk
- );
-
--- TTC history buffer
-
- hist : entity work.ttc_history_new
- port map(
- clk => clk_ipb,
- rst => rst_ipb,
- ipb_in => ipbw(N_SLV_HIST),
- ipb_out => ipbr(N_SLV_HIST),
- ttc_clk => clk40_a,
- ttc_rst => rst40_a,
- ttc_l1a => l1a_del,
- ttc_cmd => cmd_del,
- ttc_bx => bunch_ctr_i,
- ttc_orb => orb_ctr_i,
- ttc_evt => evt_ctr
- );
-
--- Command counters
-
- cmdctrs : entity work.ttc_cmd_ctrs
- port map(
- clk => clk_ipb,
- rst => rst_ipb,
- ipb_in => ipbw(N_SLV_CMD_CTRS),
- ipb_out => ipbr(N_SLV_CMD_CTRS),
- ttc_clk => clk40_a,
- clr => ctr_clr,
- ttc_cmd => cmd_del
- );
-
-end rtl;
--------------------------------------------------------------------------------
diff --git a/top/addr_table/emp_payload.xml b/top/addr_table/emp_payload.xml
index 12acae9558aaac50caa6c976eeff9b581fec48ed..f37df61257a4f900107b812560a831791898e26a 100644
--- a/top/addr_table/emp_payload.xml
+++ b/top/addr_table/emp_payload.xml
@@ -4,24 +4,19 @@
<node id="chan_sel" mask="0x7f"/>
</node>
- <node id="csr" address="0x00004" description="Histogram control and status" fwinfo="endpoint;width=2">
- <node id="windowL" address="0x0"/>
- <node id="windowH" address="0x1" mask="0x000f"/>
- <node id="histogram_enable" address="0x1" mask="0x0010"/>
- <node id="histogram_sel" address="0x1" mask="0xffe0"/>
- <node id="histogram0" address="0x2"/>
- <node id="histogram1" address="0x3"/>
- </node>
-
- <node id="fe_chan" address="0x040" description="FE channel control and status" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=6"/>
+ <node id="fe_chan" address="0x200" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=9"/>
- <node id="mproc_ctrl" address="0x1ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
+
+ <node id="mprocessor" address="0x400" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
+ <node id="mproc_ctrl" address="0x4ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
<node id="chan_sel" mask="0x7f"/>
+ <node id="srst" mask="0x80"/>
+ <node id="sync_fastreset" mask="0x100"/>
</node>
- <node id="mprocessor" address="0x200" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
+
+ <node id="tcds_fast_cmd" address="0x600" module="file://dtc_tcds_fastcmd.xml"/>
+
+ <node id="link_monitor" address="0x10000" module="file://LinkMonitorInterface.xml"/>
<node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>
-
- <node id="mem1" address="0x1000" size="0x200" mode="incremental" fwinfo="endpoint;width=9"/>
- <node id="mem2" address="0x2000" size="0x200" mode="incremental" fwinfo="endpoint;width=9"/>
</node>
diff --git a/top/firmware/cfg/top.dep b/top/firmware/cfg/top.dep
index 1ab335d61fafefd901ee3a424e750657f8c8d334..2b37dc34fb52519cea4a6724b0c16a47e881702b 100644
--- a/top/firmware/cfg/top.dep
+++ b/top/firmware/cfg/top.dep
@@ -1,5 +1,3 @@
-setup -f --cd ../cfg settings.tcl
-
include -c histogram:top histogram.dep
include -c dtc:dtc-fe/2S/5G-FEC12 module.dep
include -c dtc:dtc-fe/2S/5G-FEC12 framer.dep
@@ -21,35 +19,13 @@ include -c emp-fwk:components/links/fe_mgt/lpgbt/interface interface_lpgbt.dep
? toolset.lower() == "vivado" ? setup -c emp-fwk:components/payload emp_simple_payload_msg_suppressions.tcl
include -c 10gb-ethernet:eth10g emp_eth10g.dep
+include -c dtc-monitoring:common module.dep
+include -c common module.dep
src emp_project_decl.vhd
src emp_payload.vhd
src link_maps.vhd
-src ipbus_decode_emp_payload.vhd
-src mprocessor_constants.vhd
-src MProcessor.vhd
-src ipbus_decode_mprocessor.vhd
-src LinkAggregatorCore.vhd
-src LinkAggregatorIPBus.vhd
-src ipbus_decode_link_aggregator.vhd
-src fixed_pkg_2008.vhd
-src --vhdl2008 TrackReconstructor.vhd
-src LinkCombinerCore.vhd
-src LinkCombinerIPBus.vhd
-
-src --cd ../cgn link_agg_single_link_fifo.xci
-setup -f --cd ../cgn link_agg_single_link_fifo.tcl
-
-src --cd ../cgn link_agg_single_link_fifo_fwft.xci
-setup -f --cd ../cgn link_agg_single_link_fifo_fwft.tcl
-
-src --cd ../cgn link_agg_all_links_fifo.xci
-setup -f --cd ../cgn link_agg_all_links_fifo.tcl
-
-src --cd ../cgn link_combin_buffer.xci
-setup -f --cd ../cgn link_combin_buffer.tcl
+src ipbus_decode_emp_payload.vhd
-addrtab link_aggregator.xml
-addrtab emp_payload.xml
-addrtab mprocessor.xml
+addrtab -t emp_payload.xml
\ No newline at end of file
diff --git a/top/firmware/hdl/emp_payload.vhd b/top/firmware/hdl/emp_payload.vhd
index d156d95d35240bc95a0cf350e2f9c224bb39ca86..9830d5926666fcb0b548910cea39b8da7cc5b851 100644
--- a/top/firmware/hdl/emp_payload.vhd
+++ b/top/firmware/hdl/emp_payload.vhd
@@ -1,51 +1,55 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-
+---
use work.ipbus.all;
use work.ipbus_reg_types.all;
-
+use work.ipbus_decode_emp_payload.all;
+---
use work.emp_data_types.all;
use work.emp_project_decl.all;
use work.emp_device_decl.all;
use work.emp_ttc_decl.all;
-
-use work.ipbus_decode_emp_payload.all;
-
+use work.emp_slink_types.all;
+---
use work.dtc_link_maps.all;
use work.front_end_data_types.all;
use work.gbt_module_constants.all;
use work.mprocessor_constants.all;
-use work.dtc_data_types.all;
use work.dtc_constants.all;
+use work.dtc_data_types.all;
entity emp_payload is
-port(
- --- Input Ports ---
- clk_p : in std_logic;
- clk40 : in std_logic := '0';
- clk_payload : in std_logic_vector(2 downto 0);
- rst_payload : in std_logic_vector(2 downto 0);
- rst_loc : in std_logic_vector(N_REGION - 1 downto 0);
- clken_loc : in std_logic_vector(N_REGION - 1 downto 0);
- ctrs : in ttc_stuff_array;
- d : in ldata(4 * N_REGION - 1 downto 0);
- --- Output Ports ---
- bc0 : out std_logic;
- gpio : out std_logic_vector(29 downto 0);
- gpio_en : out std_logic_vector(29 downto 0);
- q : out ldata(4 * N_REGION - 1 downto 0);
- --- IPBus Ports ---
- clk : in std_logic;
- rst : in std_logic;
- ipb_in : in ipb_wbus;
- ipb_out : out ipb_rbus;
- -- KH
- gbe_q : out ldata := (others => LWORD_NULL);
- gbe_backpressure : in std_logic_vector(1 downto 0)
-);
-end emp_payload;
+ port (
+ --- Input Ports ---
+ clk_p : in std_logic;
+ clk40 : in std_logic := '0';
+ clk_payload : in std_logic_vector(2 downto 0);
+ rst_payload : in std_logic_vector(2 downto 0);
+ rst_loc : in std_logic_vector(N_REGION - 1 downto 0);
+ clken_loc : in std_logic_vector(N_REGION - 1 downto 0);
+ ctrs : in ttc_stuff_array;
+ d : in ldata(4 * N_REGION - 1 downto 0);
+ backpressure : in std_logic_vector(SLINK_MAX_QUADS-1 downto 0);
+ ttc_cmd : in ttc_cmd_t;
+ --- Output Ports ---
+ bc0 : out std_logic;
+ gpio : out std_logic_vector(29 downto 0);
+ gpio_en : out std_logic_vector(29 downto 0);
+ q : out ldata(4 * N_REGION - 1 downto 0);
+ slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS-1 downto 0);
+ --- IPBus Ports ---
+ clk : in std_logic;
+ rst : in std_logic;
+ ipb_in : in ipb_wbus;
+ ipb_out : out ipb_rbus;
+ -- KH
+ gbe_q : out ldata := (others => LWORD_NULL);
+ gbe_backpressure : in std_logic_vector(3 downto 0)
+ );
+end entity emp_payload;
+
architecture rtl of emp_payload is
@@ -64,37 +68,23 @@ architecture rtl of emp_payload is
signal ipb_chain : ipbdc_bus_array(cNumberOfFEModules downto 0);
signal stubs : ldata(cNumberOfFEModules - 1 downto 0);
+ signal header_array : tCICHeaderArray(cNumberOfFEModules*cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ signal header_start_array : std_logic_vector(cNumberOfFEModules*cNumberOfCICs - 1 downto 0) := (others => '0');
+
+ signal eth_link_out : ldata(3 downto 0) := (others => LWORD_NULL);
- signal linksout : ldata(cNumberOfFEModules - 1 downto 0);
- signal linkor : lword := LWORD_NULL;
-
- -- Histogrammer
-
- constant N_CTRL_HIST : integer := 2;
- constant N_STAT_HIST : integer := 2;
+
- constant bin_width : integer := 32;
- constant input_width : integer := 9;
-
- signal status_registers : ipb_reg_v(N_STAT_HIST - 1 downto 0) := (others => (others => '0'));
- signal control_registers : ipb_reg_v(N_CTRL_HIST - 1 downto 0) := (others => (others => '0'));
-
- signal trigger_window_lower : std_logic_vector(31 downto 0) := (others => '0');
- signal trigger_window_upper : std_logic_vector(3 downto 0) := (others => '0');
- signal trigger_window : std_logic_vector(36 - 1 downto 0) := X"0ffffffff";
- signal max_value0, max_value1 : std_logic_vector(bin_width - 1 downto 0) := (others => '0');
- signal histogram_reset : std_logic := '0';
- signal hist0_stub, hist1_stub : lword := LWORD_NULL;
- signal histogram_sel : integer := 0;
- signal histogram_enable : std_logic := '0';
- signal header_start_array : tHeaderStartArray := (others => (others => '0'));
- signal eth_link_out : ldata(1 downto 0) := (others => LWORD_NULL);
+ -- MProcessor
+ constant cNumberOfMProcessors : integer := 1;
+ signal mprocessor_ipb_chain : ipbdc_bus_array(cNumberOfMProcessors downto 0);
+ signal srst : std_logic := '0';
+ signal ttc_resync_reset, ttc_resync_reset_prev : std_logic := '0';
+ signal ttc_bc0, ttc_oc0, ttc_resync : std_logic := '0';
- signal header_array : tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ signal orbit_counter : unsigned(31 downto 0) := to_unsigned(0 , 32);
+ signal bunch_counter : unsigned(11 downto 0) := to_unsigned(3564, 12);
- -- MProcessor
- constant cNumberOfMProcessors : integer := 1;
- signal mprocessor_ipb_chain : ipbdc_bus_array(cNumberOfMProcessors downto 0);
-- Daqpath
@@ -102,359 +92,370 @@ architecture rtl of emp_payload is
signal daq_data : tDaqDataLinkArray(cNumberOfFEModules - 1 downto 0);
signal daq_empty : tDaqFlagLinkArray(cNumberOfFEModules - 1 downto 0);
+
+ -- TCDS & Fast commands
+
+ signal global_fcmd : tFastCommand;
+ signal tcds_fcmd : tFastCommand;
+
+
begin
+
---==============================--
--- IPBus fabric
---==============================--
-
-
---==============================--
-fabric: entity work.ipbus_fabric_sel
---==============================--
-generic map(
- NSLV => N_SLAVES,
- SEL_WIDTH => IPBUS_SEL_WIDTH
-)
-port map(
- ipb_in => ipb_in,
- ipb_out => ipb_out,
- sel => ipbus_sel_emp_payload(ipb_in.ipb_addr),
- ipb_to_slaves => ipb_to_slaves,
- ipb_from_slaves => ipb_from_slaves
-);
-
-
---==============================--
-fe_channel_ctrl: entity work.ipbus_reg_v
---==============================--
-generic map(
- N_REG => 1
-)
-port map(
- clk => clk,
- reset => rst,
- ipbus_in => ipb_to_slaves(N_SLV_FE_CTRL),
- ipbus_out => ipb_from_slaves(N_SLV_FE_CTRL),
- q => channel_sel,
- qmask => (0 => X"0000007f")
-);
-
---==============================--
-mproc_channel_ctrl: entity work.ipbus_reg_v
---==============================--
-generic map(
- N_REG => 1
-)
-port map(
- clk => clk,
- reset => rst,
- ipbus_in => ipb_to_slaves(N_SLV_MPROC_CTRL),
- ipbus_out => ipb_from_slaves(N_SLV_MPROC_CTRL),
- q => mproc_channel_sel,
- qmask => (0 => X"0000007f")
-);
-
-
---==============================--
-channel_select: entity work.ipbus_dc_fabric_sel
---==============================--
-generic map(
- SEL_WIDTH => 7
-)
-port map(
- clk => clk,
- rst => rst,
- sel => channel_sel(0)(6 downto 0),
- ipb_in => ipb_to_slaves(N_SLV_FE_CHAN),
- ipb_out => ipb_from_slaves(N_SLV_FE_CHAN),
- ipbdc_out => ipb_chain(0),
- ipbdc_in => ipb_chain(cNumberOfFEModules)
-);
-
-
-
---==============================--
--- FE data extraction and monitoring
---==============================--
-
-
---==============================--
-genLinkInterface: for i in 0 to cNumberOfFEModules - 1 generate
---==============================--
-
- signal ipb_to_channel : ipb_wbus;
- signal ipb_from_channel : ipb_rbus;
+ --==============================--
+ -- IPBus fabric
+ --==============================--
-begin
+ --==============================--
+ fabric: entity work.ipbus_fabric_sel
+ --==============================--
+ generic map (
+ NSLV => N_SLAVES,
+ SEL_WIDTH => IPBUS_SEL_WIDTH
+ )
+ port map (
+ ipb_in => ipb_in,
+ ipb_out => ipb_out,
+ sel => ipbus_sel_emp_payload(ipb_in.ipb_addr),
+ ipb_to_slaves => ipb_to_slaves,
+ ipb_from_slaves => ipb_from_slaves
+ );
--==============================--
- channel_node: entity work.ipbus_dc_node
+ fe_channel_ctrl: entity work.ipbus_reg_v
--==============================--
- generic map(
- I_SLV => i,
- SEL_WIDTH => 7,
- PIPELINE => false
+ generic map (
+ N_REG => 1
)
- port map(
- clk => clk,
- rst => rst,
- ipb_out => ipb_to_channel,
- ipb_in => ipb_from_channel,
- ipbdc_in => ipb_chain(i),
- ipbdc_out => ipb_chain(i + 1)
+ port map (
+ clk => clk,
+ reset => rst,
+ ipbus_in => ipb_to_slaves(N_SLV_FE),
+ ipbus_out => ipb_from_slaves(N_SLV_FE),
+ q => channel_sel,
+ qmask => (0 => X"0000007f")
);
--==============================--
- LinkInterfaceInstance: entity work.LinkInterface
+ channel_select : entity work.ipbus_dc_fabric_sel
--==============================--
generic map (
- module_type => "2S"
+ SEL_WIDTH => 7
)
+ port map (
+ clk => clk,
+ rst => rst,
+ sel => channel_sel(0)(6 downto 0),
+ ipb_in => ipb_to_slaves(N_SLV_FE_CHAN),
+ ipb_out => ipb_from_slaves(N_SLV_FE_CHAN),
+ ipbdc_out => ipb_chain(0),
+ ipbdc_in => ipb_chain(cNumberOfFEModules)
+ );
+
+ --==============================--
+ mproc_channel_ctrl: entity work.ipbus_reg_v
+ --==============================--
+ generic map(
+ N_REG => 1
+ )
+ port map(
+ clk => clk,
+ reset => rst,
+ ipbus_in => ipb_to_slaves(N_SLV_MPROC_CTRL),
+ ipbus_out => ipb_from_slaves(N_SLV_MPROC_CTRL),
+ q => mproc_channel_sel,
+ qmask => (0 => X"00000fff")
+ );
+
+
+
+
+
+ --==============================--
+ -- FE data extraction and monitoring
+ --==============================--
+
+ --==============================--
+ genLinkInterface: for i in 0 to cNumberOfFEModules - 1 generate
+ --==============================--
+
+ signal ipb_to_channel : ipb_wbus;
+ signal ipb_from_channel : ipb_rbus;
+
+ begin
+
+ --==============================--
+ channel_node : entity work.ipbus_dc_node
+ --==============================--
+ generic map (
+ I_SLV => i,
+ SEL_WIDTH => 7,
+ PIPELINE => false
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ ipb_out => ipb_to_channel,
+ ipb_in => ipb_from_channel,
+ ipbdc_in => ipb_chain(i),
+ ipbdc_out => ipb_chain(i + 1)
+ );
+
+ --==============================--
+ LinkInterfaceInstance : entity work.LinkInterface
+ --==============================--
+ generic map (
+ module_type => "2S"
+ )
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ clk40 => clk40,
+ link_in => d(cDTCInputLinkMap(i)),
+ daq_read => daq_read(i),
+ global_fcmd => global_fcmd,
+ --- Output Ports ---
+ link_out => q(cDTCInputLinkMap(i)),
+ stub_out => stubs(i),
+ header_out => header_array(cNumberOfCICs * i + cNumberOfCICs - 1 downto cNumberOfCICs * i),
+ daq_out => daq_data(i),
+ daq_empty => daq_empty(i),
+ --- IPBus Ports ---
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_channel,
+ ipb_out => ipb_from_channel,
+ --- Debug Ports ---
+ debug_header_start => header_start_array(cNumberOfCICs*(i + 1) - 1 downto cNumberOfCICs*i)
+ );
+ end generate genLinkInterface;
+
+
+ --==============================--
+ -- Global TCDS
+ --==============================--
+
+ --==============================--
+ GlobalFastCommand: entity work.GlobalFastCommand
+ --==============================--
port map (
--- Input Ports ---
- clk_p => clk_p,
- link_in => d(cDTCInputLinkMap(i)),
- daq_read => daq_read(i),
+ clk_p => clk_p,
+ clk40 => clk40,
+ ext_fcmd => tcds_fcmd,
--- Output Ports ---
- link_out => linksout(i),
- stub_out => stubs(i),
- daq_out => daq_data(i),
- daq_empty => daq_empty(i),
- header_out => header_array(cNumberOfCICs * i + cNumberOfCICs - 1 downto cNumberOfCICs * i),
+ global_fcmd => global_fcmd,
--- IPBus Ports ---
- clk => clk,
- rst => rst,
- ipb_in => ipb_to_channel,
- ipb_out => ipb_from_channel,
- --- Debug Ports ---
- debug_header_start => header_start_array(i)
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_slaves(N_SLV_TCDS_FAST_CMD),
+ ipb_out => ipb_from_slaves(N_SLV_TCDS_FAST_CMD)
);
-end generate;
+ tcds_fcmd.fast_reset <= ttc_resync;
+ tcds_fcmd.l1a_trig <= '0';
+ tcds_fcmd.cal_pulse <= '0';
+ tcds_fcmd.counter_reset <= ttc_bc0;
-linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0); --or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0);
---==============================--
-genHack: for i in 0 to cNumberOfFEModules - 1 generate
---==============================--
-begin
- q(cDTCInputLinkMap(i)) <= linkor;
-
-end generate;
-
-
---==============================--
--- L1 Data Aggregator
---==============================--
-
---==============================--
-L1DataAggregator : entity work.L1DataAggregator
---==============================--
-port map (
- --- Input Ports ---
- clk_p => clk_p,
- daq_in => daq_data,
- empty => daq_empty,
- --- Output Ports ---
- read => daq_read,
- --- IPBus Ports ---
- clk => clk,
- rst => rst,
- ipb_in => ipb_to_slaves(N_SLV_BE_DAQ),
- ipb_out => ipb_from_slaves(N_SLV_BE_DAQ)
-);
-
-
---==============================--
--- Histogrammer
---==============================--
-
-
---==============================--
-histogram_ctrl: entity work.ipbus_ctrlreg_v
---==============================--
-generic map(
- N_CTRL => N_CTRL_HIST,
- N_STAT => N_STAT_HIST
-)
-port map(
- clk => clk,
- reset => rst,
- ipbus_in => ipb_to_slaves(N_SLV_CSR),
- ipbus_out => ipb_from_slaves(N_SLV_CSR),
- d => status_registers,
- q => control_registers
-);
-
-status_registers(0)(bin_width - 1 downto 0) <= max_value0;
-status_registers(1)(bin_width - 1 downto 0) <= max_value1;
-
-
-trigger_window_lower <= control_registers(0);
-trigger_window_upper <= control_registers(1)(3 downto 0);
-histogram_enable <= control_registers(1)(4);
-histogram_sel <= to_integer(unsigned(control_registers(1)(15 downto 5)));
-trigger_window <= trigger_window_upper & trigger_window_lower;
-
-
---==============================--
-pHistogram: process(clk_p)
---==============================--
-begin
- if rising_edge(clk_p) then
- if stubs(histogram_sel).valid = '1' and histogram_enable = '1' then
- if stubs(histogram_sel).data(46) = '0' then
- hist0_stub <= stubs(histogram_sel);
- hist1_stub <= LWORD_NULL;
- else
- hist0_stub <= LWORD_NULL;
- hist1_stub <= stubs(histogram_sel);
- end if;
- else
- hist0_stub <= LWORD_NULL;
- hist1_stub <= LWORD_NULL;
+
+
+ --==============================--
+ -- L1 Data Aggregator
+ --==============================--
+
+ --==============================--
+ L1DataAggregator : entity work.L1DataAggregator
+ --==============================--
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ daq_in => daq_data,
+ empty => daq_empty,
+ --- Output Ports ---
+ read => daq_read,
+ --- IPBus Ports ---
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_slaves(N_SLV_BE_DAQ),
+ ipb_out => ipb_from_slaves(N_SLV_BE_DAQ)
+ );
+
+ --==============================--
+ pRouteStubsToOutput : process (clk_p) is
+ --==============================--
+ begin
+ if rising_edge(clk_p) then
+ for i in 0 to cNumberOfOutputLinks - 1 loop
+ q(cDTCOutputLinkMap(i)).valid <= d(cDTCInputLinkMap(i)).valid;
+ q(cDTCOutputLinkMap(i)).data <= d(cDTCInputLinkMap(i)).data;
+ q(cDTCOutputLinkMap(i)).strobe <= '1';
+ end loop;
end if;
- end if;
-end process;
-
-
---==============================--
-HistogramInstance0: entity work.IPBusHistogram
---==============================--
-generic map(
- input_width => input_width,
- bin_width => bin_width,
- data_offset => 10
-)
-port map(
- --- Input Ports ---
- clk_p => clk_p,
- data_in => hist0_stub,
- histogram_reset => histogram_reset,
- --- Output Ports ---
- max_bin_value => max_value0,
- --- IPBus Ports ---
- clk => clk,
- rst => rst,
- ipb_in => ipb_to_slaves(N_SLV_MEM1),
- ipb_out => ipb_from_slaves(N_SLV_MEM1)
-);
-
-
---==============================--
-HistogramInstance1: entity work.IPBusHistogram
---==============================--
-generic map(
- input_width => input_width,
- bin_width => bin_width,
- data_offset => 6
-)
-port map(
- --- Input Ports ---
- clk_p => clk_p,
- data_in => hist1_stub,
- histogram_reset => histogram_reset,
- --- Output Ports ---
- max_bin_value => max_value1,
- --- IPBus Ports ---
- clk => clk,
- rst => rst,
- ipb_in => ipb_to_slaves(N_SLV_MEM2),
- ipb_out => ipb_from_slaves(N_SLV_MEM2)
-);
-
-
---==============================--
-HistogramResetterInstance: entity work.HistogramResetter
---==============================--
-port map(
- --- Input Ports ---
- clk_p => clk_p,
- trigger_window => trigger_window,
- --- Output Ports ---
- histogram_reset => histogram_reset
-);
-
-
-
---==============================--
--- Link Aggregation and Combination
---==============================--
-
---==============================--
-mprocessor_channel_select: entity work.ipbus_dc_fabric_sel
---==============================--
-generic map(
- SEL_WIDTH => 7
-)
-port map(
- clk => clk,
- rst => rst,
- sel => mproc_channel_sel(0)(6 downto 0),
- ipb_in => ipb_to_slaves(N_SLV_MPROCESSOR),
- ipb_out => ipb_from_slaves(N_SLV_MPROCESSOR),
- ipbdc_out => mprocessor_ipb_chain(0),
- ipbdc_in => mprocessor_ipb_chain(cNumberOfMProcessors)
-);
-
-
---==============================-
-genMProcessors : for i in 0 to cNumberOfMProcessors - 1 generate
---==============================-
-
- signal ipb_to_channel : ipb_wbus;
- signal ipb_from_channel : ipb_rbus;
- constant cNumberofInputLinks : integer := 4;
+ end process pRouteStubsToOutput;
-begin
+
--==============================--
- channel_node: entity work.ipbus_dc_node
+ LinkMonitorInterfaceInstance : entity work.LinkMonitorInterface
--==============================--
- generic map(
- I_SLV => i,
- SEL_WIDTH => 7,
- PIPELINE => false
+ generic map (
+ N_LINKS => 4
)
- port map(
- clk => clk,
- rst => rst,
- ipb_out => ipb_to_channel,
- ipb_in => ipb_from_channel,
- ipbdc_in => mprocessor_ipb_chain(i),
- ipbdc_out => mprocessor_ipb_chain(i + 1)
+ port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ stubs => stubs(3 downto 0),
+ headers => header_array(7 downto 0),
+ header_start => header_start_array(7 downto 0),
+ --- IPBus Ports ---
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_slaves(N_SLV_LINK_MONITOR),
+ ipb_out => ipb_from_slaves(N_SLV_LINK_MONITOR)
);
+
+
+ --==============================--
+ -- Link Aggregation and Combination
+ --==============================--
+
--==============================--
- MProcessorInstance: entity work.MProcessor
+ mprocessor_channel_select: entity work.ipbus_dc_fabric_sel
--==============================--
generic map(
- N_LINKS => cNumberofInputLinks
+ SEL_WIDTH => 7
)
port map(
- --- Input Ports ---
- clk_p => clk_p,
- links_in => stubs(cNumberofInputLinks*i + (cNumberofInputLinks - 1) downto cNumberofInputLinks*i),
- header_in => header_array,
- header_start_array => header_start_array,
- gbe_backpressure => gbe_backpressure(i),
- --- Output Ports ---
- link_out => eth_link_out(i),
- --- IPBus Ports ---
- ipb_clk => clk,
- ipb_rst => rst,
- ipb_in => ipb_to_channel,
- ipb_out => ipb_from_channel
+ clk => clk,
+ rst => rst,
+ sel => mproc_channel_sel(0)(6 downto 0),
+ ipb_in => ipb_to_slaves(N_SLV_MPROCESSOR),
+ ipb_out => ipb_from_slaves(N_SLV_MPROCESSOR),
+ ipbdc_out => mprocessor_ipb_chain(0),
+ ipbdc_in => mprocessor_ipb_chain(cNumberOfMProcessors)
);
-end generate genMProcessors;
-gbe_q <= eth_link_out;
+ --==============================-
+ genMProcessors : for i in 0 to cNumberOfMProcessors - 1 generate
+ --==============================-
+
+ signal ipb_to_channel : ipb_wbus;
+ signal ipb_from_channel : ipb_rbus;
+ constant cNumberofInputLinks : integer := 4;
+
+ begin
+
+ --==============================--
+ channel_node: entity work.ipbus_dc_node
+ --==============================--
+ generic map(
+ I_SLV => i,
+ SEL_WIDTH => 7,
+ PIPELINE => false
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ ipb_out => ipb_to_channel,
+ ipb_in => ipb_from_channel,
+ ipbdc_in => mprocessor_ipb_chain(i),
+ ipbdc_out => mprocessor_ipb_chain(i + 1)
+ );
+
+ --==============================--
+ MProcessorInstance: entity work.MProcessor
+ --==============================--
+ generic map(
+ N_LINKS => cNumberofInputLinks
+ )
+ port map(
+ --- Input Ports ---
+ clk_p => clk_p,
+ links_in => stubs(cNumberofInputLinks*i + (cNumberofInputLinks - 1) downto cNumberofInputLinks*i),
+ header_in => header_array,
+ header_start_array => convertSLVtoHeaderStartArray(header_start_array),
+ gbe_backpressure => gbe_backpressure(i),
+ srst => srst,
+ --- Output Ports ---
+ link_out => eth_link_out(i),
+ --- IPBus Ports ---
+ ipb_clk => clk,
+ ipb_rst => rst,
+ ipb_in => ipb_to_channel,
+ ipb_out => ipb_from_channel
+ );
+ end generate genMProcessors;
+
+
+ gbe_q <= eth_link_out;
+
+
+ --==============================--
+ pTTC: process(clk40)
+ --==============================--
+ begin
+ if rising_edge(clk40) then
+
+ ttc_bc0 <= '0';
+ ttc_oc0 <= '0';
+ ttc_resync <= '0';
+
+ if ttc_cmd = TTC_BCMD_BC0 then
+ orbit_counter <= orbit_counter + 1;
+ bunch_counter <= (others => '0');
+ ttc_bc0 <= '1';
+
+ if ttc_resync_reset = '1' and ttc_resync_reset_prev = '0' then
+
+ ttc_resync <= '1';
+
+ end if;
+
+ ttc_resync_reset_prev <= ttc_resync_reset;
+
+
+ elsif ttc_cmd = TTC_BCMD_OC0 then
+
+ orbit_counter <= (others => '0');
+ bunch_counter <= to_unsigned(3564, bunch_counter'length);
+ ttc_oc0 <= '1';
+
+ elsif bunch_counter < 3564 then
+
+ bunch_counter <= bunch_counter + 1;
+
+ end if;
+
+ end if;
+ end process;
+
+ ttc_resync_reset <= mproc_channel_sel(0)(8);
+ srst <= mproc_channel_sel(0)(7) or ttc_oc0;
+
+ q(20).valid <= '1';
+ q(20).data <= "0000" & std_logic_vector(bunch_counter) & "0000000000000000" & std_logic_vector(orbit_counter);
+ q(20).start <= '1';
+ q(20).strobe <= '1';
+
+
+
+
+ bc0 <= '0';
+ gpio <= (others => '0');
+ gpio_en <= (others => '0');
+
+
+ --==============================--
+ slink_q_gen : for q in SLINK_MAX_QUADS-1 downto 0 generate
+ --==============================--
+ begin
+ slink_q(q) <= SLINK_INPUT_DATA_ARRAY_NULL;
+ end generate slink_q_gen;
+
-bc0 <= '0';
-gpio <= (others => '0');
-gpio_en <= (others => '0');
-end rtl;
+end architecture rtl;
diff --git a/top/firmware/hdl/emp_project_decl.vhd b/top/firmware/hdl/emp_project_decl.vhd
index fdc5575eec30b6c0d471caf07825f2de0b2bb1be..c4e9c7c16c0407b76b60156fe5e9fa722d6c91da 100644
--- a/top/firmware/hdl/emp_project_decl.vhd
+++ b/top/firmware/hdl/emp_project_decl.vhd
@@ -13,6 +13,8 @@ use work.emp_device_decl.all;
use work.emp_device_types.all;
use work.emp_lpgbt_decl.all;
use work.emp_data_framer_decl.all;
+use work.emp_slink_types.all;
+use work.emp_eth10g_types.all;
-------------------------------------------------------------------------------
package emp_project_decl is
@@ -20,11 +22,11 @@ package emp_project_decl is
constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"d451d001";
-- Latency buffer size
- constant LB_ADDR_WIDTH : integer := 10;
+ constant LB_ADDR_WIDTH : integer := 10;
-- Clock setup
- constant CLOCK_COMMON_RATIO : integer := 32;
- constant CLOCK_RATIO : integer := 8;
+ constant CLOCK_COMMON_RATIO : integer := 32;
+ constant CLOCK_RATIO : integer := 8;
constant CLOCK_AUX_DIV : clock_divisor_array_t := (16, 8, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz
-- Only used by nullalgo
@@ -58,8 +60,8 @@ package emp_project_decl is
-- for data framer (ic_simple, no_ec, n_ec_spare, ec_broadcast)
constant REGION_DATA_FRAMER_CONF : region_data_framer_conf_array_t := (
- 2 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
- 3 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
+ 2 => ( 0=>(false, true, 0, false, lpgbtv0), 1=>(false, true, 0, false, lpgbtv0), 2=>(false, true, 0, false, lpgbtv1), 3=>(false, true, 0, false, lpgbtv0)),
+ 3 => ( 0=>(false, true, 0, false, lpgbtv0), 1=>(false, true, 0, false, lpgbtv0), 2=>(false, true, 0, false, lpgbtv0), 3=>(false, true, 0, false, lpgbtv0)),
others => kDummyRegionDataFramer
);
@@ -70,7 +72,15 @@ package emp_project_decl is
others => kDummyRegionLpgbt
);
+ -- Specify the slink quad using the corresponding region conf ID
+ -- Specify slink channels to enable using the channel mask
+ constant SLINK_CONF : slink_conf_array_t := (
+ others => kNoSlink
+ );
+ constant ETH10G_CONF : eth10g_conf_array_t := (
+ 0 => (10, "0011", (x"000000000000", x"000000000000", x"aabbccddef53", x"aabbccddef54"))
+ );
diff --git a/top/firmware/hdl/ipbus_decode_emp_payload.vhd b/top/firmware/hdl/ipbus_decode_emp_payload.vhd
deleted file mode 100644
index 65092e3b64596d93dcd94d8e93b647f11dbbffac..0000000000000000000000000000000000000000
--- a/top/firmware/hdl/ipbus_decode_emp_payload.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_emp_payload is
-
- constant IPBUS_SEL_WIDTH: positive := 4;
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_emp_payload(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL (Wed Sep 7 13:15:33 2022)
- constant N_SLV_FE_CTRL: integer := 0;
- constant N_SLV_CSR: integer := 1;
- constant N_SLV_FE_CHAN: integer := 2;
- constant N_SLV_MPROC_CTRL: integer := 3;
- constant N_SLV_MPROCESSOR: integer := 4;
- constant N_SLV_MEM1: integer := 5;
- constant N_SLV_MEM2: integer := 6;
- constant N_SLV_BE_DAQ: integer := 7;
- constant N_SLAVES: integer := 8;
--- END automatically generated VHDL
-
-
-end ipbus_decode_emp_payload;
-
-package body ipbus_decode_emp_payload is
-
- function ipbus_sel_emp_payload(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL (Wed Sep 7 13:15:33 2022)
- if std_match(addr, "-0----------------00--0000000000") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CTRL, IPBUS_SEL_WIDTH)); -- fe_ctrl / base 0x00000000 / mask 0x400033ff
- elsif std_match(addr, "-0----------------00--00000001--") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000004 / mask 0x400033fc
- elsif std_match(addr, "-0----------------00--0001------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CHAN, IPBUS_SEL_WIDTH)); -- fe_chan / base 0x00000040 / mask 0x400033c0
- elsif std_match(addr, "-0----------------00--0111111111") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MPROC_CTRL, IPBUS_SEL_WIDTH)); -- mproc_ctrl / base 0x000001ff / mask 0x400033ff
- elsif std_match(addr, "-0----------------00--100-------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MPROCESSOR, IPBUS_SEL_WIDTH)); -- mprocessor / base 0x00000200 / mask 0x40003380
- elsif std_match(addr, "-0----------------01--0---------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MEM1, IPBUS_SEL_WIDTH)); -- mem1 / base 0x00001000 / mask 0x40003200
- elsif std_match(addr, "-0----------------10--0---------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MEM2, IPBUS_SEL_WIDTH)); -- mem2 / base 0x00002000 / mask 0x40003200
- elsif std_match(addr, "-1------------------------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_BE_DAQ, IPBUS_SEL_WIDTH)); -- be_daq / base 0x40000000 / mask 0x40000000
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_emp_payload;
-
-end ipbus_decode_emp_payload;
diff --git a/top/firmware/hdl/ipbus_decode_link_aggregator.vhd b/top/firmware/hdl/ipbus_decode_link_aggregator.vhd
deleted file mode 100644
index f7f0f178ea0cd7089fdd2a2965ca4e618e03e1d5..0000000000000000000000000000000000000000
--- a/top/firmware/hdl/ipbus_decode_link_aggregator.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_link_aggregator is
-
- constant IPBUS_SEL_WIDTH: positive := 2;
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_link_aggregator(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL (Fri Aug 26 18:31:19 2022)
- constant N_SLV_CHAN_SEL: integer := 0;
- constant N_SLV_CONTROL: integer := 1;
- constant N_SLV_MONITORING: integer := 2;
- constant N_SLAVES: integer := 3;
--- END automatically generated VHDL
-
-
-end ipbus_decode_link_aggregator;
-
-package body ipbus_decode_link_aggregator is
-
- function ipbus_sel_link_aggregator(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL (Fri Aug 26 18:31:19 2022)
- if std_match(addr, "----------------------------0--0") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN_SEL, IPBUS_SEL_WIDTH)); -- chan_sel / base 0x00000000 / mask 0x00000009
- elsif std_match(addr, "----------------------------0--1") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CONTROL, IPBUS_SEL_WIDTH)); -- control / base 0x00000001 / mask 0x00000009
- elsif std_match(addr, "----------------------------1---") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MONITORING, IPBUS_SEL_WIDTH)); -- monitoring / base 0x00000008 / mask 0x00000008
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_link_aggregator;
-
-end ipbus_decode_link_aggregator;
diff --git a/top/firmware/hdl/ipbus_decode_mprocessor.vhd b/top/firmware/hdl/ipbus_decode_mprocessor.vhd
deleted file mode 100644
index 1f97d1fac6f828b144c74d8d1cd4f4f5da6ba904..0000000000000000000000000000000000000000
--- a/top/firmware/hdl/ipbus_decode_mprocessor.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_mprocessor is
-
- constant IPBUS_SEL_WIDTH: positive := 2;
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_mprocessor(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL (Fri Aug 26 18:31:27 2022)
- constant N_SLV_LINK_AGGREGATOR: integer := 0;
- constant N_SLV_LINK_COMBINER: integer := 1;
- constant N_SLV_CSR: integer := 2;
- constant N_SLAVES: integer := 3;
--- END automatically generated VHDL
-
-
-end ipbus_decode_mprocessor;
-
-package body ipbus_decode_mprocessor is
-
- function ipbus_sel_mprocessor(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL (Fri Aug 26 18:31:27 2022)
- if std_match(addr, "--------------------------0-----") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_LINK_AGGREGATOR, IPBUS_SEL_WIDTH)); -- link_aggregator / base 0x00000000 / mask 0x00000020
- elsif std_match(addr, "--------------------------1---0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_LINK_COMBINER, IPBUS_SEL_WIDTH)); -- link_combiner / base 0x00000020 / mask 0x00000022
- elsif std_match(addr, "--------------------------1---1-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000022 / mask 0x00000022
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_mprocessor;
-
-end ipbus_decode_mprocessor;
diff --git a/top/firmware/hdl/mprocessor_constants.vhd b/top/firmware/hdl/mprocessor_constants.vhd
deleted file mode 100644
index 3a879818498d50190ee7db6eed84175a597ebae9..0000000000000000000000000000000000000000
--- a/top/firmware/hdl/mprocessor_constants.vhd
+++ /dev/null
@@ -1,11 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.dtc_link_maps.all;
-
-package mprocessor_constants is
-
- type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
-
-end package mprocessor_constants;
diff --git a/top/firmware/ucf/emp_project_constraints.tcl.old b/top/firmware/ucf/emp_project_constraints.tcl.old
deleted file mode 100644
index 3361fc7cdae4f04fd25bfb749912e17bc1f976b9..0000000000000000000000000000000000000000
--- a/top/firmware/ucf/emp_project_constraints.tcl.old
+++ /dev/null
@@ -1,321 +0,0 @@
-
-# Loop over all MGTs in GBT firmware, give their RX/TX clocks more useful names, and declare them as async to all other clocks
-foreach mgtCellPath [get_cells -hierarchical -filter NAME=~datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/gbt_gen.gbt_inst/*/*GTHE4_CHANNEL_PRIM_INST] {
- set matches [regexp -inline {datapath/rgen\[(\d+)\].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/gbt_gen.gbt_inst/.+gtxLatOpt_gen\[(\d+)\].+GTHE4_CHANNEL_PRIM_INST} $mgtCellPath]
-
- if { [llength $matches] != 3 } {
- puts "ERROR : Could not extract region and channel number from GBT RX clock pin path ''"
- exit 1
- }
-
- set regionIndex [lindex $matches 1]
- set channelIndex [lindex $matches 2]
-
- create_generated_clock -name clk_gbt_rxOut_r${regionIndex}_ch${channelIndex} $mgtCellPath/RXOUTCLK
- create_generated_clock -name clk_gbt_txOut_r${regionIndex}_ch${channelIndex} $mgtCellPath/TXOUTCLK
-
- set_clock_groups -asynchronous -group clk_gbt_rxOut_r${regionIndex}_ch${channelIndex}
- set_clock_groups -asynchronous -group clk_gbt_txOut_r${regionIndex}_ch${channelIndex}
-}
-
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/reg_no_destuffing_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_ec_data_s_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-
-#set_multicycle_path 8 -setup \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-#set_multicycle_path 7 -hold \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-#set_multicycle_path 8 -setup \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-#set_multicycle_path 7 -hold \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/D}]
-
-
-#set_multicycle_path 8 -setup \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-#set_multicycle_path 7 -hold \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-#set_multicycle_path 8 -setup \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-#set_multicycle_path 7 -hold \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-#set_multicycle_path 8 -setup \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-#set_multicycle_path 7 -hold \
-#-from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].uplink_user_data_reg[*]/C}] \
-#-to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/write_o_reg/D}]
-
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/cnter_reg[*]/R}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/D}]
-
-set_multicycle_path 8 -setup \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]
-set_multicycle_path 7 -hold \
--from [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/ongoing_reg/C}] \
--to [get_pins {datapath/rgen[*].region/mgt_gen.fe_mgt_gen.fe_mgt_inst/*/data_framers_gen[*].data_framer_inst/slow_command_ctrl_inst/sc_inst/sca_inst/sca_gen[*].rx_inst/sca_deserializer_inst/data_o_reg[*]/CE}]