diff --git a/dependencies.yml b/dependencies.yml
index 0a9518dd45c7734a8f2e9d3b66d8774a8135773c..ff69a911fde5700a346fd39624b09650f0792f0e 100644
--- a/dependencies.yml
+++ b/dependencies.yml
@@ -1,7 +1,7 @@
---
sources:
emp-fwk:
- tag: v0.7.0-alpha
+ tag: feature/daqpath_v2
url: https://gitlab.cern.ch/p2-xware/firmware/emp-fwk.git
ttc_legacy:
diff --git a/top/addr_table/emp_payload.xml b/top/addr_table/emp_payload.xml
index 2eaa7ffad503522e0fe60c40af66ecc7205788f1..12acae9558aaac50caa6c976eeff9b581fec48ed 100644
--- a/top/addr_table/emp_payload.xml
+++ b/top/addr_table/emp_payload.xml
@@ -1,6 +1,6 @@
<node description="Payload ipbus registers and RAM" fwinfo="endpoint">
- <node id="fe_ctrl" address="0x0000" description="FE channel select" fwinfo="endpoint;width=0">
+ <node id="fe" address="0x0000" description="FE channel select" fwinfo="endpoint;width=0">
<node id="chan_sel" mask="0x7f"/>
</node>
@@ -13,12 +13,14 @@
<node id="histogram1" address="0x3"/>
</node>
- <node id="fe_chan" address="0x040" description="FE channel control and status" module="file://link_interface.xml" fwinfo="endpoint;width=6"/>
+ <node id="fe_chan" address="0x040" description="FE channel control and status" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=6"/>
<node id="mproc_ctrl" address="0x1ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
<node id="chan_sel" mask="0x7f"/>
</node>
<node id="mprocessor" address="0x200" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
+
+ <node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>
<node id="mem1" address="0x1000" size="0x200" mode="incremental" fwinfo="endpoint;width=9"/>
<node id="mem2" address="0x2000" size="0x200" mode="incremental" fwinfo="endpoint;width=9"/>
diff --git a/top/firmware/cfg/top.dep b/top/firmware/cfg/top.dep
index 3c062d39ee76f45ee98d5288ea826c403ff0a0a0..1ab335d61fafefd901ee3a424e750657f8c8d334 100644
--- a/top/firmware/cfg/top.dep
+++ b/top/firmware/cfg/top.dep
@@ -3,6 +3,8 @@ setup -f --cd ../cfg settings.tcl
include -c histogram:top histogram.dep
include -c dtc:dtc-fe/2S/5G-FEC12 module.dep
include -c dtc:dtc-fe/2S/5G-FEC12 framer.dep
+include -c dtc:dtc-be/common daqpath.dep
+include -c dtc:dtc-be/common common.dep
include -c dtc-stub-processing:common tools.dep
src -c emp-fwk:components/payload ../ucf/emp_simple_payload.tcl
@@ -16,6 +18,8 @@ include -c emp-fwk:boards/serenity/dc_ku15p dc_ku15p_sm1_v1.dep
include -c emp-fwk:components/links/fe_mgt/interface interface.dep
include -c emp-fwk:components/links/fe_mgt/lpgbt/interface interface_lpgbt.dep
+? toolset.lower() == "vivado" ? setup -c emp-fwk:components/payload emp_simple_payload_msg_suppressions.tcl
+
include -c 10gb-ethernet:eth10g emp_eth10g.dep
src emp_project_decl.vhd
diff --git a/top/firmware/hdl/LinkAggregatorCore.vhd b/top/firmware/hdl/LinkAggregatorCore.vhd
index 609f1499e10917b19cd0eda63c956c51f2391cba..fbf08994a306c4f3ebf078689b7f0ad809e9583a 100644
--- a/top/firmware/hdl/LinkAggregatorCore.vhd
+++ b/top/firmware/hdl/LinkAggregatorCore.vhd
@@ -116,10 +116,11 @@ architecture compressed of LinkAggregatorCore is
function compress64bStubto32b(stub: std_logic_vector) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
- output(14 downto 0) := stub(14 downto 0);
- output(26 downto 15) := std_logic_vector(unsigned(stub(35 downto 24)) + unsigned(stub(17 downto 15)));
- output(27) := stub(46);
- output(31 downto 28) := stub(63 downto 60);
+ output(21 downto 0) := stub(21 downto 0); -- Common stub format
+ output(22) := stub(50); -- CIC Index
+ output(23) := stub(49); -- 2S/PS
+ output(27 downto 24) := stub(63 downto 60); -- Link ID
+ output(31 downto 28) := (others => '0');
return output;
end function;
@@ -149,7 +150,7 @@ begin
begin
if rising_edge(clk_p) then
wr_en_array_cache <= (others => '0');
- wr_en_array_cache(to_integer(unsigned(links_in(i).data(17 downto 15)))) <= links_in(i).valid;
+ wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid;
data_in <= std_logic_vector(to_unsigned(i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
end if;
end process pRouteInputData;
diff --git a/top/firmware/hdl/LinkCombinerCore.vhd b/top/firmware/hdl/LinkCombinerCore.vhd
index fe4df5a4fd9b2800fca5d0eaecde8daf544afe8a..54a09f1ec60364be15b0bcdc15783de00d89c54c 100644
--- a/top/firmware/hdl/LinkCombinerCore.vhd
+++ b/top/firmware/hdl/LinkCombinerCore.vhd
@@ -5,25 +5,26 @@ use work.emp_data_types.all;
use work.front_end_data_types.all;
use work.gbt_module_constants.all;
use work.dtc_link_maps.all;
+use work.dtc_data_types.all;
+use work.dtc_constants.all;
entity LinkCombinerCore is
generic (
- N_INPUT_LINKS : integer := 8;
- N_OUTPUT_LINKS : integer := 1
+ N_INPUT_LINKS : integer := 8
);
port (
--- Input Ports ---
clk_p : in std_logic;
reset : in std_logic;
output_reset : in std_logic := '0';
- output_rd_en : in std_logic_vector(N_OUTPUT_LINKS - 1 downto 0) := (others => '0');
+ output_enable : in std_logic := '0';
links_in : in ldata(N_INPUT_LINKS - 1 downto 0);
packet_start : in std_logic;
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
header_user_bits : in std_logic_vector(31 downto 0) := (others => '0');
--- Ouput Ports ---
- links_out : out ldata(N_OUTPUT_LINKS - 1 downto 0);
+ link_out : out lword := LWORD_NULL;
--- Debug Ports ---
debug : out lword := LWORD_NULL;
debug_super_id : out std_logic_vector(31 downto 0);
@@ -80,11 +81,9 @@ architecture Behavioral of LinkCombinerCore is
-- Type Definitions
type tWordArray is array(integer range <>) of std_logic_vector(cWordWidth - 1 downto 0);
- type tOutputWordArray is array(integer range <>) of std_logic_vector(cOutputWordWidth - 1 downto 0);
type tStatusShiftRegister is array(1 downto 0) of std_logic_vector(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0);
type tBCIDShiftRegister is array(1 downto 0) of std_logic_vector(12 - 1 downto 0);
type tInputDataCountArray is array(integer range <>) of std_logic_vector(5 downto 0);
- type tOutputDataCountArray is array(integer range <>) of std_logic_vector(7 downto 0);
-- Constants
constant cNullValidArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
@@ -98,12 +97,22 @@ architecture Behavioral of LinkCombinerCore is
signal input_data_valid : std_logic := '0';
signal input_data_count : tInputDataCountArray(N_INPUT_LINKS - 1 downto 0) := (others => (others => '0'));
- signal output_din_array, output_din_array_buf : tOutputWordArray(0 to N_OUTPUT_LINKS - 1) := (others => (others => '0'));
- signal output_wr_en_array, output_wr_en_array_buf, output_full_array : std_logic_vector(N_OUTPUT_LINKS - 1 downto 0) := (others => '0');
- signal output_almost_full_array, output_overflow_array : std_logic_vector(N_OUTPUT_LINKS - 1 downto 0) := (others => '0');
+ signal output_din, output_din_buf : std_logic_vector(cOutputWordWidth - 1 downto 0) := (others => '0');
+ signal output_wr_en, output_wr_en_buf, output_full : std_logic := '0';
+ signal output_almost_full, output_overflow : std_logic := '0';
signal output_pointer : integer range 0 to N_INPUT_LINKS - 1 := 0;
signal output_pointer_buffered : integer range 0 to N_INPUT_LINKS - 1 := 0;
- signal output_data_count : tOutputDataCountArray(N_OUTPUT_LINKS - 1 downto 0) := (others => (others => '0'));
+ signal output_data_count : std_logic_vector(7 downto 0) := (others => '0');
+ signal output_empty : std_logic;
+ signal output_valid : std_logic;
+ signal output_dout : std_logic_vector(cOutputWordWidth - 1 downto 0);
+ signal output_almost_empty : std_logic;
+ signal output_underflow : std_logic;
+ signal output_readout_countdown : integer range 0 to 256 := 0;
+ signal output_valid_previous : std_logic := '0';
+ signal output_strobe_buffer, output_strobe_buffer_2 : std_logic := '0';
+ signal output_rd_en_check : std_logic := '0';
+ signal output_rd_en : std_logic := '0';
signal counter : integer := 0;
signal status_sr : tStatusShiftRegister := (others => (others => '0'));
@@ -159,98 +168,78 @@ begin
end generate genInputLinkBuffers;
-
-
+
--==============================--
- genOutputLinkBuffers : for i in 0 to N_OUTPUT_LINKS - 1 generate
+ OutputLinkBufferInstance : link_combin_buffer
--==============================--
- signal empty : std_logic;
- signal valid : std_logic;
- signal dout : std_logic_vector(cOutputWordWidth - 1 downto 0);
- signal rd_en : std_logic := '0';
- signal almost_empty : std_logic;
- signal data_count : std_logic_vector(6 downto 0) := (others => '0');
- signal underflow : std_logic;
- signal readout_countdown : integer range 0 to 256 := 0;
- signal valid_previous : std_logic := '0';
- signal strobe_buffer, strobe_buffer_2 : std_logic := '0';
- signal rd_en_check : std_logic := '0';
-
- begin
+ PORT MAP (
+ clk => clk_p,
+ srst => output_reset,
+ din => output_din_buf,
+ wr_en => output_wr_en_buf,
+ rd_en => output_rd_en,
+ dout => output_dout,
+ empty => output_empty,
+ almost_full => output_almost_full,
+ full => output_full,
+ overflow => output_overflow,
+ valid => output_valid,
+ underflow => output_underflow,
+ data_count => output_data_count,
+ almost_empty => output_almost_empty
+ );
- --==============================--
- OutputLinkBufferInstance : link_combin_buffer
- --==============================--
- PORT MAP (
- clk => clk_p,
- srst => output_reset,
- din => output_din_array_buf(i),
- wr_en => output_wr_en_array_buf(i),
- rd_en => rd_en,
- dout => dout,
- empty => empty,
- almost_full => output_almost_full_array(i),
- full => output_full_array(i),
- overflow => output_overflow_array(i),
- valid => valid,
- underflow => underflow,
- data_count => output_data_count(i),
- almost_empty => almost_empty
- );
-
- --==============================--
- pOutput: process(clk_p)
- --==============================--
- variable data_count : unsigned(7 downto 0);
- begin
- if rising_edge(clk_p) then
- valid_previous <= valid;
- if valid = '1' and rd_en_check = '1' then
- links_out(i).valid <= '1';
- if valid_previous = '0' then
- links_out(i).start <= '1';
- else
- links_out(i).start <= '0';
- end if;
- links_out(i).strobe <= strobe_buffer_2;
- links_out(i).data <= dout;
+ --==============================--
+ pOutput: process(clk_p)
+ --==============================--
+ variable data_count : unsigned(7 downto 0);
+ begin
+ if rising_edge(clk_p) then
+ output_valid_previous <= output_valid;
+ if output_valid = '1' and output_rd_en_check = '1' then
+ link_out.valid <= '1';
+ if output_valid_previous = '0' then
+ link_out.start <= '1';
else
- links_out(i) <= LWORD_NULL;
+ link_out.start <= '0';
end if;
-
- data_count := unsigned(output_data_count(i));
- if input_data_valid = '0' then
- if data_count >= 2 and readout_countdown = 0 then
- rd_en_check <= output_rd_en(i);
- readout_countdown <= to_integer(data_count);
- elsif output_almost_full_array(i) = '1' and readout_countdown = 0 then
- rd_en_check <= output_rd_en(i);
- readout_countdown <= to_integer(data_count);
- end if;
- else
- if output_almost_full_array(i) = '1' and readout_countdown = 0 then
- rd_en_check <= output_rd_en(i);
- readout_countdown <= to_integer(data_count);
- end if;
+ link_out.strobe <= output_strobe_buffer_2;
+ link_out.data <= output_dout;
+ else
+ link_out <= LWORD_NULL;
+ end if;
+
+ data_count := unsigned(output_data_count);
+ if input_data_valid = '0' then
+ if data_count >= 2 and output_readout_countdown = 0 then
+ output_rd_en_check <= output_enable;
+ output_readout_countdown <= to_integer(data_count);
+ elsif output_almost_full = '1' and output_readout_countdown = 0 then
+ output_rd_en_check <= output_enable;
+ output_readout_countdown <= to_integer(data_count);
end if;
- if readout_countdown > 0 then
- readout_countdown <= readout_countdown - 1;
- rd_en <= '1';
- if readout_countdown = 1 then
- strobe_buffer <= '1';
- else
- strobe_buffer <= '0';
- end if;
+ else
+ if output_almost_full = '1' and output_readout_countdown = 0 then
+ output_rd_en_check <= output_enable;
+ output_readout_countdown <= to_integer(data_count);
+ end if;
+ end if;
+ if output_readout_countdown > 0 then
+ output_readout_countdown <= output_readout_countdown - 1;
+ output_rd_en <= '1';
+ if output_readout_countdown = 1 then
+ output_strobe_buffer <= '1';
else
- rd_en <= '0';
- strobe_buffer <= '0';
+ output_strobe_buffer <= '0';
end if;
-
- strobe_buffer_2 <= strobe_buffer;
+ else
+ output_rd_en <= '0';
+ output_strobe_buffer <= '0';
end if;
- end process pOutput;
-
- end generate genOutputLinkBuffers;
+
+ output_strobe_buffer_2 <= output_strobe_buffer;
+ end if;
+ end process pOutput;
@@ -311,8 +300,8 @@ begin
end if;
end if;
output_pointer_buffered <= output_pointer;
- output_din_array(0) <= input_dout_array(output_pointer_buffered);
- output_wr_en_array(0) <= input_valid_array(output_pointer_buffered);
+ output_din <= input_dout_array(output_pointer_buffered);
+ output_wr_en <= input_valid_array(output_pointer_buffered);
if reset = '1' then
@@ -331,27 +320,28 @@ begin
end if;
if counter = 1 then
- output_wr_en_array_buf(0) <= '1';
- output_din_array_buf(0)(63 downto 32) <= header_user_bits;
- output_din_array_buf(0)(31 downto 0) <= std_logic_vector(super_id);
+ output_wr_en_buf <= '1';
+ output_din_buf(63 downto 32) <= header_user_bits;
+ output_din_buf(31 downto 0) <= std_logic_vector(super_id);
elsif counter = 2 then
- output_din_array_buf(0) <= (others => '0');
- output_din_array_buf(0)(63 downto 56) <= std_logic_vector(packet_stub_count_previous);
- output_wr_en_array_buf(0) <= '1';
- if cNumberOfFEModules < 4 then
- output_din_array_buf(0)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high);
+ output_din_buf <= (others => '0');
+ output_din_buf(63 downto 56) <= std_logic_vector(packet_stub_count_previous);
+ output_din_buf(47 downto 36) <= bcid_sr(bcid_sr'high);
+ output_wr_en_buf <= '1';
+ if cNumberOfFEModules < 3 then
+ output_din_buf(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high);
else
- output_din_array_buf(0)(3 * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(3 * cNumberOfCICs * 9 - 1 downto 0);
+ output_din_buf(2 * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(2 * cNumberOfCICs * 9 - 1 downto 0);
end if;
elsif counter = 3 then
- output_din_array_buf(0) <= (others => '0');
- output_wr_en_array_buf(0) <= '1';
- if cNumberOfFEModules >= 4 then
- output_din_array_buf(0)((cNumberOfFEModules - 3) * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 3 * cNumberOfCICs * 9);
+ output_din_buf <= (others => '0');
+ output_wr_en_buf <= '1';
+ if cNumberOfFEModules >= 3 and cNumberOfFEModules < 6 then
+ output_din_buf((cNumberOfFEModules - 2) * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 2 * cNumberOfCICs * 9);
end if;
else
- output_wr_en_array_buf <= output_wr_en_array;
- output_din_array_buf(0) <= output_din_array(0);
+ output_wr_en_buf <= output_wr_en;
+ output_din_buf <= output_din;
end if;
end if;
@@ -361,7 +351,6 @@ begin
--==============================--
pBufferHeader: process(clk_p)
--==============================--
- variable status0, status1 : std_logic_vector(cNumberOfFEModules * 9 - 1 downto 0) := (others => '0');
variable status : std_logic_vector(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) := (others => '0');
variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
begin
@@ -371,10 +360,9 @@ begin
else
if packet_start = '1' then
for i in cNumberOfFEModules - 1 downto 0 loop
- status0(i*9 + 9 - 1 downto i*9) := std_logic_vector(header_in(i*cNumberOfCICs).status);
- status1(i*9 + 9 - 1 downto i*9) := std_logic_vector(header_in(i*cNumberOfCICs + 1).status);
+ status(i*cNumberOfCICs*9 + 8 downto i*cNumberOfCICs*9) := std_logic_vector(header_in(i*cNumberOfCICs).status);
+ status(i*cNumberOfCICs*9 + 17 downto i*cNumberOfCICs*9 + 9) := std_logic_vector(header_in(i*cNumberOfCICs + 1).status);
end loop;
- status := status0 & status1;
status_sr <= status_sr(status_sr'high - 1 downto 0) & status;
bcid := std_logic_vector(header_in(0).bcid);
bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
@@ -390,19 +378,19 @@ begin
-- Debug
--==============================--
debug.data(31 downto 0) <= std_logic_vector(super_id);
- debug.data(39 downto 32) <= output_data_count(0);
+ debug.data(39 downto 32) <= output_data_count;
debug.data(47 downto 40) <= "00" & input_data_count(0);
debug.data(51 downto 48) <= std_logic_vector(to_unsigned(counter, 4));
- debug.data(52) <= output_rd_en(0);
+ debug.data(52) <= output_rd_en;
debug.data(56) <= packet_start;
debug.data(57) <= reset;
debug.data(58) <= input_data_valid;
debug.valid <= '1';
debug.strobe <= '1';
debug_super_id <= std_logic_vector(super_id);
- debug_fifo(7 downto 0) <= output_data_count(0);
- debug_fifo(8) <= output_full_array(0);
- debug_fifo(9) <= output_rd_en(0);
- debug_fifo(10) <= output_overflow_array(0);
+ debug_fifo(7 downto 0) <= output_data_count;
+ debug_fifo(8) <= output_full;
+ debug_fifo(9) <= output_rd_en;
+ debug_fifo(10) <= output_overflow;
end Behavioral;
diff --git a/top/firmware/hdl/LinkCombinerIPBus.vhd b/top/firmware/hdl/LinkCombinerIPBus.vhd
index 1ceb50e1d2f2b2876f663d2e44b10dfd3c3fd617..e551dd4996b14aa11800c93a01927d4b307ef2ef 100644
--- a/top/firmware/hdl/LinkCombinerIPBus.vhd
+++ b/top/firmware/hdl/LinkCombinerIPBus.vhd
@@ -9,6 +9,8 @@ use work.ipbus_reg_types.all;
use work.front_end_data_types.all;
use work.gbt_module_constants.all;
use work.dtc_link_maps.all;
+use work.dtc_data_types.all;
+use work.dtc_constants.all;
entity LinkCombinerIPBus is
@@ -24,7 +26,7 @@ entity LinkCombinerIPBus is
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
lff : in std_logic;
--- Ouput Ports ---
- links_out : out ldata(1 - 1 downto 0);
+ link_out : out lword := LWORD_NULL;
--- IPBus Ports ---
ipb_clk : in std_logic;
ipb_rst : in std_logic;
@@ -36,7 +38,7 @@ end LinkCombinerIPBus;
architecture Behavioral of LinkCombinerIPBus is
signal link_combiner_debug : lword := LWORD_NULL;
- signal link_combiner_rd_en : std_logic_vector(0 downto 0) := "0";
+ signal link_combiner_rd_en : std_logic := '0';
signal link_combiner_debug_super_id : std_logic_vector(31 downto 0);
signal masked_stubs : ldata(cNumberOfFEModules - 1 downto 0) := (others => LWORD_NULL);
signal masked_input : ldata(8 - 1 downto 0) := (others => LWORD_NULL);
@@ -85,9 +87,7 @@ begin
--==============================--
begin
if rising_edge(clk_p) then
- for i in 0 downto 0 loop
- link_combiner_rd_en(i) <= not lff and control_registers(0)(N_INPUT_LINKS + 2 - 1);
- end loop;
+ link_combiner_rd_en <= not lff and control_registers(0)(N_INPUT_LINKS + 2 - 1);
end if;
end process pReadEnable;
@@ -102,13 +102,13 @@ begin
clk_p => clk_p,
reset => reset,
output_reset => control_registers(0)(N_INPUT_LINKS + 1 - 1),
- output_rd_en => link_combiner_rd_en,
+ output_enable => link_combiner_rd_en,
links_in => masked_input,
packet_start => packet_start,
header_in => header_in,
header_user_bits => control_registers(1),
--- Output Ports ---
- links_out => links_out
+ link_out => link_out
--- Debug Ports ---
-- debug => link_combiner_debug,
-- debug_super_id => link_combiner_debug_super_id,
diff --git a/top/firmware/hdl/MProcessor.vhd b/top/firmware/hdl/MProcessor.vhd
index 8922ea9e9be537663ecb19e39fde38bf39061106..f9b3a4d1c3973bb0648bf5e25f3512a039cbbbbd 100644
--- a/top/firmware/hdl/MProcessor.vhd
+++ b/top/firmware/hdl/MProcessor.vhd
@@ -12,6 +12,8 @@ use work.dtc_link_maps.all;
use work.front_end_data_types.all;
use work.gbt_module_constants.all;
use work.mprocessor_constants.all;
+use work.dtc_data_types.all;
+use work.dtc_constants.all;
entity MProcessor is
@@ -45,7 +47,6 @@ architecture Behavorial of MProcessor is
signal readout_reset : std_logic := '0';
signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL);
signal link_aggregator_input : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
- signal eth_link_out : ldata(0 downto 0) := (others => LWORD_NULL);
signal status_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
@@ -124,7 +125,7 @@ begin
header_in => header_in,
lff => gbe_backpressure,
--- Output Ports ---
- links_out => eth_link_out,
+ link_out => link_out,
--- IPBus Ports ---
ipb_clk => ipb_clk,
ipb_rst => ipb_rst,
@@ -142,7 +143,6 @@ begin
-- );
link_aggregator_input(N_LINKS - 1 downto 0) <= links_in;
- link_out <= eth_link_out(0);
status_registers(0)(0) <= gbe_backpressure;
packet_start <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0);
diff --git a/top/firmware/hdl/emp_payload.vhd b/top/firmware/hdl/emp_payload.vhd
index 55f212c698eead19b56b66d0c27a2ffbb047c644..d156d95d35240bc95a0cf350e2f9c224bb39ca86 100644
--- a/top/firmware/hdl/emp_payload.vhd
+++ b/top/firmware/hdl/emp_payload.vhd
@@ -16,6 +16,8 @@ use work.dtc_link_maps.all;
use work.front_end_data_types.all;
use work.gbt_module_constants.all;
use work.mprocessor_constants.all;
+use work.dtc_data_types.all;
+use work.dtc_constants.all;
entity emp_payload is
@@ -48,50 +50,57 @@ end emp_payload;
architecture rtl of emp_payload is
--- IPBus fabric
+ -- IPBus fabric
-signal ipb_to_slaves : ipb_wbus_array(N_SLAVES - 1 downto 0);
-signal ipb_from_slaves : ipb_rbus_array(N_SLAVES - 1 downto 0);
+ signal ipb_to_slaves : ipb_wbus_array(N_SLAVES - 1 downto 0);
+ signal ipb_from_slaves : ipb_rbus_array(N_SLAVES - 1 downto 0);
-signal channel_sel : ipb_reg_v(0 downto 0);
-signal mproc_channel_sel : ipb_reg_v(0 downto 0);
-signal link_aggr_control : ipb_reg_v(0 downto 0);
+ signal channel_sel : ipb_reg_v(0 downto 0);
+ signal mproc_channel_sel : ipb_reg_v(0 downto 0);
+ signal link_aggr_control : ipb_reg_v(0 downto 0);
--- FE data extraction and monitoring
+ -- FE data extraction and monitoring
-signal ipb_chain : ipbdc_bus_array(cNumberOfFEModules downto 0);
-signal stubs : ldata(cNumberOfFEModules - 1 downto 0);
+ signal ipb_chain : ipbdc_bus_array(cNumberOfFEModules downto 0);
+ signal stubs : ldata(cNumberOfFEModules - 1 downto 0);
-signal linksout : ldata(cNumberOfFEModules - 1 downto 0);
-signal linkor : lword := LWORD_NULL;
+ signal linksout : ldata(cNumberOfFEModules - 1 downto 0);
+ signal linkor : lword := LWORD_NULL;
--- Histogrammer
+ -- Histogrammer
-constant N_CTRL_HIST : integer := 2;
-constant N_STAT_HIST : integer := 2;
+ constant N_CTRL_HIST : integer := 2;
+ constant N_STAT_HIST : integer := 2;
-constant bin_width : integer := 32;
-constant input_width : integer := 9;
+ constant bin_width : integer := 32;
+ constant input_width : integer := 9;
-signal status_registers : ipb_reg_v(N_STAT_HIST - 1 downto 0) := (others => (others => '0'));
-signal control_registers : ipb_reg_v(N_CTRL_HIST - 1 downto 0) := (others => (others => '0'));
+ signal status_registers : ipb_reg_v(N_STAT_HIST - 1 downto 0) := (others => (others => '0'));
+ signal control_registers : ipb_reg_v(N_CTRL_HIST - 1 downto 0) := (others => (others => '0'));
-signal trigger_window_lower : std_logic_vector(31 downto 0) := (others => '0');
-signal trigger_window_upper : std_logic_vector(3 downto 0) := (others => '0');
-signal trigger_window : std_logic_vector(36 - 1 downto 0) := X"0ffffffff";
-signal max_value0, max_value1 : std_logic_vector(bin_width - 1 downto 0) := (others => '0');
-signal histogram_reset : std_logic := '0';
-signal hist0_stub, hist1_stub : lword := LWORD_NULL;
-signal histogram_sel : integer := 0;
-signal histogram_enable : std_logic := '0';
-signal header_start_array : tHeaderStartArray := (others => (others => '0'));
+ signal trigger_window_lower : std_logic_vector(31 downto 0) := (others => '0');
+ signal trigger_window_upper : std_logic_vector(3 downto 0) := (others => '0');
+ signal trigger_window : std_logic_vector(36 - 1 downto 0) := X"0ffffffff";
+ signal max_value0, max_value1 : std_logic_vector(bin_width - 1 downto 0) := (others => '0');
+ signal histogram_reset : std_logic := '0';
+ signal hist0_stub, hist1_stub : lword := LWORD_NULL;
+ signal histogram_sel : integer := 0;
+ signal histogram_enable : std_logic := '0';
+ signal header_start_array : tHeaderStartArray := (others => (others => '0'));
+ signal eth_link_out : ldata(1 downto 0) := (others => LWORD_NULL);
-signal header_array : tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+ signal header_array : tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
--- MProcessor
-constant cNumberOfMProcessors : integer := 1;
-signal mprocessor_ipb_chain : ipbdc_bus_array(cNumberOfMProcessors downto 0);
+ -- MProcessor
+ constant cNumberOfMProcessors : integer := 1;
+ signal mprocessor_ipb_chain : ipbdc_bus_array(cNumberOfMProcessors downto 0);
+
+ -- Daqpath
+
+ signal daq_read : tDaqFlagLinkArray(cNumberOfFEModules - 1 downto 0);
+ signal daq_data : tDaqDataLinkArray(cNumberOfFEModules - 1 downto 0);
+ signal daq_empty : tDaqFlagLinkArray(cNumberOfFEModules - 1 downto 0);
begin
@@ -199,32 +208,35 @@ begin
--==============================--
LinkInterfaceInstance: entity work.LinkInterface
--==============================--
- port map(
+ generic map (
+ module_type => "2S"
+ )
+ port map (
--- Input Ports ---
- clk_p => clk_p,
- link_in => d(cDTCInputLinkMap(i)),
+ clk_p => clk_p,
+ link_in => d(cDTCInputLinkMap(i)),
+ daq_read => daq_read(i),
--- Output Ports ---
- --link_out => q(cDTCInputLinkMap(i)),
- link_out => linksout(i),
- stub_out => stubs(i),
+ link_out => linksout(i),
+ stub_out => stubs(i),
+ daq_out => daq_data(i),
+ daq_empty => daq_empty(i),
header_out => header_array(cNumberOfCICs * i + cNumberOfCICs - 1 downto cNumberOfCICs * i),
--- IPBus Ports ---
- clk => clk,
- rst => rst,
- ipb_in => ipb_to_channel,
- ipb_out => ipb_from_channel,
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_channel,
+ ipb_out => ipb_from_channel,
--- Debug Ports ---
- debug_header_start => header_start_array(i),
- debug_header_match => q(i+30).data(5 downto 4),
- debug_aligner_state => q(i+30).data(13 downto 8)
- );
+ debug_header_start => header_start_array(i)
+ );
end generate;
linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0); --or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0);
--==============================--
-hack: for i in 0 to cNumberOfFEModules - 1 generate
+genHack: for i in 0 to cNumberOfFEModules - 1 generate
--==============================--
begin
@@ -233,6 +245,28 @@ begin
end generate;
+--==============================--
+-- L1 Data Aggregator
+--==============================--
+
+--==============================--
+L1DataAggregator : entity work.L1DataAggregator
+--==============================--
+port map (
+ --- Input Ports ---
+ clk_p => clk_p,
+ daq_in => daq_data,
+ empty => daq_empty,
+ --- Output Ports ---
+ read => daq_read,
+ --- IPBus Ports ---
+ clk => clk,
+ rst => rst,
+ ipb_in => ipb_to_slaves(N_SLV_BE_DAQ),
+ ipb_out => ipb_from_slaves(N_SLV_BE_DAQ)
+);
+
+
--==============================--
-- Histogrammer
--==============================--
@@ -292,7 +326,7 @@ HistogramInstance0: entity work.IPBusHistogram
generic map(
input_width => input_width,
bin_width => bin_width,
- data_offset => 6 -- 7 for converted stubs
+ data_offset => 10
)
port map(
--- Input Ports ---
@@ -365,7 +399,10 @@ port map(
ipbdc_in => mprocessor_ipb_chain(cNumberOfMProcessors)
);
+
+--==============================-
genMProcessors : for i in 0 to cNumberOfMProcessors - 1 generate
+--==============================-
signal ipb_to_channel : ipb_wbus;
signal ipb_from_channel : ipb_rbus;
@@ -404,7 +441,7 @@ begin
header_start_array => header_start_array,
gbe_backpressure => gbe_backpressure(i),
--- Output Ports ---
- link_out => gbe_q(i),
+ link_out => eth_link_out(i),
--- IPBus Ports ---
ipb_clk => clk,
ipb_rst => rst,
@@ -413,6 +450,9 @@ begin
);
end generate genMProcessors;
+
+gbe_q <= eth_link_out;
+
bc0 <= '0';
gpio <= (others => '0');
gpio_en <= (others => '0');
diff --git a/top/firmware/hdl/ipbus_decode_emp_payload.vhd b/top/firmware/hdl/ipbus_decode_emp_payload.vhd
index 67da9d568ed2cbb86910acca8e505f877e48cb53..65092e3b64596d93dcd94d8e93b647f11dbbffac 100644
--- a/top/firmware/hdl/ipbus_decode_emp_payload.vhd
+++ b/top/firmware/hdl/ipbus_decode_emp_payload.vhd
@@ -13,11 +13,11 @@ use ieee.numeric_std.all;
package ipbus_decode_emp_payload is
- constant IPBUS_SEL_WIDTH: positive := 3;
+ constant IPBUS_SEL_WIDTH: positive := 4;
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_emp_payload(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
--- START automatically generated VHDL (Thu Sep 1 14:33:48 2022)
+-- START automatically generated VHDL (Wed Sep 7 13:15:33 2022)
constant N_SLV_FE_CTRL: integer := 0;
constant N_SLV_CSR: integer := 1;
constant N_SLV_FE_CHAN: integer := 2;
@@ -25,7 +25,8 @@ package ipbus_decode_emp_payload is
constant N_SLV_MPROCESSOR: integer := 4;
constant N_SLV_MEM1: integer := 5;
constant N_SLV_MEM2: integer := 6;
- constant N_SLAVES: integer := 7;
+ constant N_SLV_BE_DAQ: integer := 7;
+ constant N_SLAVES: integer := 8;
-- END automatically generated VHDL
@@ -37,21 +38,23 @@ package body ipbus_decode_emp_payload is
variable sel: ipbus_sel_t;
begin
--- START automatically generated VHDL (Thu Sep 1 14:33:48 2022)
- if std_match(addr, "------------------00--0000000000") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CTRL, IPBUS_SEL_WIDTH)); -- fe_ctrl / base 0x00000000 / mask 0x000033ff
- elsif std_match(addr, "------------------00--00000001--") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000004 / mask 0x000033fc
- elsif std_match(addr, "------------------00--0001------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CHAN, IPBUS_SEL_WIDTH)); -- fe_chan / base 0x00000040 / mask 0x000033c0
- elsif std_match(addr, "------------------00--0111111111") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MPROC_CTRL, IPBUS_SEL_WIDTH)); -- mproc_ctrl / base 0x000001ff / mask 0x000033ff
- elsif std_match(addr, "------------------00--100-------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MPROCESSOR, IPBUS_SEL_WIDTH)); -- mprocessor / base 0x00000200 / mask 0x00003380
- elsif std_match(addr, "------------------01--0---------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MEM1, IPBUS_SEL_WIDTH)); -- mem1 / base 0x00001000 / mask 0x00003200
- elsif std_match(addr, "------------------10--0---------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_MEM2, IPBUS_SEL_WIDTH)); -- mem2 / base 0x00002000 / mask 0x00003200
+-- START automatically generated VHDL (Wed Sep 7 13:15:33 2022)
+ if std_match(addr, "-0----------------00--0000000000") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CTRL, IPBUS_SEL_WIDTH)); -- fe_ctrl / base 0x00000000 / mask 0x400033ff
+ elsif std_match(addr, "-0----------------00--00000001--") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000004 / mask 0x400033fc
+ elsif std_match(addr, "-0----------------00--0001------") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CHAN, IPBUS_SEL_WIDTH)); -- fe_chan / base 0x00000040 / mask 0x400033c0
+ elsif std_match(addr, "-0----------------00--0111111111") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_MPROC_CTRL, IPBUS_SEL_WIDTH)); -- mproc_ctrl / base 0x000001ff / mask 0x400033ff
+ elsif std_match(addr, "-0----------------00--100-------") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_MPROCESSOR, IPBUS_SEL_WIDTH)); -- mprocessor / base 0x00000200 / mask 0x40003380
+ elsif std_match(addr, "-0----------------01--0---------") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_MEM1, IPBUS_SEL_WIDTH)); -- mem1 / base 0x00001000 / mask 0x40003200
+ elsif std_match(addr, "-0----------------10--0---------") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_MEM2, IPBUS_SEL_WIDTH)); -- mem2 / base 0x00002000 / mask 0x40003200
+ elsif std_match(addr, "-1------------------------------") then
+ sel := ipbus_sel_t(to_unsigned(N_SLV_BE_DAQ, IPBUS_SEL_WIDTH)); -- be_daq / base 0x40000000 / mask 0x40000000
-- END automatically generated VHDL
else
diff --git a/top/firmware/hdl/mprocessor_constants.vhd b/top/firmware/hdl/mprocessor_constants.vhd
index 90f2f75fb2499e65ab77d2c5c22bf05e87624425..3a879818498d50190ee7db6eed84175a597ebae9 100644
--- a/top/firmware/hdl/mprocessor_constants.vhd
+++ b/top/firmware/hdl/mprocessor_constants.vhd
@@ -8,4 +8,4 @@ package mprocessor_constants is
type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
-end package mprocessor_constants;
\ No newline at end of file
+end package mprocessor_constants;