Communication Test for each Chip before Full and Fast Sequence

Implementation of a communication check after the LV is turned on into the Common_FullPerformance_Test and Common_FullPerformance_Test_Fast sequences

I often encounter communication problems after LV is turned off. When I start the tuning process, I first check communication with the module by hand and make sure, that the communication to all 4 chips is stable. When I start the tuning sequence, while LV is still on, Dirigent turns it off and then on again. This causes the communication error to one or more chips. Dirigent then turns on HV and ramps up to -350V. The ramp up of HV takes quite a while. But you can only see the communication when the first step of the tuning sequence starts, i.e. after the ramp up of HV and PixelAlive_Analog. When I see that the communication failed to one or more chips, I have to abort it and wait again until HV is ramped down. This again takes some time. Afterwards, I have to restore the communication by hand and go through the ramp up of HV again and check the communication afterwards again. And if it is still not working, aborting it again and so on (I think you get the procedure). So it would be good to have a communication check first after LV is turned on and before HV is turned on. In addition, it should also check for the error Empty FIFO... that comes up when checking for communication for each chip. The best would be, in the sequence, if the communication to at least one chip fails, turns of LV and then on again, until there is a stable communication to all four chips per module.