Set Sbits differential pair timing parameters after OH FPGA programming

Summary

In GE1/1, and likely in GE2/1 and ME0, the Sbits differential pair delays and polarities are different between GEB types (long/short, m[1-8],...) For GE1/1, two OH firmware flavors are built; this is not the case for GE1/1 (yet? ever?)

The various settings can be changed through those registers:

GEM_AMC.OH.OHX.FPGA.TRIG.TIMING.TAP_DELAY_VFATY_BITZ, Sbits tap delays; there are NOH * NVFAT * 8 registers in total (each VFAT has 8 Sbits differential pairs)
GEM_AMC.OH.OHX.FPGA.TRIG.TIMING.SOT_TAP_DELAY_VFATY, SOT (start of transmission) tap delay; there are NOH * NVFAT registers
GEM_AMC.OH.OHX.FPGA.TRIG.CTRL.SOT_INVERT, there are NOH registers
GEM_AMC.OH.OHX.FPGA.TRIG.CTRL.VFATY_TU_INVERT, there are NOH * NVFAT registers

Where X, Y and Z are integers respectively specifying OH number, VFAT position, and Sbits different pair number.

With the aim of optimizing the FPGA PROMless programming during the hard reset sequence, a single OH firmware per back-end board is preferred. Therefore, the Sbits differential pair parameter registers must be "manually" written to the front-end. This can be done through single writes before the blaster becomes available and then through the blaster once it is avaible.

A different, but related issue is about the Sbit-to-strip mapping itself. This issue can be treated differently since work in on-going to embed relevant Sbit-to-strip mappings into the same OH firmware.

What is the expected correct behavior?

The right Sbit timing parameters are set after OH FPGA programming depending on the chamber length, in general. Or, depending on the actual chamber, if per-chamber parameters are required.