According to AMBA AXI and ACE Protocol Specification, the RVALID and BVALID signals must be asserted one clock cycle after other channels READY signals. Xilinx AXI4-Lite IPIF is also implemented that way (https://www.xilinx.com/support/documentation/ip_documentation/axi_lite_ipif/v3_0/pg155-axi-lite-ipif.pdf).
AMBA AXI and ACE Protocol Specification, A3.3.1:
- Read transaction dependencies: The slave must wait for both ARVALID and ARREADY to be asserted before it asserts RVALID to indicate that valid data is available.
- AXI4 and AXI5 write transaction dependencies: The slave must wait for AWVALID, AWREADY, WVALID, and WREADY to be asserted before asserting BVALID.
Possible regression: generates invalid read transactions if read pipelining is totally disabled on registers (but works fine if disabled on an interface which takes an extra clock cycle to respond, or if at least rd-in or rd-out is enabled on registers).