Cheby is a file format to describe the interface between hardware and software, and a set of tools to generate HDL, C headers, drivers, or documentation from these files.
You first need to convert your map(s) using
gena2cheby which accepts an XML file and generate a YAML file on the standard output. Then using a dedicated code generator of
cheby, you can generate the VHDL. This VHDL is almost identical the the VHDL file generated by Gena; some whitespaces change.
Cheby for HDL designers presentation (2019-03-25) Cheby-for-hdl.pdf
Mailing list: email@example.com
Automatically generating code from a description is certainly not a new idea and there are many existing tools with similar features. Here is a non-exhaustive list.
wbgen (from CERN BE-CO-HT). One of the predecessor of Cheby. It can directly generate cross clock-domain logic, FIFOs and an interrupt controller. But it was limited to WB bus and cannot handle hierarchy of designs.
Cheburashka + Gena (from CERN BE-RF and CERN BE-BI). Also a predecessor of Cheby. The input file is XML, which is seen as difficult to write by hand and to read; this was mitigated by a graphical editor. It supports many features commonly used at CERN (but not outside), including its non-standard bus.
bitvis.no Register Wizard. A commercial (and non open source) tool with a JSON input.
IP-xact. A standard using XML files to describe interface, including the registers. Not widely used or used with many private extensions.
SystemRDL. Register Description Language. A standard that is apparently not used.
airhdl. A nice web site that can generate hdl and doc, but closed-source.
LiTex is able to generate register map by extracting the registers from the python description.
|2017-11-10||Start of the project|