Commit 0ec6853f authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@747 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent dd271518
......@@ -765,8 +765,8 @@ U1_setpoints: setpoints PORT MAP(
CavQ => cavQR,
ErrI => cavIErr,
ErrQ => cavQErr,
OutI => cavIFF,
OutQ => cavQFF,
OutI => cavIToMod,
OutQ => cavQToMod,
AddrFromRM => rmAddrToRAM,
DataToRM => diagDataToRM,
DataToRMValid => diagDataValid,
......@@ -913,9 +913,9 @@ U0_snapshots: snapshots PORT MAP(
LrnIOut => registers(LRNDIAGIR),
LrnQIn => cavQC,
LrnQOut => registers(LRNDIAGQR),
OutIIn => cavIFF,
OutIIn => cavIToMod,
OutIOut => registers(OUTDIAGIR),
OutQIn => cavQFF,
OutQIn => cavQToMod,
OutQOut => registers(OUTDIAGQR)
);
......
......@@ -16,12 +16,12 @@ entity PIControllerCW is
SetPoints : in std_logic_vector(13 downto 0);
SetPointsValid : in std_logic;
DataOut : out std_logic_vector(13 downto 0);
DataOutSat: out std_logic_vector(13 downto 0);
DataOutSat: out std_logic_vector(28 downto 0);
KP : out std_logic_vector(15 downto 0);
KI : out std_logic_vector(15 downto 0);
PropOut : out std_logic_vector(13 downto 0);
IntOut : out std_logic_vector(13 downto 0);
LongIntOut: out std_logic_vector(17 downto 0);
LongIntOut: out std_logic_vector(26 downto 0);
ErrorOut : out std_logic_vector(13 downto 0));
end PIControllerCW;
......@@ -42,8 +42,9 @@ signal integral19: signed(18 downto 0);
signal integrateOn: std_logic;
signal propOutAux, intOutAux, dataOutAux14, error14, kiErrorSat: signed(13 downto 0);
signal dataOutAux15: signed(14 downto 0);
signal dataSatAux: signed(19 downto 0);
signal intOutLongAux: signed(18 downto 0);
signal dataSatAux: signed(28 downto 0);
signal intOutLongAux: signed(27 downto 0);
signal propOutLongAux: signed(21 downto 0);
signal intHigh, intLow: signed(13 downto 0);
begin
......@@ -56,7 +57,7 @@ intLow <= '0' & integral27(12 downto 0);
kiErrorAux <= (kiErrorHigh & "0000000000000") + ("0000000000000" & kiErrorLow);
kiError <= kiErrorAux(40 downto 13);
LongIntOut <= std_logic_vector(integral18);
LongIntOut <= std_logic_vector(integral27);
dataInSigned <= signed(DataIn);
error15 <= (resize(currentSP, error15'length) - resize(dataInSigned, error15'length))
......@@ -64,12 +65,13 @@ error15 <= (resize(currentSP, error15'length) - resize(dataInSigned, error15'len
-- propOutAux <= kpError(27 downto 14);
intOutAux <= kiErrorSat;
intOutLongAux <= kiErrorLong(31 downto 13);
intOutLongAux <= kiError;
propOutLongAux <= kpError(27 downto 6);
dataOutAux15 <= resize(intOutAux, dataOutAux15'length) +
resize(propOutAux, dataOutAux15'length);
dataSatAux <= resize(intOutLongAux, dataSatAux'length) +
resize(propOutAux, dataSatAux'length);
resize(propOutLongAux, dataSatAux'length);
DataOut <= std_logic_vector(dataOutAux14);
integral14 <= integral27(26 downto 13);
......@@ -196,7 +198,7 @@ end process Sum;
SatSum: process(Clk40)
begin
if Clk40'event and Clk40='1' then
DataOutSat <= std_logic_vector(dataOutAux15(14 downto 1));
DataOutSat <= std_logic_vector(dataSatAux);
end if;
end process SatSum;
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment