Commit 19bec96a authored by Pablo Alvarez's avatar Pablo Alvarez Committed by Dimitris Lampridis
Browse files

Desing files as stored in SVN and EDMS

git-svn-id: https://www.ohwr.org/svn/lrfsc/trunk@1 6473569e-ccbe-4206-bb48-f381304e9851
parent 514ca5a4
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JDF G
// Created by Project Navigator ver 1.0
PROJECT RFControl
DESIGN rfcontrol
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v2000
DEVICETIME 315558000
DEVPKG fg676
DEVPKGTIME 315558000
DEVSPEED -4
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL Synplify (VHDL)
SYNTHESISTOOLTIME 1088520530
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\sources\mul2x2.vhd
SOURCE ..\sources\ClockManager.vhd
SOURCE ..\sources\LedsTest.vhd
SOURCE ..\sources\SineCosine.vhd
SOURCE ..\sources\iqdemod.vhd
SOURCE ..\sources\ResControl.vhd
SOURCE ..\sources\CavityControl.vhd
SOURCE ..\sources\VmeIntfce.vhd
SOURCE ..\sources\IQModulator.vhd
SOURCE ..\sources\IrqControl.vhd
SOURCE ..\sources\IQCounter.vhd
SOURCE ..\sources\RegistersMap.vhd
SOURCE ..\sources\VMEDecoder.vhd
SOURCE ..\sources\Commands.vhd
SOURCE ..\sources\RAMManager.vhd
SOURCE ..\sources\SetPoints.vhd
SOURCE ..\sources\PIController.vhd
SOURCE ..\sources\Snapshots.vhd
SOURCE ..\sources\FeedForward.vhd
SOURCE ..\sources\Diagnostics.vhd
SOURCE ..\sources\SatControl.vhd
SOURCE ..\sources\OneShot.vhd
SOURCE ..\sources\CavityControlCW.vhd
SOURCE ..\sources\PIControllerCW.vhd
SOURCE ..\sources\SatControlCW.vhd
SOURCE ..\sources\iqdemodcw.vhd
DEPASSOC ledstest ..\sources\ledsconstraints.ucf
DEPASSOC cavitycontrol ..\sources\cavityconstraints.ucf
DEPASSOC cavitycontrolcw ..\sources\cavityCWconstraints.ucf
[Normal]
p_AutoGenFile=synvhd, virtex2, Implementation.t_genImpactFile, 1068747285, True
p_ChainDescFile=synvhd, virtex2, Implementation.t_genImpactFile, 1087824130,
xilxMapCoverMode=synvhd, virtex2, VHDL.t_map, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, VHDL.t_map, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, VHDL.t_map, 1070037511, False
xilxMapTimingDrivenPacking=synvhd, virtex2, VHDL.t_map, 1088672628, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1049383307, Medium
_SynthFrequency=synvhd, virtex2, Synthesis.t_synthesize, 1049879617, 40
_SynthResourceSharing=synvhd, virtex2, Synthesis.t_synthesize, 1070036051, True
[STATUS-ALL]
cavitycontrolcw.ncdFile=WARNINGS,1089114860
cavitycontrolcw.ngdFile=WARNINGS,1089107262
[STRATEGY-LIST]
Normal=True
JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode PFF */
/* Mode BS */
/* Mode SS */
/* Mode SM */
/* Mode BSFILE */
/* Mode HW140 */
/* Supermode FileMode */
/* ConfigDevice PFF "xcf08p" 0 0 */
/* PromDevice "xcf08p" 1048576 */
/* Serial */
/* ConfigDevicePath ("c:\fpgadesigns\rfcontrol\xilinx/") */
/* Format mcs */
/* FillValue FF */
/* BitSwap FALSE */
/* LoadDirection UP */
/* Collection "cavitycontrolcwv3" */
/* Version 0 "0" */
/* ConcurrentChain 0 */
P ActionCode(Cfg)
Device
PartName(xc2v2000)
File("C:\FPGADesigns\RFControl\xilinx\cavitycontrolcwv3.bit")
;
ChainEnd;
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