Commit 2bc4f51d authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@1241 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent b4a4c146
......@@ -659,6 +659,7 @@ signal cwMode, antiWindUp: std_logic;
signal resetC, prodLocalMode, prodRemoteMode, startCycleRising: std_logic;
signal timeTracker: std_logic_vector(15 downto 0);
signal cavOvrC, fwdOvrC, refOvrC, iqAlarm: std_logic;
signal resCSNAux: std_logic;
begin
......@@ -674,6 +675,7 @@ RAM1OEN <= ram1OEAux;
RAM1CSN <= ram1CSAux;
RAM1WEN <= ram1WEAux;
IQSel1 <= iqSel1Aux;
ResCSN <= resCSNAux;
XIrq2N <= vmeIntReqAux(2);
......@@ -908,7 +910,7 @@ U1_setpoints: setpoints PORT MAP(
Diag4Select => registers(DIAG4SELECTR)
);
-- temp stuff
TestOut <= (others=>'0');
TestOut <= "000000" & resCSNAux & "00000000000";
U0_commands: commands PORT MAP(
Clk40 => clk40,
......@@ -1210,7 +1212,7 @@ U0_rescontrol: rescontrol PORT MAP(
DataFromDecoder => dataFromDecoder,
TimeTracker => timeTracker,
RESCTRL => registers(RESCTRLR),
CSN => ResCSN,
CSN => resCSNAux,
ResCtrlD => ResCtrlD,
ResSClk => ResSClk
);
......
......@@ -40,6 +40,14 @@ signal rmPendingAddr: std_logic_vector(17 downto 0);
signal rmPendingData: std_logic_vector(15 downto 0);
signal rmPendingWrite, rmPendingRead: std_logic;
signal ramAddrAux: unsigned(17 downto 0);
signal spCounter: unsigned(4 downto 0);
signal signedSPCounter: signed(13 downto 0);
signal iAuxn, qAuxn, iAuxnp1, qAuxnp1: signed(13 downto 0); -- I(n), Q(n), I(n+1), Q(n+1)
signal iCurrent, qCurrent: signed(13 downto 0);
signal bigStepI, bigStepQ: signed(13 downto 0);
signal smallStepI, smallStepQ: signed(13 downto 0);
signal incrementI, incrementQ: signed(13 downto 0);
signal iOutAux, qOutAux: signed(13 downto 0);
begin
......@@ -48,6 +56,18 @@ ramDataIn <= RAMData;
-- RAMCS <= '0';
RAMAddress <= std_logic_vector(ramAddrAux);
smallStepI <= bigStepI(13) & bigStepI(13) & bigStepI(13) & bigStepI(13)
& bigStepI(13) & bigStepI(13 downto 5);
smallStepQ <= bigStepQ(13) & bigStepQ(13) & bigStepQ(13) & bigStepQ(13)
& bigStepQ(13) & bigStepQ(13 downto 5);
signedSPCounter <= signed("000000000" & spCounter);
incrementI <= (signedSPCounter * smallStepI) (13 downto 0);
incrementQ <= (signedSPCounter * smallStepQ) (13 downto 0);
IDataToProcess <= std_logic_vector(iOutAux(13) & iOutAux(13) & iOutAux);
QDataToProcess <= std_logic_vector(qOutAux(13) & qOutAux(13) & qOutAux);
PendingRM: process(Clk40)
begin
if Clk40'event and Clk40='1' then
......@@ -68,6 +88,17 @@ begin
end if;
end process PendingRM;
CounterProcess: process(Clk40)
begin
if Clk40'event and Clk40='1' then
if RFONRising = '1' then
spCounter <= (others=>'0');
else
spCounter <= spCounter + 1;
end if;
end if;
end process CounterProcess;
States: process(Clk40)
begin
......@@ -121,6 +152,16 @@ begin
case currentState is
when Idle =>
writing <= '0';
iAuxn <= (others=>'0');
qAuxn <= (others=>'0');
iAuxnp1 <= (others=>'0');
qAuxnp1 <= (others=>'0');
iCurrent <= (others=>'0');
qCurrent <= (others=>'0');
bigStepI <= (others=>'0');
bigStepQ <= (others=>'0');
iOutAux <= (others=>'0');
qOutAux <= (others=>'0');
if configMode='0' and RFONRising='1' then
RAMOE <= '0';
RAMCS <= '0';
......@@ -131,8 +172,6 @@ begin
RAMWE <= '1';
DataToRMValid <= '0';
ramAddrAux <= (others=>'0');
IDataToProcess <= (others =>'0');
QDataToProcess <= (others =>'0');
DataToProcessValid <= '0';
when rmRead =>
ramAddrAux <= unsigned(rmPendingAddr);
......@@ -155,18 +194,27 @@ begin
RAMWE <= '1';
RAMCS <= '1';
when rfOnRead =>
ramAddrAux <= ramAddrAux + 1;
if ramAddrAux(0)='1' then
IDataToProcess <= ramDataInC;
DataToProcessValid <= '0';
else
QDataToProcess <= ramDataInC;
if ramAddrAux /= "000000000000000000" then
DataToProcessValid <= '1';
else
DataToProcessValid <= '0';
end if;
end if;
DataToProcessValid <= '1';
iOutAux <= iCurrent + incrementI;
qOutAux <= qCurrent + incrementQ;
if spCounter=to_unsigned(10, spCounter'length) or
spCounter=to_unsigned(20, spCounter'length) then
ramAddrAux <= ramAddrAux + 1;
end if;
if spCounter=to_unsigned(5, spCounter'length) then
iAuxnp1 <= signed(ramDataInC(13 downto 0));
iAuxn <= iAuxnp1;
end if;
if spCounter=to_unsigned(15, spCounter'length) then
qAuxnp1 <= signed(ramDataInC(13 downto 0));
qAuxn <= qAuxnp1;
end if;
if spCounter=to_unsigned(31, spCounter'length) then
iCurrent <= iAuxn;
qCurrent <= qAuxn;
bigStepI <= iAuxnp1 - iAuxn;
bigStepQ <= qAuxnp1 - qAuxn;
end if;
when others =>
writing <= '0';
RAMOE <= '1';
......
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